diff --git a/codereview.cfg b/codereview.cfg
index 77a74f108eae36..e59a1c89121b4c 100644
--- a/codereview.cfg
+++ b/codereview.cfg
@@ -1 +1,2 @@
-branch: master
+branch: dev.simd
+parent-branch: master
diff --git a/src/cmd/compile/internal/abi/abiutils.go b/src/cmd/compile/internal/abi/abiutils.go
index c013aba19c41a6..cef78858151501 100644
--- a/src/cmd/compile/internal/abi/abiutils.go
+++ b/src/cmd/compile/internal/abi/abiutils.go
@@ -150,12 +150,12 @@ func appendParamTypes(rts []*types.Type, t *types.Type) []*types.Type {
 	if w == 0 {
 		return rts
 	}
-	if t.IsScalar() || t.IsPtrShaped() {
+	if t.IsScalar() || t.IsPtrShaped() || t.IsSIMD() {
 		if t.IsComplex() {
 			c := types.FloatForComplex(t)
 			return append(rts, c, c)
 		} else {
-			if int(t.Size()) <= types.RegSize {
+			if int(t.Size()) <= types.RegSize || t.IsSIMD() {
 				return append(rts, t)
 			}
 			// assume 64bit int on 32-bit machine
@@ -199,6 +199,9 @@ func appendParamOffsets(offsets []int64, at int64, t *types.Type) ([]int64, int6
 	if w == 0 {
 		return offsets, at
 	}
+	if t.IsSIMD() {
+		return append(offsets, at), at + w
+	}
 	if t.IsScalar() || t.IsPtrShaped() {
 		if t.IsComplex() || int(t.Size()) > types.RegSize { // complex and *int64 on 32-bit
 			s := w / 2
@@ -521,11 +524,11 @@ func (state *assignState) allocateRegs(regs []RegIndex, t *types.Type) []RegInde
 	}
 	ri := state.rUsed.intRegs
 	rf := state.rUsed.floatRegs
-	if t.IsScalar() || t.IsPtrShaped() {
+	if t.IsScalar() || t.IsPtrShaped() || t.IsSIMD() {
 		if t.IsComplex() {
 			regs = append(regs, RegIndex(rf+state.rTotal.intRegs), RegIndex(rf+1+state.rTotal.intRegs))
 			rf += 2
-		} else if t.IsFloat() {
+		} else if t.IsFloat() || t.IsSIMD() {
 			regs = append(regs, RegIndex(rf+state.rTotal.intRegs))
 			rf += 1
 		} else {
diff --git a/src/cmd/compile/internal/amd64/simdssa.go b/src/cmd/compile/internal/amd64/simdssa.go
new file mode 100644
index 00000000000000..67179ef12d6594
--- /dev/null
+++ b/src/cmd/compile/internal/amd64/simdssa.go
@@ -0,0 +1,1477 @@
+// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT.
+
+package amd64
+
+import (
+	"cmd/compile/internal/ssa"
+	"cmd/compile/internal/ssagen"
+	"cmd/internal/obj"
+	"cmd/internal/obj/x86"
+)
+
+func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
+	var p *obj.Prog
+	switch v.Op {
+	case ssa.OpAMD64VPABSB128,
+		ssa.OpAMD64VPABSB256,
+		ssa.OpAMD64VPABSB512,
+		ssa.OpAMD64VPABSW128,
+		ssa.OpAMD64VPABSW256,
+		ssa.OpAMD64VPABSW512,
+		ssa.OpAMD64VPABSD128,
+		ssa.OpAMD64VPABSD256,
+		ssa.OpAMD64VPABSD512,
+		ssa.OpAMD64VPABSQ128,
+		ssa.OpAMD64VPABSQ256,
+		ssa.OpAMD64VPABSQ512,
+		ssa.OpAMD64VRCP14PS128,
+		ssa.OpAMD64VRCP14PS256,
+		ssa.OpAMD64VRCP14PS512,
+		ssa.OpAMD64VRCP14PD128,
+		ssa.OpAMD64VRCP14PD256,
+		ssa.OpAMD64VRCP14PD512,
+		ssa.OpAMD64VRSQRTPS128,
+		ssa.OpAMD64VRSQRTPS256,
+		ssa.OpAMD64VRSQRT14PS512,
+		ssa.OpAMD64VRSQRT14PD128,
+		ssa.OpAMD64VRSQRT14PD256,
+		ssa.OpAMD64VRSQRT14PD512,
+		ssa.OpAMD64VPOPCNTB128,
+		ssa.OpAMD64VPOPCNTB256,
+		ssa.OpAMD64VPOPCNTB512,
+		ssa.OpAMD64VPOPCNTW128,
+		ssa.OpAMD64VPOPCNTW256,
+		ssa.OpAMD64VPOPCNTW512,
+		ssa.OpAMD64VPOPCNTD128,
+		ssa.OpAMD64VPOPCNTD256,
+		ssa.OpAMD64VPOPCNTD512,
+		ssa.OpAMD64VPOPCNTQ128,
+		ssa.OpAMD64VPOPCNTQ256,
+		ssa.OpAMD64VPOPCNTQ512,
+		ssa.OpAMD64VSQRTPS128,
+		ssa.OpAMD64VSQRTPS256,
+		ssa.OpAMD64VSQRTPS512,
+		ssa.OpAMD64VSQRTPD128,
+		ssa.OpAMD64VSQRTPD256,
+		ssa.OpAMD64VSQRTPD512:
+		p = simdV11(s, v)
+
+	case ssa.OpAMD64VADDPS128,
+		ssa.OpAMD64VADDPS256,
+		ssa.OpAMD64VADDPS512,
+		ssa.OpAMD64VADDPD128,
+		ssa.OpAMD64VADDPD256,
+		ssa.OpAMD64VADDPD512,
+		ssa.OpAMD64VPADDB128,
+		ssa.OpAMD64VPADDB256,
+		ssa.OpAMD64VPADDB512,
+		ssa.OpAMD64VPADDW128,
+		ssa.OpAMD64VPADDW256,
+		ssa.OpAMD64VPADDW512,
+		ssa.OpAMD64VPADDD128,
+		ssa.OpAMD64VPADDD256,
+		ssa.OpAMD64VPADDD512,
+		ssa.OpAMD64VPADDQ128,
+		ssa.OpAMD64VPADDQ256,
+		ssa.OpAMD64VPADDQ512,
+		ssa.OpAMD64VADDSUBPS128,
+		ssa.OpAMD64VADDSUBPS256,
+		ssa.OpAMD64VADDSUBPD128,
+		ssa.OpAMD64VADDSUBPD256,
+		ssa.OpAMD64VPAND128,
+		ssa.OpAMD64VPAND256,
+		ssa.OpAMD64VPANDD512,
+		ssa.OpAMD64VPANDQ512,
+		ssa.OpAMD64VPANDN128,
+		ssa.OpAMD64VPANDN256,
+		ssa.OpAMD64VPANDND512,
+		ssa.OpAMD64VPANDNQ512,
+		ssa.OpAMD64VPAVGB128,
+		ssa.OpAMD64VPAVGB256,
+		ssa.OpAMD64VPAVGB512,
+		ssa.OpAMD64VPAVGW128,
+		ssa.OpAMD64VPAVGW256,
+		ssa.OpAMD64VPAVGW512,
+		ssa.OpAMD64VDIVPS128,
+		ssa.OpAMD64VDIVPS256,
+		ssa.OpAMD64VDIVPS512,
+		ssa.OpAMD64VDIVPD128,
+		ssa.OpAMD64VDIVPD256,
+		ssa.OpAMD64VDIVPD512,
+		ssa.OpAMD64VPCMPEQB128,
+		ssa.OpAMD64VPCMPEQB256,
+		ssa.OpAMD64VPCMPEQW128,
+		ssa.OpAMD64VPCMPEQW256,
+		ssa.OpAMD64VPCMPEQD128,
+		ssa.OpAMD64VPCMPEQD256,
+		ssa.OpAMD64VPCMPEQQ128,
+		ssa.OpAMD64VPCMPEQQ256,
+		ssa.OpAMD64VGF2P8MULB128,
+		ssa.OpAMD64VGF2P8MULB256,
+		ssa.OpAMD64VGF2P8MULB512,
+		ssa.OpAMD64VPCMPGTB128,
+		ssa.OpAMD64VPCMPGTB256,
+		ssa.OpAMD64VPCMPGTW128,
+		ssa.OpAMD64VPCMPGTW256,
+		ssa.OpAMD64VPCMPGTD128,
+		ssa.OpAMD64VPCMPGTD256,
+		ssa.OpAMD64VPCMPGTQ128,
+		ssa.OpAMD64VPCMPGTQ256,
+		ssa.OpAMD64VMAXPS128,
+		ssa.OpAMD64VMAXPS256,
+		ssa.OpAMD64VMAXPS512,
+		ssa.OpAMD64VMAXPD128,
+		ssa.OpAMD64VMAXPD256,
+		ssa.OpAMD64VMAXPD512,
+		ssa.OpAMD64VPMAXSB128,
+		ssa.OpAMD64VPMAXSB256,
+		ssa.OpAMD64VPMAXSB512,
+		ssa.OpAMD64VPMAXSW128,
+		ssa.OpAMD64VPMAXSW256,
+		ssa.OpAMD64VPMAXSW512,
+		ssa.OpAMD64VPMAXSD128,
+		ssa.OpAMD64VPMAXSD256,
+		ssa.OpAMD64VPMAXSD512,
+		ssa.OpAMD64VPMAXSQ128,
+		ssa.OpAMD64VPMAXSQ256,
+		ssa.OpAMD64VPMAXSQ512,
+		ssa.OpAMD64VPMAXUB128,
+		ssa.OpAMD64VPMAXUB256,
+		ssa.OpAMD64VPMAXUB512,
+		ssa.OpAMD64VPMAXUW128,
+		ssa.OpAMD64VPMAXUW256,
+		ssa.OpAMD64VPMAXUW512,
+		ssa.OpAMD64VPMAXUD128,
+		ssa.OpAMD64VPMAXUD256,
+		ssa.OpAMD64VPMAXUD512,
+		ssa.OpAMD64VPMAXUQ128,
+		ssa.OpAMD64VPMAXUQ256,
+		ssa.OpAMD64VPMAXUQ512,
+		ssa.OpAMD64VMINPS128,
+		ssa.OpAMD64VMINPS256,
+		ssa.OpAMD64VMINPS512,
+		ssa.OpAMD64VMINPD128,
+		ssa.OpAMD64VMINPD256,
+		ssa.OpAMD64VMINPD512,
+		ssa.OpAMD64VPMINSB128,
+		ssa.OpAMD64VPMINSB256,
+		ssa.OpAMD64VPMINSB512,
+		ssa.OpAMD64VPMINSW128,
+		ssa.OpAMD64VPMINSW256,
+		ssa.OpAMD64VPMINSW512,
+		ssa.OpAMD64VPMINSD128,
+		ssa.OpAMD64VPMINSD256,
+		ssa.OpAMD64VPMINSD512,
+		ssa.OpAMD64VPMINSQ128,
+		ssa.OpAMD64VPMINSQ256,
+		ssa.OpAMD64VPMINSQ512,
+		ssa.OpAMD64VPMINUB128,
+		ssa.OpAMD64VPMINUB256,
+		ssa.OpAMD64VPMINUB512,
+		ssa.OpAMD64VPMINUW128,
+		ssa.OpAMD64VPMINUW256,
+		ssa.OpAMD64VPMINUW512,
+		ssa.OpAMD64VPMINUD128,
+		ssa.OpAMD64VPMINUD256,
+		ssa.OpAMD64VPMINUD512,
+		ssa.OpAMD64VPMINUQ128,
+		ssa.OpAMD64VPMINUQ256,
+		ssa.OpAMD64VPMINUQ512,
+		ssa.OpAMD64VMULPS128,
+		ssa.OpAMD64VMULPS256,
+		ssa.OpAMD64VMULPS512,
+		ssa.OpAMD64VMULPD128,
+		ssa.OpAMD64VMULPD256,
+		ssa.OpAMD64VMULPD512,
+		ssa.OpAMD64VSCALEFPS128,
+		ssa.OpAMD64VSCALEFPS256,
+		ssa.OpAMD64VSCALEFPS512,
+		ssa.OpAMD64VSCALEFPD128,
+		ssa.OpAMD64VSCALEFPD256,
+		ssa.OpAMD64VSCALEFPD512,
+		ssa.OpAMD64VPMULDQ128,
+		ssa.OpAMD64VPMULDQ256,
+		ssa.OpAMD64VPMULDQ512,
+		ssa.OpAMD64VPMULUDQ128,
+		ssa.OpAMD64VPMULUDQ256,
+		ssa.OpAMD64VPMULUDQ512,
+		ssa.OpAMD64VPMULHW128,
+		ssa.OpAMD64VPMULHW256,
+		ssa.OpAMD64VPMULHW512,
+		ssa.OpAMD64VPMULHUW128,
+		ssa.OpAMD64VPMULHUW256,
+		ssa.OpAMD64VPMULHUW512,
+		ssa.OpAMD64VPMULLW128,
+		ssa.OpAMD64VPMULLW256,
+		ssa.OpAMD64VPMULLW512,
+		ssa.OpAMD64VPMULLD128,
+		ssa.OpAMD64VPMULLD256,
+		ssa.OpAMD64VPMULLD512,
+		ssa.OpAMD64VPMULLQ128,
+		ssa.OpAMD64VPMULLQ256,
+		ssa.OpAMD64VPMULLQ512,
+		ssa.OpAMD64VPOR128,
+		ssa.OpAMD64VPOR256,
+		ssa.OpAMD64VPORD512,
+		ssa.OpAMD64VPORQ512,
+		ssa.OpAMD64VPMADDWD128,
+		ssa.OpAMD64VPMADDWD256,
+		ssa.OpAMD64VPMADDWD512,
+		ssa.OpAMD64VHADDPS128,
+		ssa.OpAMD64VHADDPS256,
+		ssa.OpAMD64VHADDPD128,
+		ssa.OpAMD64VHADDPD256,
+		ssa.OpAMD64VPHADDW128,
+		ssa.OpAMD64VPHADDW256,
+		ssa.OpAMD64VPHADDD128,
+		ssa.OpAMD64VPHADDD256,
+		ssa.OpAMD64VHSUBPS128,
+		ssa.OpAMD64VHSUBPS256,
+		ssa.OpAMD64VHSUBPD128,
+		ssa.OpAMD64VHSUBPD256,
+		ssa.OpAMD64VPHSUBW128,
+		ssa.OpAMD64VPHSUBW256,
+		ssa.OpAMD64VPHSUBD128,
+		ssa.OpAMD64VPHSUBD256,
+		ssa.OpAMD64VPERMB128,
+		ssa.OpAMD64VPERMB256,
+		ssa.OpAMD64VPERMB512,
+		ssa.OpAMD64VPERMW128,
+		ssa.OpAMD64VPERMW256,
+		ssa.OpAMD64VPERMW512,
+		ssa.OpAMD64VPERMPS256,
+		ssa.OpAMD64VPERMD256,
+		ssa.OpAMD64VPERMPS512,
+		ssa.OpAMD64VPERMD512,
+		ssa.OpAMD64VPERMPD256,
+		ssa.OpAMD64VPERMQ256,
+		ssa.OpAMD64VPERMPD512,
+		ssa.OpAMD64VPERMQ512,
+		ssa.OpAMD64VPROLVD128,
+		ssa.OpAMD64VPROLVD256,
+		ssa.OpAMD64VPROLVD512,
+		ssa.OpAMD64VPROLVQ128,
+		ssa.OpAMD64VPROLVQ256,
+		ssa.OpAMD64VPROLVQ512,
+		ssa.OpAMD64VPRORVD128,
+		ssa.OpAMD64VPRORVD256,
+		ssa.OpAMD64VPRORVD512,
+		ssa.OpAMD64VPRORVQ128,
+		ssa.OpAMD64VPRORVQ256,
+		ssa.OpAMD64VPRORVQ512,
+		ssa.OpAMD64VPADDSB128,
+		ssa.OpAMD64VPADDSB256,
+		ssa.OpAMD64VPADDSB512,
+		ssa.OpAMD64VPADDSW128,
+		ssa.OpAMD64VPADDSW256,
+		ssa.OpAMD64VPADDSW512,
+		ssa.OpAMD64VPHADDSW128,
+		ssa.OpAMD64VPHADDSW256,
+		ssa.OpAMD64VPHSUBSW128,
+		ssa.OpAMD64VPHSUBSW256,
+		ssa.OpAMD64VPSUBSB128,
+		ssa.OpAMD64VPSUBSB256,
+		ssa.OpAMD64VPSUBSB512,
+		ssa.OpAMD64VPSUBSW128,
+		ssa.OpAMD64VPSUBSW256,
+		ssa.OpAMD64VPSUBSW512,
+		ssa.OpAMD64VPMADDUBSW128,
+		ssa.OpAMD64VPMADDUBSW256,
+		ssa.OpAMD64VPMADDUBSW512,
+		ssa.OpAMD64VPSLLVW128,
+		ssa.OpAMD64VPSLLVW256,
+		ssa.OpAMD64VPSLLVW512,
+		ssa.OpAMD64VPSLLVD128,
+		ssa.OpAMD64VPSLLVD256,
+		ssa.OpAMD64VPSLLVD512,
+		ssa.OpAMD64VPSLLVQ128,
+		ssa.OpAMD64VPSLLVQ256,
+		ssa.OpAMD64VPSLLVQ512,
+		ssa.OpAMD64VPSRAVW128,
+		ssa.OpAMD64VPSRAVW256,
+		ssa.OpAMD64VPSRAVW512,
+		ssa.OpAMD64VPSRAVD128,
+		ssa.OpAMD64VPSRAVD256,
+		ssa.OpAMD64VPSRAVD512,
+		ssa.OpAMD64VPSRAVQ128,
+		ssa.OpAMD64VPSRAVQ256,
+		ssa.OpAMD64VPSRAVQ512,
+		ssa.OpAMD64VPSRLVW128,
+		ssa.OpAMD64VPSRLVW256,
+		ssa.OpAMD64VPSRLVW512,
+		ssa.OpAMD64VPSRLVD128,
+		ssa.OpAMD64VPSRLVD256,
+		ssa.OpAMD64VPSRLVD512,
+		ssa.OpAMD64VPSRLVQ128,
+		ssa.OpAMD64VPSRLVQ256,
+		ssa.OpAMD64VPSRLVQ512,
+		ssa.OpAMD64VPSIGNB128,
+		ssa.OpAMD64VPSIGNB256,
+		ssa.OpAMD64VPSIGNW128,
+		ssa.OpAMD64VPSIGNW256,
+		ssa.OpAMD64VPSIGND128,
+		ssa.OpAMD64VPSIGND256,
+		ssa.OpAMD64VSUBPS128,
+		ssa.OpAMD64VSUBPS256,
+		ssa.OpAMD64VSUBPS512,
+		ssa.OpAMD64VSUBPD128,
+		ssa.OpAMD64VSUBPD256,
+		ssa.OpAMD64VSUBPD512,
+		ssa.OpAMD64VPSUBB128,
+		ssa.OpAMD64VPSUBB256,
+		ssa.OpAMD64VPSUBB512,
+		ssa.OpAMD64VPSUBW128,
+		ssa.OpAMD64VPSUBW256,
+		ssa.OpAMD64VPSUBW512,
+		ssa.OpAMD64VPSUBD128,
+		ssa.OpAMD64VPSUBD256,
+		ssa.OpAMD64VPSUBD512,
+		ssa.OpAMD64VPSUBQ128,
+		ssa.OpAMD64VPSUBQ256,
+		ssa.OpAMD64VPSUBQ512,
+		ssa.OpAMD64VPXOR128,
+		ssa.OpAMD64VPXOR256,
+		ssa.OpAMD64VPXORD512,
+		ssa.OpAMD64VPXORQ512:
+		p = simdV21(s, v)
+
+	case ssa.OpAMD64VADDPSMasked128,
+		ssa.OpAMD64VADDPSMasked256,
+		ssa.OpAMD64VADDPSMasked512,
+		ssa.OpAMD64VADDPDMasked128,
+		ssa.OpAMD64VADDPDMasked256,
+		ssa.OpAMD64VADDPDMasked512,
+		ssa.OpAMD64VPADDBMasked128,
+		ssa.OpAMD64VPADDBMasked256,
+		ssa.OpAMD64VPADDBMasked512,
+		ssa.OpAMD64VPADDWMasked128,
+		ssa.OpAMD64VPADDWMasked256,
+		ssa.OpAMD64VPADDWMasked512,
+		ssa.OpAMD64VPADDDMasked128,
+		ssa.OpAMD64VPADDDMasked256,
+		ssa.OpAMD64VPADDDMasked512,
+		ssa.OpAMD64VPADDQMasked128,
+		ssa.OpAMD64VPADDQMasked256,
+		ssa.OpAMD64VPADDQMasked512,
+		ssa.OpAMD64VPANDDMasked128,
+		ssa.OpAMD64VPANDDMasked256,
+		ssa.OpAMD64VPANDDMasked512,
+		ssa.OpAMD64VPANDQMasked128,
+		ssa.OpAMD64VPANDQMasked256,
+		ssa.OpAMD64VPANDQMasked512,
+		ssa.OpAMD64VPANDNDMasked128,
+		ssa.OpAMD64VPANDNDMasked256,
+		ssa.OpAMD64VPANDNDMasked512,
+		ssa.OpAMD64VPANDNQMasked128,
+		ssa.OpAMD64VPANDNQMasked256,
+		ssa.OpAMD64VPANDNQMasked512,
+		ssa.OpAMD64VPAVGBMasked128,
+		ssa.OpAMD64VPAVGBMasked256,
+		ssa.OpAMD64VPAVGBMasked512,
+		ssa.OpAMD64VPAVGWMasked128,
+		ssa.OpAMD64VPAVGWMasked256,
+		ssa.OpAMD64VPAVGWMasked512,
+		ssa.OpAMD64VDIVPSMasked128,
+		ssa.OpAMD64VDIVPSMasked256,
+		ssa.OpAMD64VDIVPSMasked512,
+		ssa.OpAMD64VDIVPDMasked128,
+		ssa.OpAMD64VDIVPDMasked256,
+		ssa.OpAMD64VDIVPDMasked512,
+		ssa.OpAMD64VGF2P8MULBMasked128,
+		ssa.OpAMD64VGF2P8MULBMasked256,
+		ssa.OpAMD64VGF2P8MULBMasked512,
+		ssa.OpAMD64VMAXPSMasked128,
+		ssa.OpAMD64VMAXPSMasked256,
+		ssa.OpAMD64VMAXPSMasked512,
+		ssa.OpAMD64VMAXPDMasked128,
+		ssa.OpAMD64VMAXPDMasked256,
+		ssa.OpAMD64VMAXPDMasked512,
+		ssa.OpAMD64VPMAXSBMasked128,
+		ssa.OpAMD64VPMAXSBMasked256,
+		ssa.OpAMD64VPMAXSBMasked512,
+		ssa.OpAMD64VPMAXSWMasked128,
+		ssa.OpAMD64VPMAXSWMasked256,
+		ssa.OpAMD64VPMAXSWMasked512,
+		ssa.OpAMD64VPMAXSDMasked128,
+		ssa.OpAMD64VPMAXSDMasked256,
+		ssa.OpAMD64VPMAXSDMasked512,
+		ssa.OpAMD64VPMAXSQMasked128,
+		ssa.OpAMD64VPMAXSQMasked256,
+		ssa.OpAMD64VPMAXSQMasked512,
+		ssa.OpAMD64VPMAXUBMasked128,
+		ssa.OpAMD64VPMAXUBMasked256,
+		ssa.OpAMD64VPMAXUBMasked512,
+		ssa.OpAMD64VPMAXUWMasked128,
+		ssa.OpAMD64VPMAXUWMasked256,
+		ssa.OpAMD64VPMAXUWMasked512,
+		ssa.OpAMD64VPMAXUDMasked128,
+		ssa.OpAMD64VPMAXUDMasked256,
+		ssa.OpAMD64VPMAXUDMasked512,
+		ssa.OpAMD64VPMAXUQMasked128,
+		ssa.OpAMD64VPMAXUQMasked256,
+		ssa.OpAMD64VPMAXUQMasked512,
+		ssa.OpAMD64VMINPSMasked128,
+		ssa.OpAMD64VMINPSMasked256,
+		ssa.OpAMD64VMINPSMasked512,
+		ssa.OpAMD64VMINPDMasked128,
+		ssa.OpAMD64VMINPDMasked256,
+		ssa.OpAMD64VMINPDMasked512,
+		ssa.OpAMD64VPMINSBMasked128,
+		ssa.OpAMD64VPMINSBMasked256,
+		ssa.OpAMD64VPMINSBMasked512,
+		ssa.OpAMD64VPMINSWMasked128,
+		ssa.OpAMD64VPMINSWMasked256,
+		ssa.OpAMD64VPMINSWMasked512,
+		ssa.OpAMD64VPMINSDMasked128,
+		ssa.OpAMD64VPMINSDMasked256,
+		ssa.OpAMD64VPMINSDMasked512,
+		ssa.OpAMD64VPMINSQMasked128,
+		ssa.OpAMD64VPMINSQMasked256,
+		ssa.OpAMD64VPMINSQMasked512,
+		ssa.OpAMD64VPMINUBMasked128,
+		ssa.OpAMD64VPMINUBMasked256,
+		ssa.OpAMD64VPMINUBMasked512,
+		ssa.OpAMD64VPMINUWMasked128,
+		ssa.OpAMD64VPMINUWMasked256,
+		ssa.OpAMD64VPMINUWMasked512,
+		ssa.OpAMD64VPMINUDMasked128,
+		ssa.OpAMD64VPMINUDMasked256,
+		ssa.OpAMD64VPMINUDMasked512,
+		ssa.OpAMD64VPMINUQMasked128,
+		ssa.OpAMD64VPMINUQMasked256,
+		ssa.OpAMD64VPMINUQMasked512,
+		ssa.OpAMD64VSCALEFPSMasked128,
+		ssa.OpAMD64VSCALEFPSMasked256,
+		ssa.OpAMD64VSCALEFPSMasked512,
+		ssa.OpAMD64VSCALEFPDMasked128,
+		ssa.OpAMD64VSCALEFPDMasked256,
+		ssa.OpAMD64VSCALEFPDMasked512,
+		ssa.OpAMD64VPMULDQMasked128,
+		ssa.OpAMD64VPMULDQMasked256,
+		ssa.OpAMD64VPMULDQMasked512,
+		ssa.OpAMD64VPMULUDQMasked128,
+		ssa.OpAMD64VPMULUDQMasked256,
+		ssa.OpAMD64VPMULUDQMasked512,
+		ssa.OpAMD64VPMULHWMasked128,
+		ssa.OpAMD64VPMULHWMasked256,
+		ssa.OpAMD64VPMULHWMasked512,
+		ssa.OpAMD64VPMULHUWMasked128,
+		ssa.OpAMD64VPMULHUWMasked256,
+		ssa.OpAMD64VPMULHUWMasked512,
+		ssa.OpAMD64VPMULLWMasked128,
+		ssa.OpAMD64VPMULLWMasked256,
+		ssa.OpAMD64VPMULLWMasked512,
+		ssa.OpAMD64VPMULLDMasked128,
+		ssa.OpAMD64VPMULLDMasked256,
+		ssa.OpAMD64VPMULLDMasked512,
+		ssa.OpAMD64VPMULLQMasked128,
+		ssa.OpAMD64VPMULLQMasked256,
+		ssa.OpAMD64VPMULLQMasked512,
+		ssa.OpAMD64VMULPSMasked128,
+		ssa.OpAMD64VMULPSMasked256,
+		ssa.OpAMD64VMULPSMasked512,
+		ssa.OpAMD64VMULPDMasked128,
+		ssa.OpAMD64VMULPDMasked256,
+		ssa.OpAMD64VMULPDMasked512,
+		ssa.OpAMD64VPORDMasked128,
+		ssa.OpAMD64VPORDMasked256,
+		ssa.OpAMD64VPORDMasked512,
+		ssa.OpAMD64VPORQMasked128,
+		ssa.OpAMD64VPORQMasked256,
+		ssa.OpAMD64VPORQMasked512,
+		ssa.OpAMD64VPMADDWDMasked128,
+		ssa.OpAMD64VPMADDWDMasked256,
+		ssa.OpAMD64VPMADDWDMasked512,
+		ssa.OpAMD64VPERMBMasked128,
+		ssa.OpAMD64VPERMBMasked256,
+		ssa.OpAMD64VPERMBMasked512,
+		ssa.OpAMD64VPERMWMasked128,
+		ssa.OpAMD64VPERMWMasked256,
+		ssa.OpAMD64VPERMWMasked512,
+		ssa.OpAMD64VPERMPSMasked256,
+		ssa.OpAMD64VPERMDMasked256,
+		ssa.OpAMD64VPERMPSMasked512,
+		ssa.OpAMD64VPERMDMasked512,
+		ssa.OpAMD64VPERMPDMasked256,
+		ssa.OpAMD64VPERMQMasked256,
+		ssa.OpAMD64VPERMPDMasked512,
+		ssa.OpAMD64VPERMQMasked512,
+		ssa.OpAMD64VPROLVDMasked128,
+		ssa.OpAMD64VPROLVDMasked256,
+		ssa.OpAMD64VPROLVDMasked512,
+		ssa.OpAMD64VPROLVQMasked128,
+		ssa.OpAMD64VPROLVQMasked256,
+		ssa.OpAMD64VPROLVQMasked512,
+		ssa.OpAMD64VPRORVDMasked128,
+		ssa.OpAMD64VPRORVDMasked256,
+		ssa.OpAMD64VPRORVDMasked512,
+		ssa.OpAMD64VPRORVQMasked128,
+		ssa.OpAMD64VPRORVQMasked256,
+		ssa.OpAMD64VPRORVQMasked512,
+		ssa.OpAMD64VPADDSBMasked128,
+		ssa.OpAMD64VPADDSBMasked256,
+		ssa.OpAMD64VPADDSBMasked512,
+		ssa.OpAMD64VPADDSWMasked128,
+		ssa.OpAMD64VPADDSWMasked256,
+		ssa.OpAMD64VPADDSWMasked512,
+		ssa.OpAMD64VPSUBSBMasked128,
+		ssa.OpAMD64VPSUBSBMasked256,
+		ssa.OpAMD64VPSUBSBMasked512,
+		ssa.OpAMD64VPSUBSWMasked128,
+		ssa.OpAMD64VPSUBSWMasked256,
+		ssa.OpAMD64VPSUBSWMasked512,
+		ssa.OpAMD64VPMADDUBSWMasked128,
+		ssa.OpAMD64VPMADDUBSWMasked256,
+		ssa.OpAMD64VPMADDUBSWMasked512,
+		ssa.OpAMD64VPSLLVWMasked128,
+		ssa.OpAMD64VPSLLVWMasked256,
+		ssa.OpAMD64VPSLLVWMasked512,
+		ssa.OpAMD64VPSLLVDMasked128,
+		ssa.OpAMD64VPSLLVDMasked256,
+		ssa.OpAMD64VPSLLVDMasked512,
+		ssa.OpAMD64VPSLLVQMasked128,
+		ssa.OpAMD64VPSLLVQMasked256,
+		ssa.OpAMD64VPSLLVQMasked512,
+		ssa.OpAMD64VPSRAVWMasked128,
+		ssa.OpAMD64VPSRAVWMasked256,
+		ssa.OpAMD64VPSRAVWMasked512,
+		ssa.OpAMD64VPSRAVDMasked128,
+		ssa.OpAMD64VPSRAVDMasked256,
+		ssa.OpAMD64VPSRAVDMasked512,
+		ssa.OpAMD64VPSRAVQMasked128,
+		ssa.OpAMD64VPSRAVQMasked256,
+		ssa.OpAMD64VPSRAVQMasked512,
+		ssa.OpAMD64VPSRLVWMasked128,
+		ssa.OpAMD64VPSRLVWMasked256,
+		ssa.OpAMD64VPSRLVWMasked512,
+		ssa.OpAMD64VPSRLVDMasked128,
+		ssa.OpAMD64VPSRLVDMasked256,
+		ssa.OpAMD64VPSRLVDMasked512,
+		ssa.OpAMD64VPSRLVQMasked128,
+		ssa.OpAMD64VPSRLVQMasked256,
+		ssa.OpAMD64VPSRLVQMasked512,
+		ssa.OpAMD64VSUBPSMasked128,
+		ssa.OpAMD64VSUBPSMasked256,
+		ssa.OpAMD64VSUBPSMasked512,
+		ssa.OpAMD64VSUBPDMasked128,
+		ssa.OpAMD64VSUBPDMasked256,
+		ssa.OpAMD64VSUBPDMasked512,
+		ssa.OpAMD64VPSUBBMasked128,
+		ssa.OpAMD64VPSUBBMasked256,
+		ssa.OpAMD64VPSUBBMasked512,
+		ssa.OpAMD64VPSUBWMasked128,
+		ssa.OpAMD64VPSUBWMasked256,
+		ssa.OpAMD64VPSUBWMasked512,
+		ssa.OpAMD64VPSUBDMasked128,
+		ssa.OpAMD64VPSUBDMasked256,
+		ssa.OpAMD64VPSUBDMasked512,
+		ssa.OpAMD64VPSUBQMasked128,
+		ssa.OpAMD64VPSUBQMasked256,
+		ssa.OpAMD64VPSUBQMasked512,
+		ssa.OpAMD64VPXORDMasked128,
+		ssa.OpAMD64VPXORDMasked256,
+		ssa.OpAMD64VPXORDMasked512,
+		ssa.OpAMD64VPXORQMasked128,
+		ssa.OpAMD64VPXORQMasked256,
+		ssa.OpAMD64VPXORQMasked512:
+		p = simdV2kv(s, v)
+
+	case ssa.OpAMD64VPABSBMasked128,
+		ssa.OpAMD64VPABSBMasked256,
+		ssa.OpAMD64VPABSBMasked512,
+		ssa.OpAMD64VPABSWMasked128,
+		ssa.OpAMD64VPABSWMasked256,
+		ssa.OpAMD64VPABSWMasked512,
+		ssa.OpAMD64VPABSDMasked128,
+		ssa.OpAMD64VPABSDMasked256,
+		ssa.OpAMD64VPABSDMasked512,
+		ssa.OpAMD64VPABSQMasked128,
+		ssa.OpAMD64VPABSQMasked256,
+		ssa.OpAMD64VPABSQMasked512,
+		ssa.OpAMD64VRCP14PSMasked128,
+		ssa.OpAMD64VRCP14PSMasked256,
+		ssa.OpAMD64VRCP14PSMasked512,
+		ssa.OpAMD64VRCP14PDMasked128,
+		ssa.OpAMD64VRCP14PDMasked256,
+		ssa.OpAMD64VRCP14PDMasked512,
+		ssa.OpAMD64VRSQRT14PSMasked128,
+		ssa.OpAMD64VRSQRT14PSMasked256,
+		ssa.OpAMD64VRSQRT14PSMasked512,
+		ssa.OpAMD64VRSQRT14PDMasked128,
+		ssa.OpAMD64VRSQRT14PDMasked256,
+		ssa.OpAMD64VRSQRT14PDMasked512,
+		ssa.OpAMD64VCOMPRESSPSMasked128,
+		ssa.OpAMD64VCOMPRESSPSMasked256,
+		ssa.OpAMD64VCOMPRESSPSMasked512,
+		ssa.OpAMD64VCOMPRESSPDMasked128,
+		ssa.OpAMD64VCOMPRESSPDMasked256,
+		ssa.OpAMD64VCOMPRESSPDMasked512,
+		ssa.OpAMD64VPCOMPRESSBMasked128,
+		ssa.OpAMD64VPCOMPRESSBMasked256,
+		ssa.OpAMD64VPCOMPRESSBMasked512,
+		ssa.OpAMD64VPCOMPRESSWMasked128,
+		ssa.OpAMD64VPCOMPRESSWMasked256,
+		ssa.OpAMD64VPCOMPRESSWMasked512,
+		ssa.OpAMD64VPCOMPRESSDMasked128,
+		ssa.OpAMD64VPCOMPRESSDMasked256,
+		ssa.OpAMD64VPCOMPRESSDMasked512,
+		ssa.OpAMD64VPCOMPRESSQMasked128,
+		ssa.OpAMD64VPCOMPRESSQMasked256,
+		ssa.OpAMD64VPCOMPRESSQMasked512,
+		ssa.OpAMD64VPOPCNTBMasked128,
+		ssa.OpAMD64VPOPCNTBMasked256,
+		ssa.OpAMD64VPOPCNTBMasked512,
+		ssa.OpAMD64VPOPCNTWMasked128,
+		ssa.OpAMD64VPOPCNTWMasked256,
+		ssa.OpAMD64VPOPCNTWMasked512,
+		ssa.OpAMD64VPOPCNTDMasked128,
+		ssa.OpAMD64VPOPCNTDMasked256,
+		ssa.OpAMD64VPOPCNTDMasked512,
+		ssa.OpAMD64VPOPCNTQMasked128,
+		ssa.OpAMD64VPOPCNTQMasked256,
+		ssa.OpAMD64VPOPCNTQMasked512,
+		ssa.OpAMD64VSQRTPSMasked128,
+		ssa.OpAMD64VSQRTPSMasked256,
+		ssa.OpAMD64VSQRTPSMasked512,
+		ssa.OpAMD64VSQRTPDMasked128,
+		ssa.OpAMD64VSQRTPDMasked256,
+		ssa.OpAMD64VSQRTPDMasked512:
+		p = simdVkv(s, v)
+
+	case ssa.OpAMD64VROUNDPS128,
+		ssa.OpAMD64VROUNDPS256,
+		ssa.OpAMD64VROUNDPD128,
+		ssa.OpAMD64VROUNDPD256,
+		ssa.OpAMD64VRNDSCALEPS128,
+		ssa.OpAMD64VRNDSCALEPS256,
+		ssa.OpAMD64VRNDSCALEPS512,
+		ssa.OpAMD64VRNDSCALEPD128,
+		ssa.OpAMD64VRNDSCALEPD256,
+		ssa.OpAMD64VRNDSCALEPD512,
+		ssa.OpAMD64VREDUCEPS128,
+		ssa.OpAMD64VREDUCEPS256,
+		ssa.OpAMD64VREDUCEPS512,
+		ssa.OpAMD64VREDUCEPD128,
+		ssa.OpAMD64VREDUCEPD256,
+		ssa.OpAMD64VREDUCEPD512,
+		ssa.OpAMD64VEXTRACTF128128,
+		ssa.OpAMD64VEXTRACTI128128,
+		ssa.OpAMD64VPROLD128,
+		ssa.OpAMD64VPROLD256,
+		ssa.OpAMD64VPROLD512,
+		ssa.OpAMD64VPROLQ128,
+		ssa.OpAMD64VPROLQ256,
+		ssa.OpAMD64VPROLQ512,
+		ssa.OpAMD64VPRORD128,
+		ssa.OpAMD64VPRORD256,
+		ssa.OpAMD64VPRORD512,
+		ssa.OpAMD64VPRORQ128,
+		ssa.OpAMD64VPRORQ256,
+		ssa.OpAMD64VPRORQ512:
+		p = simdV11Imm8(s, v)
+
+	case ssa.OpAMD64VRNDSCALEPSMasked128,
+		ssa.OpAMD64VRNDSCALEPSMasked256,
+		ssa.OpAMD64VRNDSCALEPSMasked512,
+		ssa.OpAMD64VRNDSCALEPDMasked128,
+		ssa.OpAMD64VRNDSCALEPDMasked256,
+		ssa.OpAMD64VRNDSCALEPDMasked512,
+		ssa.OpAMD64VREDUCEPSMasked128,
+		ssa.OpAMD64VREDUCEPSMasked256,
+		ssa.OpAMD64VREDUCEPSMasked512,
+		ssa.OpAMD64VREDUCEPDMasked128,
+		ssa.OpAMD64VREDUCEPDMasked256,
+		ssa.OpAMD64VREDUCEPDMasked512,
+		ssa.OpAMD64VPROLDMasked128,
+		ssa.OpAMD64VPROLDMasked256,
+		ssa.OpAMD64VPROLDMasked512,
+		ssa.OpAMD64VPROLQMasked128,
+		ssa.OpAMD64VPROLQMasked256,
+		ssa.OpAMD64VPROLQMasked512,
+		ssa.OpAMD64VPRORDMasked128,
+		ssa.OpAMD64VPRORDMasked256,
+		ssa.OpAMD64VPRORDMasked512,
+		ssa.OpAMD64VPRORQMasked128,
+		ssa.OpAMD64VPRORQMasked256,
+		ssa.OpAMD64VPRORQMasked512:
+		p = simdVkvImm8(s, v)
+
+	case ssa.OpAMD64VDPPS128,
+		ssa.OpAMD64VDPPS256,
+		ssa.OpAMD64VDPPD128,
+		ssa.OpAMD64VCMPPS128,
+		ssa.OpAMD64VCMPPS256,
+		ssa.OpAMD64VCMPPD128,
+		ssa.OpAMD64VCMPPD256,
+		ssa.OpAMD64VGF2P8AFFINEQB128,
+		ssa.OpAMD64VGF2P8AFFINEQB256,
+		ssa.OpAMD64VGF2P8AFFINEQB512,
+		ssa.OpAMD64VGF2P8AFFINEINVQB128,
+		ssa.OpAMD64VGF2P8AFFINEINVQB256,
+		ssa.OpAMD64VGF2P8AFFINEINVQB512,
+		ssa.OpAMD64VINSERTF128256,
+		ssa.OpAMD64VINSERTI128256,
+		ssa.OpAMD64VPSHLDW128,
+		ssa.OpAMD64VPSHLDW256,
+		ssa.OpAMD64VPSHLDW512,
+		ssa.OpAMD64VPSHLDD128,
+		ssa.OpAMD64VPSHLDD256,
+		ssa.OpAMD64VPSHLDD512,
+		ssa.OpAMD64VPSHLDQ128,
+		ssa.OpAMD64VPSHLDQ256,
+		ssa.OpAMD64VPSHLDQ512,
+		ssa.OpAMD64VPSHRDW128,
+		ssa.OpAMD64VPSHRDW256,
+		ssa.OpAMD64VPSHRDW512,
+		ssa.OpAMD64VPSHRDD128,
+		ssa.OpAMD64VPSHRDD256,
+		ssa.OpAMD64VPSHRDD512,
+		ssa.OpAMD64VPSHRDQ128,
+		ssa.OpAMD64VPSHRDQ256,
+		ssa.OpAMD64VPSHRDQ512:
+		p = simdV21Imm8(s, v)
+
+	case ssa.OpAMD64VCMPPS512,
+		ssa.OpAMD64VCMPPD512,
+		ssa.OpAMD64VPCMPB512,
+		ssa.OpAMD64VPCMPW512,
+		ssa.OpAMD64VPCMPD512,
+		ssa.OpAMD64VPCMPQ512,
+		ssa.OpAMD64VPCMPUB512,
+		ssa.OpAMD64VPCMPUW512,
+		ssa.OpAMD64VPCMPUD512,
+		ssa.OpAMD64VPCMPUQ512,
+		ssa.OpAMD64VPCMPUB128,
+		ssa.OpAMD64VPCMPUB256,
+		ssa.OpAMD64VPCMPUW128,
+		ssa.OpAMD64VPCMPUW256,
+		ssa.OpAMD64VPCMPUD128,
+		ssa.OpAMD64VPCMPUD256,
+		ssa.OpAMD64VPCMPUQ128,
+		ssa.OpAMD64VPCMPUQ256,
+		ssa.OpAMD64VPCMPB128,
+		ssa.OpAMD64VPCMPB256,
+		ssa.OpAMD64VPCMPW128,
+		ssa.OpAMD64VPCMPW256,
+		ssa.OpAMD64VPCMPD128,
+		ssa.OpAMD64VPCMPD256,
+		ssa.OpAMD64VPCMPQ128,
+		ssa.OpAMD64VPCMPQ256:
+		p = simdV2kImm8(s, v)
+
+	case ssa.OpAMD64VCMPPSMasked128,
+		ssa.OpAMD64VCMPPSMasked256,
+		ssa.OpAMD64VCMPPSMasked512,
+		ssa.OpAMD64VCMPPDMasked128,
+		ssa.OpAMD64VCMPPDMasked256,
+		ssa.OpAMD64VCMPPDMasked512,
+		ssa.OpAMD64VPCMPBMasked128,
+		ssa.OpAMD64VPCMPBMasked256,
+		ssa.OpAMD64VPCMPBMasked512,
+		ssa.OpAMD64VPCMPWMasked128,
+		ssa.OpAMD64VPCMPWMasked256,
+		ssa.OpAMD64VPCMPWMasked512,
+		ssa.OpAMD64VPCMPDMasked128,
+		ssa.OpAMD64VPCMPDMasked256,
+		ssa.OpAMD64VPCMPDMasked512,
+		ssa.OpAMD64VPCMPQMasked128,
+		ssa.OpAMD64VPCMPQMasked256,
+		ssa.OpAMD64VPCMPQMasked512,
+		ssa.OpAMD64VPCMPUBMasked128,
+		ssa.OpAMD64VPCMPUBMasked256,
+		ssa.OpAMD64VPCMPUBMasked512,
+		ssa.OpAMD64VPCMPUWMasked128,
+		ssa.OpAMD64VPCMPUWMasked256,
+		ssa.OpAMD64VPCMPUWMasked512,
+		ssa.OpAMD64VPCMPUDMasked128,
+		ssa.OpAMD64VPCMPUDMasked256,
+		ssa.OpAMD64VPCMPUDMasked512,
+		ssa.OpAMD64VPCMPUQMasked128,
+		ssa.OpAMD64VPCMPUQMasked256,
+		ssa.OpAMD64VPCMPUQMasked512:
+		p = simdV2kkImm8(s, v)
+
+	case ssa.OpAMD64VFMADD213PS128,
+		ssa.OpAMD64VFMADD213PS256,
+		ssa.OpAMD64VFMADD213PS512,
+		ssa.OpAMD64VFMADD213PD128,
+		ssa.OpAMD64VFMADD213PD256,
+		ssa.OpAMD64VFMADD213PD512,
+		ssa.OpAMD64VFMADDSUB213PS128,
+		ssa.OpAMD64VFMADDSUB213PS256,
+		ssa.OpAMD64VFMADDSUB213PS512,
+		ssa.OpAMD64VFMADDSUB213PD128,
+		ssa.OpAMD64VFMADDSUB213PD256,
+		ssa.OpAMD64VFMADDSUB213PD512,
+		ssa.OpAMD64VFMSUBADD213PS128,
+		ssa.OpAMD64VFMSUBADD213PS256,
+		ssa.OpAMD64VFMSUBADD213PS512,
+		ssa.OpAMD64VFMSUBADD213PD128,
+		ssa.OpAMD64VFMSUBADD213PD256,
+		ssa.OpAMD64VFMSUBADD213PD512,
+		ssa.OpAMD64VPDPWSSD128,
+		ssa.OpAMD64VPDPWSSD256,
+		ssa.OpAMD64VPDPWSSD512,
+		ssa.OpAMD64VPERMI2B128,
+		ssa.OpAMD64VPERMI2B256,
+		ssa.OpAMD64VPERMI2B512,
+		ssa.OpAMD64VPERMI2W128,
+		ssa.OpAMD64VPERMI2W256,
+		ssa.OpAMD64VPERMI2W512,
+		ssa.OpAMD64VPERMI2PS128,
+		ssa.OpAMD64VPERMI2D128,
+		ssa.OpAMD64VPERMI2PS256,
+		ssa.OpAMD64VPERMI2D256,
+		ssa.OpAMD64VPERMI2PS512,
+		ssa.OpAMD64VPERMI2D512,
+		ssa.OpAMD64VPERMI2PD128,
+		ssa.OpAMD64VPERMI2Q128,
+		ssa.OpAMD64VPERMI2PD256,
+		ssa.OpAMD64VPERMI2Q256,
+		ssa.OpAMD64VPERMI2PD512,
+		ssa.OpAMD64VPERMI2Q512,
+		ssa.OpAMD64VPDPWSSDS128,
+		ssa.OpAMD64VPDPWSSDS256,
+		ssa.OpAMD64VPDPWSSDS512,
+		ssa.OpAMD64VPDPBUSDS128,
+		ssa.OpAMD64VPDPBUSDS256,
+		ssa.OpAMD64VPDPBUSDS512,
+		ssa.OpAMD64VPSHLDVW128,
+		ssa.OpAMD64VPSHLDVW256,
+		ssa.OpAMD64VPSHLDVW512,
+		ssa.OpAMD64VPSHLDVD128,
+		ssa.OpAMD64VPSHLDVD256,
+		ssa.OpAMD64VPSHLDVD512,
+		ssa.OpAMD64VPSHLDVQ128,
+		ssa.OpAMD64VPSHLDVQ256,
+		ssa.OpAMD64VPSHLDVQ512,
+		ssa.OpAMD64VPSHRDVW128,
+		ssa.OpAMD64VPSHRDVW256,
+		ssa.OpAMD64VPSHRDVW512,
+		ssa.OpAMD64VPSHRDVD128,
+		ssa.OpAMD64VPSHRDVD256,
+		ssa.OpAMD64VPSHRDVD512,
+		ssa.OpAMD64VPSHRDVQ128,
+		ssa.OpAMD64VPSHRDVQ256,
+		ssa.OpAMD64VPSHRDVQ512,
+		ssa.OpAMD64VPDPBUSD128,
+		ssa.OpAMD64VPDPBUSD256,
+		ssa.OpAMD64VPDPBUSD512:
+		p = simdV31ResultInArg0(s, v)
+
+	case ssa.OpAMD64VFMADD213PSMasked128,
+		ssa.OpAMD64VFMADD213PSMasked256,
+		ssa.OpAMD64VFMADD213PSMasked512,
+		ssa.OpAMD64VFMADD213PDMasked128,
+		ssa.OpAMD64VFMADD213PDMasked256,
+		ssa.OpAMD64VFMADD213PDMasked512,
+		ssa.OpAMD64VFMADDSUB213PSMasked128,
+		ssa.OpAMD64VFMADDSUB213PSMasked256,
+		ssa.OpAMD64VFMADDSUB213PSMasked512,
+		ssa.OpAMD64VFMADDSUB213PDMasked128,
+		ssa.OpAMD64VFMADDSUB213PDMasked256,
+		ssa.OpAMD64VFMADDSUB213PDMasked512,
+		ssa.OpAMD64VFMSUBADD213PSMasked128,
+		ssa.OpAMD64VFMSUBADD213PSMasked256,
+		ssa.OpAMD64VFMSUBADD213PSMasked512,
+		ssa.OpAMD64VFMSUBADD213PDMasked128,
+		ssa.OpAMD64VFMSUBADD213PDMasked256,
+		ssa.OpAMD64VFMSUBADD213PDMasked512,
+		ssa.OpAMD64VPDPWSSDMasked128,
+		ssa.OpAMD64VPDPWSSDMasked256,
+		ssa.OpAMD64VPDPWSSDMasked512,
+		ssa.OpAMD64VPERMI2BMasked128,
+		ssa.OpAMD64VPERMI2BMasked256,
+		ssa.OpAMD64VPERMI2BMasked512,
+		ssa.OpAMD64VPERMI2WMasked128,
+		ssa.OpAMD64VPERMI2WMasked256,
+		ssa.OpAMD64VPERMI2WMasked512,
+		ssa.OpAMD64VPERMI2PSMasked128,
+		ssa.OpAMD64VPERMI2DMasked128,
+		ssa.OpAMD64VPERMI2PSMasked256,
+		ssa.OpAMD64VPERMI2DMasked256,
+		ssa.OpAMD64VPERMI2PSMasked512,
+		ssa.OpAMD64VPERMI2DMasked512,
+		ssa.OpAMD64VPERMI2PDMasked128,
+		ssa.OpAMD64VPERMI2QMasked128,
+		ssa.OpAMD64VPERMI2PDMasked256,
+		ssa.OpAMD64VPERMI2QMasked256,
+		ssa.OpAMD64VPERMI2PDMasked512,
+		ssa.OpAMD64VPERMI2QMasked512,
+		ssa.OpAMD64VPDPWSSDSMasked128,
+		ssa.OpAMD64VPDPWSSDSMasked256,
+		ssa.OpAMD64VPDPWSSDSMasked512,
+		ssa.OpAMD64VPDPBUSDSMasked128,
+		ssa.OpAMD64VPDPBUSDSMasked256,
+		ssa.OpAMD64VPDPBUSDSMasked512,
+		ssa.OpAMD64VPSHLDVWMasked128,
+		ssa.OpAMD64VPSHLDVWMasked256,
+		ssa.OpAMD64VPSHLDVWMasked512,
+		ssa.OpAMD64VPSHLDVDMasked128,
+		ssa.OpAMD64VPSHLDVDMasked256,
+		ssa.OpAMD64VPSHLDVDMasked512,
+		ssa.OpAMD64VPSHLDVQMasked128,
+		ssa.OpAMD64VPSHLDVQMasked256,
+		ssa.OpAMD64VPSHLDVQMasked512,
+		ssa.OpAMD64VPSHRDVWMasked128,
+		ssa.OpAMD64VPSHRDVWMasked256,
+		ssa.OpAMD64VPSHRDVWMasked512,
+		ssa.OpAMD64VPSHRDVDMasked128,
+		ssa.OpAMD64VPSHRDVDMasked256,
+		ssa.OpAMD64VPSHRDVDMasked512,
+		ssa.OpAMD64VPSHRDVQMasked128,
+		ssa.OpAMD64VPSHRDVQMasked256,
+		ssa.OpAMD64VPSHRDVQMasked512,
+		ssa.OpAMD64VPDPBUSDMasked128,
+		ssa.OpAMD64VPDPBUSDMasked256,
+		ssa.OpAMD64VPDPBUSDMasked512:
+		p = simdV3kvResultInArg0(s, v)
+
+	case ssa.OpAMD64VPSLLW128,
+		ssa.OpAMD64VPSLLW256,
+		ssa.OpAMD64VPSLLW512,
+		ssa.OpAMD64VPSLLD128,
+		ssa.OpAMD64VPSLLD256,
+		ssa.OpAMD64VPSLLD512,
+		ssa.OpAMD64VPSLLQ128,
+		ssa.OpAMD64VPSLLQ256,
+		ssa.OpAMD64VPSLLQ512,
+		ssa.OpAMD64VPSRAW128,
+		ssa.OpAMD64VPSRAW256,
+		ssa.OpAMD64VPSRAW512,
+		ssa.OpAMD64VPSRAD128,
+		ssa.OpAMD64VPSRAD256,
+		ssa.OpAMD64VPSRAD512,
+		ssa.OpAMD64VPSRAQ128,
+		ssa.OpAMD64VPSRAQ256,
+		ssa.OpAMD64VPSRAQ512,
+		ssa.OpAMD64VPSRLW128,
+		ssa.OpAMD64VPSRLW256,
+		ssa.OpAMD64VPSRLW512,
+		ssa.OpAMD64VPSRLD128,
+		ssa.OpAMD64VPSRLD256,
+		ssa.OpAMD64VPSRLD512,
+		ssa.OpAMD64VPSRLQ128,
+		ssa.OpAMD64VPSRLQ256,
+		ssa.OpAMD64VPSRLQ512:
+		p = simdVfpv(s, v)
+
+	case ssa.OpAMD64VPSLLWMasked128,
+		ssa.OpAMD64VPSLLWMasked256,
+		ssa.OpAMD64VPSLLWMasked512,
+		ssa.OpAMD64VPSLLDMasked128,
+		ssa.OpAMD64VPSLLDMasked256,
+		ssa.OpAMD64VPSLLDMasked512,
+		ssa.OpAMD64VPSLLQMasked128,
+		ssa.OpAMD64VPSLLQMasked256,
+		ssa.OpAMD64VPSLLQMasked512,
+		ssa.OpAMD64VPSRAWMasked128,
+		ssa.OpAMD64VPSRAWMasked256,
+		ssa.OpAMD64VPSRAWMasked512,
+		ssa.OpAMD64VPSRADMasked128,
+		ssa.OpAMD64VPSRADMasked256,
+		ssa.OpAMD64VPSRADMasked512,
+		ssa.OpAMD64VPSRAQMasked128,
+		ssa.OpAMD64VPSRAQMasked256,
+		ssa.OpAMD64VPSRAQMasked512,
+		ssa.OpAMD64VPSRLWMasked128,
+		ssa.OpAMD64VPSRLWMasked256,
+		ssa.OpAMD64VPSRLWMasked512,
+		ssa.OpAMD64VPSRLDMasked128,
+		ssa.OpAMD64VPSRLDMasked256,
+		ssa.OpAMD64VPSRLDMasked512,
+		ssa.OpAMD64VPSRLQMasked128,
+		ssa.OpAMD64VPSRLQMasked256,
+		ssa.OpAMD64VPSRLQMasked512:
+		p = simdVfpkv(s, v)
+
+	case ssa.OpAMD64VPINSRB128,
+		ssa.OpAMD64VPINSRW128,
+		ssa.OpAMD64VPINSRD128,
+		ssa.OpAMD64VPINSRQ128:
+		p = simdVgpvImm8(s, v)
+
+	case ssa.OpAMD64VPEXTRB128,
+		ssa.OpAMD64VPEXTRW128,
+		ssa.OpAMD64VPEXTRD128,
+		ssa.OpAMD64VPEXTRQ128:
+		p = simdVgpImm8(s, v)
+
+	case ssa.OpAMD64VGF2P8AFFINEINVQBMasked128,
+		ssa.OpAMD64VGF2P8AFFINEINVQBMasked256,
+		ssa.OpAMD64VGF2P8AFFINEINVQBMasked512,
+		ssa.OpAMD64VGF2P8AFFINEQBMasked128,
+		ssa.OpAMD64VGF2P8AFFINEQBMasked256,
+		ssa.OpAMD64VGF2P8AFFINEQBMasked512,
+		ssa.OpAMD64VPSHLDWMasked128,
+		ssa.OpAMD64VPSHLDWMasked256,
+		ssa.OpAMD64VPSHLDWMasked512,
+		ssa.OpAMD64VPSHLDDMasked128,
+		ssa.OpAMD64VPSHLDDMasked256,
+		ssa.OpAMD64VPSHLDDMasked512,
+		ssa.OpAMD64VPSHLDQMasked128,
+		ssa.OpAMD64VPSHLDQMasked256,
+		ssa.OpAMD64VPSHLDQMasked512,
+		ssa.OpAMD64VPSHRDWMasked128,
+		ssa.OpAMD64VPSHRDWMasked256,
+		ssa.OpAMD64VPSHRDWMasked512,
+		ssa.OpAMD64VPSHRDDMasked128,
+		ssa.OpAMD64VPSHRDDMasked256,
+		ssa.OpAMD64VPSHRDDMasked512,
+		ssa.OpAMD64VPSHRDQMasked128,
+		ssa.OpAMD64VPSHRDQMasked256,
+		ssa.OpAMD64VPSHRDQMasked512:
+		p = simdV2kvImm8(s, v)
+
+	default:
+		// Unknown reg shape
+		return false
+	}
+
+	// Masked operation are always compiled with zeroing.
+	switch v.Op {
+	case ssa.OpAMD64VPABSBMasked128,
+		ssa.OpAMD64VPABSBMasked256,
+		ssa.OpAMD64VPABSBMasked512,
+		ssa.OpAMD64VPABSWMasked128,
+		ssa.OpAMD64VPABSWMasked256,
+		ssa.OpAMD64VPABSWMasked512,
+		ssa.OpAMD64VPABSDMasked128,
+		ssa.OpAMD64VPABSDMasked256,
+		ssa.OpAMD64VPABSDMasked512,
+		ssa.OpAMD64VPABSQMasked128,
+		ssa.OpAMD64VPABSQMasked256,
+		ssa.OpAMD64VPABSQMasked512,
+		ssa.OpAMD64VADDPSMasked128,
+		ssa.OpAMD64VADDPSMasked256,
+		ssa.OpAMD64VADDPSMasked512,
+		ssa.OpAMD64VADDPDMasked128,
+		ssa.OpAMD64VADDPDMasked256,
+		ssa.OpAMD64VADDPDMasked512,
+		ssa.OpAMD64VPADDBMasked128,
+		ssa.OpAMD64VPADDBMasked256,
+		ssa.OpAMD64VPADDBMasked512,
+		ssa.OpAMD64VPADDWMasked128,
+		ssa.OpAMD64VPADDWMasked256,
+		ssa.OpAMD64VPADDWMasked512,
+		ssa.OpAMD64VPADDDMasked128,
+		ssa.OpAMD64VPADDDMasked256,
+		ssa.OpAMD64VPADDDMasked512,
+		ssa.OpAMD64VPADDQMasked128,
+		ssa.OpAMD64VPADDQMasked256,
+		ssa.OpAMD64VPADDQMasked512,
+		ssa.OpAMD64VPANDDMasked128,
+		ssa.OpAMD64VPANDDMasked256,
+		ssa.OpAMD64VPANDDMasked512,
+		ssa.OpAMD64VPANDQMasked128,
+		ssa.OpAMD64VPANDQMasked256,
+		ssa.OpAMD64VPANDQMasked512,
+		ssa.OpAMD64VPANDNDMasked128,
+		ssa.OpAMD64VPANDNDMasked256,
+		ssa.OpAMD64VPANDNDMasked512,
+		ssa.OpAMD64VPANDNQMasked128,
+		ssa.OpAMD64VPANDNQMasked256,
+		ssa.OpAMD64VPANDNQMasked512,
+		ssa.OpAMD64VRCP14PSMasked128,
+		ssa.OpAMD64VRCP14PSMasked256,
+		ssa.OpAMD64VRCP14PSMasked512,
+		ssa.OpAMD64VRCP14PDMasked128,
+		ssa.OpAMD64VRCP14PDMasked256,
+		ssa.OpAMD64VRCP14PDMasked512,
+		ssa.OpAMD64VRSQRT14PSMasked128,
+		ssa.OpAMD64VRSQRT14PSMasked256,
+		ssa.OpAMD64VRSQRT14PSMasked512,
+		ssa.OpAMD64VRSQRT14PDMasked128,
+		ssa.OpAMD64VRSQRT14PDMasked256,
+		ssa.OpAMD64VRSQRT14PDMasked512,
+		ssa.OpAMD64VPAVGBMasked128,
+		ssa.OpAMD64VPAVGBMasked256,
+		ssa.OpAMD64VPAVGBMasked512,
+		ssa.OpAMD64VPAVGWMasked128,
+		ssa.OpAMD64VPAVGWMasked256,
+		ssa.OpAMD64VPAVGWMasked512,
+		ssa.OpAMD64VRNDSCALEPSMasked128,
+		ssa.OpAMD64VRNDSCALEPSMasked256,
+		ssa.OpAMD64VRNDSCALEPSMasked512,
+		ssa.OpAMD64VRNDSCALEPDMasked128,
+		ssa.OpAMD64VRNDSCALEPDMasked256,
+		ssa.OpAMD64VRNDSCALEPDMasked512,
+		ssa.OpAMD64VCOMPRESSPSMasked128,
+		ssa.OpAMD64VCOMPRESSPSMasked256,
+		ssa.OpAMD64VCOMPRESSPSMasked512,
+		ssa.OpAMD64VCOMPRESSPDMasked128,
+		ssa.OpAMD64VCOMPRESSPDMasked256,
+		ssa.OpAMD64VCOMPRESSPDMasked512,
+		ssa.OpAMD64VPCOMPRESSBMasked128,
+		ssa.OpAMD64VPCOMPRESSBMasked256,
+		ssa.OpAMD64VPCOMPRESSBMasked512,
+		ssa.OpAMD64VPCOMPRESSWMasked128,
+		ssa.OpAMD64VPCOMPRESSWMasked256,
+		ssa.OpAMD64VPCOMPRESSWMasked512,
+		ssa.OpAMD64VPCOMPRESSDMasked128,
+		ssa.OpAMD64VPCOMPRESSDMasked256,
+		ssa.OpAMD64VPCOMPRESSDMasked512,
+		ssa.OpAMD64VPCOMPRESSQMasked128,
+		ssa.OpAMD64VPCOMPRESSQMasked256,
+		ssa.OpAMD64VPCOMPRESSQMasked512,
+		ssa.OpAMD64VREDUCEPSMasked128,
+		ssa.OpAMD64VREDUCEPSMasked256,
+		ssa.OpAMD64VREDUCEPSMasked512,
+		ssa.OpAMD64VREDUCEPDMasked128,
+		ssa.OpAMD64VREDUCEPDMasked256,
+		ssa.OpAMD64VREDUCEPDMasked512,
+		ssa.OpAMD64VDIVPSMasked128,
+		ssa.OpAMD64VDIVPSMasked256,
+		ssa.OpAMD64VDIVPSMasked512,
+		ssa.OpAMD64VDIVPDMasked128,
+		ssa.OpAMD64VDIVPDMasked256,
+		ssa.OpAMD64VDIVPDMasked512,
+		ssa.OpAMD64VFMADD213PSMasked128,
+		ssa.OpAMD64VFMADD213PSMasked256,
+		ssa.OpAMD64VFMADD213PSMasked512,
+		ssa.OpAMD64VFMADD213PDMasked128,
+		ssa.OpAMD64VFMADD213PDMasked256,
+		ssa.OpAMD64VFMADD213PDMasked512,
+		ssa.OpAMD64VFMADDSUB213PSMasked128,
+		ssa.OpAMD64VFMADDSUB213PSMasked256,
+		ssa.OpAMD64VFMADDSUB213PSMasked512,
+		ssa.OpAMD64VFMADDSUB213PDMasked128,
+		ssa.OpAMD64VFMADDSUB213PDMasked256,
+		ssa.OpAMD64VFMADDSUB213PDMasked512,
+		ssa.OpAMD64VFMSUBADD213PSMasked128,
+		ssa.OpAMD64VFMSUBADD213PSMasked256,
+		ssa.OpAMD64VFMSUBADD213PSMasked512,
+		ssa.OpAMD64VFMSUBADD213PDMasked128,
+		ssa.OpAMD64VFMSUBADD213PDMasked256,
+		ssa.OpAMD64VFMSUBADD213PDMasked512,
+		ssa.OpAMD64VGF2P8AFFINEINVQBMasked128,
+		ssa.OpAMD64VGF2P8AFFINEINVQBMasked256,
+		ssa.OpAMD64VGF2P8AFFINEINVQBMasked512,
+		ssa.OpAMD64VGF2P8AFFINEQBMasked128,
+		ssa.OpAMD64VGF2P8AFFINEQBMasked256,
+		ssa.OpAMD64VGF2P8AFFINEQBMasked512,
+		ssa.OpAMD64VGF2P8MULBMasked128,
+		ssa.OpAMD64VGF2P8MULBMasked256,
+		ssa.OpAMD64VGF2P8MULBMasked512,
+		ssa.OpAMD64VMAXPSMasked128,
+		ssa.OpAMD64VMAXPSMasked256,
+		ssa.OpAMD64VMAXPSMasked512,
+		ssa.OpAMD64VMAXPDMasked128,
+		ssa.OpAMD64VMAXPDMasked256,
+		ssa.OpAMD64VMAXPDMasked512,
+		ssa.OpAMD64VPMAXSBMasked128,
+		ssa.OpAMD64VPMAXSBMasked256,
+		ssa.OpAMD64VPMAXSBMasked512,
+		ssa.OpAMD64VPMAXSWMasked128,
+		ssa.OpAMD64VPMAXSWMasked256,
+		ssa.OpAMD64VPMAXSWMasked512,
+		ssa.OpAMD64VPMAXSDMasked128,
+		ssa.OpAMD64VPMAXSDMasked256,
+		ssa.OpAMD64VPMAXSDMasked512,
+		ssa.OpAMD64VPMAXSQMasked128,
+		ssa.OpAMD64VPMAXSQMasked256,
+		ssa.OpAMD64VPMAXSQMasked512,
+		ssa.OpAMD64VPMAXUBMasked128,
+		ssa.OpAMD64VPMAXUBMasked256,
+		ssa.OpAMD64VPMAXUBMasked512,
+		ssa.OpAMD64VPMAXUWMasked128,
+		ssa.OpAMD64VPMAXUWMasked256,
+		ssa.OpAMD64VPMAXUWMasked512,
+		ssa.OpAMD64VPMAXUDMasked128,
+		ssa.OpAMD64VPMAXUDMasked256,
+		ssa.OpAMD64VPMAXUDMasked512,
+		ssa.OpAMD64VPMAXUQMasked128,
+		ssa.OpAMD64VPMAXUQMasked256,
+		ssa.OpAMD64VPMAXUQMasked512,
+		ssa.OpAMD64VMINPSMasked128,
+		ssa.OpAMD64VMINPSMasked256,
+		ssa.OpAMD64VMINPSMasked512,
+		ssa.OpAMD64VMINPDMasked128,
+		ssa.OpAMD64VMINPDMasked256,
+		ssa.OpAMD64VMINPDMasked512,
+		ssa.OpAMD64VPMINSBMasked128,
+		ssa.OpAMD64VPMINSBMasked256,
+		ssa.OpAMD64VPMINSBMasked512,
+		ssa.OpAMD64VPMINSWMasked128,
+		ssa.OpAMD64VPMINSWMasked256,
+		ssa.OpAMD64VPMINSWMasked512,
+		ssa.OpAMD64VPMINSDMasked128,
+		ssa.OpAMD64VPMINSDMasked256,
+		ssa.OpAMD64VPMINSDMasked512,
+		ssa.OpAMD64VPMINSQMasked128,
+		ssa.OpAMD64VPMINSQMasked256,
+		ssa.OpAMD64VPMINSQMasked512,
+		ssa.OpAMD64VPMINUBMasked128,
+		ssa.OpAMD64VPMINUBMasked256,
+		ssa.OpAMD64VPMINUBMasked512,
+		ssa.OpAMD64VPMINUWMasked128,
+		ssa.OpAMD64VPMINUWMasked256,
+		ssa.OpAMD64VPMINUWMasked512,
+		ssa.OpAMD64VPMINUDMasked128,
+		ssa.OpAMD64VPMINUDMasked256,
+		ssa.OpAMD64VPMINUDMasked512,
+		ssa.OpAMD64VPMINUQMasked128,
+		ssa.OpAMD64VPMINUQMasked256,
+		ssa.OpAMD64VPMINUQMasked512,
+		ssa.OpAMD64VSCALEFPSMasked128,
+		ssa.OpAMD64VSCALEFPSMasked256,
+		ssa.OpAMD64VSCALEFPSMasked512,
+		ssa.OpAMD64VSCALEFPDMasked128,
+		ssa.OpAMD64VSCALEFPDMasked256,
+		ssa.OpAMD64VSCALEFPDMasked512,
+		ssa.OpAMD64VPMULDQMasked128,
+		ssa.OpAMD64VPMULDQMasked256,
+		ssa.OpAMD64VPMULDQMasked512,
+		ssa.OpAMD64VPMULUDQMasked128,
+		ssa.OpAMD64VPMULUDQMasked256,
+		ssa.OpAMD64VPMULUDQMasked512,
+		ssa.OpAMD64VPMULHWMasked128,
+		ssa.OpAMD64VPMULHWMasked256,
+		ssa.OpAMD64VPMULHWMasked512,
+		ssa.OpAMD64VPMULHUWMasked128,
+		ssa.OpAMD64VPMULHUWMasked256,
+		ssa.OpAMD64VPMULHUWMasked512,
+		ssa.OpAMD64VPMULLWMasked128,
+		ssa.OpAMD64VPMULLWMasked256,
+		ssa.OpAMD64VPMULLWMasked512,
+		ssa.OpAMD64VPMULLDMasked128,
+		ssa.OpAMD64VPMULLDMasked256,
+		ssa.OpAMD64VPMULLDMasked512,
+		ssa.OpAMD64VPMULLQMasked128,
+		ssa.OpAMD64VPMULLQMasked256,
+		ssa.OpAMD64VPMULLQMasked512,
+		ssa.OpAMD64VMULPSMasked128,
+		ssa.OpAMD64VMULPSMasked256,
+		ssa.OpAMD64VMULPSMasked512,
+		ssa.OpAMD64VMULPDMasked128,
+		ssa.OpAMD64VMULPDMasked256,
+		ssa.OpAMD64VMULPDMasked512,
+		ssa.OpAMD64VPORDMasked128,
+		ssa.OpAMD64VPORDMasked256,
+		ssa.OpAMD64VPORDMasked512,
+		ssa.OpAMD64VPORQMasked128,
+		ssa.OpAMD64VPORQMasked256,
+		ssa.OpAMD64VPORQMasked512,
+		ssa.OpAMD64VPDPWSSDMasked128,
+		ssa.OpAMD64VPDPWSSDMasked256,
+		ssa.OpAMD64VPDPWSSDMasked512,
+		ssa.OpAMD64VPMADDWDMasked128,
+		ssa.OpAMD64VPMADDWDMasked256,
+		ssa.OpAMD64VPMADDWDMasked512,
+		ssa.OpAMD64VPERMI2BMasked128,
+		ssa.OpAMD64VPERMI2BMasked256,
+		ssa.OpAMD64VPERMI2BMasked512,
+		ssa.OpAMD64VPERMI2WMasked128,
+		ssa.OpAMD64VPERMI2WMasked256,
+		ssa.OpAMD64VPERMI2WMasked512,
+		ssa.OpAMD64VPERMI2PSMasked128,
+		ssa.OpAMD64VPERMI2DMasked128,
+		ssa.OpAMD64VPERMI2PSMasked256,
+		ssa.OpAMD64VPERMI2DMasked256,
+		ssa.OpAMD64VPERMI2PSMasked512,
+		ssa.OpAMD64VPERMI2DMasked512,
+		ssa.OpAMD64VPERMI2PDMasked128,
+		ssa.OpAMD64VPERMI2QMasked128,
+		ssa.OpAMD64VPERMI2PDMasked256,
+		ssa.OpAMD64VPERMI2QMasked256,
+		ssa.OpAMD64VPERMI2PDMasked512,
+		ssa.OpAMD64VPERMI2QMasked512,
+		ssa.OpAMD64VPERMBMasked128,
+		ssa.OpAMD64VPERMBMasked256,
+		ssa.OpAMD64VPERMBMasked512,
+		ssa.OpAMD64VPERMWMasked128,
+		ssa.OpAMD64VPERMWMasked256,
+		ssa.OpAMD64VPERMWMasked512,
+		ssa.OpAMD64VPERMPSMasked256,
+		ssa.OpAMD64VPERMDMasked256,
+		ssa.OpAMD64VPERMPSMasked512,
+		ssa.OpAMD64VPERMDMasked512,
+		ssa.OpAMD64VPERMPDMasked256,
+		ssa.OpAMD64VPERMQMasked256,
+		ssa.OpAMD64VPERMPDMasked512,
+		ssa.OpAMD64VPERMQMasked512,
+		ssa.OpAMD64VPOPCNTBMasked128,
+		ssa.OpAMD64VPOPCNTBMasked256,
+		ssa.OpAMD64VPOPCNTBMasked512,
+		ssa.OpAMD64VPOPCNTWMasked128,
+		ssa.OpAMD64VPOPCNTWMasked256,
+		ssa.OpAMD64VPOPCNTWMasked512,
+		ssa.OpAMD64VPOPCNTDMasked128,
+		ssa.OpAMD64VPOPCNTDMasked256,
+		ssa.OpAMD64VPOPCNTDMasked512,
+		ssa.OpAMD64VPOPCNTQMasked128,
+		ssa.OpAMD64VPOPCNTQMasked256,
+		ssa.OpAMD64VPOPCNTQMasked512,
+		ssa.OpAMD64VPROLDMasked128,
+		ssa.OpAMD64VPROLDMasked256,
+		ssa.OpAMD64VPROLDMasked512,
+		ssa.OpAMD64VPROLQMasked128,
+		ssa.OpAMD64VPROLQMasked256,
+		ssa.OpAMD64VPROLQMasked512,
+		ssa.OpAMD64VPRORDMasked128,
+		ssa.OpAMD64VPRORDMasked256,
+		ssa.OpAMD64VPRORDMasked512,
+		ssa.OpAMD64VPRORQMasked128,
+		ssa.OpAMD64VPRORQMasked256,
+		ssa.OpAMD64VPRORQMasked512,
+		ssa.OpAMD64VPROLVDMasked128,
+		ssa.OpAMD64VPROLVDMasked256,
+		ssa.OpAMD64VPROLVDMasked512,
+		ssa.OpAMD64VPROLVQMasked128,
+		ssa.OpAMD64VPROLVQMasked256,
+		ssa.OpAMD64VPROLVQMasked512,
+		ssa.OpAMD64VPRORVDMasked128,
+		ssa.OpAMD64VPRORVDMasked256,
+		ssa.OpAMD64VPRORVDMasked512,
+		ssa.OpAMD64VPRORVQMasked128,
+		ssa.OpAMD64VPRORVQMasked256,
+		ssa.OpAMD64VPRORVQMasked512,
+		ssa.OpAMD64VPADDSBMasked128,
+		ssa.OpAMD64VPADDSBMasked256,
+		ssa.OpAMD64VPADDSBMasked512,
+		ssa.OpAMD64VPADDSWMasked128,
+		ssa.OpAMD64VPADDSWMasked256,
+		ssa.OpAMD64VPADDSWMasked512,
+		ssa.OpAMD64VPDPWSSDSMasked128,
+		ssa.OpAMD64VPDPWSSDSMasked256,
+		ssa.OpAMD64VPDPWSSDSMasked512,
+		ssa.OpAMD64VPSUBSBMasked128,
+		ssa.OpAMD64VPSUBSBMasked256,
+		ssa.OpAMD64VPSUBSBMasked512,
+		ssa.OpAMD64VPSUBSWMasked128,
+		ssa.OpAMD64VPSUBSWMasked256,
+		ssa.OpAMD64VPSUBSWMasked512,
+		ssa.OpAMD64VPMADDUBSWMasked128,
+		ssa.OpAMD64VPMADDUBSWMasked256,
+		ssa.OpAMD64VPMADDUBSWMasked512,
+		ssa.OpAMD64VPDPBUSDSMasked128,
+		ssa.OpAMD64VPDPBUSDSMasked256,
+		ssa.OpAMD64VPDPBUSDSMasked512,
+		ssa.OpAMD64VPSHLDWMasked128,
+		ssa.OpAMD64VPSHLDWMasked256,
+		ssa.OpAMD64VPSHLDWMasked512,
+		ssa.OpAMD64VPSHLDDMasked128,
+		ssa.OpAMD64VPSHLDDMasked256,
+		ssa.OpAMD64VPSHLDDMasked512,
+		ssa.OpAMD64VPSHLDQMasked128,
+		ssa.OpAMD64VPSHLDQMasked256,
+		ssa.OpAMD64VPSHLDQMasked512,
+		ssa.OpAMD64VPSLLWMasked128,
+		ssa.OpAMD64VPSLLWMasked256,
+		ssa.OpAMD64VPSLLWMasked512,
+		ssa.OpAMD64VPSLLDMasked128,
+		ssa.OpAMD64VPSLLDMasked256,
+		ssa.OpAMD64VPSLLDMasked512,
+		ssa.OpAMD64VPSLLQMasked128,
+		ssa.OpAMD64VPSLLQMasked256,
+		ssa.OpAMD64VPSLLQMasked512,
+		ssa.OpAMD64VPSHRDWMasked128,
+		ssa.OpAMD64VPSHRDWMasked256,
+		ssa.OpAMD64VPSHRDWMasked512,
+		ssa.OpAMD64VPSHRDDMasked128,
+		ssa.OpAMD64VPSHRDDMasked256,
+		ssa.OpAMD64VPSHRDDMasked512,
+		ssa.OpAMD64VPSHRDQMasked128,
+		ssa.OpAMD64VPSHRDQMasked256,
+		ssa.OpAMD64VPSHRDQMasked512,
+		ssa.OpAMD64VPSRAWMasked128,
+		ssa.OpAMD64VPSRAWMasked256,
+		ssa.OpAMD64VPSRAWMasked512,
+		ssa.OpAMD64VPSRADMasked128,
+		ssa.OpAMD64VPSRADMasked256,
+		ssa.OpAMD64VPSRADMasked512,
+		ssa.OpAMD64VPSRAQMasked128,
+		ssa.OpAMD64VPSRAQMasked256,
+		ssa.OpAMD64VPSRAQMasked512,
+		ssa.OpAMD64VPSRLWMasked128,
+		ssa.OpAMD64VPSRLWMasked256,
+		ssa.OpAMD64VPSRLWMasked512,
+		ssa.OpAMD64VPSRLDMasked128,
+		ssa.OpAMD64VPSRLDMasked256,
+		ssa.OpAMD64VPSRLDMasked512,
+		ssa.OpAMD64VPSRLQMasked128,
+		ssa.OpAMD64VPSRLQMasked256,
+		ssa.OpAMD64VPSRLQMasked512,
+		ssa.OpAMD64VPSHLDVWMasked128,
+		ssa.OpAMD64VPSHLDVWMasked256,
+		ssa.OpAMD64VPSHLDVWMasked512,
+		ssa.OpAMD64VPSHLDVDMasked128,
+		ssa.OpAMD64VPSHLDVDMasked256,
+		ssa.OpAMD64VPSHLDVDMasked512,
+		ssa.OpAMD64VPSHLDVQMasked128,
+		ssa.OpAMD64VPSHLDVQMasked256,
+		ssa.OpAMD64VPSHLDVQMasked512,
+		ssa.OpAMD64VPSLLVWMasked128,
+		ssa.OpAMD64VPSLLVWMasked256,
+		ssa.OpAMD64VPSLLVWMasked512,
+		ssa.OpAMD64VPSLLVDMasked128,
+		ssa.OpAMD64VPSLLVDMasked256,
+		ssa.OpAMD64VPSLLVDMasked512,
+		ssa.OpAMD64VPSLLVQMasked128,
+		ssa.OpAMD64VPSLLVQMasked256,
+		ssa.OpAMD64VPSLLVQMasked512,
+		ssa.OpAMD64VPSHRDVWMasked128,
+		ssa.OpAMD64VPSHRDVWMasked256,
+		ssa.OpAMD64VPSHRDVWMasked512,
+		ssa.OpAMD64VPSHRDVDMasked128,
+		ssa.OpAMD64VPSHRDVDMasked256,
+		ssa.OpAMD64VPSHRDVDMasked512,
+		ssa.OpAMD64VPSHRDVQMasked128,
+		ssa.OpAMD64VPSHRDVQMasked256,
+		ssa.OpAMD64VPSHRDVQMasked512,
+		ssa.OpAMD64VPSRAVWMasked128,
+		ssa.OpAMD64VPSRAVWMasked256,
+		ssa.OpAMD64VPSRAVWMasked512,
+		ssa.OpAMD64VPSRAVDMasked128,
+		ssa.OpAMD64VPSRAVDMasked256,
+		ssa.OpAMD64VPSRAVDMasked512,
+		ssa.OpAMD64VPSRAVQMasked128,
+		ssa.OpAMD64VPSRAVQMasked256,
+		ssa.OpAMD64VPSRAVQMasked512,
+		ssa.OpAMD64VPSRLVWMasked128,
+		ssa.OpAMD64VPSRLVWMasked256,
+		ssa.OpAMD64VPSRLVWMasked512,
+		ssa.OpAMD64VPSRLVDMasked128,
+		ssa.OpAMD64VPSRLVDMasked256,
+		ssa.OpAMD64VPSRLVDMasked512,
+		ssa.OpAMD64VPSRLVQMasked128,
+		ssa.OpAMD64VPSRLVQMasked256,
+		ssa.OpAMD64VPSRLVQMasked512,
+		ssa.OpAMD64VSQRTPSMasked128,
+		ssa.OpAMD64VSQRTPSMasked256,
+		ssa.OpAMD64VSQRTPSMasked512,
+		ssa.OpAMD64VSQRTPDMasked128,
+		ssa.OpAMD64VSQRTPDMasked256,
+		ssa.OpAMD64VSQRTPDMasked512,
+		ssa.OpAMD64VSUBPSMasked128,
+		ssa.OpAMD64VSUBPSMasked256,
+		ssa.OpAMD64VSUBPSMasked512,
+		ssa.OpAMD64VSUBPDMasked128,
+		ssa.OpAMD64VSUBPDMasked256,
+		ssa.OpAMD64VSUBPDMasked512,
+		ssa.OpAMD64VPSUBBMasked128,
+		ssa.OpAMD64VPSUBBMasked256,
+		ssa.OpAMD64VPSUBBMasked512,
+		ssa.OpAMD64VPSUBWMasked128,
+		ssa.OpAMD64VPSUBWMasked256,
+		ssa.OpAMD64VPSUBWMasked512,
+		ssa.OpAMD64VPSUBDMasked128,
+		ssa.OpAMD64VPSUBDMasked256,
+		ssa.OpAMD64VPSUBDMasked512,
+		ssa.OpAMD64VPSUBQMasked128,
+		ssa.OpAMD64VPSUBQMasked256,
+		ssa.OpAMD64VPSUBQMasked512,
+		ssa.OpAMD64VPDPBUSDMasked128,
+		ssa.OpAMD64VPDPBUSDMasked256,
+		ssa.OpAMD64VPDPBUSDMasked512,
+		ssa.OpAMD64VPXORDMasked128,
+		ssa.OpAMD64VPXORDMasked256,
+		ssa.OpAMD64VPXORDMasked512,
+		ssa.OpAMD64VPXORQMasked128,
+		ssa.OpAMD64VPXORQMasked256,
+		ssa.OpAMD64VPXORQMasked512:
+		x86.ParseSuffix(p, "Z")
+	}
+
+	return true
+}
diff --git a/src/cmd/compile/internal/amd64/ssa.go b/src/cmd/compile/internal/amd64/ssa.go
index 3af513773d3b2e..9c31b77e7031fb 100644
--- a/src/cmd/compile/internal/amd64/ssa.go
+++ b/src/cmd/compile/internal/amd64/ssa.go
@@ -67,6 +67,8 @@ func storeByType(t *types.Type) obj.As {
 		case 8:
 			return x86.AMOVSD
 		}
+	} else if t.IsSIMD() {
+		return simdMov(width)
 	} else {
 		switch width {
 		case 1:
@@ -92,6 +94,8 @@ func moveByType(t *types.Type) obj.As {
 		// There is no xmm->xmm move with 1 byte opcode,
 		// so use movups, which has 2 byte opcode.
 		return x86.AMOVUPS
+	} else if t.IsSIMD() {
+		return simdMov(t.Size())
 	} else {
 		switch t.Size() {
 		case 1:
@@ -1038,6 +1042,10 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
 		}
 		x := v.Args[0].Reg()
 		y := v.Reg()
+		if v.Type.IsSIMD() {
+			x = simdOrMaskReg(v.Args[0])
+			y = simdOrMaskReg(v)
+		}
 		if x != y {
 			opregreg(s, moveByType(v.Type), y, x)
 		}
@@ -1049,16 +1057,24 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
 		p := s.Prog(loadByType(v.Type))
 		ssagen.AddrAuto(&p.From, v.Args[0])
 		p.To.Type = obj.TYPE_REG
-		p.To.Reg = v.Reg()
+		r := v.Reg()
+		if v.Type.IsSIMD() {
+			r = simdOrMaskReg(v)
+		}
+		p.To.Reg = r
 
 	case ssa.OpStoreReg:
 		if v.Type.IsFlags() {
 			v.Fatalf("store flags not implemented: %v", v.LongString())
 			return
 		}
+		r := v.Args[0].Reg()
+		if v.Type.IsSIMD() {
+			r = simdOrMaskReg(v.Args[0])
+		}
 		p := s.Prog(storeByType(v.Type))
 		p.From.Type = obj.TYPE_REG
-		p.From.Reg = v.Args[0].Reg()
+		p.From.Reg = r
 		ssagen.AddrAuto(&p.To, v)
 	case ssa.OpAMD64LoweredHasCPUFeature:
 		p := s.Prog(x86.AMOVBLZX)
@@ -1426,9 +1442,346 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
 		p.From.Offset = int64(x)
 		p.To.Type = obj.TYPE_REG
 		p.To.Reg = v.Reg()
+
+	// XXX SIMD
+	// XXX may change depending on how we handle aliased registers
+	case ssa.OpAMD64VZEROUPPER, ssa.OpAMD64VZEROALL:
+		s.Prog(v.Op.Asm())
+	case ssa.OpAMD64Zero128, ssa.OpAMD64Zero256, ssa.OpAMD64Zero512:
+		p := s.Prog(v.Op.Asm())
+		p.From.Type = obj.TYPE_REG
+		p.From.Reg = simdReg(v)
+		p.AddRestSourceReg(simdReg(v))
+		p.To.Type = obj.TYPE_REG
+		p.To.Reg = simdReg(v)
+	case ssa.OpAMD64VPADDD4:
+		p := s.Prog(v.Op.Asm())
+		p.From.Type = obj.TYPE_REG
+		p.From.Reg = simdReg(v.Args[0])
+		p.AddRestSourceReg(simdReg(v.Args[1]))
+		p.To.Type = obj.TYPE_REG
+		p.To.Reg = simdReg(v)
+	case ssa.OpAMD64VMOVDQUload128, ssa.OpAMD64VMOVDQUload256, ssa.OpAMD64VMOVDQUload512:
+		p := s.Prog(v.Op.Asm())
+		p.From.Type = obj.TYPE_MEM
+		p.From.Reg = v.Args[0].Reg()
+		ssagen.AddAux(&p.From, v)
+		p.To.Type = obj.TYPE_REG
+		p.To.Reg = simdReg(v)
+	case ssa.OpAMD64VMOVDQUstore128, ssa.OpAMD64VMOVDQUstore256, ssa.OpAMD64VMOVDQUstore512:
+		p := s.Prog(v.Op.Asm())
+		p.From.Type = obj.TYPE_REG
+		p.From.Reg = simdReg(v.Args[1])
+		p.To.Type = obj.TYPE_MEM
+		p.To.Reg = v.Args[0].Reg()
+		ssagen.AddAux(&p.To, v)
+
+	case ssa.OpAMD64VPMOVMToVec8x16,
+		ssa.OpAMD64VPMOVMToVec8x32,
+		ssa.OpAMD64VPMOVMToVec8x64,
+		ssa.OpAMD64VPMOVMToVec16x8,
+		ssa.OpAMD64VPMOVMToVec16x16,
+		ssa.OpAMD64VPMOVMToVec16x32,
+		ssa.OpAMD64VPMOVMToVec32x4,
+		ssa.OpAMD64VPMOVMToVec32x8,
+		ssa.OpAMD64VPMOVMToVec32x16,
+		ssa.OpAMD64VPMOVMToVec64x2,
+		ssa.OpAMD64VPMOVMToVec64x4,
+		ssa.OpAMD64VPMOVMToVec64x8:
+		p := s.Prog(v.Op.Asm())
+		p.From.Type = obj.TYPE_REG
+		p.From.Reg = v.Args[0].Reg()
+		p.To.Type = obj.TYPE_REG
+		p.To.Reg = simdReg(v)
+
+	case ssa.OpAMD64VPMOVVec8x16ToM,
+		ssa.OpAMD64VPMOVVec8x32ToM,
+		ssa.OpAMD64VPMOVVec8x64ToM,
+		ssa.OpAMD64VPMOVVec16x8ToM,
+		ssa.OpAMD64VPMOVVec16x16ToM,
+		ssa.OpAMD64VPMOVVec16x32ToM,
+		ssa.OpAMD64VPMOVVec32x4ToM,
+		ssa.OpAMD64VPMOVVec32x8ToM,
+		ssa.OpAMD64VPMOVVec32x16ToM,
+		ssa.OpAMD64VPMOVVec64x2ToM,
+		ssa.OpAMD64VPMOVVec64x4ToM,
+		ssa.OpAMD64VPMOVVec64x8ToM:
+		p := s.Prog(v.Op.Asm())
+		p.From.Type = obj.TYPE_REG
+		p.From.Reg = simdReg(v.Args[0])
+		p.To.Type = obj.TYPE_REG
+		p.To.Reg = v.Reg()
+
 	default:
-		v.Fatalf("genValue not implemented: %s", v.LongString())
+		if !ssaGenSIMDValue(s, v) {
+			v.Fatalf("genValue not implemented: %s", v.LongString())
+		}
+	}
+}
+
+// Example instruction: VRSQRTPS X1, X1
+func simdV11(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	p.From.Type = obj.TYPE_REG
+	p.From.Reg = simdReg(v.Args[0])
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
+}
+
+// Example instruction: VPSUBD X1, X2, X3
+func simdV21(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	p.From.Type = obj.TYPE_REG
+	// Vector registers operands follows a right-to-left order.
+	// e.g. VPSUBD X1, X2, X3 means X3 = X2 - X1.
+	p.From.Reg = simdReg(v.Args[1])
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
+}
+
+// This function is to accustomize the shifts.
+// The 2nd arg is an XMM, and this function merely checks that.
+// Example instruction: VPSLLQ Z1, X1, Z2
+func simdVfpv(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	p.From.Type = obj.TYPE_REG
+	// Vector registers operands follows a right-to-left order.
+	// e.g. VPSUBD X1, X2, X3 means X3 = X2 - X1.
+	p.From.Reg = v.Args[1].Reg()
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
+}
+
+// Example instruction: VPCMPEQW Z26, Z30, K4
+func simdV2k(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	p.From.Type = obj.TYPE_REG
+	p.From.Reg = simdReg(v.Args[1])
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = maskReg(v)
+	return p
+}
+
+// Example instruction: VPMINUQ X21, X3, K3, X31
+func simdV2kv(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	p.From.Type = obj.TYPE_REG
+	p.From.Reg = simdReg(v.Args[1])
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	// These "simd*" series of functions assumes:
+	// Any "K" register that serves as the write-mask
+	// or "predicate" for "predicated AVX512 instructions"
+	// sits right at the end of the operand list.
+	// TODO: verify this assumption.
+	p.AddRestSourceReg(maskReg(v.Args[2]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
+}
+
+// This function is to accustomize the shifts.
+// The 2nd arg is an XMM, and this function merely checks that.
+// Example instruction: VPSLLQ Z1, X1, K1, Z2
+func simdVfpkv(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	p.From.Type = obj.TYPE_REG
+	p.From.Reg = v.Args[1].Reg()
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.AddRestSourceReg(maskReg(v.Args[2]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
+}
+
+// Example instruction: VPCMPEQW Z26, Z30, K1, K4
+func simdV2kk(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	p.From.Type = obj.TYPE_REG
+	p.From.Reg = simdReg(v.Args[1])
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.AddRestSourceReg(maskReg(v.Args[2]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = maskReg(v)
+	return p
+}
+
+// Example instruction: VPOPCNTB X14, K4, X16
+func simdVkv(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	p.From.Type = obj.TYPE_REG
+	p.From.Reg = simdReg(v.Args[0])
+	p.AddRestSourceReg(maskReg(v.Args[1]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
+}
+
+// Example instruction: VROUNDPD $7, X2, X2
+func simdV11Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	imm := v.AuxInt
+	if imm < 0 || imm > 255 {
+		v.Fatalf("Invalid source selection immediate")
+	}
+	p.From.Offset = imm
+	p.From.Type = obj.TYPE_CONST
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
+}
+
+// Example instruction: VREDUCEPD $126, X1, K3, X31
+func simdVkvImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	imm := v.AuxInt
+	if imm < 0 || imm > 255 {
+		v.Fatalf("Invalid source selection immediate")
+	}
+	p.From.Offset = imm
+	p.From.Type = obj.TYPE_CONST
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.AddRestSourceReg(maskReg(v.Args[1]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
+}
+
+// Example instruction: VCMPPS $7, X2, X9, X2
+func simdV21Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	imm := v.AuxInt
+	if imm < 0 || imm > 255 {
+		v.Fatalf("Invalid source selection immediate")
+	}
+	p.From.Offset = imm
+	p.From.Type = obj.TYPE_CONST
+	p.AddRestSourceReg(simdReg(v.Args[1]))
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
+}
+
+// Example instruction: VPINSRB $3, DX, X0, X0
+func simdVgpvImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	imm := v.AuxInt
+	if imm < 0 || imm > 255 {
+		v.Fatalf("Invalid source selection immediate")
 	}
+	p.From.Offset = imm
+	p.From.Type = obj.TYPE_CONST
+	p.AddRestSourceReg(v.Args[1].Reg())
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
+}
+
+// Example instruction: VPCMPD $1, Z1, Z2, K1
+func simdV2kImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	imm := v.AuxInt
+	if imm < 0 || imm > 255 {
+		v.Fatalf("Invalid source selection immediate")
+	}
+	p.From.Offset = imm
+	p.From.Type = obj.TYPE_CONST
+	p.AddRestSourceReg(simdReg(v.Args[1]))
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = maskReg(v)
+	return p
+}
+
+// Example instruction: VPCMPD $1, Z1, Z2, K2, K1
+func simdV2kkImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	imm := v.AuxInt
+	if imm < 0 || imm > 255 {
+		v.Fatalf("Invalid source selection immediate")
+	}
+	p.From.Offset = imm
+	p.From.Type = obj.TYPE_CONST
+	p.AddRestSourceReg(simdReg(v.Args[1]))
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.AddRestSourceReg(maskReg(v.Args[2]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = maskReg(v)
+	return p
+}
+
+func simdV2kvImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	return simdV2kkImm8(s, v)
+}
+
+// Example instruction: VFMADD213PD Z2, Z1, Z0
+func simdV31ResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	p.From.Type = obj.TYPE_REG
+	p.From.Reg = simdReg(v.Args[2])
+	p.AddRestSourceReg(simdReg(v.Args[1]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
+}
+
+// Example instruction: VFMADD213PD Z2, Z1, K1, Z0
+func simdV3kvResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	p.From.Type = obj.TYPE_REG
+	p.From.Reg = simdReg(v.Args[2])
+	p.AddRestSourceReg(simdReg(v.Args[1]))
+	p.AddRestSourceReg(maskReg(v.Args[3]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
+}
+
+func simdVgpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	imm := v.AuxInt
+	if imm < 0 || imm > 255 {
+		v.Fatalf("Invalid source selection immediate")
+	}
+	p.From.Offset = imm
+	p.From.Type = obj.TYPE_CONST
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = v.Reg()
+	return p
+}
+
+// Currently unused
+func simdV31(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	p.From.Type = obj.TYPE_REG
+	p.From.Reg = simdReg(v.Args[2])
+	p.AddRestSourceReg(simdReg(v.Args[1]))
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
+}
+
+// Currently unused
+func simdV3kv(s *ssagen.State, v *ssa.Value) *obj.Prog {
+	p := s.Prog(v.Op.Asm())
+	p.From.Type = obj.TYPE_REG
+	p.From.Reg = simdReg(v.Args[2])
+	p.AddRestSourceReg(simdReg(v.Args[1]))
+	p.AddRestSourceReg(simdReg(v.Args[0]))
+	p.AddRestSourceReg(maskReg(v.Args[3]))
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = simdReg(v)
+	return p
 }
 
 var blockJump = [...]struct {
@@ -1532,3 +1885,63 @@ func spillArgReg(pp *objw.Progs, p *obj.Prog, f *ssa.Func, t *types.Type, reg in
 	p.Pos = p.Pos.WithNotStmt()
 	return p
 }
+
+// XXX maybe make this part of v.Reg?
+// On the other hand, it is architecture-specific.
+func simdReg(v *ssa.Value) int16 {
+	t := v.Type
+	if !t.IsSIMD() {
+		base.Fatalf("simdReg: not a simd type; v=%s, b=b%d, f=%s", v.LongString(), v.Block.ID, v.Block.Func.Name)
+	}
+	switch t.Size() {
+	case 16:
+		return v.Reg()
+	case 32:
+		return v.Reg() + (x86.REG_Y0 - x86.REG_X0)
+	case 64:
+		return v.Reg() + (x86.REG_Z0 - x86.REG_X0)
+	}
+	panic("unreachable")
+}
+
+// XXX k mask
+func maskReg(v *ssa.Value) int16 {
+	t := v.Type
+	if !t.IsSIMD() {
+		base.Fatalf("maskReg: not a simd type; v=%s, b=b%d, f=%s", v.LongString(), v.Block.ID, v.Block.Func.Name)
+	}
+	switch t.Size() {
+	case 8:
+		return v.Reg()
+	}
+	panic("unreachable")
+}
+
+// XXX k mask + vec
+func simdOrMaskReg(v *ssa.Value) int16 {
+	t := v.Type
+	if t.Size() <= 8 {
+		return maskReg(v)
+	}
+	return simdReg(v)
+}
+
+// XXX this is used for shift operations only.
+// regalloc will issue OpCopy with incorrect type, but the assigned
+// register should be correct, and this function is merely checking
+// the sanity of this part.
+func simdCheckRegOnly(v *ssa.Value, regStart, regEnd int16) int16 {
+	if v.Reg() > regEnd || v.Reg() < regStart {
+		panic("simdCheckRegOnly: not the desired register")
+	}
+	return v.Reg()
+}
+
+func simdMov(width int64) obj.As {
+	if width >= 64 {
+		return x86.AVMOVDQU64
+	} else if width >= 16 {
+		return x86.AVMOVDQU
+	}
+	return x86.AKMOVQ
+}
diff --git a/src/cmd/compile/internal/base/print.go b/src/cmd/compile/internal/base/print.go
index 119f06fbc03351..9e3348c1ecca89 100644
--- a/src/cmd/compile/internal/base/print.go
+++ b/src/cmd/compile/internal/base/print.go
@@ -220,7 +220,7 @@ func FatalfAt(pos src.XPos, format string, args ...interface{}) {
 		fmt.Printf("\n")
 
 		// If this is a released compiler version, ask for a bug report.
-		if Debug.Panic == 0 && strings.HasPrefix(buildcfg.Version, "go") {
+		if Debug.Panic == 0 && strings.HasPrefix(buildcfg.Version, "go") && !strings.Contains(buildcfg.Version, "devel") {
 			fmt.Printf("\n")
 			fmt.Printf("Please file a bug report including a short program that triggers the error.\n")
 			fmt.Printf("https://go.dev/issue/new\n")
diff --git a/src/cmd/compile/internal/gc/compile.go b/src/cmd/compile/internal/gc/compile.go
index 1a40df9a84ff04..1eb4b8cc37c30c 100644
--- a/src/cmd/compile/internal/gc/compile.go
+++ b/src/cmd/compile/internal/gc/compile.go
@@ -29,7 +29,7 @@ var (
 	compilequeue []*ir.Func // functions waiting to be compiled
 )
 
-func enqueueFunc(fn *ir.Func) {
+func enqueueFunc(fn *ir.Func, symABIs *ssagen.SymABIs) {
 	if ir.CurFunc != nil {
 		base.FatalfAt(fn.Pos(), "enqueueFunc %v inside %v", fn, ir.CurFunc)
 	}
@@ -49,22 +49,30 @@ func enqueueFunc(fn *ir.Func) {
 	}
 
 	if len(fn.Body) == 0 {
-		// Initialize ABI wrappers if necessary.
-		ir.InitLSym(fn, false)
-		types.CalcSize(fn.Type())
-		a := ssagen.AbiForBodylessFuncStackMap(fn)
-		abiInfo := a.ABIAnalyzeFuncType(fn.Type()) // abiInfo has spill/home locations for wrapper
-		if fn.ABI == obj.ABI0 {
-			// The current args_stackmap generation assumes the function
-			// is ABI0, and only ABI0 assembly function can have a FUNCDATA
-			// reference to args_stackmap (see cmd/internal/obj/plist.go:Flushplist).
-			// So avoid introducing an args_stackmap if the func is not ABI0.
-			liveness.WriteFuncMap(fn, abiInfo)
-
-			x := ssagen.EmitArgInfo(fn, abiInfo)
-			objw.Global(x, int32(len(x.P)), obj.RODATA|obj.LOCAL)
+		if ir.IsIntrinsicSym(fn.Sym()) && fn.Sym().Linkname == "" && !symABIs.HasDef(fn.Sym()) {
+			// Generate the function body for a bodyless intrinsic, in case it
+			// is used in a non-call context (e.g. as a function pointer).
+			// We skip functions defined in assembly, or has a linkname (which
+			// could be defined in another package).
+			ssagen.GenIntrinsicBody(fn)
+		} else {
+			// Initialize ABI wrappers if necessary.
+			ir.InitLSym(fn, false)
+			types.CalcSize(fn.Type())
+			a := ssagen.AbiForBodylessFuncStackMap(fn)
+			abiInfo := a.ABIAnalyzeFuncType(fn.Type()) // abiInfo has spill/home locations for wrapper
+			if fn.ABI == obj.ABI0 {
+				// The current args_stackmap generation assumes the function
+				// is ABI0, and only ABI0 assembly function can have a FUNCDATA
+				// reference to args_stackmap (see cmd/internal/obj/plist.go:Flushplist).
+				// So avoid introducing an args_stackmap if the func is not ABI0.
+				liveness.WriteFuncMap(fn, abiInfo)
+
+				x := ssagen.EmitArgInfo(fn, abiInfo)
+				objw.Global(x, int32(len(x.P)), obj.RODATA|obj.LOCAL)
+			}
+			return
 		}
-		return
 	}
 
 	errorsBefore := base.Errors()
diff --git a/src/cmd/compile/internal/gc/main.go b/src/cmd/compile/internal/gc/main.go
index 253ec3257a1a3b..20899df04ddd3d 100644
--- a/src/cmd/compile/internal/gc/main.go
+++ b/src/cmd/compile/internal/gc/main.go
@@ -188,9 +188,9 @@ func Main(archInit func(*ssagen.ArchInfo)) {
 
 	ir.EscFmt = escape.Fmt
 	ir.IsIntrinsicCall = ssagen.IsIntrinsicCall
+	ir.IsIntrinsicSym = ssagen.IsIntrinsicSym
 	inline.SSADumpInline = ssagen.DumpInline
 	ssagen.InitEnv()
-	ssagen.InitTables()
 
 	types.PtrSize = ssagen.Arch.LinkArch.PtrSize
 	types.RegSize = ssagen.Arch.LinkArch.RegSize
@@ -204,6 +204,11 @@ func Main(archInit func(*ssagen.ArchInfo)) {
 	typecheck.InitRuntime()
 	rttype.Init()
 
+	// Some intrinsics (notably, the simd intrinsics) mention
+	// types "eagerly", thus ssagen must be initialized AFTER
+	// the type system is ready.
+	ssagen.InitTables()
+
 	// Parse and typecheck input.
 	noder.LoadPackage(flag.Args())
 
@@ -304,7 +309,7 @@ func Main(archInit func(*ssagen.ArchInfo)) {
 		}
 
 		if nextFunc < len(typecheck.Target.Funcs) {
-			enqueueFunc(typecheck.Target.Funcs[nextFunc])
+			enqueueFunc(typecheck.Target.Funcs[nextFunc], symABIs)
 			nextFunc++
 			continue
 		}
diff --git a/src/cmd/compile/internal/ir/expr.go b/src/cmd/compile/internal/ir/expr.go
index 702adfdd84ef5e..e27e4336c973ff 100644
--- a/src/cmd/compile/internal/ir/expr.go
+++ b/src/cmd/compile/internal/ir/expr.go
@@ -1022,6 +1022,9 @@ func StaticCalleeName(n Node) *Name {
 // IsIntrinsicCall reports whether the compiler back end will treat the call as an intrinsic operation.
 var IsIntrinsicCall = func(*CallExpr) bool { return false }
 
+// IsIntrinsicSym reports whether the compiler back end will treat a call to this symbol as an intrinsic operation.
+var IsIntrinsicSym = func(*types.Sym) bool { return false }
+
 // SameSafeExpr checks whether it is safe to reuse one of l and r
 // instead of computing both. SameSafeExpr assumes that l and r are
 // used in the same statement or expression. In order for it to be
@@ -1140,6 +1143,14 @@ func ParamNames(ft *types.Type) []Node {
 	return args
 }
 
+func RecvParamNames(ft *types.Type) []Node {
+	args := make([]Node, ft.NumRecvs()+ft.NumParams())
+	for i, f := range ft.RecvParams() {
+		args[i] = f.Nname.(*Name)
+	}
+	return args
+}
+
 // MethodSym returns the method symbol representing a method name
 // associated with a specific receiver type.
 //
diff --git a/src/cmd/compile/internal/liveness/plive.go b/src/cmd/compile/internal/liveness/plive.go
index 5a2a22ee8f5c82..b9d3030e96ab77 100644
--- a/src/cmd/compile/internal/liveness/plive.go
+++ b/src/cmd/compile/internal/liveness/plive.go
@@ -1534,6 +1534,9 @@ func isfat(t *types.Type) bool {
 			}
 			return true
 		case types.TSTRUCT:
+			if t.IsSIMD() {
+				return false
+			}
 			// Struct with 1 field, check if field is fat
 			if t.NumFields() == 1 {
 				return isfat(t.Field(0).Type)
diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64.rules b/src/cmd/compile/internal/ssa/_gen/AMD64.rules
index d55dfe70acc155..2972eae87d5479 100644
--- a/src/cmd/compile/internal/ssa/_gen/AMD64.rules
+++ b/src/cmd/compile/internal/ssa/_gen/AMD64.rules
@@ -1680,3 +1680,36 @@
 
 // If we don't use the flags any more, just use the standard op.
 (Select0 a:(ADD(Q|L)constflags [c] x)) && a.Uses == 1 => (ADD(Q|L)const [c] x)
+
+// XXX SIMD
+(Load <t> ptr mem) && t.Size() == 16 => (VMOVDQUload128 ptr mem)
+
+(Store {t} ptr val mem) && t.Size() == 16 => (VMOVDQUstore128 ptr val mem)
+
+(Load <t> ptr mem) && t.Size() == 32 => (VMOVDQUload256 ptr mem)
+
+(Store {t} ptr val mem) && t.Size() == 32 => (VMOVDQUstore256 ptr val mem)
+
+(Load <t> ptr mem) && t.Size() == 64 => (VMOVDQUload512 ptr mem)
+
+(Store {t} ptr val mem) && t.Size() == 64 => (VMOVDQUstore512 ptr val mem)
+
+(ZeroSIMD <t>) && t.Size() == 16 => (Zero128 <t>)
+(ZeroSIMD <t>) && t.Size() == 32 => (Zero256 <t>)
+(ZeroSIMD <t>) && t.Size() == 64 => (Zero512 <t>)
+
+(VPMOVVec8x16ToM (VPMOVMToVec8x16 x)) => x
+(VPMOVVec8x32ToM (VPMOVMToVec8x32 x)) => x
+(VPMOVVec8x64ToM (VPMOVMToVec8x64 x)) => x
+
+(VPMOVVec16x8ToM (VPMOVMToVec16x8 x)) => x
+(VPMOVVec16x16ToM (VPMOVMToVec16x16 x)) => x
+(VPMOVVec16x32ToM (VPMOVMToVec16x32 x)) => x
+
+(VPMOVVec32x4ToM (VPMOVMToVec32x4 x)) => x
+(VPMOVVec32x8ToM (VPMOVMToVec32x8 x)) => x
+(VPMOVVec32x16ToM (VPMOVMToVec32x16 x)) => x
+
+(VPMOVVec64x2ToM (VPMOVMToVec64x2 x)) => x
+(VPMOVVec64x4ToM (VPMOVMToVec64x4 x)) => x
+(VPMOVVec64x8ToM (VPMOVMToVec64x8 x)) => x
diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
index 0f17843565276a..543233f4d831fe 100644
--- a/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
+++ b/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
@@ -62,7 +62,33 @@ var regNamesAMD64 = []string{
 	"X13",
 	"X14",
 	"X15", // constant 0 in ABIInternal
-
+	"X16",
+	"X17",
+	"X18",
+	"X19",
+	"X20",
+	"X21",
+	"X22",
+	"X23",
+	"X24",
+	"X25",
+	"X26",
+	"X27",
+	"X28",
+	"X29",
+	"X30",
+	"X31",
+
+	// TODO: update asyncPreempt for K registers.
+	// asyncPreempt also needs to store Z0-Z15 properly.
+	"K0",
+	"K1",
+	"K2",
+	"K3",
+	"K4",
+	"K5",
+	"K6",
+	"K7",
 	// If you add registers, update asyncPreempt in runtime
 
 	// pseudo-registers
@@ -99,7 +125,10 @@ func init() {
 		gp         = buildReg("AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15")
 		g          = buildReg("g")
 		fp         = buildReg("X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14")
+		v          = buildReg("X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14")
+		w          = buildReg("X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31")
 		x15        = buildReg("X15")
+		mask       = buildReg("K1 K2 K3 K4 K5 K6 K7")
 		gpsp       = gp | buildReg("SP")
 		gpspsb     = gpsp | buildReg("SB")
 		gpspsbg    = gpspsb | g
@@ -107,8 +136,11 @@ func init() {
 	)
 	// Common slices of register masks
 	var (
-		gponly = []regMask{gp}
-		fponly = []regMask{fp}
+		gponly   = []regMask{gp}
+		fponly   = []regMask{fp}
+		vonly    = []regMask{v}
+		wonly    = []regMask{w}
+		maskonly = []regMask{mask}
 	)
 
 	// Common regInfo
@@ -170,6 +202,38 @@ func init() {
 		fpstore    = regInfo{inputs: []regMask{gpspsb, fp, 0}}
 		fpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, fp, 0}}
 
+		v01   = regInfo{inputs: nil, outputs: vonly}
+		v11   = regInfo{inputs: vonly, outputs: vonly}
+		v21   = regInfo{inputs: []regMask{v, v}, outputs: vonly}
+		vk    = regInfo{inputs: vonly, outputs: maskonly}
+		kv    = regInfo{inputs: maskonly, outputs: vonly}
+		v2k   = regInfo{inputs: []regMask{v, v}, outputs: maskonly}
+		vkv   = regInfo{inputs: []regMask{v, mask}, outputs: vonly}
+		v2kv  = regInfo{inputs: []regMask{v, v, mask}, outputs: vonly}
+		v2kk  = regInfo{inputs: []regMask{v, v, mask}, outputs: maskonly}
+		v31   = regInfo{inputs: []regMask{v, v, v}, outputs: vonly}
+		v3kv  = regInfo{inputs: []regMask{v, v, v, mask}, outputs: vonly}
+		vgpv  = regInfo{inputs: []regMask{v, gp}, outputs: vonly}
+		vgp   = regInfo{inputs: vonly, outputs: gponly}
+		vfpv  = regInfo{inputs: []regMask{v, fp}, outputs: vonly}
+		vfpkv = regInfo{inputs: []regMask{v, fp, mask}, outputs: vonly}
+
+		w01   = regInfo{inputs: nil, outputs: wonly}
+		w11   = regInfo{inputs: wonly, outputs: wonly}
+		w21   = regInfo{inputs: []regMask{w, w}, outputs: wonly}
+		wk    = regInfo{inputs: wonly, outputs: maskonly}
+		kw    = regInfo{inputs: maskonly, outputs: wonly}
+		w2k   = regInfo{inputs: []regMask{fp, fp}, outputs: maskonly}
+		wkw   = regInfo{inputs: []regMask{fp, mask}, outputs: fponly}
+		w2kw  = regInfo{inputs: []regMask{fp, fp, mask}, outputs: fponly}
+		w2kk  = regInfo{inputs: []regMask{fp, fp, mask}, outputs: maskonly}
+		w31   = regInfo{inputs: []regMask{fp, fp, fp}, outputs: fponly}
+		w3kw  = regInfo{inputs: []regMask{fp, fp, fp, mask}, outputs: fponly}
+		wgpw  = regInfo{inputs: []regMask{fp, gp}, outputs: fponly}
+		wgp   = regInfo{inputs: wonly, outputs: gponly}
+		wfpw  = regInfo{inputs: []regMask{w, fp}, outputs: wonly}
+		wfpkw = regInfo{inputs: []regMask{w, fp, mask}, outputs: wonly}
+
 		prefreg = regInfo{inputs: []regMask{gpspsbg}}
 	)
 
@@ -1199,6 +1263,57 @@ func init() {
 		//
 		// output[i] = (input[i] >> 7) & 1
 		{name: "PMOVMSKB", argLength: 1, reg: fpgp, asm: "PMOVMSKB"},
+
+		// XXX SIMD
+		{name: "VPADDD4", argLength: 2, reg: fp21, asm: "VPADDD", commutative: true}, // arg0 + arg1
+
+		{name: "VMOVDQUload128", argLength: 2, reg: fpload, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"},    // load from arg0+auxint+aux, arg1 = mem
+		{name: "VMOVDQUstore128", argLength: 3, reg: fpstore, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg1, arg2 = mem
+
+		{name: "VMOVDQUload256", argLength: 2, reg: fpload, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"},    // load from arg0+auxint+aux, arg1 = mem
+		{name: "VMOVDQUstore256", argLength: 3, reg: fpstore, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg1, arg2 = mem
+
+		{name: "VMOVDQUload512", argLength: 2, reg: fpload, asm: "VMOVDQU64", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"},    // load from arg0+auxint+aux, arg1 = mem
+		{name: "VMOVDQUstore512", argLength: 3, reg: fpstore, asm: "VMOVDQU64", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg1, arg2 = mem
+
+		{name: "VPMOVMToVec8x16", argLength: 1, reg: kv, asm: "VPMOVM2B"},
+		{name: "VPMOVMToVec8x32", argLength: 1, reg: kv, asm: "VPMOVM2B"},
+		{name: "VPMOVMToVec8x64", argLength: 1, reg: kw, asm: "VPMOVM2B"},
+
+		{name: "VPMOVMToVec16x8", argLength: 1, reg: kv, asm: "VPMOVM2W"},
+		{name: "VPMOVMToVec16x16", argLength: 1, reg: kv, asm: "VPMOVM2W"},
+		{name: "VPMOVMToVec16x32", argLength: 1, reg: kw, asm: "VPMOVM2W"},
+
+		{name: "VPMOVMToVec32x4", argLength: 1, reg: kv, asm: "VPMOVM2D"},
+		{name: "VPMOVMToVec32x8", argLength: 1, reg: kv, asm: "VPMOVM2D"},
+		{name: "VPMOVMToVec32x16", argLength: 1, reg: kw, asm: "VPMOVM2D"},
+
+		{name: "VPMOVMToVec64x2", argLength: 1, reg: kv, asm: "VPMOVM2Q"},
+		{name: "VPMOVMToVec64x4", argLength: 1, reg: kv, asm: "VPMOVM2Q"},
+		{name: "VPMOVMToVec64x8", argLength: 1, reg: kw, asm: "VPMOVM2Q"},
+
+		{name: "VPMOVVec8x16ToM", argLength: 1, reg: vk, asm: "VPMOVB2M"},
+		{name: "VPMOVVec8x32ToM", argLength: 1, reg: vk, asm: "VPMOVB2M"},
+		{name: "VPMOVVec8x64ToM", argLength: 1, reg: wk, asm: "VPMOVB2M"},
+
+		{name: "VPMOVVec16x8ToM", argLength: 1, reg: vk, asm: "VPMOVW2M"},
+		{name: "VPMOVVec16x16ToM", argLength: 1, reg: vk, asm: "VPMOVW2M"},
+		{name: "VPMOVVec16x32ToM", argLength: 1, reg: wk, asm: "VPMOVW2M"},
+
+		{name: "VPMOVVec32x4ToM", argLength: 1, reg: vk, asm: "VPMOVD2M"},
+		{name: "VPMOVVec32x8ToM", argLength: 1, reg: vk, asm: "VPMOVD2M"},
+		{name: "VPMOVVec32x16ToM", argLength: 1, reg: wk, asm: "VPMOVD2M"},
+
+		{name: "VPMOVVec64x2ToM", argLength: 1, reg: vk, asm: "VPMOVQ2M"},
+		{name: "VPMOVVec64x4ToM", argLength: 1, reg: vk, asm: "VPMOVQ2M"},
+		{name: "VPMOVVec64x8ToM", argLength: 1, reg: wk, asm: "VPMOVQ2M"},
+
+		{name: "Zero128", argLength: 0, reg: v01, asm: "VPXOR"},
+		{name: "Zero256", argLength: 0, reg: v01, asm: "VPXOR"},
+		{name: "Zero512", argLength: 0, reg: w01, asm: "VPXORQ"},
+
+		{name: "VZEROUPPER", argLength: 0, asm: "VZEROUPPER"},
+		{name: "VZEROALL", argLength: 0, asm: "VZEROALL"},
 	}
 
 	var AMD64blocks = []blockData{
@@ -1230,14 +1345,15 @@ func init() {
 		name:               "AMD64",
 		pkg:                "cmd/internal/obj/x86",
 		genfile:            "../../amd64/ssa.go",
-		ops:                AMD64ops,
+		genSIMDfile:        "../../amd64/simdssa.go",
+		ops:                append(AMD64ops, simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vfpkv, w11, w21, w2k, wkw, w2kw, w2kk, w31, w3kw, wgpw, wgp, wfpw, wfpkw)...), // AMD64ops,
 		blocks:             AMD64blocks,
 		regnames:           regNamesAMD64,
 		ParamIntRegNames:   "AX BX CX DI SI R8 R9 R10 R11",
 		ParamFloatRegNames: "X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14",
 		gpregmask:          gp,
 		fpregmask:          fp,
-		specialregmask:     x15,
+		specialregmask:     x15 | mask,
 		framepointerreg:    int8(num["BP"]),
 		linkreg:            -1, // not used
 	})
diff --git a/src/cmd/compile/internal/ssa/_gen/generic.rules b/src/cmd/compile/internal/ssa/_gen/generic.rules
index b178a1add6de29..1077921f93400c 100644
--- a/src/cmd/compile/internal/ssa/_gen/generic.rules
+++ b/src/cmd/compile/internal/ssa/_gen/generic.rules
@@ -910,7 +910,7 @@
 
 // struct operations
 (StructSelect [i] x:(StructMake ___)) => x.Args[i]
-(Load <t> _ _) && t.IsStruct() && CanSSA(t) => rewriteStructLoad(v)
+(Load <t> _ _) && t.IsStruct() && CanSSA(t) && !t.IsSIMD() => rewriteStructLoad(v)
 (Store _ (StructMake ___) _) => rewriteStructStore(v)
 
 (StructSelect [i] x:(Load <t> ptr mem)) && !CanSSA(t) =>
diff --git a/src/cmd/compile/internal/ssa/_gen/genericOps.go b/src/cmd/compile/internal/ssa/_gen/genericOps.go
index 1f6ad4e16d98f8..2d44cc85f8242e 100644
--- a/src/cmd/compile/internal/ssa/_gen/genericOps.go
+++ b/src/cmd/compile/internal/ssa/_gen/genericOps.go
@@ -662,6 +662,10 @@ var genericOps = []opData{
 	// Prefetch instruction
 	{name: "PrefetchCache", argLength: 2, hasSideEffects: true},         // Do prefetch arg0 to cache. arg0=addr, arg1=memory.
 	{name: "PrefetchCacheStreamed", argLength: 2, hasSideEffects: true}, // Do non-temporal or streamed prefetch arg0 to cache. arg0=addr, arg1=memory.
+
+	// XXX SIMD
+	{name: "Add32x4", argLength: 2}, // arg0 + arg1
+	{name: "ZeroSIMD", argLength: 0},
 }
 
 //     kind          controls          successors   implicit exit
@@ -689,6 +693,7 @@ var genericBlocks = []blockData{
 }
 
 func init() {
+	genericOps = append(genericOps, simdGenericOps()...)
 	archs = append(archs, arch{
 		name:    "generic",
 		ops:     genericOps,
diff --git a/src/cmd/compile/internal/ssa/_gen/main.go b/src/cmd/compile/internal/ssa/_gen/main.go
index f20603245ba321..5b85cec79c0e93 100644
--- a/src/cmd/compile/internal/ssa/_gen/main.go
+++ b/src/cmd/compile/internal/ssa/_gen/main.go
@@ -32,6 +32,7 @@ type arch struct {
 	name               string
 	pkg                string // obj package to import for this arch.
 	genfile            string // source file containing opcode code generation.
+	genSIMDfile        string // source file containing opcode code generation for SIMD.
 	ops                []opData
 	blocks             []blockData
 	regnames           []string
@@ -537,6 +538,15 @@ func genOp() {
 		if err != nil {
 			log.Fatalf("can't read %s: %v", a.genfile, err)
 		}
+		// Append the file of simd operations, too
+		if a.genSIMDfile != "" {
+			simdSrc, err := os.ReadFile(a.genSIMDfile)
+			if err != nil {
+				log.Fatalf("can't read %s: %v", a.genSIMDfile, err)
+			}
+			src = append(src, simdSrc...)
+		}
+
 		seen := make(map[string]bool, len(a.ops))
 		for _, m := range rxOp.FindAllSubmatch(src, -1) {
 			seen[string(m[1])] = true
diff --git a/src/cmd/compile/internal/ssa/_gen/rulegen.go b/src/cmd/compile/internal/ssa/_gen/rulegen.go
index 3854d58b7f9e56..5e66398927793b 100644
--- a/src/cmd/compile/internal/ssa/_gen/rulegen.go
+++ b/src/cmd/compile/internal/ssa/_gen/rulegen.go
@@ -95,6 +95,7 @@ func genLateLowerRules(arch arch) { genRulesSuffix(arch, "latelower") }
 
 func genRulesSuffix(arch arch, suff string) {
 	// Open input file.
+	var text io.Reader
 	text, err := os.Open(arch.name + suff + ".rules")
 	if err != nil {
 		if suff == "" {
@@ -105,6 +106,14 @@ func genRulesSuffix(arch arch, suff string) {
 		return
 	}
 
+	// Check for file of SIMD rules to add
+	if suff == "" {
+		simdtext, err := os.Open("simd" + arch.name + ".rules")
+		if err == nil {
+			text = io.MultiReader(text, simdtext)
+		}
+	}
+
 	// oprules contains a list of rules for each block and opcode
 	blockrules := map[string][]Rule{}
 	oprules := map[string][]Rule{}
diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
new file mode 100644
index 00000000000000..e5f17bdb1b29dd
--- /dev/null
+++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
@@ -0,0 +1,1793 @@
+// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT.
+
+(AbsoluteInt8x16 ...) => (VPABSB128 ...)
+(AbsoluteInt8x32 ...) => (VPABSB256 ...)
+(AbsoluteInt8x64 ...) => (VPABSB512 ...)
+(AbsoluteInt16x8 ...) => (VPABSW128 ...)
+(AbsoluteInt16x16 ...) => (VPABSW256 ...)
+(AbsoluteInt16x32 ...) => (VPABSW512 ...)
+(AbsoluteInt32x4 ...) => (VPABSD128 ...)
+(AbsoluteInt32x8 ...) => (VPABSD256 ...)
+(AbsoluteInt32x16 ...) => (VPABSD512 ...)
+(AbsoluteInt64x2 ...) => (VPABSQ128 ...)
+(AbsoluteInt64x4 ...) => (VPABSQ256 ...)
+(AbsoluteInt64x8 ...) => (VPABSQ512 ...)
+(AbsoluteMaskedInt8x16 x mask) => (VPABSBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
+(AbsoluteMaskedInt8x32 x mask) => (VPABSBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
+(AbsoluteMaskedInt8x64 x mask) => (VPABSBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
+(AbsoluteMaskedInt16x8 x mask) => (VPABSWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
+(AbsoluteMaskedInt16x16 x mask) => (VPABSWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
+(AbsoluteMaskedInt16x32 x mask) => (VPABSWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
+(AbsoluteMaskedInt32x4 x mask) => (VPABSDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(AbsoluteMaskedInt32x8 x mask) => (VPABSDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(AbsoluteMaskedInt32x16 x mask) => (VPABSDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(AbsoluteMaskedInt64x2 x mask) => (VPABSQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(AbsoluteMaskedInt64x4 x mask) => (VPABSQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(AbsoluteMaskedInt64x8 x mask) => (VPABSQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(AddFloat32x4 ...) => (VADDPS128 ...)
+(AddFloat32x8 ...) => (VADDPS256 ...)
+(AddFloat32x16 ...) => (VADDPS512 ...)
+(AddFloat64x2 ...) => (VADDPD128 ...)
+(AddFloat64x4 ...) => (VADDPD256 ...)
+(AddFloat64x8 ...) => (VADDPD512 ...)
+(AddInt8x16 ...) => (VPADDB128 ...)
+(AddInt8x32 ...) => (VPADDB256 ...)
+(AddInt8x64 ...) => (VPADDB512 ...)
+(AddInt16x8 ...) => (VPADDW128 ...)
+(AddInt16x16 ...) => (VPADDW256 ...)
+(AddInt16x32 ...) => (VPADDW512 ...)
+(AddInt32x4 ...) => (VPADDD128 ...)
+(AddInt32x8 ...) => (VPADDD256 ...)
+(AddInt32x16 ...) => (VPADDD512 ...)
+(AddInt64x2 ...) => (VPADDQ128 ...)
+(AddInt64x4 ...) => (VPADDQ256 ...)
+(AddInt64x8 ...) => (VPADDQ512 ...)
+(AddUint8x16 ...) => (VPADDB128 ...)
+(AddUint8x32 ...) => (VPADDB256 ...)
+(AddUint8x64 ...) => (VPADDB512 ...)
+(AddUint16x8 ...) => (VPADDW128 ...)
+(AddUint16x16 ...) => (VPADDW256 ...)
+(AddUint16x32 ...) => (VPADDW512 ...)
+(AddUint32x4 ...) => (VPADDD128 ...)
+(AddUint32x8 ...) => (VPADDD256 ...)
+(AddUint32x16 ...) => (VPADDD512 ...)
+(AddUint64x2 ...) => (VPADDQ128 ...)
+(AddUint64x4 ...) => (VPADDQ256 ...)
+(AddUint64x8 ...) => (VPADDQ512 ...)
+(AddMaskedFloat32x4 x y mask) => (VADDPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(AddMaskedFloat32x8 x y mask) => (VADDPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(AddMaskedFloat32x16 x y mask) => (VADDPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(AddMaskedFloat64x2 x y mask) => (VADDPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(AddMaskedFloat64x4 x y mask) => (VADDPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(AddMaskedFloat64x8 x y mask) => (VADDPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(AddMaskedInt8x16 x y mask) => (VPADDBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(AddMaskedInt8x32 x y mask) => (VPADDBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(AddMaskedInt8x64 x y mask) => (VPADDBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(AddMaskedInt16x8 x y mask) => (VPADDWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(AddMaskedInt16x16 x y mask) => (VPADDWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(AddMaskedInt16x32 x y mask) => (VPADDWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(AddMaskedInt32x4 x y mask) => (VPADDDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(AddMaskedInt32x8 x y mask) => (VPADDDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(AddMaskedInt32x16 x y mask) => (VPADDDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(AddMaskedInt64x2 x y mask) => (VPADDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(AddMaskedInt64x4 x y mask) => (VPADDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(AddMaskedInt64x8 x y mask) => (VPADDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(AddMaskedUint8x16 x y mask) => (VPADDBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(AddMaskedUint8x32 x y mask) => (VPADDBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(AddMaskedUint8x64 x y mask) => (VPADDBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(AddMaskedUint16x8 x y mask) => (VPADDWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(AddMaskedUint16x16 x y mask) => (VPADDWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(AddMaskedUint16x32 x y mask) => (VPADDWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(AddMaskedUint32x4 x y mask) => (VPADDDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(AddMaskedUint32x8 x y mask) => (VPADDDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(AddMaskedUint32x16 x y mask) => (VPADDDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(AddMaskedUint64x2 x y mask) => (VPADDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(AddMaskedUint64x4 x y mask) => (VPADDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(AddMaskedUint64x8 x y mask) => (VPADDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(AddSubFloat32x4 ...) => (VADDSUBPS128 ...)
+(AddSubFloat32x8 ...) => (VADDSUBPS256 ...)
+(AddSubFloat64x2 ...) => (VADDSUBPD128 ...)
+(AddSubFloat64x4 ...) => (VADDSUBPD256 ...)
+(AndInt8x16 ...) => (VPAND128 ...)
+(AndInt8x32 ...) => (VPAND256 ...)
+(AndInt16x8 ...) => (VPAND128 ...)
+(AndInt16x16 ...) => (VPAND256 ...)
+(AndInt32x4 ...) => (VPAND128 ...)
+(AndInt32x8 ...) => (VPAND256 ...)
+(AndInt32x16 ...) => (VPANDD512 ...)
+(AndInt64x2 ...) => (VPAND128 ...)
+(AndInt64x4 ...) => (VPAND256 ...)
+(AndInt64x8 ...) => (VPANDQ512 ...)
+(AndUint8x16 ...) => (VPAND128 ...)
+(AndUint8x32 ...) => (VPAND256 ...)
+(AndUint16x8 ...) => (VPAND128 ...)
+(AndUint16x16 ...) => (VPAND256 ...)
+(AndUint32x4 ...) => (VPAND128 ...)
+(AndUint32x8 ...) => (VPAND256 ...)
+(AndUint32x16 ...) => (VPANDD512 ...)
+(AndUint64x2 ...) => (VPAND128 ...)
+(AndUint64x4 ...) => (VPAND256 ...)
+(AndUint64x8 ...) => (VPANDQ512 ...)
+(AndMaskedInt32x4 x y mask) => (VPANDDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(AndMaskedInt32x8 x y mask) => (VPANDDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(AndMaskedInt32x16 x y mask) => (VPANDDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(AndMaskedInt64x2 x y mask) => (VPANDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(AndMaskedInt64x4 x y mask) => (VPANDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(AndMaskedInt64x8 x y mask) => (VPANDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(AndMaskedUint32x4 x y mask) => (VPANDDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(AndMaskedUint32x8 x y mask) => (VPANDDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(AndMaskedUint32x16 x y mask) => (VPANDDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(AndMaskedUint64x2 x y mask) => (VPANDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(AndMaskedUint64x4 x y mask) => (VPANDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(AndMaskedUint64x8 x y mask) => (VPANDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(AndNotInt8x16 ...) => (VPANDN128 ...)
+(AndNotInt8x32 ...) => (VPANDN256 ...)
+(AndNotInt16x8 ...) => (VPANDN128 ...)
+(AndNotInt16x16 ...) => (VPANDN256 ...)
+(AndNotInt32x4 ...) => (VPANDN128 ...)
+(AndNotInt32x8 ...) => (VPANDN256 ...)
+(AndNotInt32x16 ...) => (VPANDND512 ...)
+(AndNotInt64x2 ...) => (VPANDN128 ...)
+(AndNotInt64x4 ...) => (VPANDN256 ...)
+(AndNotInt64x8 ...) => (VPANDNQ512 ...)
+(AndNotUint8x16 ...) => (VPANDN128 ...)
+(AndNotUint8x32 ...) => (VPANDN256 ...)
+(AndNotUint16x8 ...) => (VPANDN128 ...)
+(AndNotUint16x16 ...) => (VPANDN256 ...)
+(AndNotUint32x4 ...) => (VPANDN128 ...)
+(AndNotUint32x8 ...) => (VPANDN256 ...)
+(AndNotUint32x16 ...) => (VPANDND512 ...)
+(AndNotUint64x2 ...) => (VPANDN128 ...)
+(AndNotUint64x4 ...) => (VPANDN256 ...)
+(AndNotUint64x8 ...) => (VPANDNQ512 ...)
+(AndNotMaskedInt32x4 x y mask) => (VPANDNDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(AndNotMaskedInt32x8 x y mask) => (VPANDNDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(AndNotMaskedInt32x16 x y mask) => (VPANDNDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(AndNotMaskedInt64x2 x y mask) => (VPANDNQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(AndNotMaskedInt64x4 x y mask) => (VPANDNQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(AndNotMaskedInt64x8 x y mask) => (VPANDNQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(AndNotMaskedUint32x4 x y mask) => (VPANDNDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(AndNotMaskedUint32x8 x y mask) => (VPANDNDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(AndNotMaskedUint32x16 x y mask) => (VPANDNDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(AndNotMaskedUint64x2 x y mask) => (VPANDNQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(AndNotMaskedUint64x4 x y mask) => (VPANDNQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(AndNotMaskedUint64x8 x y mask) => (VPANDNQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ApproximateReciprocalFloat32x4 ...) => (VRCP14PS128 ...)
+(ApproximateReciprocalFloat32x8 ...) => (VRCP14PS256 ...)
+(ApproximateReciprocalFloat32x16 ...) => (VRCP14PS512 ...)
+(ApproximateReciprocalFloat64x2 ...) => (VRCP14PD128 ...)
+(ApproximateReciprocalFloat64x4 ...) => (VRCP14PD256 ...)
+(ApproximateReciprocalFloat64x8 ...) => (VRCP14PD512 ...)
+(ApproximateReciprocalMaskedFloat32x4 x mask) => (VRCP14PSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ApproximateReciprocalMaskedFloat32x8 x mask) => (VRCP14PSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ApproximateReciprocalMaskedFloat32x16 x mask) => (VRCP14PSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ApproximateReciprocalMaskedFloat64x2 x mask) => (VRCP14PDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ApproximateReciprocalMaskedFloat64x4 x mask) => (VRCP14PDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ApproximateReciprocalMaskedFloat64x8 x mask) => (VRCP14PDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ApproximateReciprocalOfSqrtFloat32x4 ...) => (VRSQRTPS128 ...)
+(ApproximateReciprocalOfSqrtFloat32x8 ...) => (VRSQRTPS256 ...)
+(ApproximateReciprocalOfSqrtFloat32x16 ...) => (VRSQRT14PS512 ...)
+(ApproximateReciprocalOfSqrtFloat64x2 ...) => (VRSQRT14PD128 ...)
+(ApproximateReciprocalOfSqrtFloat64x4 ...) => (VRSQRT14PD256 ...)
+(ApproximateReciprocalOfSqrtFloat64x8 ...) => (VRSQRT14PD512 ...)
+(ApproximateReciprocalOfSqrtMaskedFloat32x4 x mask) => (VRSQRT14PSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ApproximateReciprocalOfSqrtMaskedFloat32x8 x mask) => (VRSQRT14PSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ApproximateReciprocalOfSqrtMaskedFloat32x16 x mask) => (VRSQRT14PSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ApproximateReciprocalOfSqrtMaskedFloat64x2 x mask) => (VRSQRT14PDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ApproximateReciprocalOfSqrtMaskedFloat64x4 x mask) => (VRSQRT14PDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ApproximateReciprocalOfSqrtMaskedFloat64x8 x mask) => (VRSQRT14PDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(AverageUint8x16 ...) => (VPAVGB128 ...)
+(AverageUint8x32 ...) => (VPAVGB256 ...)
+(AverageUint8x64 ...) => (VPAVGB512 ...)
+(AverageUint16x8 ...) => (VPAVGW128 ...)
+(AverageUint16x16 ...) => (VPAVGW256 ...)
+(AverageUint16x32 ...) => (VPAVGW512 ...)
+(AverageMaskedUint8x16 x y mask) => (VPAVGBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(AverageMaskedUint8x32 x y mask) => (VPAVGBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(AverageMaskedUint8x64 x y mask) => (VPAVGBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(AverageMaskedUint16x8 x y mask) => (VPAVGWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(AverageMaskedUint16x16 x y mask) => (VPAVGWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(AverageMaskedUint16x32 x y mask) => (VPAVGWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(CeilFloat32x4 x) => (VROUNDPS128 [2] x)
+(CeilFloat32x8 x) => (VROUNDPS256 [2] x)
+(CeilFloat64x2 x) => (VROUNDPD128 [2] x)
+(CeilFloat64x4 x) => (VROUNDPD256 [2] x)
+(CeilWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+2] x)
+(CeilWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+2] x)
+(CeilWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+2] x)
+(CeilWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+2] x)
+(CeilWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+2] x)
+(CeilWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+2] x)
+(CeilWithPrecisionMaskedFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+2] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(CeilWithPrecisionMaskedFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+2] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(CeilWithPrecisionMaskedFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+2] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(CeilWithPrecisionMaskedFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+2] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(CeilWithPrecisionMaskedFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+2] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(CeilWithPrecisionMaskedFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+2] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(CompressFloat32x4 x mask) => (VCOMPRESSPSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(CompressFloat32x8 x mask) => (VCOMPRESSPSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(CompressFloat32x16 x mask) => (VCOMPRESSPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(CompressFloat64x2 x mask) => (VCOMPRESSPDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(CompressFloat64x4 x mask) => (VCOMPRESSPDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(CompressFloat64x8 x mask) => (VCOMPRESSPDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(CompressInt8x16 x mask) => (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
+(CompressInt8x32 x mask) => (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
+(CompressInt8x64 x mask) => (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
+(CompressInt16x8 x mask) => (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
+(CompressInt16x16 x mask) => (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
+(CompressInt16x32 x mask) => (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
+(CompressInt32x4 x mask) => (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(CompressInt32x8 x mask) => (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(CompressInt32x16 x mask) => (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(CompressInt64x2 x mask) => (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(CompressInt64x4 x mask) => (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(CompressInt64x8 x mask) => (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(CompressUint8x16 x mask) => (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
+(CompressUint8x32 x mask) => (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
+(CompressUint8x64 x mask) => (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
+(CompressUint16x8 x mask) => (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
+(CompressUint16x16 x mask) => (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
+(CompressUint16x32 x mask) => (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
+(CompressUint32x4 x mask) => (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(CompressUint32x8 x mask) => (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(CompressUint32x16 x mask) => (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(CompressUint64x2 x mask) => (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(CompressUint64x4 x mask) => (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(CompressUint64x8 x mask) => (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(DiffWithCeilWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+2] x)
+(DiffWithCeilWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+2] x)
+(DiffWithCeilWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+2] x)
+(DiffWithCeilWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+2] x)
+(DiffWithCeilWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+2] x)
+(DiffWithCeilWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+2] x)
+(DiffWithCeilWithPrecisionMaskedFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+2] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(DiffWithCeilWithPrecisionMaskedFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+2] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(DiffWithCeilWithPrecisionMaskedFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+2] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(DiffWithCeilWithPrecisionMaskedFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+2] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(DiffWithCeilWithPrecisionMaskedFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+2] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(DiffWithCeilWithPrecisionMaskedFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+2] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(DiffWithFloorWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+1] x)
+(DiffWithFloorWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+1] x)
+(DiffWithFloorWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+1] x)
+(DiffWithFloorWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+1] x)
+(DiffWithFloorWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+1] x)
+(DiffWithFloorWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+1] x)
+(DiffWithFloorWithPrecisionMaskedFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+1] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(DiffWithFloorWithPrecisionMaskedFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+1] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(DiffWithFloorWithPrecisionMaskedFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+1] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(DiffWithFloorWithPrecisionMaskedFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+1] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(DiffWithFloorWithPrecisionMaskedFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+1] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(DiffWithFloorWithPrecisionMaskedFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+1] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(DiffWithRoundWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+0] x)
+(DiffWithRoundWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+0] x)
+(DiffWithRoundWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+0] x)
+(DiffWithRoundWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+0] x)
+(DiffWithRoundWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+0] x)
+(DiffWithRoundWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+0] x)
+(DiffWithRoundWithPrecisionMaskedFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+0] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(DiffWithRoundWithPrecisionMaskedFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+0] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(DiffWithRoundWithPrecisionMaskedFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+0] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(DiffWithRoundWithPrecisionMaskedFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+0] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(DiffWithRoundWithPrecisionMaskedFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+0] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(DiffWithRoundWithPrecisionMaskedFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+0] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(DiffWithTruncWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+3] x)
+(DiffWithTruncWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+3] x)
+(DiffWithTruncWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+3] x)
+(DiffWithTruncWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+3] x)
+(DiffWithTruncWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+3] x)
+(DiffWithTruncWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+3] x)
+(DiffWithTruncWithPrecisionMaskedFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+3] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(DiffWithTruncWithPrecisionMaskedFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+3] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(DiffWithTruncWithPrecisionMaskedFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+3] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(DiffWithTruncWithPrecisionMaskedFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+3] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(DiffWithTruncWithPrecisionMaskedFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+3] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(DiffWithTruncWithPrecisionMaskedFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+3] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(DivFloat32x4 ...) => (VDIVPS128 ...)
+(DivFloat32x8 ...) => (VDIVPS256 ...)
+(DivFloat32x16 ...) => (VDIVPS512 ...)
+(DivFloat64x2 ...) => (VDIVPD128 ...)
+(DivFloat64x4 ...) => (VDIVPD256 ...)
+(DivFloat64x8 ...) => (VDIVPD512 ...)
+(DivMaskedFloat32x4 x y mask) => (VDIVPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(DivMaskedFloat32x8 x y mask) => (VDIVPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(DivMaskedFloat32x16 x y mask) => (VDIVPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(DivMaskedFloat64x2 x y mask) => (VDIVPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(DivMaskedFloat64x4 x y mask) => (VDIVPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(DivMaskedFloat64x8 x y mask) => (VDIVPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(DotProdBroadcastFloat32x4 x y) => (VDPPS128 [127] x y)
+(DotProdBroadcastFloat32x8 x y) => (VDPPS256 [127] x y)
+(DotProdBroadcastFloat64x2 x y) => (VDPPD128 [127] x y)
+(EqualFloat32x4 x y) => (VCMPPS128 [0] x y)
+(EqualFloat32x8 x y) => (VCMPPS256 [0] x y)
+(EqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [0] x y))
+(EqualFloat64x2 x y) => (VCMPPD128 [0] x y)
+(EqualFloat64x4 x y) => (VCMPPD256 [0] x y)
+(EqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [0] x y))
+(EqualInt8x16 ...) => (VPCMPEQB128 ...)
+(EqualInt8x32 ...) => (VPCMPEQB256 ...)
+(EqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [0] x y))
+(EqualInt16x8 ...) => (VPCMPEQW128 ...)
+(EqualInt16x16 ...) => (VPCMPEQW256 ...)
+(EqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [0] x y))
+(EqualInt32x4 ...) => (VPCMPEQD128 ...)
+(EqualInt32x8 ...) => (VPCMPEQD256 ...)
+(EqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [0] x y))
+(EqualInt64x2 ...) => (VPCMPEQQ128 ...)
+(EqualInt64x4 ...) => (VPCMPEQQ256 ...)
+(EqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [0] x y))
+(EqualUint8x16 ...) => (VPCMPEQB128 ...)
+(EqualUint8x32 ...) => (VPCMPEQB256 ...)
+(EqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [0] x y))
+(EqualUint16x8 ...) => (VPCMPEQW128 ...)
+(EqualUint16x16 ...) => (VPCMPEQW256 ...)
+(EqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [0] x y))
+(EqualUint32x4 ...) => (VPCMPEQD128 ...)
+(EqualUint32x8 ...) => (VPCMPEQD256 ...)
+(EqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [0] x y))
+(EqualUint64x2 ...) => (VPCMPEQQ128 ...)
+(EqualUint64x4 ...) => (VPCMPEQQ256 ...)
+(EqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [0] x y))
+(EqualMaskedFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [0] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(EqualMaskedFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [0] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(EqualMaskedFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [0] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(EqualMaskedFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [0] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(EqualMaskedFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [0] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(EqualMaskedFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [0] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(EqualMaskedInt8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPBMasked128 [0] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+(EqualMaskedInt8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPBMasked256 [0] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+(EqualMaskedInt8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPBMasked512 [0] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+(EqualMaskedInt16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPWMasked128 [0] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+(EqualMaskedInt16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPWMasked256 [0] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+(EqualMaskedInt16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPWMasked512 [0] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+(EqualMaskedInt32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPDMasked128 [0] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(EqualMaskedInt32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPDMasked256 [0] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(EqualMaskedInt32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPDMasked512 [0] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(EqualMaskedInt64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPQMasked128 [0] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(EqualMaskedInt64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPQMasked256 [0] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(EqualMaskedInt64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPQMasked512 [0] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(EqualMaskedUint8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPUBMasked128 [0] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+(EqualMaskedUint8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPUBMasked256 [0] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+(EqualMaskedUint8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPUBMasked512 [0] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+(EqualMaskedUint16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPUWMasked128 [0] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+(EqualMaskedUint16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPUWMasked256 [0] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+(EqualMaskedUint16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPUWMasked512 [0] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+(EqualMaskedUint32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPUDMasked128 [0] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(EqualMaskedUint32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPUDMasked256 [0] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(EqualMaskedUint32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPUDMasked512 [0] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(EqualMaskedUint64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPUQMasked128 [0] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(EqualMaskedUint64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPUQMasked256 [0] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(EqualMaskedUint64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPUQMasked512 [0] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(FloorFloat32x4 x) => (VROUNDPS128 [1] x)
+(FloorFloat32x8 x) => (VROUNDPS256 [1] x)
+(FloorFloat64x2 x) => (VROUNDPD128 [1] x)
+(FloorFloat64x4 x) => (VROUNDPD256 [1] x)
+(FloorWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+1] x)
+(FloorWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+1] x)
+(FloorWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+1] x)
+(FloorWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+1] x)
+(FloorWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+1] x)
+(FloorWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+1] x)
+(FloorWithPrecisionMaskedFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+1] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(FloorWithPrecisionMaskedFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+1] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(FloorWithPrecisionMaskedFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+1] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(FloorWithPrecisionMaskedFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+1] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(FloorWithPrecisionMaskedFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+1] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(FloorWithPrecisionMaskedFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+1] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(FusedMultiplyAddFloat32x4 ...) => (VFMADD213PS128 ...)
+(FusedMultiplyAddFloat32x8 ...) => (VFMADD213PS256 ...)
+(FusedMultiplyAddFloat32x16 ...) => (VFMADD213PS512 ...)
+(FusedMultiplyAddFloat64x2 ...) => (VFMADD213PD128 ...)
+(FusedMultiplyAddFloat64x4 ...) => (VFMADD213PD256 ...)
+(FusedMultiplyAddFloat64x8 ...) => (VFMADD213PD512 ...)
+(FusedMultiplyAddMaskedFloat32x4 x y z mask) => (VFMADD213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(FusedMultiplyAddMaskedFloat32x8 x y z mask) => (VFMADD213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(FusedMultiplyAddMaskedFloat32x16 x y z mask) => (VFMADD213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(FusedMultiplyAddMaskedFloat64x2 x y z mask) => (VFMADD213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(FusedMultiplyAddMaskedFloat64x4 x y z mask) => (VFMADD213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(FusedMultiplyAddMaskedFloat64x8 x y z mask) => (VFMADD213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(FusedMultiplyAddSubFloat32x4 ...) => (VFMADDSUB213PS128 ...)
+(FusedMultiplyAddSubFloat32x8 ...) => (VFMADDSUB213PS256 ...)
+(FusedMultiplyAddSubFloat32x16 ...) => (VFMADDSUB213PS512 ...)
+(FusedMultiplyAddSubFloat64x2 ...) => (VFMADDSUB213PD128 ...)
+(FusedMultiplyAddSubFloat64x4 ...) => (VFMADDSUB213PD256 ...)
+(FusedMultiplyAddSubFloat64x8 ...) => (VFMADDSUB213PD512 ...)
+(FusedMultiplyAddSubMaskedFloat32x4 x y z mask) => (VFMADDSUB213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(FusedMultiplyAddSubMaskedFloat32x8 x y z mask) => (VFMADDSUB213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(FusedMultiplyAddSubMaskedFloat32x16 x y z mask) => (VFMADDSUB213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(FusedMultiplyAddSubMaskedFloat64x2 x y z mask) => (VFMADDSUB213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(FusedMultiplyAddSubMaskedFloat64x4 x y z mask) => (VFMADDSUB213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(FusedMultiplyAddSubMaskedFloat64x8 x y z mask) => (VFMADDSUB213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(FusedMultiplySubAddFloat32x4 ...) => (VFMSUBADD213PS128 ...)
+(FusedMultiplySubAddFloat32x8 ...) => (VFMSUBADD213PS256 ...)
+(FusedMultiplySubAddFloat32x16 ...) => (VFMSUBADD213PS512 ...)
+(FusedMultiplySubAddFloat64x2 ...) => (VFMSUBADD213PD128 ...)
+(FusedMultiplySubAddFloat64x4 ...) => (VFMSUBADD213PD256 ...)
+(FusedMultiplySubAddFloat64x8 ...) => (VFMSUBADD213PD512 ...)
+(FusedMultiplySubAddMaskedFloat32x4 x y z mask) => (VFMSUBADD213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(FusedMultiplySubAddMaskedFloat32x8 x y z mask) => (VFMSUBADD213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(FusedMultiplySubAddMaskedFloat32x16 x y z mask) => (VFMSUBADD213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(FusedMultiplySubAddMaskedFloat64x2 x y z mask) => (VFMSUBADD213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(FusedMultiplySubAddMaskedFloat64x4 x y z mask) => (VFMSUBADD213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(FusedMultiplySubAddMaskedFloat64x8 x y z mask) => (VFMSUBADD213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(GaloisFieldAffineTransformUint8x16 ...) => (VGF2P8AFFINEQB128 ...)
+(GaloisFieldAffineTransformUint8x32 ...) => (VGF2P8AFFINEQB256 ...)
+(GaloisFieldAffineTransformUint8x64 ...) => (VGF2P8AFFINEQB512 ...)
+(GaloisFieldAffineTransformInverseUint8x16 ...) => (VGF2P8AFFINEINVQB128 ...)
+(GaloisFieldAffineTransformInverseUint8x32 ...) => (VGF2P8AFFINEINVQB256 ...)
+(GaloisFieldAffineTransformInverseUint8x64 ...) => (VGF2P8AFFINEINVQB512 ...)
+(GaloisFieldAffineTransformInverseMaskedUint8x16 [a] x y mask) => (VGF2P8AFFINEINVQBMasked128 [a] x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(GaloisFieldAffineTransformInverseMaskedUint8x32 [a] x y mask) => (VGF2P8AFFINEINVQBMasked256 [a] x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(GaloisFieldAffineTransformInverseMaskedUint8x64 [a] x y mask) => (VGF2P8AFFINEINVQBMasked512 [a] x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(GaloisFieldAffineTransformMaskedUint8x16 [a] x y mask) => (VGF2P8AFFINEQBMasked128 [a] x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(GaloisFieldAffineTransformMaskedUint8x32 [a] x y mask) => (VGF2P8AFFINEQBMasked256 [a] x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(GaloisFieldAffineTransformMaskedUint8x64 [a] x y mask) => (VGF2P8AFFINEQBMasked512 [a] x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(GaloisFieldMulUint8x16 ...) => (VGF2P8MULB128 ...)
+(GaloisFieldMulUint8x32 ...) => (VGF2P8MULB256 ...)
+(GaloisFieldMulUint8x64 ...) => (VGF2P8MULB512 ...)
+(GaloisFieldMulMaskedUint8x16 x y mask) => (VGF2P8MULBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(GaloisFieldMulMaskedUint8x32 x y mask) => (VGF2P8MULBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(GaloisFieldMulMaskedUint8x64 x y mask) => (VGF2P8MULBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(Get128Float32x8 ...) => (VEXTRACTF128128 ...)
+(Get128Float64x4 ...) => (VEXTRACTF128128 ...)
+(Get128Int8x32 ...) => (VEXTRACTI128128 ...)
+(Get128Int16x16 ...) => (VEXTRACTI128128 ...)
+(Get128Int32x8 ...) => (VEXTRACTI128128 ...)
+(Get128Int64x4 ...) => (VEXTRACTI128128 ...)
+(Get128Uint8x32 ...) => (VEXTRACTI128128 ...)
+(Get128Uint16x16 ...) => (VEXTRACTI128128 ...)
+(Get128Uint32x8 ...) => (VEXTRACTI128128 ...)
+(Get128Uint64x4 ...) => (VEXTRACTI128128 ...)
+(GetElemInt8x16 ...) => (VPEXTRB128 ...)
+(GetElemInt16x8 ...) => (VPEXTRW128 ...)
+(GetElemInt32x4 ...) => (VPEXTRD128 ...)
+(GetElemInt64x2 ...) => (VPEXTRQ128 ...)
+(GetElemUint8x16 ...) => (VPEXTRB128 ...)
+(GetElemUint16x8 ...) => (VPEXTRW128 ...)
+(GetElemUint32x4 ...) => (VPEXTRD128 ...)
+(GetElemUint64x2 ...) => (VPEXTRQ128 ...)
+(GreaterFloat32x4 x y) => (VCMPPS128 [14] x y)
+(GreaterFloat32x8 x y) => (VCMPPS256 [14] x y)
+(GreaterFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [14] x y))
+(GreaterFloat64x2 x y) => (VCMPPD128 [14] x y)
+(GreaterFloat64x4 x y) => (VCMPPD256 [14] x y)
+(GreaterFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [14] x y))
+(GreaterInt8x16 ...) => (VPCMPGTB128 ...)
+(GreaterInt8x32 ...) => (VPCMPGTB256 ...)
+(GreaterInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [14] x y))
+(GreaterInt16x8 ...) => (VPCMPGTW128 ...)
+(GreaterInt16x16 ...) => (VPCMPGTW256 ...)
+(GreaterInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [14] x y))
+(GreaterInt32x4 ...) => (VPCMPGTD128 ...)
+(GreaterInt32x8 ...) => (VPCMPGTD256 ...)
+(GreaterInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [14] x y))
+(GreaterInt64x2 ...) => (VPCMPGTQ128 ...)
+(GreaterInt64x4 ...) => (VPCMPGTQ256 ...)
+(GreaterInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [14] x y))
+(GreaterUint8x16 x y) => (VPMOVMToVec8x16 (VPCMPUB128 [14] x y))
+(GreaterUint8x32 x y) => (VPMOVMToVec8x32 (VPCMPUB256 [14] x y))
+(GreaterUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [14] x y))
+(GreaterUint16x8 x y) => (VPMOVMToVec16x8 (VPCMPUW128 [14] x y))
+(GreaterUint16x16 x y) => (VPMOVMToVec16x16 (VPCMPUW256 [14] x y))
+(GreaterUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [14] x y))
+(GreaterUint32x4 x y) => (VPMOVMToVec32x4 (VPCMPUD128 [14] x y))
+(GreaterUint32x8 x y) => (VPMOVMToVec32x8 (VPCMPUD256 [14] x y))
+(GreaterUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [14] x y))
+(GreaterUint64x2 x y) => (VPMOVMToVec64x2 (VPCMPUQ128 [14] x y))
+(GreaterUint64x4 x y) => (VPMOVMToVec64x4 (VPCMPUQ256 [14] x y))
+(GreaterUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [14] x y))
+(GreaterEqualFloat32x4 x y) => (VCMPPS128 [13] x y)
+(GreaterEqualFloat32x8 x y) => (VCMPPS256 [13] x y)
+(GreaterEqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [13] x y))
+(GreaterEqualFloat64x2 x y) => (VCMPPD128 [13] x y)
+(GreaterEqualFloat64x4 x y) => (VCMPPD256 [13] x y)
+(GreaterEqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [13] x y))
+(GreaterEqualInt8x16 x y) => (VPMOVMToVec8x16 (VPCMPB128 [13] x y))
+(GreaterEqualInt8x32 x y) => (VPMOVMToVec8x32 (VPCMPB256 [13] x y))
+(GreaterEqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [13] x y))
+(GreaterEqualInt16x8 x y) => (VPMOVMToVec16x8 (VPCMPW128 [13] x y))
+(GreaterEqualInt16x16 x y) => (VPMOVMToVec16x16 (VPCMPW256 [13] x y))
+(GreaterEqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [13] x y))
+(GreaterEqualInt32x4 x y) => (VPMOVMToVec32x4 (VPCMPD128 [13] x y))
+(GreaterEqualInt32x8 x y) => (VPMOVMToVec32x8 (VPCMPD256 [13] x y))
+(GreaterEqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [13] x y))
+(GreaterEqualInt64x2 x y) => (VPMOVMToVec64x2 (VPCMPQ128 [13] x y))
+(GreaterEqualInt64x4 x y) => (VPMOVMToVec64x4 (VPCMPQ256 [13] x y))
+(GreaterEqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [13] x y))
+(GreaterEqualUint8x16 x y) => (VPMOVMToVec8x16 (VPCMPUB128 [13] x y))
+(GreaterEqualUint8x32 x y) => (VPMOVMToVec8x32 (VPCMPUB256 [13] x y))
+(GreaterEqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [13] x y))
+(GreaterEqualUint16x8 x y) => (VPMOVMToVec16x8 (VPCMPUW128 [13] x y))
+(GreaterEqualUint16x16 x y) => (VPMOVMToVec16x16 (VPCMPUW256 [13] x y))
+(GreaterEqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [13] x y))
+(GreaterEqualUint32x4 x y) => (VPMOVMToVec32x4 (VPCMPUD128 [13] x y))
+(GreaterEqualUint32x8 x y) => (VPMOVMToVec32x8 (VPCMPUD256 [13] x y))
+(GreaterEqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [13] x y))
+(GreaterEqualUint64x2 x y) => (VPMOVMToVec64x2 (VPCMPUQ128 [13] x y))
+(GreaterEqualUint64x4 x y) => (VPMOVMToVec64x4 (VPCMPUQ256 [13] x y))
+(GreaterEqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [13] x y))
+(GreaterEqualMaskedFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [13] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [13] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [13] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [13] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [13] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [13] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedInt8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPBMasked128 [13] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedInt8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPBMasked256 [13] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedInt8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPBMasked512 [13] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedInt16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPWMasked128 [13] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedInt16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPWMasked256 [13] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedInt16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPWMasked512 [13] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedInt32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPDMasked128 [13] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedInt32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPDMasked256 [13] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedInt32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPDMasked512 [13] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedInt64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPQMasked128 [13] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedInt64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPQMasked256 [13] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedInt64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPQMasked512 [13] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedUint8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPUBMasked128 [13] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedUint8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPUBMasked256 [13] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedUint8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPUBMasked512 [13] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedUint16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPUWMasked128 [13] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedUint16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPUWMasked256 [13] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedUint16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPUWMasked512 [13] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedUint32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPUDMasked128 [13] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedUint32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPUDMasked256 [13] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedUint32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPUDMasked512 [13] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedUint64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPUQMasked128 [13] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedUint64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPUQMasked256 [13] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(GreaterEqualMaskedUint64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPUQMasked512 [13] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(GreaterMaskedFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [14] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(GreaterMaskedFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [14] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(GreaterMaskedFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [14] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(GreaterMaskedFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [14] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(GreaterMaskedFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [14] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(GreaterMaskedFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [14] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(GreaterMaskedInt8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPBMasked128 [14] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+(GreaterMaskedInt8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPBMasked256 [14] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+(GreaterMaskedInt8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPBMasked512 [14] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+(GreaterMaskedInt16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPWMasked128 [14] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+(GreaterMaskedInt16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPWMasked256 [14] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+(GreaterMaskedInt16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPWMasked512 [14] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+(GreaterMaskedInt32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPDMasked128 [14] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(GreaterMaskedInt32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPDMasked256 [14] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(GreaterMaskedInt32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPDMasked512 [14] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(GreaterMaskedInt64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPQMasked128 [14] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(GreaterMaskedInt64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPQMasked256 [14] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(GreaterMaskedInt64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPQMasked512 [14] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(GreaterMaskedUint8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPUBMasked128 [14] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+(GreaterMaskedUint8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPUBMasked256 [14] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+(GreaterMaskedUint8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPUBMasked512 [14] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+(GreaterMaskedUint16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPUWMasked128 [14] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+(GreaterMaskedUint16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPUWMasked256 [14] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+(GreaterMaskedUint16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPUWMasked512 [14] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+(GreaterMaskedUint32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPUDMasked128 [14] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(GreaterMaskedUint32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPUDMasked256 [14] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(GreaterMaskedUint32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPUDMasked512 [14] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(GreaterMaskedUint64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPUQMasked128 [14] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(GreaterMaskedUint64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPUQMasked256 [14] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(GreaterMaskedUint64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPUQMasked512 [14] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(IsNanFloat32x4 x y) => (VCMPPS128 [3] x y)
+(IsNanFloat32x8 x y) => (VCMPPS256 [3] x y)
+(IsNanFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [3] x y))
+(IsNanFloat64x2 x y) => (VCMPPD128 [3] x y)
+(IsNanFloat64x4 x y) => (VCMPPD256 [3] x y)
+(IsNanFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [3] x y))
+(IsNanMaskedFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [3] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(IsNanMaskedFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [3] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(IsNanMaskedFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [3] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(IsNanMaskedFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [3] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(IsNanMaskedFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [3] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(IsNanMaskedFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [3] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(LessFloat32x4 x y) => (VCMPPS128 [1] x y)
+(LessFloat32x8 x y) => (VCMPPS256 [1] x y)
+(LessFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [1] x y))
+(LessFloat64x2 x y) => (VCMPPD128 [1] x y)
+(LessFloat64x4 x y) => (VCMPPD256 [1] x y)
+(LessFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [1] x y))
+(LessInt8x16 x y) => (VPMOVMToVec8x16 (VPCMPB128 [1] x y))
+(LessInt8x32 x y) => (VPMOVMToVec8x32 (VPCMPB256 [1] x y))
+(LessInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [1] x y))
+(LessInt16x8 x y) => (VPMOVMToVec16x8 (VPCMPW128 [1] x y))
+(LessInt16x16 x y) => (VPMOVMToVec16x16 (VPCMPW256 [1] x y))
+(LessInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [1] x y))
+(LessInt32x4 x y) => (VPMOVMToVec32x4 (VPCMPD128 [1] x y))
+(LessInt32x8 x y) => (VPMOVMToVec32x8 (VPCMPD256 [1] x y))
+(LessInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [1] x y))
+(LessInt64x2 x y) => (VPMOVMToVec64x2 (VPCMPQ128 [1] x y))
+(LessInt64x4 x y) => (VPMOVMToVec64x4 (VPCMPQ256 [1] x y))
+(LessInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [1] x y))
+(LessUint8x16 x y) => (VPMOVMToVec8x16 (VPCMPUB128 [1] x y))
+(LessUint8x32 x y) => (VPMOVMToVec8x32 (VPCMPUB256 [1] x y))
+(LessUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [1] x y))
+(LessUint16x8 x y) => (VPMOVMToVec16x8 (VPCMPUW128 [1] x y))
+(LessUint16x16 x y) => (VPMOVMToVec16x16 (VPCMPUW256 [1] x y))
+(LessUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [1] x y))
+(LessUint32x4 x y) => (VPMOVMToVec32x4 (VPCMPUD128 [1] x y))
+(LessUint32x8 x y) => (VPMOVMToVec32x8 (VPCMPUD256 [1] x y))
+(LessUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [1] x y))
+(LessUint64x2 x y) => (VPMOVMToVec64x2 (VPCMPUQ128 [1] x y))
+(LessUint64x4 x y) => (VPMOVMToVec64x4 (VPCMPUQ256 [1] x y))
+(LessUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [1] x y))
+(LessEqualFloat32x4 x y) => (VCMPPS128 [2] x y)
+(LessEqualFloat32x8 x y) => (VCMPPS256 [2] x y)
+(LessEqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [2] x y))
+(LessEqualFloat64x2 x y) => (VCMPPD128 [2] x y)
+(LessEqualFloat64x4 x y) => (VCMPPD256 [2] x y)
+(LessEqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [2] x y))
+(LessEqualInt8x16 x y) => (VPMOVMToVec8x16 (VPCMPB128 [2] x y))
+(LessEqualInt8x32 x y) => (VPMOVMToVec8x32 (VPCMPB256 [2] x y))
+(LessEqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [2] x y))
+(LessEqualInt16x8 x y) => (VPMOVMToVec16x8 (VPCMPW128 [2] x y))
+(LessEqualInt16x16 x y) => (VPMOVMToVec16x16 (VPCMPW256 [2] x y))
+(LessEqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [2] x y))
+(LessEqualInt32x4 x y) => (VPMOVMToVec32x4 (VPCMPD128 [2] x y))
+(LessEqualInt32x8 x y) => (VPMOVMToVec32x8 (VPCMPD256 [2] x y))
+(LessEqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [2] x y))
+(LessEqualInt64x2 x y) => (VPMOVMToVec64x2 (VPCMPQ128 [2] x y))
+(LessEqualInt64x4 x y) => (VPMOVMToVec64x4 (VPCMPQ256 [2] x y))
+(LessEqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [2] x y))
+(LessEqualUint8x16 x y) => (VPMOVMToVec8x16 (VPCMPUB128 [2] x y))
+(LessEqualUint8x32 x y) => (VPMOVMToVec8x32 (VPCMPUB256 [2] x y))
+(LessEqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [2] x y))
+(LessEqualUint16x8 x y) => (VPMOVMToVec16x8 (VPCMPUW128 [2] x y))
+(LessEqualUint16x16 x y) => (VPMOVMToVec16x16 (VPCMPUW256 [2] x y))
+(LessEqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [2] x y))
+(LessEqualUint32x4 x y) => (VPMOVMToVec32x4 (VPCMPUD128 [2] x y))
+(LessEqualUint32x8 x y) => (VPMOVMToVec32x8 (VPCMPUD256 [2] x y))
+(LessEqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [2] x y))
+(LessEqualUint64x2 x y) => (VPMOVMToVec64x2 (VPCMPUQ128 [2] x y))
+(LessEqualUint64x4 x y) => (VPMOVMToVec64x4 (VPCMPUQ256 [2] x y))
+(LessEqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [2] x y))
+(LessEqualMaskedFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [2] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(LessEqualMaskedFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [2] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(LessEqualMaskedFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [2] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(LessEqualMaskedFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [2] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(LessEqualMaskedFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [2] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(LessEqualMaskedFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [2] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(LessEqualMaskedInt8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPBMasked128 [2] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+(LessEqualMaskedInt8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPBMasked256 [2] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+(LessEqualMaskedInt8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPBMasked512 [2] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+(LessEqualMaskedInt16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPWMasked128 [2] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+(LessEqualMaskedInt16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPWMasked256 [2] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+(LessEqualMaskedInt16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPWMasked512 [2] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+(LessEqualMaskedInt32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPDMasked128 [2] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(LessEqualMaskedInt32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPDMasked256 [2] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(LessEqualMaskedInt32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPDMasked512 [2] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(LessEqualMaskedInt64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPQMasked128 [2] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(LessEqualMaskedInt64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPQMasked256 [2] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(LessEqualMaskedInt64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPQMasked512 [2] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(LessEqualMaskedUint8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPUBMasked128 [2] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+(LessEqualMaskedUint8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPUBMasked256 [2] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+(LessEqualMaskedUint8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPUBMasked512 [2] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+(LessEqualMaskedUint16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPUWMasked128 [2] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+(LessEqualMaskedUint16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPUWMasked256 [2] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+(LessEqualMaskedUint16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPUWMasked512 [2] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+(LessEqualMaskedUint32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPUDMasked128 [2] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(LessEqualMaskedUint32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPUDMasked256 [2] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(LessEqualMaskedUint32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPUDMasked512 [2] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(LessEqualMaskedUint64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPUQMasked128 [2] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(LessEqualMaskedUint64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPUQMasked256 [2] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(LessEqualMaskedUint64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPUQMasked512 [2] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(LessMaskedFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [1] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(LessMaskedFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [1] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(LessMaskedFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [1] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(LessMaskedFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [1] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(LessMaskedFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [1] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(LessMaskedFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [1] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(LessMaskedInt8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPBMasked128 [1] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+(LessMaskedInt8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPBMasked256 [1] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+(LessMaskedInt8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPBMasked512 [1] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+(LessMaskedInt16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPWMasked128 [1] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+(LessMaskedInt16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPWMasked256 [1] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+(LessMaskedInt16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPWMasked512 [1] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+(LessMaskedInt32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPDMasked128 [1] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(LessMaskedInt32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPDMasked256 [1] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(LessMaskedInt32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPDMasked512 [1] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(LessMaskedInt64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPQMasked128 [1] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(LessMaskedInt64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPQMasked256 [1] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(LessMaskedInt64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPQMasked512 [1] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(LessMaskedUint8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPUBMasked128 [1] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+(LessMaskedUint8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPUBMasked256 [1] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+(LessMaskedUint8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPUBMasked512 [1] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+(LessMaskedUint16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPUWMasked128 [1] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+(LessMaskedUint16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPUWMasked256 [1] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+(LessMaskedUint16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPUWMasked512 [1] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+(LessMaskedUint32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPUDMasked128 [1] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(LessMaskedUint32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPUDMasked256 [1] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(LessMaskedUint32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPUDMasked512 [1] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(LessMaskedUint64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPUQMasked128 [1] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(LessMaskedUint64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPUQMasked256 [1] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(LessMaskedUint64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPUQMasked512 [1] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(MaxFloat32x4 ...) => (VMAXPS128 ...)
+(MaxFloat32x8 ...) => (VMAXPS256 ...)
+(MaxFloat32x16 ...) => (VMAXPS512 ...)
+(MaxFloat64x2 ...) => (VMAXPD128 ...)
+(MaxFloat64x4 ...) => (VMAXPD256 ...)
+(MaxFloat64x8 ...) => (VMAXPD512 ...)
+(MaxInt8x16 ...) => (VPMAXSB128 ...)
+(MaxInt8x32 ...) => (VPMAXSB256 ...)
+(MaxInt8x64 ...) => (VPMAXSB512 ...)
+(MaxInt16x8 ...) => (VPMAXSW128 ...)
+(MaxInt16x16 ...) => (VPMAXSW256 ...)
+(MaxInt16x32 ...) => (VPMAXSW512 ...)
+(MaxInt32x4 ...) => (VPMAXSD128 ...)
+(MaxInt32x8 ...) => (VPMAXSD256 ...)
+(MaxInt32x16 ...) => (VPMAXSD512 ...)
+(MaxInt64x2 ...) => (VPMAXSQ128 ...)
+(MaxInt64x4 ...) => (VPMAXSQ256 ...)
+(MaxInt64x8 ...) => (VPMAXSQ512 ...)
+(MaxUint8x16 ...) => (VPMAXUB128 ...)
+(MaxUint8x32 ...) => (VPMAXUB256 ...)
+(MaxUint8x64 ...) => (VPMAXUB512 ...)
+(MaxUint16x8 ...) => (VPMAXUW128 ...)
+(MaxUint16x16 ...) => (VPMAXUW256 ...)
+(MaxUint16x32 ...) => (VPMAXUW512 ...)
+(MaxUint32x4 ...) => (VPMAXUD128 ...)
+(MaxUint32x8 ...) => (VPMAXUD256 ...)
+(MaxUint32x16 ...) => (VPMAXUD512 ...)
+(MaxUint64x2 ...) => (VPMAXUQ128 ...)
+(MaxUint64x4 ...) => (VPMAXUQ256 ...)
+(MaxUint64x8 ...) => (VPMAXUQ512 ...)
+(MaxMaskedFloat32x4 x y mask) => (VMAXPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaxMaskedFloat32x8 x y mask) => (VMAXPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaxMaskedFloat32x16 x y mask) => (VMAXPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaxMaskedFloat64x2 x y mask) => (VMAXPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaxMaskedFloat64x4 x y mask) => (VMAXPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaxMaskedFloat64x8 x y mask) => (VMAXPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaxMaskedInt8x16 x y mask) => (VPMAXSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(MaxMaskedInt8x32 x y mask) => (VPMAXSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(MaxMaskedInt8x64 x y mask) => (VPMAXSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(MaxMaskedInt16x8 x y mask) => (VPMAXSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaxMaskedInt16x16 x y mask) => (VPMAXSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaxMaskedInt16x32 x y mask) => (VPMAXSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaxMaskedInt32x4 x y mask) => (VPMAXSDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaxMaskedInt32x8 x y mask) => (VPMAXSDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaxMaskedInt32x16 x y mask) => (VPMAXSDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaxMaskedInt64x2 x y mask) => (VPMAXSQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaxMaskedInt64x4 x y mask) => (VPMAXSQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaxMaskedInt64x8 x y mask) => (VPMAXSQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaxMaskedUint8x16 x y mask) => (VPMAXUBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(MaxMaskedUint8x32 x y mask) => (VPMAXUBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(MaxMaskedUint8x64 x y mask) => (VPMAXUBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(MaxMaskedUint16x8 x y mask) => (VPMAXUWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaxMaskedUint16x16 x y mask) => (VPMAXUWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaxMaskedUint16x32 x y mask) => (VPMAXUWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaxMaskedUint32x4 x y mask) => (VPMAXUDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaxMaskedUint32x8 x y mask) => (VPMAXUDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaxMaskedUint32x16 x y mask) => (VPMAXUDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaxMaskedUint64x2 x y mask) => (VPMAXUQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaxMaskedUint64x4 x y mask) => (VPMAXUQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaxMaskedUint64x8 x y mask) => (VPMAXUQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MinFloat32x4 ...) => (VMINPS128 ...)
+(MinFloat32x8 ...) => (VMINPS256 ...)
+(MinFloat32x16 ...) => (VMINPS512 ...)
+(MinFloat64x2 ...) => (VMINPD128 ...)
+(MinFloat64x4 ...) => (VMINPD256 ...)
+(MinFloat64x8 ...) => (VMINPD512 ...)
+(MinInt8x16 ...) => (VPMINSB128 ...)
+(MinInt8x32 ...) => (VPMINSB256 ...)
+(MinInt8x64 ...) => (VPMINSB512 ...)
+(MinInt16x8 ...) => (VPMINSW128 ...)
+(MinInt16x16 ...) => (VPMINSW256 ...)
+(MinInt16x32 ...) => (VPMINSW512 ...)
+(MinInt32x4 ...) => (VPMINSD128 ...)
+(MinInt32x8 ...) => (VPMINSD256 ...)
+(MinInt32x16 ...) => (VPMINSD512 ...)
+(MinInt64x2 ...) => (VPMINSQ128 ...)
+(MinInt64x4 ...) => (VPMINSQ256 ...)
+(MinInt64x8 ...) => (VPMINSQ512 ...)
+(MinUint8x16 ...) => (VPMINUB128 ...)
+(MinUint8x32 ...) => (VPMINUB256 ...)
+(MinUint8x64 ...) => (VPMINUB512 ...)
+(MinUint16x8 ...) => (VPMINUW128 ...)
+(MinUint16x16 ...) => (VPMINUW256 ...)
+(MinUint16x32 ...) => (VPMINUW512 ...)
+(MinUint32x4 ...) => (VPMINUD128 ...)
+(MinUint32x8 ...) => (VPMINUD256 ...)
+(MinUint32x16 ...) => (VPMINUD512 ...)
+(MinUint64x2 ...) => (VPMINUQ128 ...)
+(MinUint64x4 ...) => (VPMINUQ256 ...)
+(MinUint64x8 ...) => (VPMINUQ512 ...)
+(MinMaskedFloat32x4 x y mask) => (VMINPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MinMaskedFloat32x8 x y mask) => (VMINPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MinMaskedFloat32x16 x y mask) => (VMINPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MinMaskedFloat64x2 x y mask) => (VMINPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MinMaskedFloat64x4 x y mask) => (VMINPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MinMaskedFloat64x8 x y mask) => (VMINPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MinMaskedInt8x16 x y mask) => (VPMINSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(MinMaskedInt8x32 x y mask) => (VPMINSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(MinMaskedInt8x64 x y mask) => (VPMINSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(MinMaskedInt16x8 x y mask) => (VPMINSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MinMaskedInt16x16 x y mask) => (VPMINSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MinMaskedInt16x32 x y mask) => (VPMINSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MinMaskedInt32x4 x y mask) => (VPMINSDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MinMaskedInt32x8 x y mask) => (VPMINSDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MinMaskedInt32x16 x y mask) => (VPMINSDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MinMaskedInt64x2 x y mask) => (VPMINSQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MinMaskedInt64x4 x y mask) => (VPMINSQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MinMaskedInt64x8 x y mask) => (VPMINSQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MinMaskedUint8x16 x y mask) => (VPMINUBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(MinMaskedUint8x32 x y mask) => (VPMINUBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(MinMaskedUint8x64 x y mask) => (VPMINUBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(MinMaskedUint16x8 x y mask) => (VPMINUWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MinMaskedUint16x16 x y mask) => (VPMINUWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MinMaskedUint16x32 x y mask) => (VPMINUWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MinMaskedUint32x4 x y mask) => (VPMINUDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MinMaskedUint32x8 x y mask) => (VPMINUDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MinMaskedUint32x16 x y mask) => (VPMINUDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MinMaskedUint64x2 x y mask) => (VPMINUQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MinMaskedUint64x4 x y mask) => (VPMINUQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MinMaskedUint64x8 x y mask) => (VPMINUQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MulFloat32x4 ...) => (VMULPS128 ...)
+(MulFloat32x8 ...) => (VMULPS256 ...)
+(MulFloat32x16 ...) => (VMULPS512 ...)
+(MulFloat64x2 ...) => (VMULPD128 ...)
+(MulFloat64x4 ...) => (VMULPD256 ...)
+(MulFloat64x8 ...) => (VMULPD512 ...)
+(MulByPowOf2Float32x4 ...) => (VSCALEFPS128 ...)
+(MulByPowOf2Float32x8 ...) => (VSCALEFPS256 ...)
+(MulByPowOf2Float32x16 ...) => (VSCALEFPS512 ...)
+(MulByPowOf2Float64x2 ...) => (VSCALEFPD128 ...)
+(MulByPowOf2Float64x4 ...) => (VSCALEFPD256 ...)
+(MulByPowOf2Float64x8 ...) => (VSCALEFPD512 ...)
+(MulByPowOf2MaskedFloat32x4 x y mask) => (VSCALEFPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MulByPowOf2MaskedFloat32x8 x y mask) => (VSCALEFPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MulByPowOf2MaskedFloat32x16 x y mask) => (VSCALEFPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MulByPowOf2MaskedFloat64x2 x y mask) => (VSCALEFPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MulByPowOf2MaskedFloat64x4 x y mask) => (VSCALEFPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MulByPowOf2MaskedFloat64x8 x y mask) => (VSCALEFPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MulEvenWidenInt32x4 ...) => (VPMULDQ128 ...)
+(MulEvenWidenInt32x8 ...) => (VPMULDQ256 ...)
+(MulEvenWidenInt64x2 ...) => (VPMULDQ128 ...)
+(MulEvenWidenInt64x4 ...) => (VPMULDQ256 ...)
+(MulEvenWidenInt64x8 ...) => (VPMULDQ512 ...)
+(MulEvenWidenUint32x4 ...) => (VPMULUDQ128 ...)
+(MulEvenWidenUint32x8 ...) => (VPMULUDQ256 ...)
+(MulEvenWidenUint64x2 ...) => (VPMULUDQ128 ...)
+(MulEvenWidenUint64x4 ...) => (VPMULUDQ256 ...)
+(MulEvenWidenUint64x8 ...) => (VPMULUDQ512 ...)
+(MulEvenWidenMaskedInt64x2 x y mask) => (VPMULDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MulEvenWidenMaskedInt64x4 x y mask) => (VPMULDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MulEvenWidenMaskedInt64x8 x y mask) => (VPMULDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MulEvenWidenMaskedUint64x2 x y mask) => (VPMULUDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MulEvenWidenMaskedUint64x4 x y mask) => (VPMULUDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MulEvenWidenMaskedUint64x8 x y mask) => (VPMULUDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MulHighInt16x8 ...) => (VPMULHW128 ...)
+(MulHighInt16x16 ...) => (VPMULHW256 ...)
+(MulHighInt16x32 ...) => (VPMULHW512 ...)
+(MulHighUint16x8 ...) => (VPMULHUW128 ...)
+(MulHighUint16x16 ...) => (VPMULHUW256 ...)
+(MulHighUint16x32 ...) => (VPMULHUW512 ...)
+(MulHighMaskedInt16x8 x y mask) => (VPMULHWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MulHighMaskedInt16x16 x y mask) => (VPMULHWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MulHighMaskedInt16x32 x y mask) => (VPMULHWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MulHighMaskedUint16x8 x y mask) => (VPMULHUWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MulHighMaskedUint16x16 x y mask) => (VPMULHUWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MulHighMaskedUint16x32 x y mask) => (VPMULHUWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MulLowInt16x8 ...) => (VPMULLW128 ...)
+(MulLowInt16x16 ...) => (VPMULLW256 ...)
+(MulLowInt16x32 ...) => (VPMULLW512 ...)
+(MulLowInt32x4 ...) => (VPMULLD128 ...)
+(MulLowInt32x8 ...) => (VPMULLD256 ...)
+(MulLowInt32x16 ...) => (VPMULLD512 ...)
+(MulLowInt64x2 ...) => (VPMULLQ128 ...)
+(MulLowInt64x4 ...) => (VPMULLQ256 ...)
+(MulLowInt64x8 ...) => (VPMULLQ512 ...)
+(MulLowMaskedInt16x8 x y mask) => (VPMULLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MulLowMaskedInt16x16 x y mask) => (VPMULLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MulLowMaskedInt16x32 x y mask) => (VPMULLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MulLowMaskedInt32x4 x y mask) => (VPMULLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MulLowMaskedInt32x8 x y mask) => (VPMULLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MulLowMaskedInt32x16 x y mask) => (VPMULLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MulLowMaskedInt64x2 x y mask) => (VPMULLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MulLowMaskedInt64x4 x y mask) => (VPMULLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MulLowMaskedInt64x8 x y mask) => (VPMULLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MulMaskedFloat32x4 x y mask) => (VMULPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MulMaskedFloat32x8 x y mask) => (VMULPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MulMaskedFloat32x16 x y mask) => (VMULPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MulMaskedFloat64x2 x y mask) => (VMULPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MulMaskedFloat64x4 x y mask) => (VMULPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MulMaskedFloat64x8 x y mask) => (VMULPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(NotEqualFloat32x4 x y) => (VCMPPS128 [4] x y)
+(NotEqualFloat32x8 x y) => (VCMPPS256 [4] x y)
+(NotEqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [4] x y))
+(NotEqualFloat64x2 x y) => (VCMPPD128 [4] x y)
+(NotEqualFloat64x4 x y) => (VCMPPD256 [4] x y)
+(NotEqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [4] x y))
+(NotEqualInt8x16 x y) => (VPMOVMToVec8x16 (VPCMPB128 [4] x y))
+(NotEqualInt8x32 x y) => (VPMOVMToVec8x32 (VPCMPB256 [4] x y))
+(NotEqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [4] x y))
+(NotEqualInt16x8 x y) => (VPMOVMToVec16x8 (VPCMPW128 [4] x y))
+(NotEqualInt16x16 x y) => (VPMOVMToVec16x16 (VPCMPW256 [4] x y))
+(NotEqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [4] x y))
+(NotEqualInt32x4 x y) => (VPMOVMToVec32x4 (VPCMPD128 [4] x y))
+(NotEqualInt32x8 x y) => (VPMOVMToVec32x8 (VPCMPD256 [4] x y))
+(NotEqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [4] x y))
+(NotEqualInt64x2 x y) => (VPMOVMToVec64x2 (VPCMPQ128 [4] x y))
+(NotEqualInt64x4 x y) => (VPMOVMToVec64x4 (VPCMPQ256 [4] x y))
+(NotEqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [4] x y))
+(NotEqualUint8x16 x y) => (VPMOVMToVec8x16 (VPCMPUB128 [4] x y))
+(NotEqualUint8x32 x y) => (VPMOVMToVec8x32 (VPCMPUB256 [4] x y))
+(NotEqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [4] x y))
+(NotEqualUint16x8 x y) => (VPMOVMToVec16x8 (VPCMPUW128 [4] x y))
+(NotEqualUint16x16 x y) => (VPMOVMToVec16x16 (VPCMPUW256 [4] x y))
+(NotEqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [4] x y))
+(NotEqualUint32x4 x y) => (VPMOVMToVec32x4 (VPCMPUD128 [4] x y))
+(NotEqualUint32x8 x y) => (VPMOVMToVec32x8 (VPCMPUD256 [4] x y))
+(NotEqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [4] x y))
+(NotEqualUint64x2 x y) => (VPMOVMToVec64x2 (VPCMPUQ128 [4] x y))
+(NotEqualUint64x4 x y) => (VPMOVMToVec64x4 (VPCMPUQ256 [4] x y))
+(NotEqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [4] x y))
+(NotEqualMaskedFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [4] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(NotEqualMaskedFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [4] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(NotEqualMaskedFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [4] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(NotEqualMaskedFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [4] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(NotEqualMaskedFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [4] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(NotEqualMaskedFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [4] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(NotEqualMaskedInt8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPBMasked128 [4] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+(NotEqualMaskedInt8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPBMasked256 [4] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+(NotEqualMaskedInt8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPBMasked512 [4] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+(NotEqualMaskedInt16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPWMasked128 [4] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+(NotEqualMaskedInt16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPWMasked256 [4] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+(NotEqualMaskedInt16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPWMasked512 [4] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+(NotEqualMaskedInt32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPDMasked128 [4] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(NotEqualMaskedInt32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPDMasked256 [4] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(NotEqualMaskedInt32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPDMasked512 [4] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(NotEqualMaskedInt64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPQMasked128 [4] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(NotEqualMaskedInt64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPQMasked256 [4] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(NotEqualMaskedInt64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPQMasked512 [4] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(NotEqualMaskedUint8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPUBMasked128 [4] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+(NotEqualMaskedUint8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPUBMasked256 [4] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+(NotEqualMaskedUint8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPUBMasked512 [4] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+(NotEqualMaskedUint16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPUWMasked128 [4] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+(NotEqualMaskedUint16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPUWMasked256 [4] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+(NotEqualMaskedUint16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPUWMasked512 [4] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+(NotEqualMaskedUint32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPUDMasked128 [4] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+(NotEqualMaskedUint32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPUDMasked256 [4] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+(NotEqualMaskedUint32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPUDMasked512 [4] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+(NotEqualMaskedUint64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPUQMasked128 [4] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+(NotEqualMaskedUint64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPUQMasked256 [4] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+(NotEqualMaskedUint64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPUQMasked512 [4] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+(OrInt8x16 ...) => (VPOR128 ...)
+(OrInt8x32 ...) => (VPOR256 ...)
+(OrInt16x8 ...) => (VPOR128 ...)
+(OrInt16x16 ...) => (VPOR256 ...)
+(OrInt32x4 ...) => (VPOR128 ...)
+(OrInt32x8 ...) => (VPOR256 ...)
+(OrInt32x16 ...) => (VPORD512 ...)
+(OrInt64x2 ...) => (VPOR128 ...)
+(OrInt64x4 ...) => (VPOR256 ...)
+(OrInt64x8 ...) => (VPORQ512 ...)
+(OrUint8x16 ...) => (VPOR128 ...)
+(OrUint8x32 ...) => (VPOR256 ...)
+(OrUint16x8 ...) => (VPOR128 ...)
+(OrUint16x16 ...) => (VPOR256 ...)
+(OrUint32x4 ...) => (VPOR128 ...)
+(OrUint32x8 ...) => (VPOR256 ...)
+(OrUint32x16 ...) => (VPORD512 ...)
+(OrUint64x2 ...) => (VPOR128 ...)
+(OrUint64x4 ...) => (VPOR256 ...)
+(OrUint64x8 ...) => (VPORQ512 ...)
+(OrMaskedInt32x4 x y mask) => (VPORDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(OrMaskedInt32x8 x y mask) => (VPORDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(OrMaskedInt32x16 x y mask) => (VPORDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(OrMaskedInt64x2 x y mask) => (VPORQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(OrMaskedInt64x4 x y mask) => (VPORQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(OrMaskedInt64x8 x y mask) => (VPORQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(OrMaskedUint32x4 x y mask) => (VPORDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(OrMaskedUint32x8 x y mask) => (VPORDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(OrMaskedUint32x16 x y mask) => (VPORDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(OrMaskedUint64x2 x y mask) => (VPORQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(OrMaskedUint64x4 x y mask) => (VPORQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(OrMaskedUint64x8 x y mask) => (VPORQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(PairDotProdInt16x8 ...) => (VPMADDWD128 ...)
+(PairDotProdInt16x16 ...) => (VPMADDWD256 ...)
+(PairDotProdInt16x32 ...) => (VPMADDWD512 ...)
+(PairDotProdAccumulateInt32x4 ...) => (VPDPWSSD128 ...)
+(PairDotProdAccumulateInt32x8 ...) => (VPDPWSSD256 ...)
+(PairDotProdAccumulateInt32x16 ...) => (VPDPWSSD512 ...)
+(PairDotProdAccumulateMaskedInt32x4 x y z mask) => (VPDPWSSDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(PairDotProdAccumulateMaskedInt32x8 x y z mask) => (VPDPWSSDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(PairDotProdAccumulateMaskedInt32x16 x y z mask) => (VPDPWSSDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(PairDotProdMaskedInt16x8 x y mask) => (VPMADDWDMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(PairDotProdMaskedInt16x16 x y mask) => (VPMADDWDMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(PairDotProdMaskedInt16x32 x y mask) => (VPMADDWDMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(PairwiseAddFloat32x4 ...) => (VHADDPS128 ...)
+(PairwiseAddFloat32x8 ...) => (VHADDPS256 ...)
+(PairwiseAddFloat64x2 ...) => (VHADDPD128 ...)
+(PairwiseAddFloat64x4 ...) => (VHADDPD256 ...)
+(PairwiseAddInt16x8 ...) => (VPHADDW128 ...)
+(PairwiseAddInt16x16 ...) => (VPHADDW256 ...)
+(PairwiseAddInt32x4 ...) => (VPHADDD128 ...)
+(PairwiseAddInt32x8 ...) => (VPHADDD256 ...)
+(PairwiseAddUint16x8 ...) => (VPHADDW128 ...)
+(PairwiseAddUint16x16 ...) => (VPHADDW256 ...)
+(PairwiseAddUint32x4 ...) => (VPHADDD128 ...)
+(PairwiseAddUint32x8 ...) => (VPHADDD256 ...)
+(PairwiseSubFloat32x4 ...) => (VHSUBPS128 ...)
+(PairwiseSubFloat32x8 ...) => (VHSUBPS256 ...)
+(PairwiseSubFloat64x2 ...) => (VHSUBPD128 ...)
+(PairwiseSubFloat64x4 ...) => (VHSUBPD256 ...)
+(PairwiseSubInt16x8 ...) => (VPHSUBW128 ...)
+(PairwiseSubInt16x16 ...) => (VPHSUBW256 ...)
+(PairwiseSubInt32x4 ...) => (VPHSUBD128 ...)
+(PairwiseSubInt32x8 ...) => (VPHSUBD256 ...)
+(PairwiseSubUint16x8 ...) => (VPHSUBW128 ...)
+(PairwiseSubUint16x16 ...) => (VPHSUBW256 ...)
+(PairwiseSubUint32x4 ...) => (VPHSUBD128 ...)
+(PairwiseSubUint32x8 ...) => (VPHSUBD256 ...)
+(PermuteFloat32x8 ...) => (VPERMPS256 ...)
+(PermuteFloat32x16 ...) => (VPERMPS512 ...)
+(PermuteFloat64x4 ...) => (VPERMPD256 ...)
+(PermuteFloat64x8 ...) => (VPERMPD512 ...)
+(PermuteInt8x16 ...) => (VPERMB128 ...)
+(PermuteInt8x32 ...) => (VPERMB256 ...)
+(PermuteInt8x64 ...) => (VPERMB512 ...)
+(PermuteInt16x8 ...) => (VPERMW128 ...)
+(PermuteInt16x16 ...) => (VPERMW256 ...)
+(PermuteInt16x32 ...) => (VPERMW512 ...)
+(PermuteInt32x8 ...) => (VPERMD256 ...)
+(PermuteInt32x16 ...) => (VPERMD512 ...)
+(PermuteInt64x4 ...) => (VPERMQ256 ...)
+(PermuteInt64x8 ...) => (VPERMQ512 ...)
+(PermuteUint8x16 ...) => (VPERMB128 ...)
+(PermuteUint8x32 ...) => (VPERMB256 ...)
+(PermuteUint8x64 ...) => (VPERMB512 ...)
+(PermuteUint16x8 ...) => (VPERMW128 ...)
+(PermuteUint16x16 ...) => (VPERMW256 ...)
+(PermuteUint16x32 ...) => (VPERMW512 ...)
+(PermuteUint32x8 ...) => (VPERMD256 ...)
+(PermuteUint32x16 ...) => (VPERMD512 ...)
+(PermuteUint64x4 ...) => (VPERMQ256 ...)
+(PermuteUint64x8 ...) => (VPERMQ512 ...)
+(Permute2Float32x4 ...) => (VPERMI2PS128 ...)
+(Permute2Float32x8 ...) => (VPERMI2PS256 ...)
+(Permute2Float32x16 ...) => (VPERMI2PS512 ...)
+(Permute2Float64x2 ...) => (VPERMI2PD128 ...)
+(Permute2Float64x4 ...) => (VPERMI2PD256 ...)
+(Permute2Float64x8 ...) => (VPERMI2PD512 ...)
+(Permute2Int8x16 ...) => (VPERMI2B128 ...)
+(Permute2Int8x32 ...) => (VPERMI2B256 ...)
+(Permute2Int8x64 ...) => (VPERMI2B512 ...)
+(Permute2Int16x8 ...) => (VPERMI2W128 ...)
+(Permute2Int16x16 ...) => (VPERMI2W256 ...)
+(Permute2Int16x32 ...) => (VPERMI2W512 ...)
+(Permute2Int32x4 ...) => (VPERMI2D128 ...)
+(Permute2Int32x8 ...) => (VPERMI2D256 ...)
+(Permute2Int32x16 ...) => (VPERMI2D512 ...)
+(Permute2Int64x2 ...) => (VPERMI2Q128 ...)
+(Permute2Int64x4 ...) => (VPERMI2Q256 ...)
+(Permute2Int64x8 ...) => (VPERMI2Q512 ...)
+(Permute2Uint8x16 ...) => (VPERMI2B128 ...)
+(Permute2Uint8x32 ...) => (VPERMI2B256 ...)
+(Permute2Uint8x64 ...) => (VPERMI2B512 ...)
+(Permute2Uint16x8 ...) => (VPERMI2W128 ...)
+(Permute2Uint16x16 ...) => (VPERMI2W256 ...)
+(Permute2Uint16x32 ...) => (VPERMI2W512 ...)
+(Permute2Uint32x4 ...) => (VPERMI2D128 ...)
+(Permute2Uint32x8 ...) => (VPERMI2D256 ...)
+(Permute2Uint32x16 ...) => (VPERMI2D512 ...)
+(Permute2Uint64x2 ...) => (VPERMI2Q128 ...)
+(Permute2Uint64x4 ...) => (VPERMI2Q256 ...)
+(Permute2Uint64x8 ...) => (VPERMI2Q512 ...)
+(Permute2MaskedFloat32x4 x y z mask) => (VPERMI2PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(Permute2MaskedFloat32x8 x y z mask) => (VPERMI2PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(Permute2MaskedFloat32x16 x y z mask) => (VPERMI2PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(Permute2MaskedFloat64x2 x y z mask) => (VPERMI2PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(Permute2MaskedFloat64x4 x y z mask) => (VPERMI2PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(Permute2MaskedFloat64x8 x y z mask) => (VPERMI2PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(Permute2MaskedInt8x16 x y z mask) => (VPERMI2BMasked128 x y z (VPMOVVec8x16ToM <types.TypeMask> mask))
+(Permute2MaskedInt8x32 x y z mask) => (VPERMI2BMasked256 x y z (VPMOVVec8x32ToM <types.TypeMask> mask))
+(Permute2MaskedInt8x64 x y z mask) => (VPERMI2BMasked512 x y z (VPMOVVec8x64ToM <types.TypeMask> mask))
+(Permute2MaskedInt16x8 x y z mask) => (VPERMI2WMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+(Permute2MaskedInt16x16 x y z mask) => (VPERMI2WMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+(Permute2MaskedInt16x32 x y z mask) => (VPERMI2WMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+(Permute2MaskedInt32x4 x y z mask) => (VPERMI2DMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(Permute2MaskedInt32x8 x y z mask) => (VPERMI2DMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(Permute2MaskedInt32x16 x y z mask) => (VPERMI2DMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(Permute2MaskedInt64x2 x y z mask) => (VPERMI2QMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(Permute2MaskedInt64x4 x y z mask) => (VPERMI2QMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(Permute2MaskedInt64x8 x y z mask) => (VPERMI2QMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(Permute2MaskedUint8x16 x y z mask) => (VPERMI2BMasked128 x y z (VPMOVVec8x16ToM <types.TypeMask> mask))
+(Permute2MaskedUint8x32 x y z mask) => (VPERMI2BMasked256 x y z (VPMOVVec8x32ToM <types.TypeMask> mask))
+(Permute2MaskedUint8x64 x y z mask) => (VPERMI2BMasked512 x y z (VPMOVVec8x64ToM <types.TypeMask> mask))
+(Permute2MaskedUint16x8 x y z mask) => (VPERMI2WMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+(Permute2MaskedUint16x16 x y z mask) => (VPERMI2WMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+(Permute2MaskedUint16x32 x y z mask) => (VPERMI2WMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+(Permute2MaskedUint32x4 x y z mask) => (VPERMI2DMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(Permute2MaskedUint32x8 x y z mask) => (VPERMI2DMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(Permute2MaskedUint32x16 x y z mask) => (VPERMI2DMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(Permute2MaskedUint64x2 x y z mask) => (VPERMI2QMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(Permute2MaskedUint64x4 x y z mask) => (VPERMI2QMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(Permute2MaskedUint64x8 x y z mask) => (VPERMI2QMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(PermuteMaskedFloat32x8 x y mask) => (VPERMPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(PermuteMaskedFloat32x16 x y mask) => (VPERMPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(PermuteMaskedFloat64x4 x y mask) => (VPERMPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(PermuteMaskedFloat64x8 x y mask) => (VPERMPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(PermuteMaskedInt8x16 x y mask) => (VPERMBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(PermuteMaskedInt8x32 x y mask) => (VPERMBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(PermuteMaskedInt8x64 x y mask) => (VPERMBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(PermuteMaskedInt16x8 x y mask) => (VPERMWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(PermuteMaskedInt16x16 x y mask) => (VPERMWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(PermuteMaskedInt16x32 x y mask) => (VPERMWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(PermuteMaskedInt32x8 x y mask) => (VPERMDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(PermuteMaskedInt32x16 x y mask) => (VPERMDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(PermuteMaskedInt64x4 x y mask) => (VPERMQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(PermuteMaskedInt64x8 x y mask) => (VPERMQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(PermuteMaskedUint8x16 x y mask) => (VPERMBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(PermuteMaskedUint8x32 x y mask) => (VPERMBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(PermuteMaskedUint8x64 x y mask) => (VPERMBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(PermuteMaskedUint16x8 x y mask) => (VPERMWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(PermuteMaskedUint16x16 x y mask) => (VPERMWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(PermuteMaskedUint16x32 x y mask) => (VPERMWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(PermuteMaskedUint32x8 x y mask) => (VPERMDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(PermuteMaskedUint32x16 x y mask) => (VPERMDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(PermuteMaskedUint64x4 x y mask) => (VPERMQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(PermuteMaskedUint64x8 x y mask) => (VPERMQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(PopCountInt8x16 ...) => (VPOPCNTB128 ...)
+(PopCountInt8x32 ...) => (VPOPCNTB256 ...)
+(PopCountInt8x64 ...) => (VPOPCNTB512 ...)
+(PopCountInt16x8 ...) => (VPOPCNTW128 ...)
+(PopCountInt16x16 ...) => (VPOPCNTW256 ...)
+(PopCountInt16x32 ...) => (VPOPCNTW512 ...)
+(PopCountInt32x4 ...) => (VPOPCNTD128 ...)
+(PopCountInt32x8 ...) => (VPOPCNTD256 ...)
+(PopCountInt32x16 ...) => (VPOPCNTD512 ...)
+(PopCountInt64x2 ...) => (VPOPCNTQ128 ...)
+(PopCountInt64x4 ...) => (VPOPCNTQ256 ...)
+(PopCountInt64x8 ...) => (VPOPCNTQ512 ...)
+(PopCountUint8x16 ...) => (VPOPCNTB128 ...)
+(PopCountUint8x32 ...) => (VPOPCNTB256 ...)
+(PopCountUint8x64 ...) => (VPOPCNTB512 ...)
+(PopCountUint16x8 ...) => (VPOPCNTW128 ...)
+(PopCountUint16x16 ...) => (VPOPCNTW256 ...)
+(PopCountUint16x32 ...) => (VPOPCNTW512 ...)
+(PopCountUint32x4 ...) => (VPOPCNTD128 ...)
+(PopCountUint32x8 ...) => (VPOPCNTD256 ...)
+(PopCountUint32x16 ...) => (VPOPCNTD512 ...)
+(PopCountUint64x2 ...) => (VPOPCNTQ128 ...)
+(PopCountUint64x4 ...) => (VPOPCNTQ256 ...)
+(PopCountUint64x8 ...) => (VPOPCNTQ512 ...)
+(PopCountMaskedInt8x16 x mask) => (VPOPCNTBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
+(PopCountMaskedInt8x32 x mask) => (VPOPCNTBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
+(PopCountMaskedInt8x64 x mask) => (VPOPCNTBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
+(PopCountMaskedInt16x8 x mask) => (VPOPCNTWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
+(PopCountMaskedInt16x16 x mask) => (VPOPCNTWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
+(PopCountMaskedInt16x32 x mask) => (VPOPCNTWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
+(PopCountMaskedInt32x4 x mask) => (VPOPCNTDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(PopCountMaskedInt32x8 x mask) => (VPOPCNTDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(PopCountMaskedInt32x16 x mask) => (VPOPCNTDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(PopCountMaskedInt64x2 x mask) => (VPOPCNTQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(PopCountMaskedInt64x4 x mask) => (VPOPCNTQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(PopCountMaskedInt64x8 x mask) => (VPOPCNTQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(PopCountMaskedUint8x16 x mask) => (VPOPCNTBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
+(PopCountMaskedUint8x32 x mask) => (VPOPCNTBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
+(PopCountMaskedUint8x64 x mask) => (VPOPCNTBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
+(PopCountMaskedUint16x8 x mask) => (VPOPCNTWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
+(PopCountMaskedUint16x16 x mask) => (VPOPCNTWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
+(PopCountMaskedUint16x32 x mask) => (VPOPCNTWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
+(PopCountMaskedUint32x4 x mask) => (VPOPCNTDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(PopCountMaskedUint32x8 x mask) => (VPOPCNTDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(PopCountMaskedUint32x16 x mask) => (VPOPCNTDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(PopCountMaskedUint64x2 x mask) => (VPOPCNTQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(PopCountMaskedUint64x4 x mask) => (VPOPCNTQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(PopCountMaskedUint64x8 x mask) => (VPOPCNTQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(RotateAllLeftInt32x4 ...) => (VPROLD128 ...)
+(RotateAllLeftInt32x8 ...) => (VPROLD256 ...)
+(RotateAllLeftInt32x16 ...) => (VPROLD512 ...)
+(RotateAllLeftInt64x2 ...) => (VPROLQ128 ...)
+(RotateAllLeftInt64x4 ...) => (VPROLQ256 ...)
+(RotateAllLeftInt64x8 ...) => (VPROLQ512 ...)
+(RotateAllLeftUint32x4 ...) => (VPROLD128 ...)
+(RotateAllLeftUint32x8 ...) => (VPROLD256 ...)
+(RotateAllLeftUint32x16 ...) => (VPROLD512 ...)
+(RotateAllLeftUint64x2 ...) => (VPROLQ128 ...)
+(RotateAllLeftUint64x4 ...) => (VPROLQ256 ...)
+(RotateAllLeftUint64x8 ...) => (VPROLQ512 ...)
+(RotateAllLeftMaskedInt32x4 [a] x mask) => (VPROLDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(RotateAllLeftMaskedInt32x8 [a] x mask) => (VPROLDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(RotateAllLeftMaskedInt32x16 [a] x mask) => (VPROLDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(RotateAllLeftMaskedInt64x2 [a] x mask) => (VPROLQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(RotateAllLeftMaskedInt64x4 [a] x mask) => (VPROLQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(RotateAllLeftMaskedInt64x8 [a] x mask) => (VPROLQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(RotateAllLeftMaskedUint32x4 [a] x mask) => (VPROLDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(RotateAllLeftMaskedUint32x8 [a] x mask) => (VPROLDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(RotateAllLeftMaskedUint32x16 [a] x mask) => (VPROLDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(RotateAllLeftMaskedUint64x2 [a] x mask) => (VPROLQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(RotateAllLeftMaskedUint64x4 [a] x mask) => (VPROLQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(RotateAllLeftMaskedUint64x8 [a] x mask) => (VPROLQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(RotateAllRightInt32x4 ...) => (VPRORD128 ...)
+(RotateAllRightInt32x8 ...) => (VPRORD256 ...)
+(RotateAllRightInt32x16 ...) => (VPRORD512 ...)
+(RotateAllRightInt64x2 ...) => (VPRORQ128 ...)
+(RotateAllRightInt64x4 ...) => (VPRORQ256 ...)
+(RotateAllRightInt64x8 ...) => (VPRORQ512 ...)
+(RotateAllRightUint32x4 ...) => (VPRORD128 ...)
+(RotateAllRightUint32x8 ...) => (VPRORD256 ...)
+(RotateAllRightUint32x16 ...) => (VPRORD512 ...)
+(RotateAllRightUint64x2 ...) => (VPRORQ128 ...)
+(RotateAllRightUint64x4 ...) => (VPRORQ256 ...)
+(RotateAllRightUint64x8 ...) => (VPRORQ512 ...)
+(RotateAllRightMaskedInt32x4 [a] x mask) => (VPRORDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(RotateAllRightMaskedInt32x8 [a] x mask) => (VPRORDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(RotateAllRightMaskedInt32x16 [a] x mask) => (VPRORDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(RotateAllRightMaskedInt64x2 [a] x mask) => (VPRORQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(RotateAllRightMaskedInt64x4 [a] x mask) => (VPRORQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(RotateAllRightMaskedInt64x8 [a] x mask) => (VPRORQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(RotateAllRightMaskedUint32x4 [a] x mask) => (VPRORDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(RotateAllRightMaskedUint32x8 [a] x mask) => (VPRORDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(RotateAllRightMaskedUint32x16 [a] x mask) => (VPRORDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(RotateAllRightMaskedUint64x2 [a] x mask) => (VPRORQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(RotateAllRightMaskedUint64x4 [a] x mask) => (VPRORQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(RotateAllRightMaskedUint64x8 [a] x mask) => (VPRORQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(RotateLeftInt32x4 ...) => (VPROLVD128 ...)
+(RotateLeftInt32x8 ...) => (VPROLVD256 ...)
+(RotateLeftInt32x16 ...) => (VPROLVD512 ...)
+(RotateLeftInt64x2 ...) => (VPROLVQ128 ...)
+(RotateLeftInt64x4 ...) => (VPROLVQ256 ...)
+(RotateLeftInt64x8 ...) => (VPROLVQ512 ...)
+(RotateLeftUint32x4 ...) => (VPROLVD128 ...)
+(RotateLeftUint32x8 ...) => (VPROLVD256 ...)
+(RotateLeftUint32x16 ...) => (VPROLVD512 ...)
+(RotateLeftUint64x2 ...) => (VPROLVQ128 ...)
+(RotateLeftUint64x4 ...) => (VPROLVQ256 ...)
+(RotateLeftUint64x8 ...) => (VPROLVQ512 ...)
+(RotateLeftMaskedInt32x4 x y mask) => (VPROLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(RotateLeftMaskedInt32x8 x y mask) => (VPROLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(RotateLeftMaskedInt32x16 x y mask) => (VPROLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(RotateLeftMaskedInt64x2 x y mask) => (VPROLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(RotateLeftMaskedInt64x4 x y mask) => (VPROLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(RotateLeftMaskedInt64x8 x y mask) => (VPROLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(RotateLeftMaskedUint32x4 x y mask) => (VPROLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(RotateLeftMaskedUint32x8 x y mask) => (VPROLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(RotateLeftMaskedUint32x16 x y mask) => (VPROLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(RotateLeftMaskedUint64x2 x y mask) => (VPROLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(RotateLeftMaskedUint64x4 x y mask) => (VPROLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(RotateLeftMaskedUint64x8 x y mask) => (VPROLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(RotateRightInt32x4 ...) => (VPRORVD128 ...)
+(RotateRightInt32x8 ...) => (VPRORVD256 ...)
+(RotateRightInt32x16 ...) => (VPRORVD512 ...)
+(RotateRightInt64x2 ...) => (VPRORVQ128 ...)
+(RotateRightInt64x4 ...) => (VPRORVQ256 ...)
+(RotateRightInt64x8 ...) => (VPRORVQ512 ...)
+(RotateRightUint32x4 ...) => (VPRORVD128 ...)
+(RotateRightUint32x8 ...) => (VPRORVD256 ...)
+(RotateRightUint32x16 ...) => (VPRORVD512 ...)
+(RotateRightUint64x2 ...) => (VPRORVQ128 ...)
+(RotateRightUint64x4 ...) => (VPRORVQ256 ...)
+(RotateRightUint64x8 ...) => (VPRORVQ512 ...)
+(RotateRightMaskedInt32x4 x y mask) => (VPRORVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(RotateRightMaskedInt32x8 x y mask) => (VPRORVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(RotateRightMaskedInt32x16 x y mask) => (VPRORVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(RotateRightMaskedInt64x2 x y mask) => (VPRORVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(RotateRightMaskedInt64x4 x y mask) => (VPRORVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(RotateRightMaskedInt64x8 x y mask) => (VPRORVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(RotateRightMaskedUint32x4 x y mask) => (VPRORVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(RotateRightMaskedUint32x8 x y mask) => (VPRORVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(RotateRightMaskedUint32x16 x y mask) => (VPRORVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(RotateRightMaskedUint64x2 x y mask) => (VPRORVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(RotateRightMaskedUint64x4 x y mask) => (VPRORVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(RotateRightMaskedUint64x8 x y mask) => (VPRORVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(RoundFloat32x4 x) => (VROUNDPS128 [0] x)
+(RoundFloat32x8 x) => (VROUNDPS256 [0] x)
+(RoundFloat64x2 x) => (VROUNDPD128 [0] x)
+(RoundFloat64x4 x) => (VROUNDPD256 [0] x)
+(RoundWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+0] x)
+(RoundWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+0] x)
+(RoundWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+0] x)
+(RoundWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+0] x)
+(RoundWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+0] x)
+(RoundWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+0] x)
+(RoundWithPrecisionMaskedFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+0] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(RoundWithPrecisionMaskedFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+0] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(RoundWithPrecisionMaskedFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+0] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(RoundWithPrecisionMaskedFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+0] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(RoundWithPrecisionMaskedFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+0] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(RoundWithPrecisionMaskedFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+0] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(SaturatedAddInt8x16 ...) => (VPADDSB128 ...)
+(SaturatedAddInt8x32 ...) => (VPADDSB256 ...)
+(SaturatedAddInt8x64 ...) => (VPADDSB512 ...)
+(SaturatedAddInt16x8 ...) => (VPADDSW128 ...)
+(SaturatedAddInt16x16 ...) => (VPADDSW256 ...)
+(SaturatedAddInt16x32 ...) => (VPADDSW512 ...)
+(SaturatedAddUint8x16 ...) => (VPADDSB128 ...)
+(SaturatedAddUint8x32 ...) => (VPADDSB256 ...)
+(SaturatedAddUint8x64 ...) => (VPADDSB512 ...)
+(SaturatedAddUint16x8 ...) => (VPADDSW128 ...)
+(SaturatedAddUint16x16 ...) => (VPADDSW256 ...)
+(SaturatedAddUint16x32 ...) => (VPADDSW512 ...)
+(SaturatedAddMaskedInt8x16 x y mask) => (VPADDSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(SaturatedAddMaskedInt8x32 x y mask) => (VPADDSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(SaturatedAddMaskedInt8x64 x y mask) => (VPADDSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(SaturatedAddMaskedInt16x8 x y mask) => (VPADDSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(SaturatedAddMaskedInt16x16 x y mask) => (VPADDSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(SaturatedAddMaskedInt16x32 x y mask) => (VPADDSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(SaturatedAddMaskedUint8x16 x y mask) => (VPADDSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(SaturatedAddMaskedUint8x32 x y mask) => (VPADDSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(SaturatedAddMaskedUint8x64 x y mask) => (VPADDSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(SaturatedAddMaskedUint16x8 x y mask) => (VPADDSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(SaturatedAddMaskedUint16x16 x y mask) => (VPADDSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(SaturatedAddMaskedUint16x32 x y mask) => (VPADDSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(SaturatedPairDotProdAccumulateInt32x4 ...) => (VPDPWSSDS128 ...)
+(SaturatedPairDotProdAccumulateInt32x8 ...) => (VPDPWSSDS256 ...)
+(SaturatedPairDotProdAccumulateInt32x16 ...) => (VPDPWSSDS512 ...)
+(SaturatedPairDotProdAccumulateMaskedInt32x4 x y z mask) => (VPDPWSSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(SaturatedPairDotProdAccumulateMaskedInt32x8 x y z mask) => (VPDPWSSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(SaturatedPairDotProdAccumulateMaskedInt32x16 x y z mask) => (VPDPWSSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(SaturatedPairwiseAddInt16x8 ...) => (VPHADDSW128 ...)
+(SaturatedPairwiseAddInt16x16 ...) => (VPHADDSW256 ...)
+(SaturatedPairwiseSubInt16x8 ...) => (VPHSUBSW128 ...)
+(SaturatedPairwiseSubInt16x16 ...) => (VPHSUBSW256 ...)
+(SaturatedSubInt8x16 ...) => (VPSUBSB128 ...)
+(SaturatedSubInt8x32 ...) => (VPSUBSB256 ...)
+(SaturatedSubInt8x64 ...) => (VPSUBSB512 ...)
+(SaturatedSubInt16x8 ...) => (VPSUBSW128 ...)
+(SaturatedSubInt16x16 ...) => (VPSUBSW256 ...)
+(SaturatedSubInt16x32 ...) => (VPSUBSW512 ...)
+(SaturatedSubUint8x16 ...) => (VPSUBSB128 ...)
+(SaturatedSubUint8x32 ...) => (VPSUBSB256 ...)
+(SaturatedSubUint8x64 ...) => (VPSUBSB512 ...)
+(SaturatedSubUint16x8 ...) => (VPSUBSW128 ...)
+(SaturatedSubUint16x16 ...) => (VPSUBSW256 ...)
+(SaturatedSubUint16x32 ...) => (VPSUBSW512 ...)
+(SaturatedSubMaskedInt8x16 x y mask) => (VPSUBSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(SaturatedSubMaskedInt8x32 x y mask) => (VPSUBSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(SaturatedSubMaskedInt8x64 x y mask) => (VPSUBSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(SaturatedSubMaskedInt16x8 x y mask) => (VPSUBSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(SaturatedSubMaskedInt16x16 x y mask) => (VPSUBSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(SaturatedSubMaskedInt16x32 x y mask) => (VPSUBSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(SaturatedSubMaskedUint8x16 x y mask) => (VPSUBSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(SaturatedSubMaskedUint8x32 x y mask) => (VPSUBSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(SaturatedSubMaskedUint8x64 x y mask) => (VPSUBSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(SaturatedSubMaskedUint16x8 x y mask) => (VPSUBSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(SaturatedSubMaskedUint16x16 x y mask) => (VPSUBSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(SaturatedSubMaskedUint16x32 x y mask) => (VPSUBSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(SaturatedUnsignedSignedPairDotProdUint8x16 ...) => (VPMADDUBSW128 ...)
+(SaturatedUnsignedSignedPairDotProdUint8x32 ...) => (VPMADDUBSW256 ...)
+(SaturatedUnsignedSignedPairDotProdUint8x64 ...) => (VPMADDUBSW512 ...)
+(SaturatedUnsignedSignedPairDotProdMaskedUint8x16 x y mask) => (VPMADDUBSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(SaturatedUnsignedSignedPairDotProdMaskedUint8x32 x y mask) => (VPMADDUBSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(SaturatedUnsignedSignedPairDotProdMaskedUint8x64 x y mask) => (VPMADDUBSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4 ...) => (VPDPBUSDS128 ...)
+(SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8 ...) => (VPDPBUSDS256 ...)
+(SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16 ...) => (VPDPBUSDS512 ...)
+(SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4 x y z mask) => (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x8 x y z mask) => (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x16 x y z mask) => (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(Set128Float32x8 ...) => (VINSERTF128256 ...)
+(Set128Float64x4 ...) => (VINSERTF128256 ...)
+(Set128Int8x32 ...) => (VINSERTI128256 ...)
+(Set128Int16x16 ...) => (VINSERTI128256 ...)
+(Set128Int32x8 ...) => (VINSERTI128256 ...)
+(Set128Int64x4 ...) => (VINSERTI128256 ...)
+(Set128Uint8x32 ...) => (VINSERTI128256 ...)
+(Set128Uint16x16 ...) => (VINSERTI128256 ...)
+(Set128Uint32x8 ...) => (VINSERTI128256 ...)
+(Set128Uint64x4 ...) => (VINSERTI128256 ...)
+(SetElemInt8x16 ...) => (VPINSRB128 ...)
+(SetElemInt16x8 ...) => (VPINSRW128 ...)
+(SetElemInt32x4 ...) => (VPINSRD128 ...)
+(SetElemInt64x2 ...) => (VPINSRQ128 ...)
+(SetElemUint8x16 ...) => (VPINSRB128 ...)
+(SetElemUint16x8 ...) => (VPINSRW128 ...)
+(SetElemUint32x4 ...) => (VPINSRD128 ...)
+(SetElemUint64x2 ...) => (VPINSRQ128 ...)
+(ShiftAllLeftInt16x8 ...) => (VPSLLW128 ...)
+(ShiftAllLeftInt16x16 ...) => (VPSLLW256 ...)
+(ShiftAllLeftInt16x32 ...) => (VPSLLW512 ...)
+(ShiftAllLeftInt32x4 ...) => (VPSLLD128 ...)
+(ShiftAllLeftInt32x8 ...) => (VPSLLD256 ...)
+(ShiftAllLeftInt32x16 ...) => (VPSLLD512 ...)
+(ShiftAllLeftInt64x2 ...) => (VPSLLQ128 ...)
+(ShiftAllLeftInt64x4 ...) => (VPSLLQ256 ...)
+(ShiftAllLeftInt64x8 ...) => (VPSLLQ512 ...)
+(ShiftAllLeftUint16x8 ...) => (VPSLLW128 ...)
+(ShiftAllLeftUint16x16 ...) => (VPSLLW256 ...)
+(ShiftAllLeftUint16x32 ...) => (VPSLLW512 ...)
+(ShiftAllLeftUint32x4 ...) => (VPSLLD128 ...)
+(ShiftAllLeftUint32x8 ...) => (VPSLLD256 ...)
+(ShiftAllLeftUint32x16 ...) => (VPSLLD512 ...)
+(ShiftAllLeftUint64x2 ...) => (VPSLLQ128 ...)
+(ShiftAllLeftUint64x4 ...) => (VPSLLQ256 ...)
+(ShiftAllLeftUint64x8 ...) => (VPSLLQ512 ...)
+(ShiftAllLeftAndFillUpperFromInt16x8 ...) => (VPSHLDW128 ...)
+(ShiftAllLeftAndFillUpperFromInt16x16 ...) => (VPSHLDW256 ...)
+(ShiftAllLeftAndFillUpperFromInt16x32 ...) => (VPSHLDW512 ...)
+(ShiftAllLeftAndFillUpperFromInt32x4 ...) => (VPSHLDD128 ...)
+(ShiftAllLeftAndFillUpperFromInt32x8 ...) => (VPSHLDD256 ...)
+(ShiftAllLeftAndFillUpperFromInt32x16 ...) => (VPSHLDD512 ...)
+(ShiftAllLeftAndFillUpperFromInt64x2 ...) => (VPSHLDQ128 ...)
+(ShiftAllLeftAndFillUpperFromInt64x4 ...) => (VPSHLDQ256 ...)
+(ShiftAllLeftAndFillUpperFromInt64x8 ...) => (VPSHLDQ512 ...)
+(ShiftAllLeftAndFillUpperFromUint16x8 ...) => (VPSHLDW128 ...)
+(ShiftAllLeftAndFillUpperFromUint16x16 ...) => (VPSHLDW256 ...)
+(ShiftAllLeftAndFillUpperFromUint16x32 ...) => (VPSHLDW512 ...)
+(ShiftAllLeftAndFillUpperFromUint32x4 ...) => (VPSHLDD128 ...)
+(ShiftAllLeftAndFillUpperFromUint32x8 ...) => (VPSHLDD256 ...)
+(ShiftAllLeftAndFillUpperFromUint32x16 ...) => (VPSHLDD512 ...)
+(ShiftAllLeftAndFillUpperFromUint64x2 ...) => (VPSHLDQ128 ...)
+(ShiftAllLeftAndFillUpperFromUint64x4 ...) => (VPSHLDQ256 ...)
+(ShiftAllLeftAndFillUpperFromUint64x8 ...) => (VPSHLDQ512 ...)
+(ShiftAllLeftAndFillUpperFromMaskedInt16x8 [a] x y mask) => (VPSHLDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedInt16x16 [a] x y mask) => (VPSHLDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedInt16x32 [a] x y mask) => (VPSHLDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedInt32x4 [a] x y mask) => (VPSHLDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedInt32x8 [a] x y mask) => (VPSHLDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedInt32x16 [a] x y mask) => (VPSHLDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedInt64x2 [a] x y mask) => (VPSHLDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedInt64x4 [a] x y mask) => (VPSHLDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedInt64x8 [a] x y mask) => (VPSHLDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedUint16x8 [a] x y mask) => (VPSHLDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedUint16x16 [a] x y mask) => (VPSHLDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedUint16x32 [a] x y mask) => (VPSHLDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedUint32x4 [a] x y mask) => (VPSHLDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedUint32x8 [a] x y mask) => (VPSHLDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedUint32x16 [a] x y mask) => (VPSHLDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedUint64x2 [a] x y mask) => (VPSHLDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedUint64x4 [a] x y mask) => (VPSHLDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftAllLeftAndFillUpperFromMaskedUint64x8 [a] x y mask) => (VPSHLDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedInt16x8 x y mask) => (VPSLLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedInt16x16 x y mask) => (VPSLLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedInt16x32 x y mask) => (VPSLLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedInt32x4 x y mask) => (VPSLLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedInt32x8 x y mask) => (VPSLLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedInt32x16 x y mask) => (VPSLLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedInt64x2 x y mask) => (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedInt64x4 x y mask) => (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedInt64x8 x y mask) => (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedUint16x8 x y mask) => (VPSLLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedUint16x16 x y mask) => (VPSLLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedUint16x32 x y mask) => (VPSLLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedUint32x4 x y mask) => (VPSLLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedUint32x8 x y mask) => (VPSLLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedUint32x16 x y mask) => (VPSLLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedUint64x2 x y mask) => (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedUint64x4 x y mask) => (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftAllLeftMaskedUint64x8 x y mask) => (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftAllRightInt16x8 ...) => (VPSRAW128 ...)
+(ShiftAllRightInt16x16 ...) => (VPSRAW256 ...)
+(ShiftAllRightInt16x32 ...) => (VPSRAW512 ...)
+(ShiftAllRightInt32x4 ...) => (VPSRAD128 ...)
+(ShiftAllRightInt32x8 ...) => (VPSRAD256 ...)
+(ShiftAllRightInt32x16 ...) => (VPSRAD512 ...)
+(ShiftAllRightInt64x2 ...) => (VPSRAQ128 ...)
+(ShiftAllRightInt64x4 ...) => (VPSRAQ256 ...)
+(ShiftAllRightInt64x8 ...) => (VPSRAQ512 ...)
+(ShiftAllRightUint16x8 ...) => (VPSRLW128 ...)
+(ShiftAllRightUint16x16 ...) => (VPSRLW256 ...)
+(ShiftAllRightUint16x32 ...) => (VPSRLW512 ...)
+(ShiftAllRightUint32x4 ...) => (VPSRLD128 ...)
+(ShiftAllRightUint32x8 ...) => (VPSRLD256 ...)
+(ShiftAllRightUint32x16 ...) => (VPSRLD512 ...)
+(ShiftAllRightUint64x2 ...) => (VPSRLQ128 ...)
+(ShiftAllRightUint64x4 ...) => (VPSRLQ256 ...)
+(ShiftAllRightUint64x8 ...) => (VPSRLQ512 ...)
+(ShiftAllRightAndFillUpperFromInt16x8 ...) => (VPSHRDW128 ...)
+(ShiftAllRightAndFillUpperFromInt16x16 ...) => (VPSHRDW256 ...)
+(ShiftAllRightAndFillUpperFromInt16x32 ...) => (VPSHRDW512 ...)
+(ShiftAllRightAndFillUpperFromInt32x4 ...) => (VPSHRDD128 ...)
+(ShiftAllRightAndFillUpperFromInt32x8 ...) => (VPSHRDD256 ...)
+(ShiftAllRightAndFillUpperFromInt32x16 ...) => (VPSHRDD512 ...)
+(ShiftAllRightAndFillUpperFromInt64x2 ...) => (VPSHRDQ128 ...)
+(ShiftAllRightAndFillUpperFromInt64x4 ...) => (VPSHRDQ256 ...)
+(ShiftAllRightAndFillUpperFromInt64x8 ...) => (VPSHRDQ512 ...)
+(ShiftAllRightAndFillUpperFromUint16x8 ...) => (VPSHRDW128 ...)
+(ShiftAllRightAndFillUpperFromUint16x16 ...) => (VPSHRDW256 ...)
+(ShiftAllRightAndFillUpperFromUint16x32 ...) => (VPSHRDW512 ...)
+(ShiftAllRightAndFillUpperFromUint32x4 ...) => (VPSHRDD128 ...)
+(ShiftAllRightAndFillUpperFromUint32x8 ...) => (VPSHRDD256 ...)
+(ShiftAllRightAndFillUpperFromUint32x16 ...) => (VPSHRDD512 ...)
+(ShiftAllRightAndFillUpperFromUint64x2 ...) => (VPSHRDQ128 ...)
+(ShiftAllRightAndFillUpperFromUint64x4 ...) => (VPSHRDQ256 ...)
+(ShiftAllRightAndFillUpperFromUint64x8 ...) => (VPSHRDQ512 ...)
+(ShiftAllRightAndFillUpperFromMaskedInt16x8 [a] x y mask) => (VPSHRDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedInt16x16 [a] x y mask) => (VPSHRDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedInt16x32 [a] x y mask) => (VPSHRDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedInt32x4 [a] x y mask) => (VPSHRDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedInt32x8 [a] x y mask) => (VPSHRDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedInt32x16 [a] x y mask) => (VPSHRDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedInt64x2 [a] x y mask) => (VPSHRDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedInt64x4 [a] x y mask) => (VPSHRDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedInt64x8 [a] x y mask) => (VPSHRDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedUint16x8 [a] x y mask) => (VPSHRDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedUint16x16 [a] x y mask) => (VPSHRDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedUint16x32 [a] x y mask) => (VPSHRDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedUint32x4 [a] x y mask) => (VPSHRDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedUint32x8 [a] x y mask) => (VPSHRDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedUint32x16 [a] x y mask) => (VPSHRDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedUint64x2 [a] x y mask) => (VPSHRDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedUint64x4 [a] x y mask) => (VPSHRDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftAllRightAndFillUpperFromMaskedUint64x8 [a] x y mask) => (VPSHRDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedInt16x8 x y mask) => (VPSRAWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedInt16x16 x y mask) => (VPSRAWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedInt16x32 x y mask) => (VPSRAWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedInt32x4 x y mask) => (VPSRADMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedInt32x8 x y mask) => (VPSRADMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedInt32x16 x y mask) => (VPSRADMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedInt64x2 x y mask) => (VPSRAQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedInt64x4 x y mask) => (VPSRAQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedInt64x8 x y mask) => (VPSRAQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedUint16x8 x y mask) => (VPSRLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedUint16x16 x y mask) => (VPSRLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedUint16x32 x y mask) => (VPSRLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedUint32x4 x y mask) => (VPSRLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedUint32x8 x y mask) => (VPSRLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedUint32x16 x y mask) => (VPSRLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedUint64x2 x y mask) => (VPSRLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedUint64x4 x y mask) => (VPSRLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftAllRightMaskedUint64x8 x y mask) => (VPSRLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftLeftInt16x8 ...) => (VPSLLVW128 ...)
+(ShiftLeftInt16x16 ...) => (VPSLLVW256 ...)
+(ShiftLeftInt16x32 ...) => (VPSLLVW512 ...)
+(ShiftLeftInt32x4 ...) => (VPSLLVD128 ...)
+(ShiftLeftInt32x8 ...) => (VPSLLVD256 ...)
+(ShiftLeftInt32x16 ...) => (VPSLLVD512 ...)
+(ShiftLeftInt64x2 ...) => (VPSLLVQ128 ...)
+(ShiftLeftInt64x4 ...) => (VPSLLVQ256 ...)
+(ShiftLeftInt64x8 ...) => (VPSLLVQ512 ...)
+(ShiftLeftUint16x8 ...) => (VPSLLVW128 ...)
+(ShiftLeftUint16x16 ...) => (VPSLLVW256 ...)
+(ShiftLeftUint16x32 ...) => (VPSLLVW512 ...)
+(ShiftLeftUint32x4 ...) => (VPSLLVD128 ...)
+(ShiftLeftUint32x8 ...) => (VPSLLVD256 ...)
+(ShiftLeftUint32x16 ...) => (VPSLLVD512 ...)
+(ShiftLeftUint64x2 ...) => (VPSLLVQ128 ...)
+(ShiftLeftUint64x4 ...) => (VPSLLVQ256 ...)
+(ShiftLeftUint64x8 ...) => (VPSLLVQ512 ...)
+(ShiftLeftAndFillUpperFromInt16x8 ...) => (VPSHLDVW128 ...)
+(ShiftLeftAndFillUpperFromInt16x16 ...) => (VPSHLDVW256 ...)
+(ShiftLeftAndFillUpperFromInt16x32 ...) => (VPSHLDVW512 ...)
+(ShiftLeftAndFillUpperFromInt32x4 ...) => (VPSHLDVD128 ...)
+(ShiftLeftAndFillUpperFromInt32x8 ...) => (VPSHLDVD256 ...)
+(ShiftLeftAndFillUpperFromInt32x16 ...) => (VPSHLDVD512 ...)
+(ShiftLeftAndFillUpperFromInt64x2 ...) => (VPSHLDVQ128 ...)
+(ShiftLeftAndFillUpperFromInt64x4 ...) => (VPSHLDVQ256 ...)
+(ShiftLeftAndFillUpperFromInt64x8 ...) => (VPSHLDVQ512 ...)
+(ShiftLeftAndFillUpperFromUint16x8 ...) => (VPSHLDVW128 ...)
+(ShiftLeftAndFillUpperFromUint16x16 ...) => (VPSHLDVW256 ...)
+(ShiftLeftAndFillUpperFromUint16x32 ...) => (VPSHLDVW512 ...)
+(ShiftLeftAndFillUpperFromUint32x4 ...) => (VPSHLDVD128 ...)
+(ShiftLeftAndFillUpperFromUint32x8 ...) => (VPSHLDVD256 ...)
+(ShiftLeftAndFillUpperFromUint32x16 ...) => (VPSHLDVD512 ...)
+(ShiftLeftAndFillUpperFromUint64x2 ...) => (VPSHLDVQ128 ...)
+(ShiftLeftAndFillUpperFromUint64x4 ...) => (VPSHLDVQ256 ...)
+(ShiftLeftAndFillUpperFromUint64x8 ...) => (VPSHLDVQ512 ...)
+(ShiftLeftAndFillUpperFromMaskedInt16x8 x y z mask) => (VPSHLDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedInt16x16 x y z mask) => (VPSHLDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedInt16x32 x y z mask) => (VPSHLDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedInt32x4 x y z mask) => (VPSHLDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedInt32x8 x y z mask) => (VPSHLDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedInt32x16 x y z mask) => (VPSHLDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedInt64x2 x y z mask) => (VPSHLDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedInt64x4 x y z mask) => (VPSHLDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedInt64x8 x y z mask) => (VPSHLDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedUint16x8 x y z mask) => (VPSHLDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedUint16x16 x y z mask) => (VPSHLDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedUint16x32 x y z mask) => (VPSHLDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedUint32x4 x y z mask) => (VPSHLDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedUint32x8 x y z mask) => (VPSHLDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedUint32x16 x y z mask) => (VPSHLDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedUint64x2 x y z mask) => (VPSHLDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedUint64x4 x y z mask) => (VPSHLDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftLeftAndFillUpperFromMaskedUint64x8 x y z mask) => (VPSHLDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftLeftMaskedInt16x8 x y mask) => (VPSLLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftLeftMaskedInt16x16 x y mask) => (VPSLLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftLeftMaskedInt16x32 x y mask) => (VPSLLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftLeftMaskedInt32x4 x y mask) => (VPSLLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftLeftMaskedInt32x8 x y mask) => (VPSLLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftLeftMaskedInt32x16 x y mask) => (VPSLLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftLeftMaskedInt64x2 x y mask) => (VPSLLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftLeftMaskedInt64x4 x y mask) => (VPSLLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftLeftMaskedInt64x8 x y mask) => (VPSLLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftLeftMaskedUint16x8 x y mask) => (VPSLLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftLeftMaskedUint16x16 x y mask) => (VPSLLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftLeftMaskedUint16x32 x y mask) => (VPSLLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftLeftMaskedUint32x4 x y mask) => (VPSLLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftLeftMaskedUint32x8 x y mask) => (VPSLLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftLeftMaskedUint32x16 x y mask) => (VPSLLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftLeftMaskedUint64x2 x y mask) => (VPSLLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftLeftMaskedUint64x4 x y mask) => (VPSLLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftLeftMaskedUint64x8 x y mask) => (VPSLLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftRightInt16x8 ...) => (VPSRAVW128 ...)
+(ShiftRightInt16x16 ...) => (VPSRAVW256 ...)
+(ShiftRightInt16x32 ...) => (VPSRAVW512 ...)
+(ShiftRightInt32x4 ...) => (VPSRAVD128 ...)
+(ShiftRightInt32x8 ...) => (VPSRAVD256 ...)
+(ShiftRightInt32x16 ...) => (VPSRAVD512 ...)
+(ShiftRightInt64x2 ...) => (VPSRAVQ128 ...)
+(ShiftRightInt64x4 ...) => (VPSRAVQ256 ...)
+(ShiftRightInt64x8 ...) => (VPSRAVQ512 ...)
+(ShiftRightUint16x8 ...) => (VPSRLVW128 ...)
+(ShiftRightUint16x16 ...) => (VPSRLVW256 ...)
+(ShiftRightUint16x32 ...) => (VPSRLVW512 ...)
+(ShiftRightUint32x4 ...) => (VPSRLVD128 ...)
+(ShiftRightUint32x8 ...) => (VPSRLVD256 ...)
+(ShiftRightUint32x16 ...) => (VPSRLVD512 ...)
+(ShiftRightUint64x2 ...) => (VPSRLVQ128 ...)
+(ShiftRightUint64x4 ...) => (VPSRLVQ256 ...)
+(ShiftRightUint64x8 ...) => (VPSRLVQ512 ...)
+(ShiftRightAndFillUpperFromInt16x8 ...) => (VPSHRDVW128 ...)
+(ShiftRightAndFillUpperFromInt16x16 ...) => (VPSHRDVW256 ...)
+(ShiftRightAndFillUpperFromInt16x32 ...) => (VPSHRDVW512 ...)
+(ShiftRightAndFillUpperFromInt32x4 ...) => (VPSHRDVD128 ...)
+(ShiftRightAndFillUpperFromInt32x8 ...) => (VPSHRDVD256 ...)
+(ShiftRightAndFillUpperFromInt32x16 ...) => (VPSHRDVD512 ...)
+(ShiftRightAndFillUpperFromInt64x2 ...) => (VPSHRDVQ128 ...)
+(ShiftRightAndFillUpperFromInt64x4 ...) => (VPSHRDVQ256 ...)
+(ShiftRightAndFillUpperFromInt64x8 ...) => (VPSHRDVQ512 ...)
+(ShiftRightAndFillUpperFromUint16x8 ...) => (VPSHRDVW128 ...)
+(ShiftRightAndFillUpperFromUint16x16 ...) => (VPSHRDVW256 ...)
+(ShiftRightAndFillUpperFromUint16x32 ...) => (VPSHRDVW512 ...)
+(ShiftRightAndFillUpperFromUint32x4 ...) => (VPSHRDVD128 ...)
+(ShiftRightAndFillUpperFromUint32x8 ...) => (VPSHRDVD256 ...)
+(ShiftRightAndFillUpperFromUint32x16 ...) => (VPSHRDVD512 ...)
+(ShiftRightAndFillUpperFromUint64x2 ...) => (VPSHRDVQ128 ...)
+(ShiftRightAndFillUpperFromUint64x4 ...) => (VPSHRDVQ256 ...)
+(ShiftRightAndFillUpperFromUint64x8 ...) => (VPSHRDVQ512 ...)
+(ShiftRightAndFillUpperFromMaskedInt16x8 x y z mask) => (VPSHRDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedInt16x16 x y z mask) => (VPSHRDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedInt16x32 x y z mask) => (VPSHRDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedInt32x4 x y z mask) => (VPSHRDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedInt32x8 x y z mask) => (VPSHRDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedInt32x16 x y z mask) => (VPSHRDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedInt64x2 x y z mask) => (VPSHRDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedInt64x4 x y z mask) => (VPSHRDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedInt64x8 x y z mask) => (VPSHRDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedUint16x8 x y z mask) => (VPSHRDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedUint16x16 x y z mask) => (VPSHRDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedUint16x32 x y z mask) => (VPSHRDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedUint32x4 x y z mask) => (VPSHRDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedUint32x8 x y z mask) => (VPSHRDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedUint32x16 x y z mask) => (VPSHRDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedUint64x2 x y z mask) => (VPSHRDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedUint64x4 x y z mask) => (VPSHRDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftRightAndFillUpperFromMaskedUint64x8 x y z mask) => (VPSHRDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftRightMaskedInt16x8 x y mask) => (VPSRAVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftRightMaskedInt16x16 x y mask) => (VPSRAVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftRightMaskedInt16x32 x y mask) => (VPSRAVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftRightMaskedInt32x4 x y mask) => (VPSRAVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftRightMaskedInt32x8 x y mask) => (VPSRAVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftRightMaskedInt32x16 x y mask) => (VPSRAVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftRightMaskedInt64x2 x y mask) => (VPSRAVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftRightMaskedInt64x4 x y mask) => (VPSRAVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftRightMaskedInt64x8 x y mask) => (VPSRAVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(ShiftRightMaskedUint16x8 x y mask) => (VPSRLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(ShiftRightMaskedUint16x16 x y mask) => (VPSRLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(ShiftRightMaskedUint16x32 x y mask) => (VPSRLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(ShiftRightMaskedUint32x4 x y mask) => (VPSRLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(ShiftRightMaskedUint32x8 x y mask) => (VPSRLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(ShiftRightMaskedUint32x16 x y mask) => (VPSRLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(ShiftRightMaskedUint64x2 x y mask) => (VPSRLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(ShiftRightMaskedUint64x4 x y mask) => (VPSRLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(ShiftRightMaskedUint64x8 x y mask) => (VPSRLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(SignInt8x16 ...) => (VPSIGNB128 ...)
+(SignInt8x32 ...) => (VPSIGNB256 ...)
+(SignInt16x8 ...) => (VPSIGNW128 ...)
+(SignInt16x16 ...) => (VPSIGNW256 ...)
+(SignInt32x4 ...) => (VPSIGND128 ...)
+(SignInt32x8 ...) => (VPSIGND256 ...)
+(SqrtFloat32x4 ...) => (VSQRTPS128 ...)
+(SqrtFloat32x8 ...) => (VSQRTPS256 ...)
+(SqrtFloat32x16 ...) => (VSQRTPS512 ...)
+(SqrtFloat64x2 ...) => (VSQRTPD128 ...)
+(SqrtFloat64x4 ...) => (VSQRTPD256 ...)
+(SqrtFloat64x8 ...) => (VSQRTPD512 ...)
+(SqrtMaskedFloat32x4 x mask) => (VSQRTPSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(SqrtMaskedFloat32x8 x mask) => (VSQRTPSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(SqrtMaskedFloat32x16 x mask) => (VSQRTPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(SqrtMaskedFloat64x2 x mask) => (VSQRTPDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(SqrtMaskedFloat64x4 x mask) => (VSQRTPDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(SqrtMaskedFloat64x8 x mask) => (VSQRTPDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(SubFloat32x4 ...) => (VSUBPS128 ...)
+(SubFloat32x8 ...) => (VSUBPS256 ...)
+(SubFloat32x16 ...) => (VSUBPS512 ...)
+(SubFloat64x2 ...) => (VSUBPD128 ...)
+(SubFloat64x4 ...) => (VSUBPD256 ...)
+(SubFloat64x8 ...) => (VSUBPD512 ...)
+(SubInt8x16 ...) => (VPSUBB128 ...)
+(SubInt8x32 ...) => (VPSUBB256 ...)
+(SubInt8x64 ...) => (VPSUBB512 ...)
+(SubInt16x8 ...) => (VPSUBW128 ...)
+(SubInt16x16 ...) => (VPSUBW256 ...)
+(SubInt16x32 ...) => (VPSUBW512 ...)
+(SubInt32x4 ...) => (VPSUBD128 ...)
+(SubInt32x8 ...) => (VPSUBD256 ...)
+(SubInt32x16 ...) => (VPSUBD512 ...)
+(SubInt64x2 ...) => (VPSUBQ128 ...)
+(SubInt64x4 ...) => (VPSUBQ256 ...)
+(SubInt64x8 ...) => (VPSUBQ512 ...)
+(SubUint8x16 ...) => (VPSUBB128 ...)
+(SubUint8x32 ...) => (VPSUBB256 ...)
+(SubUint8x64 ...) => (VPSUBB512 ...)
+(SubUint16x8 ...) => (VPSUBW128 ...)
+(SubUint16x16 ...) => (VPSUBW256 ...)
+(SubUint16x32 ...) => (VPSUBW512 ...)
+(SubUint32x4 ...) => (VPSUBD128 ...)
+(SubUint32x8 ...) => (VPSUBD256 ...)
+(SubUint32x16 ...) => (VPSUBD512 ...)
+(SubUint64x2 ...) => (VPSUBQ128 ...)
+(SubUint64x4 ...) => (VPSUBQ256 ...)
+(SubUint64x8 ...) => (VPSUBQ512 ...)
+(SubMaskedFloat32x4 x y mask) => (VSUBPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(SubMaskedFloat32x8 x y mask) => (VSUBPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(SubMaskedFloat32x16 x y mask) => (VSUBPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(SubMaskedFloat64x2 x y mask) => (VSUBPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(SubMaskedFloat64x4 x y mask) => (VSUBPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(SubMaskedFloat64x8 x y mask) => (VSUBPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(SubMaskedInt8x16 x y mask) => (VPSUBBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(SubMaskedInt8x32 x y mask) => (VPSUBBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(SubMaskedInt8x64 x y mask) => (VPSUBBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(SubMaskedInt16x8 x y mask) => (VPSUBWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(SubMaskedInt16x16 x y mask) => (VPSUBWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(SubMaskedInt16x32 x y mask) => (VPSUBWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(SubMaskedInt32x4 x y mask) => (VPSUBDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(SubMaskedInt32x8 x y mask) => (VPSUBDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(SubMaskedInt32x16 x y mask) => (VPSUBDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(SubMaskedInt64x2 x y mask) => (VPSUBQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(SubMaskedInt64x4 x y mask) => (VPSUBQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(SubMaskedInt64x8 x y mask) => (VPSUBQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(SubMaskedUint8x16 x y mask) => (VPSUBBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+(SubMaskedUint8x32 x y mask) => (VPSUBBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+(SubMaskedUint8x64 x y mask) => (VPSUBBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+(SubMaskedUint16x8 x y mask) => (VPSUBWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(SubMaskedUint16x16 x y mask) => (VPSUBWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(SubMaskedUint16x32 x y mask) => (VPSUBWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(SubMaskedUint32x4 x y mask) => (VPSUBDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(SubMaskedUint32x8 x y mask) => (VPSUBDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(SubMaskedUint32x16 x y mask) => (VPSUBDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(SubMaskedUint64x2 x y mask) => (VPSUBQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(SubMaskedUint64x4 x y mask) => (VPSUBQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(SubMaskedUint64x8 x y mask) => (VPSUBQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(TruncFloat32x4 x) => (VROUNDPS128 [3] x)
+(TruncFloat32x8 x) => (VROUNDPS256 [3] x)
+(TruncFloat64x2 x) => (VROUNDPD128 [3] x)
+(TruncFloat64x4 x) => (VROUNDPD256 [3] x)
+(TruncWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+3] x)
+(TruncWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+3] x)
+(TruncWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+3] x)
+(TruncWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+3] x)
+(TruncWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+3] x)
+(TruncWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+3] x)
+(TruncWithPrecisionMaskedFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+3] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(TruncWithPrecisionMaskedFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+3] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(TruncWithPrecisionMaskedFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+3] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(TruncWithPrecisionMaskedFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+3] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(TruncWithPrecisionMaskedFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+3] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(TruncWithPrecisionMaskedFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+3] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(UnsignedSignedQuadDotProdAccumulateInt32x4 ...) => (VPDPBUSD128 ...)
+(UnsignedSignedQuadDotProdAccumulateInt32x8 ...) => (VPDPBUSD256 ...)
+(UnsignedSignedQuadDotProdAccumulateInt32x16 ...) => (VPDPBUSD512 ...)
+(UnsignedSignedQuadDotProdAccumulateMaskedInt32x4 x y z mask) => (VPDPBUSDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(UnsignedSignedQuadDotProdAccumulateMaskedInt32x8 x y z mask) => (VPDPBUSDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(UnsignedSignedQuadDotProdAccumulateMaskedInt32x16 x y z mask) => (VPDPBUSDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(XorInt8x16 ...) => (VPXOR128 ...)
+(XorInt8x32 ...) => (VPXOR256 ...)
+(XorInt16x8 ...) => (VPXOR128 ...)
+(XorInt16x16 ...) => (VPXOR256 ...)
+(XorInt32x4 ...) => (VPXOR128 ...)
+(XorInt32x8 ...) => (VPXOR256 ...)
+(XorInt32x16 ...) => (VPXORD512 ...)
+(XorInt64x2 ...) => (VPXOR128 ...)
+(XorInt64x4 ...) => (VPXOR256 ...)
+(XorInt64x8 ...) => (VPXORQ512 ...)
+(XorUint8x16 ...) => (VPXOR128 ...)
+(XorUint8x32 ...) => (VPXOR256 ...)
+(XorUint16x8 ...) => (VPXOR128 ...)
+(XorUint16x16 ...) => (VPXOR256 ...)
+(XorUint32x4 ...) => (VPXOR128 ...)
+(XorUint32x8 ...) => (VPXOR256 ...)
+(XorUint32x16 ...) => (VPXORD512 ...)
+(XorUint64x2 ...) => (VPXOR128 ...)
+(XorUint64x4 ...) => (VPXOR256 ...)
+(XorUint64x8 ...) => (VPXORQ512 ...)
+(XorMaskedInt32x4 x y mask) => (VPXORDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(XorMaskedInt32x8 x y mask) => (VPXORDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(XorMaskedInt32x16 x y mask) => (VPXORDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(XorMaskedInt64x2 x y mask) => (VPXORQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(XorMaskedInt64x4 x y mask) => (VPXORQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(XorMaskedInt64x8 x y mask) => (VPXORQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(XorMaskedUint32x4 x y mask) => (VPXORDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(XorMaskedUint32x8 x y mask) => (VPXORDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(XorMaskedUint32x16 x y mask) => (VPXORDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(XorMaskedUint64x2 x y mask) => (VPXORQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(XorMaskedUint64x4 x y mask) => (VPXORQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(XorMaskedUint64x8 x y mask) => (VPXORQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
new file mode 100644
index 00000000000000..a7a3c9715c45cf
--- /dev/null
+++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
@@ -0,0 +1,986 @@
+// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT.
+package main
+
+func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vfpkv, w11, w21, w2k, wkw, w2kw, w2kk, w31, w3kw, wgpw, wgp, wfpw, wfpkw regInfo) []opData {
+	return []opData{
+		{name: "VADDPS512", argLength: 2, reg: w21, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VADDPSMasked512", argLength: 3, reg: w2kw, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VRCP14PS512", argLength: 1, reg: w11, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VRCP14PSMasked512", argLength: 2, reg: wkw, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VRSQRT14PS512", argLength: 1, reg: w11, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VRSQRT14PSMasked512", argLength: 2, reg: wkw, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VCOMPRESSPSMasked512", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VDIVPS512", argLength: 2, reg: w21, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VDIVPSMasked512", argLength: 3, reg: w2kw, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VFMADD213PS512", argLength: 3, reg: w31, asm: "VFMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VFMADD213PSMasked512", argLength: 4, reg: w3kw, asm: "VFMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VFMADDSUB213PS512", argLength: 3, reg: w31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VFMADDSUB213PSMasked512", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VFMSUBADD213PS512", argLength: 3, reg: w31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VFMSUBADD213PSMasked512", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VMAXPS512", argLength: 2, reg: w21, asm: "VMAXPS", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VMAXPSMasked512", argLength: 3, reg: w2kw, asm: "VMAXPS", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VMINPS512", argLength: 2, reg: w21, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VMINPSMasked512", argLength: 3, reg: w2kw, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VMULPS512", argLength: 2, reg: w21, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VSCALEFPS512", argLength: 2, reg: w21, asm: "VSCALEFPS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VSCALEFPSMasked512", argLength: 3, reg: w2kw, asm: "VSCALEFPS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VMULPSMasked512", argLength: 3, reg: w2kw, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VSQRTPS512", argLength: 1, reg: w11, asm: "VSQRTPS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VSQRTPSMasked512", argLength: 2, reg: wkw, asm: "VSQRTPS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VSUBPS512", argLength: 2, reg: w21, asm: "VSUBPS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VSUBPSMasked512", argLength: 3, reg: w2kw, asm: "VSUBPS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VADDPS128", argLength: 2, reg: v21, asm: "VADDPS", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VADDPSMasked128", argLength: 3, reg: w2kw, asm: "VADDPS", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VADDSUBPS128", argLength: 2, reg: v21, asm: "VADDSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VRCP14PS128", argLength: 1, reg: w11, asm: "VRCP14PS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VRCP14PSMasked128", argLength: 2, reg: wkw, asm: "VRCP14PS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VRSQRTPS128", argLength: 1, reg: v11, asm: "VRSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VRSQRT14PSMasked128", argLength: 2, reg: wkw, asm: "VRSQRT14PS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VCOMPRESSPSMasked128", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VDIVPS128", argLength: 2, reg: v21, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VDIVPSMasked128", argLength: 3, reg: w2kw, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VFMADD213PS128", argLength: 3, reg: w31, asm: "VFMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VFMADD213PSMasked128", argLength: 4, reg: w3kw, asm: "VFMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VFMADDSUB213PS128", argLength: 3, reg: w31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VFMADDSUB213PSMasked128", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VFMSUBADD213PS128", argLength: 3, reg: w31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VFMSUBADD213PSMasked128", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VMAXPS128", argLength: 2, reg: v21, asm: "VMAXPS", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VMAXPSMasked128", argLength: 3, reg: w2kw, asm: "VMAXPS", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VMINPS128", argLength: 2, reg: v21, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VMINPSMasked128", argLength: 3, reg: w2kw, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VMULPS128", argLength: 2, reg: v21, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VSCALEFPS128", argLength: 2, reg: w21, asm: "VSCALEFPS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VSCALEFPSMasked128", argLength: 3, reg: w2kw, asm: "VSCALEFPS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VMULPSMasked128", argLength: 3, reg: w2kw, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VHADDPS128", argLength: 2, reg: v21, asm: "VHADDPS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VHSUBPS128", argLength: 2, reg: v21, asm: "VHSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VSQRTPS128", argLength: 1, reg: v11, asm: "VSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VSQRTPSMasked128", argLength: 2, reg: wkw, asm: "VSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VSUBPS128", argLength: 2, reg: v21, asm: "VSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VSUBPSMasked128", argLength: 3, reg: w2kw, asm: "VSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VADDPS256", argLength: 2, reg: v21, asm: "VADDPS", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VADDPSMasked256", argLength: 3, reg: w2kw, asm: "VADDPS", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VADDSUBPS256", argLength: 2, reg: v21, asm: "VADDSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VRCP14PS256", argLength: 1, reg: w11, asm: "VRCP14PS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VRCP14PSMasked256", argLength: 2, reg: wkw, asm: "VRCP14PS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VRSQRTPS256", argLength: 1, reg: v11, asm: "VRSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VRSQRT14PSMasked256", argLength: 2, reg: wkw, asm: "VRSQRT14PS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VCOMPRESSPSMasked256", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VDIVPS256", argLength: 2, reg: v21, asm: "VDIVPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VDIVPSMasked256", argLength: 3, reg: w2kw, asm: "VDIVPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VFMADD213PS256", argLength: 3, reg: w31, asm: "VFMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VFMADD213PSMasked256", argLength: 4, reg: w3kw, asm: "VFMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VFMADDSUB213PS256", argLength: 3, reg: w31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VFMADDSUB213PSMasked256", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VFMSUBADD213PS256", argLength: 3, reg: w31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VFMSUBADD213PSMasked256", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VMAXPS256", argLength: 2, reg: v21, asm: "VMAXPS", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VMAXPSMasked256", argLength: 3, reg: w2kw, asm: "VMAXPS", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VMINPS256", argLength: 2, reg: v21, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VMINPSMasked256", argLength: 3, reg: w2kw, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VMULPS256", argLength: 2, reg: v21, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VSCALEFPS256", argLength: 2, reg: w21, asm: "VSCALEFPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VSCALEFPSMasked256", argLength: 3, reg: w2kw, asm: "VSCALEFPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VMULPSMasked256", argLength: 3, reg: w2kw, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VHADDPS256", argLength: 2, reg: v21, asm: "VHADDPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VHSUBPS256", argLength: 2, reg: v21, asm: "VHSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VSQRTPS256", argLength: 1, reg: v11, asm: "VSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VSQRTPSMasked256", argLength: 2, reg: wkw, asm: "VSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VSUBPS256", argLength: 2, reg: v21, asm: "VSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VSUBPSMasked256", argLength: 3, reg: w2kw, asm: "VSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VADDPD128", argLength: 2, reg: v21, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VADDPDMasked128", argLength: 3, reg: w2kw, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VADDSUBPD128", argLength: 2, reg: v21, asm: "VADDSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VRCP14PD128", argLength: 1, reg: w11, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VRCP14PDMasked128", argLength: 2, reg: wkw, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VRSQRT14PD128", argLength: 1, reg: w11, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VRSQRT14PDMasked128", argLength: 2, reg: wkw, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VCOMPRESSPDMasked128", argLength: 2, reg: wkw, asm: "VCOMPRESSPD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VDIVPD128", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VDIVPDMasked128", argLength: 3, reg: w2kw, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VFMADD213PD128", argLength: 3, reg: w31, asm: "VFMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VFMADD213PDMasked128", argLength: 4, reg: w3kw, asm: "VFMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VFMADDSUB213PD128", argLength: 3, reg: w31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VFMADDSUB213PDMasked128", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VFMSUBADD213PD128", argLength: 3, reg: w31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VFMSUBADD213PDMasked128", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VMAXPD128", argLength: 2, reg: v21, asm: "VMAXPD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VMAXPDMasked128", argLength: 3, reg: w2kw, asm: "VMAXPD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VMINPD128", argLength: 2, reg: v21, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VMINPDMasked128", argLength: 3, reg: w2kw, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VMULPD128", argLength: 2, reg: v21, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VSCALEFPD128", argLength: 2, reg: w21, asm: "VSCALEFPD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VSCALEFPDMasked128", argLength: 3, reg: w2kw, asm: "VSCALEFPD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VMULPDMasked128", argLength: 3, reg: w2kw, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VHADDPD128", argLength: 2, reg: v21, asm: "VHADDPD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VHSUBPD128", argLength: 2, reg: v21, asm: "VHSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VSQRTPD128", argLength: 1, reg: v11, asm: "VSQRTPD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VSQRTPDMasked128", argLength: 2, reg: wkw, asm: "VSQRTPD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VSUBPD128", argLength: 2, reg: v21, asm: "VSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VSUBPDMasked128", argLength: 3, reg: w2kw, asm: "VSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VADDPD256", argLength: 2, reg: v21, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VADDPDMasked256", argLength: 3, reg: w2kw, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VADDSUBPD256", argLength: 2, reg: v21, asm: "VADDSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VRCP14PD256", argLength: 1, reg: w11, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VRCP14PDMasked256", argLength: 2, reg: wkw, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VRSQRT14PD256", argLength: 1, reg: w11, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VRSQRT14PDMasked256", argLength: 2, reg: wkw, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VCOMPRESSPDMasked256", argLength: 2, reg: wkw, asm: "VCOMPRESSPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VDIVPD256", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VDIVPDMasked256", argLength: 3, reg: w2kw, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VFMADD213PD256", argLength: 3, reg: w31, asm: "VFMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VFMADD213PDMasked256", argLength: 4, reg: w3kw, asm: "VFMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VFMADDSUB213PD256", argLength: 3, reg: w31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VFMADDSUB213PDMasked256", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VFMSUBADD213PD256", argLength: 3, reg: w31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VFMSUBADD213PDMasked256", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VMAXPD256", argLength: 2, reg: v21, asm: "VMAXPD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VMAXPDMasked256", argLength: 3, reg: w2kw, asm: "VMAXPD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VMINPD256", argLength: 2, reg: v21, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VMINPDMasked256", argLength: 3, reg: w2kw, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VMULPD256", argLength: 2, reg: v21, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VSCALEFPD256", argLength: 2, reg: w21, asm: "VSCALEFPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VSCALEFPDMasked256", argLength: 3, reg: w2kw, asm: "VSCALEFPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VMULPDMasked256", argLength: 3, reg: w2kw, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VHADDPD256", argLength: 2, reg: v21, asm: "VHADDPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VHSUBPD256", argLength: 2, reg: v21, asm: "VHSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VSQRTPD256", argLength: 1, reg: v11, asm: "VSQRTPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VSQRTPDMasked256", argLength: 2, reg: wkw, asm: "VSQRTPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VSUBPD256", argLength: 2, reg: v21, asm: "VSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VSUBPDMasked256", argLength: 3, reg: w2kw, asm: "VSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VADDPD512", argLength: 2, reg: w21, asm: "VADDPD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VADDPDMasked512", argLength: 3, reg: w2kw, asm: "VADDPD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VRCP14PD512", argLength: 1, reg: w11, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VRCP14PDMasked512", argLength: 2, reg: wkw, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VRSQRT14PD512", argLength: 1, reg: w11, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VRSQRT14PDMasked512", argLength: 2, reg: wkw, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VCOMPRESSPDMasked512", argLength: 2, reg: wkw, asm: "VCOMPRESSPD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VDIVPD512", argLength: 2, reg: w21, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VDIVPDMasked512", argLength: 3, reg: w2kw, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VFMADD213PD512", argLength: 3, reg: w31, asm: "VFMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VFMADD213PDMasked512", argLength: 4, reg: w3kw, asm: "VFMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VFMADDSUB213PD512", argLength: 3, reg: w31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VFMADDSUB213PDMasked512", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VFMSUBADD213PD512", argLength: 3, reg: w31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VFMSUBADD213PDMasked512", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VMAXPD512", argLength: 2, reg: w21, asm: "VMAXPD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VMAXPDMasked512", argLength: 3, reg: w2kw, asm: "VMAXPD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VMINPD512", argLength: 2, reg: w21, asm: "VMINPD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VMINPDMasked512", argLength: 3, reg: w2kw, asm: "VMINPD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VMULPD512", argLength: 2, reg: w21, asm: "VMULPD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VSCALEFPD512", argLength: 2, reg: w21, asm: "VSCALEFPD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VSCALEFPDMasked512", argLength: 3, reg: w2kw, asm: "VSCALEFPD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VMULPDMasked512", argLength: 3, reg: w2kw, asm: "VMULPD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VSQRTPD512", argLength: 1, reg: w11, asm: "VSQRTPD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VSQRTPDMasked512", argLength: 2, reg: wkw, asm: "VSQRTPD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VSUBPD512", argLength: 2, reg: w21, asm: "VSUBPD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VSUBPDMasked512", argLength: 3, reg: w2kw, asm: "VSUBPD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPABSW256", argLength: 1, reg: v11, asm: "VPABSW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPABSWMasked256", argLength: 2, reg: wkw, asm: "VPABSW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPADDW256", argLength: 2, reg: v21, asm: "VPADDW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPADDWMasked256", argLength: 3, reg: w2kw, asm: "VPADDW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPCOMPRESSWMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPCMPEQW256", argLength: 2, reg: v21, asm: "VPCMPEQW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPCMPGTW256", argLength: 2, reg: v21, asm: "VPCMPGTW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXSW256", argLength: 2, reg: v21, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXSWMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINSW256", argLength: 2, reg: v21, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINSWMasked256", argLength: 3, reg: w2kw, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULHW256", argLength: 2, reg: v21, asm: "VPMULHW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULHWMasked256", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULLW256", argLength: 2, reg: v21, asm: "VPMULLW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULLWMasked256", argLength: 3, reg: w2kw, asm: "VPMULLW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMADDWD256", argLength: 2, reg: v21, asm: "VPMADDWD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPMADDWDMasked256", argLength: 3, reg: w2kw, asm: "VPMADDWD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPHADDW256", argLength: 2, reg: v21, asm: "VPHADDW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPHSUBW256", argLength: 2, reg: v21, asm: "VPHSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPOPCNTW256", argLength: 1, reg: w11, asm: "VPOPCNTW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPOPCNTWMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPADDSW256", argLength: 2, reg: v21, asm: "VPADDSW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPADDSWMasked256", argLength: 3, reg: w2kw, asm: "VPADDSW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPHADDSW256", argLength: 2, reg: v21, asm: "VPHADDSW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPHSUBSW256", argLength: 2, reg: v21, asm: "VPHSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSUBSW256", argLength: 2, reg: v21, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSUBSWMasked256", argLength: 3, reg: w2kw, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSLLW256", argLength: 2, reg: vfpv, asm: "VPSLLW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSLLWMasked256", argLength: 3, reg: wfpkw, asm: "VPSLLW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRAW256", argLength: 2, reg: vfpv, asm: "VPSRAW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRAWMasked256", argLength: 3, reg: wfpkw, asm: "VPSRAW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSLLVW256", argLength: 2, reg: w21, asm: "VPSLLVW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHLDVW256", argLength: 3, reg: w31, asm: "VPSHLDVW", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPSHLDVWMasked256", argLength: 4, reg: w3kw, asm: "VPSHLDVW", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPSLLVWMasked256", argLength: 3, reg: w2kw, asm: "VPSLLVW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRAVW256", argLength: 2, reg: w21, asm: "VPSRAVW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHRDVW256", argLength: 3, reg: w31, asm: "VPSHRDVW", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPSHRDVWMasked256", argLength: 4, reg: w3kw, asm: "VPSHRDVW", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPSRAVWMasked256", argLength: 3, reg: w2kw, asm: "VPSRAVW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSIGNW256", argLength: 2, reg: v21, asm: "VPSIGNW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSUBW256", argLength: 2, reg: v21, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSUBWMasked256", argLength: 3, reg: w2kw, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPABSW512", argLength: 1, reg: w11, asm: "VPABSW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPABSWMasked512", argLength: 2, reg: wkw, asm: "VPABSW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPADDW512", argLength: 2, reg: w21, asm: "VPADDW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPADDWMasked512", argLength: 3, reg: w2kw, asm: "VPADDW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPCOMPRESSWMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXSW512", argLength: 2, reg: w21, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXSWMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINSW512", argLength: 2, reg: w21, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINSWMasked512", argLength: 3, reg: w2kw, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULHW512", argLength: 2, reg: w21, asm: "VPMULHW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULHWMasked512", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULLW512", argLength: 2, reg: w21, asm: "VPMULLW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULLWMasked512", argLength: 3, reg: w2kw, asm: "VPMULLW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMADDWD512", argLength: 2, reg: w21, asm: "VPMADDWD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPMADDWDMasked512", argLength: 3, reg: w2kw, asm: "VPMADDWD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPOPCNTW512", argLength: 1, reg: w11, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPOPCNTWMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPADDSW512", argLength: 2, reg: w21, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPADDSWMasked512", argLength: 3, reg: w2kw, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPSUBSW512", argLength: 2, reg: w21, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSUBSWMasked512", argLength: 3, reg: w2kw, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSLLW512", argLength: 2, reg: wfpw, asm: "VPSLLW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSLLWMasked512", argLength: 3, reg: wfpkw, asm: "VPSLLW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRAW512", argLength: 2, reg: wfpw, asm: "VPSRAW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRAWMasked512", argLength: 3, reg: wfpkw, asm: "VPSRAW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSLLVW512", argLength: 2, reg: w21, asm: "VPSLLVW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHLDVW512", argLength: 3, reg: w31, asm: "VPSHLDVW", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPSHLDVWMasked512", argLength: 4, reg: w3kw, asm: "VPSHLDVW", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPSLLVWMasked512", argLength: 3, reg: w2kw, asm: "VPSLLVW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRAVW512", argLength: 2, reg: w21, asm: "VPSRAVW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHRDVW512", argLength: 3, reg: w31, asm: "VPSHRDVW", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPSHRDVWMasked512", argLength: 4, reg: w3kw, asm: "VPSHRDVW", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPSRAVWMasked512", argLength: 3, reg: w2kw, asm: "VPSRAVW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSUBW512", argLength: 2, reg: w21, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSUBWMasked512", argLength: 3, reg: w2kw, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPABSW128", argLength: 1, reg: v11, asm: "VPABSW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPABSWMasked128", argLength: 2, reg: wkw, asm: "VPABSW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPADDW128", argLength: 2, reg: v21, asm: "VPADDW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPADDWMasked128", argLength: 3, reg: w2kw, asm: "VPADDW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPCOMPRESSWMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPEQW128", argLength: 2, reg: v21, asm: "VPCMPEQW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPGTW128", argLength: 2, reg: v21, asm: "VPCMPGTW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXSW128", argLength: 2, reg: v21, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXSWMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINSW128", argLength: 2, reg: v21, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINSWMasked128", argLength: 3, reg: w2kw, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULHW128", argLength: 2, reg: v21, asm: "VPMULHW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULHWMasked128", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULLW128", argLength: 2, reg: v21, asm: "VPMULLW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULLWMasked128", argLength: 3, reg: w2kw, asm: "VPMULLW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMADDWD128", argLength: 2, reg: v21, asm: "VPMADDWD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPMADDWDMasked128", argLength: 3, reg: w2kw, asm: "VPMADDWD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPHADDW128", argLength: 2, reg: v21, asm: "VPHADDW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPHSUBW128", argLength: 2, reg: v21, asm: "VPHSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPOPCNTW128", argLength: 1, reg: w11, asm: "VPOPCNTW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPOPCNTWMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPADDSW128", argLength: 2, reg: v21, asm: "VPADDSW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPADDSWMasked128", argLength: 3, reg: w2kw, asm: "VPADDSW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPHADDSW128", argLength: 2, reg: v21, asm: "VPHADDSW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPHSUBSW128", argLength: 2, reg: v21, asm: "VPHSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSUBSW128", argLength: 2, reg: v21, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSUBSWMasked128", argLength: 3, reg: w2kw, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSLLW128", argLength: 2, reg: vfpv, asm: "VPSLLW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSLLWMasked128", argLength: 3, reg: wfpkw, asm: "VPSLLW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRAW128", argLength: 2, reg: vfpv, asm: "VPSRAW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRAWMasked128", argLength: 3, reg: wfpkw, asm: "VPSRAW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSLLVW128", argLength: 2, reg: w21, asm: "VPSLLVW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHLDVW128", argLength: 3, reg: w31, asm: "VPSHLDVW", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSHLDVWMasked128", argLength: 4, reg: w3kw, asm: "VPSHLDVW", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSLLVWMasked128", argLength: 3, reg: w2kw, asm: "VPSLLVW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRAVW128", argLength: 2, reg: w21, asm: "VPSRAVW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHRDVW128", argLength: 3, reg: w31, asm: "VPSHRDVW", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSHRDVWMasked128", argLength: 4, reg: w3kw, asm: "VPSHRDVW", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSRAVWMasked128", argLength: 3, reg: w2kw, asm: "VPSRAVW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSIGNW128", argLength: 2, reg: v21, asm: "VPSIGNW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSUBW128", argLength: 2, reg: v21, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSUBWMasked128", argLength: 3, reg: w2kw, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPABSD512", argLength: 1, reg: w11, asm: "VPABSD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPABSDMasked512", argLength: 2, reg: wkw, asm: "VPABSD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPADDD512", argLength: 2, reg: w21, asm: "VPADDD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPADDDMasked512", argLength: 3, reg: w2kw, asm: "VPADDD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPANDD512", argLength: 2, reg: w21, asm: "VPANDD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPANDDMasked512", argLength: 3, reg: w2kw, asm: "VPANDD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPANDND512", argLength: 2, reg: w21, asm: "VPANDND", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPANDNDMasked512", argLength: 3, reg: w2kw, asm: "VPANDND", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPCOMPRESSDMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXSD512", argLength: 2, reg: w21, asm: "VPMAXSD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXSDMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINSD512", argLength: 2, reg: w21, asm: "VPMINSD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINSDMasked512", argLength: 3, reg: w2kw, asm: "VPMINSD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULLD512", argLength: 2, reg: w21, asm: "VPMULLD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULLDMasked512", argLength: 3, reg: w2kw, asm: "VPMULLD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPORD512", argLength: 2, reg: w21, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPORDMasked512", argLength: 3, reg: w2kw, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPDPWSSD512", argLength: 3, reg: w31, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPDPWSSDMasked512", argLength: 4, reg: w3kw, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPOPCNTD512", argLength: 1, reg: w11, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPOPCNTDMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPROLVD512", argLength: 2, reg: w21, asm: "VPROLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPROLVDMasked512", argLength: 3, reg: w2kw, asm: "VPROLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPRORVD512", argLength: 2, reg: w21, asm: "VPRORVD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPRORVDMasked512", argLength: 3, reg: w2kw, asm: "VPRORVD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPDPWSSDS512", argLength: 3, reg: w31, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPDPWSSDSMasked512", argLength: 4, reg: w3kw, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPDPBUSDS512", argLength: 3, reg: w31, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPDPBUSDSMasked512", argLength: 4, reg: w3kw, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPSLLD512", argLength: 2, reg: wfpw, asm: "VPSLLD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSLLDMasked512", argLength: 3, reg: wfpkw, asm: "VPSLLD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRAD512", argLength: 2, reg: wfpw, asm: "VPSRAD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRADMasked512", argLength: 3, reg: wfpkw, asm: "VPSRAD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSLLVD512", argLength: 2, reg: w21, asm: "VPSLLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHLDVD512", argLength: 3, reg: w31, asm: "VPSHLDVD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPSHLDVDMasked512", argLength: 4, reg: w3kw, asm: "VPSHLDVD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPSLLVDMasked512", argLength: 3, reg: w2kw, asm: "VPSLLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRAVD512", argLength: 2, reg: w21, asm: "VPSRAVD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHRDVD512", argLength: 3, reg: w31, asm: "VPSHRDVD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPSHRDVDMasked512", argLength: 4, reg: w3kw, asm: "VPSHRDVD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPSRAVDMasked512", argLength: 3, reg: w2kw, asm: "VPSRAVD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSUBD512", argLength: 2, reg: w21, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSUBDMasked512", argLength: 3, reg: w2kw, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPDPBUSD512", argLength: 3, reg: w31, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPDPBUSDMasked512", argLength: 4, reg: w3kw, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPXORD512", argLength: 2, reg: w21, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPXORDMasked512", argLength: 3, reg: w2kw, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPABSD128", argLength: 1, reg: v11, asm: "VPABSD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPABSDMasked128", argLength: 2, reg: wkw, asm: "VPABSD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPADDD128", argLength: 2, reg: v21, asm: "VPADDD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPADDDMasked128", argLength: 3, reg: w2kw, asm: "VPADDD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPANDDMasked128", argLength: 3, reg: w2kw, asm: "VPANDD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPANDNDMasked128", argLength: 3, reg: w2kw, asm: "VPANDND", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPCOMPRESSDMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPEQD128", argLength: 2, reg: v21, asm: "VPCMPEQD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPGTD128", argLength: 2, reg: v21, asm: "VPCMPGTD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXSD128", argLength: 2, reg: v21, asm: "VPMAXSD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXSDMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINSD128", argLength: 2, reg: v21, asm: "VPMINSD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINSDMasked128", argLength: 3, reg: w2kw, asm: "VPMINSD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULDQ128", argLength: 2, reg: v21, asm: "VPMULDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULLD128", argLength: 2, reg: v21, asm: "VPMULLD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULLDMasked128", argLength: 3, reg: w2kw, asm: "VPMULLD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPORDMasked128", argLength: 3, reg: w2kw, asm: "VPORD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPDPWSSD128", argLength: 3, reg: v31, asm: "VPDPWSSD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPDPWSSDMasked128", argLength: 4, reg: w3kw, asm: "VPDPWSSD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPHADDD128", argLength: 2, reg: v21, asm: "VPHADDD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPHSUBD128", argLength: 2, reg: v21, asm: "VPHSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPOPCNTD128", argLength: 1, reg: w11, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPOPCNTDMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPROLVD128", argLength: 2, reg: w21, asm: "VPROLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPROLVDMasked128", argLength: 3, reg: w2kw, asm: "VPROLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPRORVD128", argLength: 2, reg: w21, asm: "VPRORVD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPRORVDMasked128", argLength: 3, reg: w2kw, asm: "VPRORVD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPDPWSSDS128", argLength: 3, reg: v31, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPDPWSSDSMasked128", argLength: 4, reg: w3kw, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPDPBUSDS128", argLength: 3, reg: v31, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPDPBUSDSMasked128", argLength: 4, reg: w3kw, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSLLD128", argLength: 2, reg: vfpv, asm: "VPSLLD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSLLDMasked128", argLength: 3, reg: wfpkw, asm: "VPSLLD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRAD128", argLength: 2, reg: vfpv, asm: "VPSRAD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRADMasked128", argLength: 3, reg: wfpkw, asm: "VPSRAD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSLLVD128", argLength: 2, reg: v21, asm: "VPSLLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHLDVD128", argLength: 3, reg: w31, asm: "VPSHLDVD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSHLDVDMasked128", argLength: 4, reg: w3kw, asm: "VPSHLDVD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSLLVDMasked128", argLength: 3, reg: w2kw, asm: "VPSLLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRAVD128", argLength: 2, reg: v21, asm: "VPSRAVD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHRDVD128", argLength: 3, reg: w31, asm: "VPSHRDVD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSHRDVDMasked128", argLength: 4, reg: w3kw, asm: "VPSHRDVD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSRAVDMasked128", argLength: 3, reg: w2kw, asm: "VPSRAVD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSIGND128", argLength: 2, reg: v21, asm: "VPSIGND", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSUBD128", argLength: 2, reg: v21, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSUBDMasked128", argLength: 3, reg: w2kw, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPDPBUSD128", argLength: 3, reg: v31, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPDPBUSDMasked128", argLength: 4, reg: w3kw, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPXORDMasked128", argLength: 3, reg: w2kw, asm: "VPXORD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPABSD256", argLength: 1, reg: v11, asm: "VPABSD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPABSDMasked256", argLength: 2, reg: wkw, asm: "VPABSD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPADDD256", argLength: 2, reg: v21, asm: "VPADDD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPADDDMasked256", argLength: 3, reg: w2kw, asm: "VPADDD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPANDDMasked256", argLength: 3, reg: w2kw, asm: "VPANDD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPANDNDMasked256", argLength: 3, reg: w2kw, asm: "VPANDND", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPCOMPRESSDMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPCMPEQD256", argLength: 2, reg: v21, asm: "VPCMPEQD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPCMPGTD256", argLength: 2, reg: v21, asm: "VPCMPGTD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXSD256", argLength: 2, reg: v21, asm: "VPMAXSD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXSDMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINSD256", argLength: 2, reg: v21, asm: "VPMINSD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINSDMasked256", argLength: 3, reg: w2kw, asm: "VPMINSD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULDQ256", argLength: 2, reg: v21, asm: "VPMULDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULLD256", argLength: 2, reg: v21, asm: "VPMULLD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULLDMasked256", argLength: 3, reg: w2kw, asm: "VPMULLD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPORDMasked256", argLength: 3, reg: w2kw, asm: "VPORD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPDPWSSD256", argLength: 3, reg: v31, asm: "VPDPWSSD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPDPWSSDMasked256", argLength: 4, reg: w3kw, asm: "VPDPWSSD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPHADDD256", argLength: 2, reg: v21, asm: "VPHADDD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPHSUBD256", argLength: 2, reg: v21, asm: "VPHSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPOPCNTD256", argLength: 1, reg: w11, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPOPCNTDMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPROLVD256", argLength: 2, reg: w21, asm: "VPROLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPROLVDMasked256", argLength: 3, reg: w2kw, asm: "VPROLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPRORVD256", argLength: 2, reg: w21, asm: "VPRORVD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPRORVDMasked256", argLength: 3, reg: w2kw, asm: "VPRORVD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPDPWSSDS256", argLength: 3, reg: v31, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPDPWSSDSMasked256", argLength: 4, reg: w3kw, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPDPBUSDS256", argLength: 3, reg: v31, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPDPBUSDSMasked256", argLength: 4, reg: w3kw, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPSLLD256", argLength: 2, reg: vfpv, asm: "VPSLLD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSLLDMasked256", argLength: 3, reg: wfpkw, asm: "VPSLLD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRAD256", argLength: 2, reg: vfpv, asm: "VPSRAD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRADMasked256", argLength: 3, reg: wfpkw, asm: "VPSRAD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSLLVD256", argLength: 2, reg: v21, asm: "VPSLLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHLDVD256", argLength: 3, reg: w31, asm: "VPSHLDVD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPSHLDVDMasked256", argLength: 4, reg: w3kw, asm: "VPSHLDVD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPSLLVDMasked256", argLength: 3, reg: w2kw, asm: "VPSLLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRAVD256", argLength: 2, reg: v21, asm: "VPSRAVD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHRDVD256", argLength: 3, reg: w31, asm: "VPSHRDVD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPSHRDVDMasked256", argLength: 4, reg: w3kw, asm: "VPSHRDVD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPSRAVDMasked256", argLength: 3, reg: w2kw, asm: "VPSRAVD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSIGND256", argLength: 2, reg: v21, asm: "VPSIGND", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSUBD256", argLength: 2, reg: v21, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSUBDMasked256", argLength: 3, reg: w2kw, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPDPBUSD256", argLength: 3, reg: v31, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPDPBUSDMasked256", argLength: 4, reg: w3kw, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPXORDMasked256", argLength: 3, reg: w2kw, asm: "VPXORD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPABSQ128", argLength: 1, reg: w11, asm: "VPABSQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPABSQMasked128", argLength: 2, reg: wkw, asm: "VPABSQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPADDQ128", argLength: 2, reg: v21, asm: "VPADDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPADDQMasked128", argLength: 3, reg: w2kw, asm: "VPADDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPANDQMasked128", argLength: 3, reg: w2kw, asm: "VPANDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPANDNQMasked128", argLength: 3, reg: w2kw, asm: "VPANDNQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPCOMPRESSQMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPEQQ128", argLength: 2, reg: v21, asm: "VPCMPEQQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPGTQ128", argLength: 2, reg: v21, asm: "VPCMPGTQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXSQ128", argLength: 2, reg: w21, asm: "VPMAXSQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXSQMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINSQ128", argLength: 2, reg: w21, asm: "VPMINSQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINSQMasked128", argLength: 3, reg: w2kw, asm: "VPMINSQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULDQMasked128", argLength: 3, reg: w2kw, asm: "VPMULDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULLQ128", argLength: 2, reg: w21, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULLQMasked128", argLength: 3, reg: w2kw, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPORQMasked128", argLength: 3, reg: w2kw, asm: "VPORQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPOPCNTQ128", argLength: 1, reg: w11, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPOPCNTQMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPROLVQ128", argLength: 2, reg: w21, asm: "VPROLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPROLVQMasked128", argLength: 3, reg: w2kw, asm: "VPROLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPRORVQ128", argLength: 2, reg: w21, asm: "VPRORVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPRORVQMasked128", argLength: 3, reg: w2kw, asm: "VPRORVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSLLQ128", argLength: 2, reg: vfpv, asm: "VPSLLQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSLLQMasked128", argLength: 3, reg: wfpkw, asm: "VPSLLQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRAQ128", argLength: 2, reg: wfpw, asm: "VPSRAQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRAQMasked128", argLength: 3, reg: wfpkw, asm: "VPSRAQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSLLVQ128", argLength: 2, reg: v21, asm: "VPSLLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHLDVQ128", argLength: 3, reg: w31, asm: "VPSHLDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSHLDVQMasked128", argLength: 4, reg: w3kw, asm: "VPSHLDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSLLVQMasked128", argLength: 3, reg: w2kw, asm: "VPSLLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRAVQ128", argLength: 2, reg: w21, asm: "VPSRAVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHRDVQ128", argLength: 3, reg: w31, asm: "VPSHRDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSHRDVQMasked128", argLength: 4, reg: w3kw, asm: "VPSHRDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSRAVQMasked128", argLength: 3, reg: w2kw, asm: "VPSRAVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSUBQ128", argLength: 2, reg: v21, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSUBQMasked128", argLength: 3, reg: w2kw, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPXORQMasked128", argLength: 3, reg: w2kw, asm: "VPXORQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPABSQ256", argLength: 1, reg: w11, asm: "VPABSQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPABSQMasked256", argLength: 2, reg: wkw, asm: "VPABSQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPADDQ256", argLength: 2, reg: v21, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPADDQMasked256", argLength: 3, reg: w2kw, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPANDQMasked256", argLength: 3, reg: w2kw, asm: "VPANDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPANDNQMasked256", argLength: 3, reg: w2kw, asm: "VPANDNQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPCOMPRESSQMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPCMPEQQ256", argLength: 2, reg: v21, asm: "VPCMPEQQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPCMPGTQ256", argLength: 2, reg: v21, asm: "VPCMPGTQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXSQ256", argLength: 2, reg: w21, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXSQMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINSQ256", argLength: 2, reg: w21, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINSQMasked256", argLength: 3, reg: w2kw, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULDQMasked256", argLength: 3, reg: w2kw, asm: "VPMULDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULLQ256", argLength: 2, reg: w21, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULLQMasked256", argLength: 3, reg: w2kw, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPORQMasked256", argLength: 3, reg: w2kw, asm: "VPORQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPOPCNTQ256", argLength: 1, reg: w11, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPOPCNTQMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPROLVQ256", argLength: 2, reg: w21, asm: "VPROLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPROLVQMasked256", argLength: 3, reg: w2kw, asm: "VPROLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPRORVQ256", argLength: 2, reg: w21, asm: "VPRORVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPRORVQMasked256", argLength: 3, reg: w2kw, asm: "VPRORVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSLLQ256", argLength: 2, reg: vfpv, asm: "VPSLLQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSLLQMasked256", argLength: 3, reg: wfpkw, asm: "VPSLLQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRAQ256", argLength: 2, reg: wfpw, asm: "VPSRAQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRAQMasked256", argLength: 3, reg: wfpkw, asm: "VPSRAQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSLLVQ256", argLength: 2, reg: v21, asm: "VPSLLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHLDVQ256", argLength: 3, reg: w31, asm: "VPSHLDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPSHLDVQMasked256", argLength: 4, reg: w3kw, asm: "VPSHLDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPSLLVQMasked256", argLength: 3, reg: w2kw, asm: "VPSLLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRAVQ256", argLength: 2, reg: w21, asm: "VPSRAVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHRDVQ256", argLength: 3, reg: w31, asm: "VPSHRDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPSHRDVQMasked256", argLength: 4, reg: w3kw, asm: "VPSHRDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPSRAVQMasked256", argLength: 3, reg: w2kw, asm: "VPSRAVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSUBQ256", argLength: 2, reg: v21, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSUBQMasked256", argLength: 3, reg: w2kw, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPXORQMasked256", argLength: 3, reg: w2kw, asm: "VPXORQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPABSQ512", argLength: 1, reg: w11, asm: "VPABSQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPABSQMasked512", argLength: 2, reg: wkw, asm: "VPABSQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPADDQ512", argLength: 2, reg: w21, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPADDQMasked512", argLength: 3, reg: w2kw, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPANDQ512", argLength: 2, reg: w21, asm: "VPANDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPANDQMasked512", argLength: 3, reg: w2kw, asm: "VPANDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPANDNQ512", argLength: 2, reg: w21, asm: "VPANDNQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPANDNQMasked512", argLength: 3, reg: w2kw, asm: "VPANDNQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPCOMPRESSQMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXSQ512", argLength: 2, reg: w21, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXSQMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINSQ512", argLength: 2, reg: w21, asm: "VPMINSQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINSQMasked512", argLength: 3, reg: w2kw, asm: "VPMINSQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULDQ512", argLength: 2, reg: w21, asm: "VPMULDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULDQMasked512", argLength: 3, reg: w2kw, asm: "VPMULDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULLQ512", argLength: 2, reg: w21, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULLQMasked512", argLength: 3, reg: w2kw, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPORQ512", argLength: 2, reg: w21, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPORQMasked512", argLength: 3, reg: w2kw, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPOPCNTQ512", argLength: 1, reg: w11, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPOPCNTQMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPROLVQ512", argLength: 2, reg: w21, asm: "VPROLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPROLVQMasked512", argLength: 3, reg: w2kw, asm: "VPROLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPRORVQ512", argLength: 2, reg: w21, asm: "VPRORVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPRORVQMasked512", argLength: 3, reg: w2kw, asm: "VPRORVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSLLQ512", argLength: 2, reg: wfpw, asm: "VPSLLQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSLLQMasked512", argLength: 3, reg: wfpkw, asm: "VPSLLQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRAQ512", argLength: 2, reg: wfpw, asm: "VPSRAQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRAQMasked512", argLength: 3, reg: wfpkw, asm: "VPSRAQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSLLVQ512", argLength: 2, reg: w21, asm: "VPSLLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHLDVQ512", argLength: 3, reg: w31, asm: "VPSHLDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPSHLDVQMasked512", argLength: 4, reg: w3kw, asm: "VPSHLDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPSLLVQMasked512", argLength: 3, reg: w2kw, asm: "VPSLLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRAVQ512", argLength: 2, reg: w21, asm: "VPSRAVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHRDVQ512", argLength: 3, reg: w31, asm: "VPSHRDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPSHRDVQMasked512", argLength: 4, reg: w3kw, asm: "VPSHRDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPSRAVQMasked512", argLength: 3, reg: w2kw, asm: "VPSRAVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSUBQ512", argLength: 2, reg: w21, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSUBQMasked512", argLength: 3, reg: w2kw, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPXORQ512", argLength: 2, reg: w21, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPXORQMasked512", argLength: 3, reg: w2kw, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPABSB128", argLength: 1, reg: v11, asm: "VPABSB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPABSBMasked128", argLength: 2, reg: wkw, asm: "VPABSB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPADDB128", argLength: 2, reg: v21, asm: "VPADDB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPADDBMasked128", argLength: 3, reg: w2kw, asm: "VPADDB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPAND128", argLength: 2, reg: v21, asm: "VPAND", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPANDN128", argLength: 2, reg: v21, asm: "VPANDN", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPCOMPRESSBMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPEQB128", argLength: 2, reg: v21, asm: "VPCMPEQB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPGTB128", argLength: 2, reg: v21, asm: "VPCMPGTB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXSB128", argLength: 2, reg: v21, asm: "VPMAXSB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXSBMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINSB128", argLength: 2, reg: v21, asm: "VPMINSB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINSBMasked128", argLength: 3, reg: w2kw, asm: "VPMINSB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPOR128", argLength: 2, reg: v21, asm: "VPOR", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPOPCNTB128", argLength: 1, reg: w11, asm: "VPOPCNTB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPOPCNTBMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPADDSB128", argLength: 2, reg: v21, asm: "VPADDSB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPADDSBMasked128", argLength: 3, reg: w2kw, asm: "VPADDSB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPSUBSB128", argLength: 2, reg: v21, asm: "VPSUBSB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSUBSBMasked128", argLength: 3, reg: w2kw, asm: "VPSUBSB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSIGNB128", argLength: 2, reg: v21, asm: "VPSIGNB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSUBB128", argLength: 2, reg: v21, asm: "VPSUBB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSUBBMasked128", argLength: 3, reg: w2kw, asm: "VPSUBB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPXOR128", argLength: 2, reg: v21, asm: "VPXOR", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPABSB256", argLength: 1, reg: v11, asm: "VPABSB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPABSBMasked256", argLength: 2, reg: wkw, asm: "VPABSB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPADDB256", argLength: 2, reg: v21, asm: "VPADDB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPADDBMasked256", argLength: 3, reg: w2kw, asm: "VPADDB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPAND256", argLength: 2, reg: v21, asm: "VPAND", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPANDN256", argLength: 2, reg: v21, asm: "VPANDN", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPCOMPRESSBMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPCMPEQB256", argLength: 2, reg: v21, asm: "VPCMPEQB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPCMPGTB256", argLength: 2, reg: v21, asm: "VPCMPGTB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXSB256", argLength: 2, reg: v21, asm: "VPMAXSB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXSBMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINSB256", argLength: 2, reg: v21, asm: "VPMINSB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINSBMasked256", argLength: 3, reg: w2kw, asm: "VPMINSB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPOR256", argLength: 2, reg: v21, asm: "VPOR", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPOPCNTB256", argLength: 1, reg: w11, asm: "VPOPCNTB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPOPCNTBMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPADDSB256", argLength: 2, reg: v21, asm: "VPADDSB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPADDSBMasked256", argLength: 3, reg: w2kw, asm: "VPADDSB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPSUBSB256", argLength: 2, reg: v21, asm: "VPSUBSB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSUBSBMasked256", argLength: 3, reg: w2kw, asm: "VPSUBSB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSIGNB256", argLength: 2, reg: v21, asm: "VPSIGNB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSUBB256", argLength: 2, reg: v21, asm: "VPSUBB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSUBBMasked256", argLength: 3, reg: w2kw, asm: "VPSUBB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPXOR256", argLength: 2, reg: v21, asm: "VPXOR", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPABSB512", argLength: 1, reg: w11, asm: "VPABSB", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPABSBMasked512", argLength: 2, reg: wkw, asm: "VPABSB", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPADDB512", argLength: 2, reg: w21, asm: "VPADDB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPADDBMasked512", argLength: 3, reg: w2kw, asm: "VPADDB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPCOMPRESSBMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSB", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXSB512", argLength: 2, reg: w21, asm: "VPMAXSB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXSBMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINSB512", argLength: 2, reg: w21, asm: "VPMINSB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINSBMasked512", argLength: 3, reg: w2kw, asm: "VPMINSB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPOPCNTB512", argLength: 1, reg: w11, asm: "VPOPCNTB", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPOPCNTBMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTB", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPADDSB512", argLength: 2, reg: w21, asm: "VPADDSB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPADDSBMasked512", argLength: 3, reg: w2kw, asm: "VPADDSB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPSUBSB512", argLength: 2, reg: w21, asm: "VPSUBSB", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSUBSBMasked512", argLength: 3, reg: w2kw, asm: "VPSUBSB", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSUBB512", argLength: 2, reg: w21, asm: "VPSUBB", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSUBBMasked512", argLength: 3, reg: w2kw, asm: "VPSUBB", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPAVGW256", argLength: 2, reg: v21, asm: "VPAVGW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPAVGWMasked256", argLength: 3, reg: w2kw, asm: "VPAVGW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXUW256", argLength: 2, reg: v21, asm: "VPMAXUW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXUWMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINUW256", argLength: 2, reg: v21, asm: "VPMINUW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINUWMasked256", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULHUW256", argLength: 2, reg: v21, asm: "VPMULHUW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULHUWMasked256", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPERMW256", argLength: 2, reg: w21, asm: "VPERMW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPERMI2W256", argLength: 3, reg: w31, asm: "VPERMI2W", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPERMI2WMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2W", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPERMWMasked256", argLength: 3, reg: w2kw, asm: "VPERMW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRLW256", argLength: 2, reg: vfpv, asm: "VPSRLW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRLWMasked256", argLength: 3, reg: wfpkw, asm: "VPSRLW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRLVW256", argLength: 2, reg: w21, asm: "VPSRLVW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRLVWMasked256", argLength: 3, reg: w2kw, asm: "VPSRLVW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPAVGW512", argLength: 2, reg: w21, asm: "VPAVGW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPAVGWMasked512", argLength: 3, reg: w2kw, asm: "VPAVGW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXUW512", argLength: 2, reg: w21, asm: "VPMAXUW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXUWMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINUW512", argLength: 2, reg: w21, asm: "VPMINUW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINUWMasked512", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULHUW512", argLength: 2, reg: w21, asm: "VPMULHUW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULHUWMasked512", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPERMW512", argLength: 2, reg: w21, asm: "VPERMW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPERMI2W512", argLength: 3, reg: w31, asm: "VPERMI2W", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPERMI2WMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2W", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPERMWMasked512", argLength: 3, reg: w2kw, asm: "VPERMW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRLW512", argLength: 2, reg: wfpw, asm: "VPSRLW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRLWMasked512", argLength: 3, reg: wfpkw, asm: "VPSRLW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRLVW512", argLength: 2, reg: w21, asm: "VPSRLVW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRLVWMasked512", argLength: 3, reg: w2kw, asm: "VPSRLVW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPAVGW128", argLength: 2, reg: v21, asm: "VPAVGW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPAVGWMasked128", argLength: 3, reg: w2kw, asm: "VPAVGW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXUW128", argLength: 2, reg: v21, asm: "VPMAXUW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXUWMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINUW128", argLength: 2, reg: v21, asm: "VPMINUW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINUWMasked128", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULHUW128", argLength: 2, reg: v21, asm: "VPMULHUW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULHUWMasked128", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPERMW128", argLength: 2, reg: w21, asm: "VPERMW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPERMI2W128", argLength: 3, reg: w31, asm: "VPERMI2W", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPERMI2WMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2W", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPERMWMasked128", argLength: 3, reg: w2kw, asm: "VPERMW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRLW128", argLength: 2, reg: vfpv, asm: "VPSRLW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRLWMasked128", argLength: 3, reg: wfpkw, asm: "VPSRLW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRLVW128", argLength: 2, reg: w21, asm: "VPSRLVW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRLVWMasked128", argLength: 3, reg: w2kw, asm: "VPSRLVW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXUD512", argLength: 2, reg: w21, asm: "VPMAXUD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXUDMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINUD512", argLength: 2, reg: w21, asm: "VPMINUD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINUDMasked512", argLength: 3, reg: w2kw, asm: "VPMINUD", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPERMD512", argLength: 2, reg: w21, asm: "VPERMD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPERMPS512", argLength: 2, reg: w21, asm: "VPERMPS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPERMI2PS512", argLength: 3, reg: w31, asm: "VPERMI2PS", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPERMI2D512", argLength: 3, reg: w31, asm: "VPERMI2D", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPERMI2PSMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2PS", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPERMI2DMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2D", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPERMPSMasked512", argLength: 3, reg: w2kw, asm: "VPERMPS", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPERMDMasked512", argLength: 3, reg: w2kw, asm: "VPERMD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRLD512", argLength: 2, reg: wfpw, asm: "VPSRLD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRLDMasked512", argLength: 3, reg: wfpkw, asm: "VPSRLD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRLVD512", argLength: 2, reg: w21, asm: "VPSRLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRLVDMasked512", argLength: 3, reg: w2kw, asm: "VPSRLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXUD128", argLength: 2, reg: v21, asm: "VPMAXUD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXUDMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINUD128", argLength: 2, reg: v21, asm: "VPMINUD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINUDMasked128", argLength: 3, reg: w2kw, asm: "VPMINUD", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULUDQ128", argLength: 2, reg: v21, asm: "VPMULUDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPERMI2D128", argLength: 3, reg: w31, asm: "VPERMI2D", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPERMI2PS128", argLength: 3, reg: w31, asm: "VPERMI2PS", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPERMI2PSMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2PS", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPERMI2DMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2D", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSRLD128", argLength: 2, reg: vfpv, asm: "VPSRLD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRLDMasked128", argLength: 3, reg: wfpkw, asm: "VPSRLD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRLVD128", argLength: 2, reg: v21, asm: "VPSRLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRLVDMasked128", argLength: 3, reg: w2kw, asm: "VPSRLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXUD256", argLength: 2, reg: v21, asm: "VPMAXUD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXUDMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINUD256", argLength: 2, reg: v21, asm: "VPMINUD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINUDMasked256", argLength: 3, reg: w2kw, asm: "VPMINUD", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULUDQ256", argLength: 2, reg: v21, asm: "VPMULUDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPERMPS256", argLength: 2, reg: v21, asm: "VPERMPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPERMD256", argLength: 2, reg: v21, asm: "VPERMD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPERMI2D256", argLength: 3, reg: w31, asm: "VPERMI2D", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPERMI2PS256", argLength: 3, reg: w31, asm: "VPERMI2PS", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPERMI2DMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2D", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPERMI2PSMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2PS", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPERMPSMasked256", argLength: 3, reg: w2kw, asm: "VPERMPS", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPERMDMasked256", argLength: 3, reg: w2kw, asm: "VPERMD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRLD256", argLength: 2, reg: vfpv, asm: "VPSRLD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRLDMasked256", argLength: 3, reg: wfpkw, asm: "VPSRLD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRLVD256", argLength: 2, reg: v21, asm: "VPSRLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRLVDMasked256", argLength: 3, reg: w2kw, asm: "VPSRLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXUQ128", argLength: 2, reg: w21, asm: "VPMAXUQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXUQMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINUQ128", argLength: 2, reg: w21, asm: "VPMINUQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINUQMasked128", argLength: 3, reg: w2kw, asm: "VPMINUQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMULUDQMasked128", argLength: 3, reg: w2kw, asm: "VPMULUDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPERMI2PD128", argLength: 3, reg: w31, asm: "VPERMI2PD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPERMI2Q128", argLength: 3, reg: w31, asm: "VPERMI2Q", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPERMI2PDMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2PD", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPERMI2QMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2Q", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPSRLQ128", argLength: 2, reg: vfpv, asm: "VPSRLQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRLQMasked128", argLength: 3, reg: wfpkw, asm: "VPSRLQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRLVQ128", argLength: 2, reg: v21, asm: "VPSRLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSRLVQMasked128", argLength: 3, reg: w2kw, asm: "VPSRLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXUQ256", argLength: 2, reg: w21, asm: "VPMAXUQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXUQMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINUQ256", argLength: 2, reg: w21, asm: "VPMINUQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINUQMasked256", argLength: 3, reg: w2kw, asm: "VPMINUQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMULUDQMasked256", argLength: 3, reg: w2kw, asm: "VPMULUDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPERMQ256", argLength: 2, reg: w21, asm: "VPERMQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPERMPD256", argLength: 2, reg: w21, asm: "VPERMPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPERMI2Q256", argLength: 3, reg: w31, asm: "VPERMI2Q", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPERMI2PD256", argLength: 3, reg: w31, asm: "VPERMI2PD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPERMI2PDMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2PD", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPERMI2QMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2Q", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPERMQMasked256", argLength: 3, reg: w2kw, asm: "VPERMQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPERMPDMasked256", argLength: 3, reg: w2kw, asm: "VPERMPD", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRLQ256", argLength: 2, reg: vfpv, asm: "VPSRLQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRLQMasked256", argLength: 3, reg: wfpkw, asm: "VPSRLQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRLVQ256", argLength: 2, reg: v21, asm: "VPSRLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSRLVQMasked256", argLength: 3, reg: w2kw, asm: "VPSRLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXUQ512", argLength: 2, reg: w21, asm: "VPMAXUQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXUQMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINUQ512", argLength: 2, reg: w21, asm: "VPMINUQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINUQMasked512", argLength: 3, reg: w2kw, asm: "VPMINUQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULUDQ512", argLength: 2, reg: w21, asm: "VPMULUDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMULUDQMasked512", argLength: 3, reg: w2kw, asm: "VPMULUDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPERMPD512", argLength: 2, reg: w21, asm: "VPERMPD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPERMQ512", argLength: 2, reg: w21, asm: "VPERMQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPERMI2Q512", argLength: 3, reg: w31, asm: "VPERMI2Q", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPERMI2PD512", argLength: 3, reg: w31, asm: "VPERMI2PD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPERMI2QMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2Q", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPERMI2PDMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2PD", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPERMQMasked512", argLength: 3, reg: w2kw, asm: "VPERMQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPERMPDMasked512", argLength: 3, reg: w2kw, asm: "VPERMPD", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRLQ512", argLength: 2, reg: wfpw, asm: "VPSRLQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRLQMasked512", argLength: 3, reg: wfpkw, asm: "VPSRLQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRLVQ512", argLength: 2, reg: w21, asm: "VPSRLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSRLVQMasked512", argLength: 3, reg: w2kw, asm: "VPSRLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPAVGB128", argLength: 2, reg: v21, asm: "VPAVGB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPAVGBMasked128", argLength: 3, reg: w2kw, asm: "VPAVGB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VGF2P8MULB128", argLength: 2, reg: w21, asm: "VGF2P8MULB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VGF2P8MULBMasked128", argLength: 3, reg: w2kw, asm: "VGF2P8MULB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXUB128", argLength: 2, reg: v21, asm: "VPMAXUB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMAXUBMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINUB128", argLength: 2, reg: v21, asm: "VPMINUB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPMINUBMasked128", argLength: 3, reg: w2kw, asm: "VPMINUB", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VPERMB128", argLength: 2, reg: w21, asm: "VPERMB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPERMI2B128", argLength: 3, reg: w31, asm: "VPERMI2B", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPERMI2BMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2B", commutative: false, typ: "Vec128", resultInArg0: true},
+		{name: "VPERMBMasked128", argLength: 3, reg: w2kw, asm: "VPERMB", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPMADDUBSW128", argLength: 2, reg: v21, asm: "VPMADDUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPMADDUBSWMasked128", argLength: 3, reg: w2kw, asm: "VPMADDUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPAVGB256", argLength: 2, reg: v21, asm: "VPAVGB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPAVGBMasked256", argLength: 3, reg: w2kw, asm: "VPAVGB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VGF2P8MULB256", argLength: 2, reg: w21, asm: "VGF2P8MULB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VGF2P8MULBMasked256", argLength: 3, reg: w2kw, asm: "VGF2P8MULB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXUB256", argLength: 2, reg: v21, asm: "VPMAXUB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMAXUBMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINUB256", argLength: 2, reg: v21, asm: "VPMINUB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPMINUBMasked256", argLength: 3, reg: w2kw, asm: "VPMINUB", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VPERMB256", argLength: 2, reg: w21, asm: "VPERMB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPERMI2B256", argLength: 3, reg: w31, asm: "VPERMI2B", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPERMI2BMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2B", commutative: false, typ: "Vec256", resultInArg0: true},
+		{name: "VPERMBMasked256", argLength: 3, reg: w2kw, asm: "VPERMB", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPMADDUBSW256", argLength: 2, reg: v21, asm: "VPMADDUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPMADDUBSWMasked256", argLength: 3, reg: w2kw, asm: "VPMADDUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPAVGB512", argLength: 2, reg: w21, asm: "VPAVGB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPAVGBMasked512", argLength: 3, reg: w2kw, asm: "VPAVGB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VGF2P8MULB512", argLength: 2, reg: w21, asm: "VGF2P8MULB", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VGF2P8MULBMasked512", argLength: 3, reg: w2kw, asm: "VGF2P8MULB", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXUB512", argLength: 2, reg: w21, asm: "VPMAXUB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMAXUBMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINUB512", argLength: 2, reg: w21, asm: "VPMINUB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPMINUBMasked512", argLength: 3, reg: w2kw, asm: "VPMINUB", commutative: true, typ: "Vec512", resultInArg0: false},
+		{name: "VPERMB512", argLength: 2, reg: w21, asm: "VPERMB", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPERMI2B512", argLength: 3, reg: w31, asm: "VPERMI2B", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPERMI2BMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2B", commutative: false, typ: "Vec512", resultInArg0: true},
+		{name: "VPERMBMasked512", argLength: 3, reg: w2kw, asm: "VPERMB", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPMADDUBSW512", argLength: 2, reg: w21, asm: "VPMADDUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPMADDUBSWMasked512", argLength: 3, reg: w2kw, asm: "VPMADDUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VRNDSCALEPS512", argLength: 1, reg: w11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VRNDSCALEPSMasked512", argLength: 2, reg: wkw, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VREDUCEPS512", argLength: 1, reg: w11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VREDUCEPSMasked512", argLength: 2, reg: wkw, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VCMPPS512", argLength: 2, reg: w2k, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VCMPPSMasked512", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VROUNDPS128", argLength: 1, reg: v11, asm: "VROUNDPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VRNDSCALEPS128", argLength: 1, reg: w11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VRNDSCALEPSMasked128", argLength: 2, reg: wkw, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VREDUCEPS128", argLength: 1, reg: w11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VREDUCEPSMasked128", argLength: 2, reg: wkw, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VDPPS128", argLength: 2, reg: v21, asm: "VDPPS", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VCMPPS128", argLength: 2, reg: v21, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VCMPPSMasked128", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VROUNDPS256", argLength: 1, reg: v11, asm: "VROUNDPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VRNDSCALEPS256", argLength: 1, reg: w11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VRNDSCALEPSMasked256", argLength: 2, reg: wkw, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VREDUCEPS256", argLength: 1, reg: w11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VREDUCEPSMasked256", argLength: 2, reg: wkw, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VDPPS256", argLength: 2, reg: v21, asm: "VDPPS", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VCMPPS256", argLength: 2, reg: v21, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VCMPPSMasked256", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VEXTRACTF128128", argLength: 1, reg: v11, asm: "VEXTRACTF128", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VINSERTF128256", argLength: 2, reg: v21, asm: "VINSERTF128", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VROUNDPD128", argLength: 1, reg: v11, asm: "VROUNDPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VRNDSCALEPD128", argLength: 1, reg: w11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VRNDSCALEPDMasked128", argLength: 2, reg: wkw, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VREDUCEPD128", argLength: 1, reg: w11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VREDUCEPDMasked128", argLength: 2, reg: wkw, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VDPPD128", argLength: 2, reg: v21, asm: "VDPPD", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VCMPPD128", argLength: 2, reg: v21, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
+		{name: "VCMPPDMasked128", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VROUNDPD256", argLength: 1, reg: v11, asm: "VROUNDPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VRNDSCALEPD256", argLength: 1, reg: w11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VRNDSCALEPDMasked256", argLength: 2, reg: wkw, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VREDUCEPD256", argLength: 1, reg: w11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VREDUCEPDMasked256", argLength: 2, reg: wkw, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VCMPPD256", argLength: 2, reg: v21, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false},
+		{name: "VCMPPDMasked256", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VRNDSCALEPD512", argLength: 1, reg: w11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VRNDSCALEPDMasked512", argLength: 2, reg: wkw, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VREDUCEPD512", argLength: 1, reg: w11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VREDUCEPDMasked512", argLength: 2, reg: wkw, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VCMPPD512", argLength: 2, reg: w2k, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VCMPPDMasked512", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPWMasked256", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPW256", argLength: 2, reg: w2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPSHLDW256", argLength: 2, reg: w21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHLDWMasked256", argLength: 3, reg: w2kw, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHRDW256", argLength: 2, reg: w21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHRDWMasked256", argLength: 3, reg: w2kw, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPCMPW512", argLength: 2, reg: w2k, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPWMasked512", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPSHLDW512", argLength: 2, reg: w21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHLDWMasked512", argLength: 3, reg: w2kw, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHRDW512", argLength: 2, reg: w21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHRDWMasked512", argLength: 3, reg: w2kw, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPCMPWMasked128", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPEXTRW128", argLength: 1, reg: wgp, asm: "VPEXTRW", aux: "Int8", commutative: false, typ: "int16", resultInArg0: false},
+		{name: "VPCMPW128", argLength: 2, reg: w2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPINSRW128", argLength: 2, reg: vgpv, asm: "VPINSRW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHLDW128", argLength: 2, reg: w21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHLDWMasked128", argLength: 3, reg: w2kw, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHRDW128", argLength: 2, reg: w21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHRDWMasked128", argLength: 3, reg: w2kw, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPD512", argLength: 2, reg: w2k, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPDMasked512", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPROLD512", argLength: 1, reg: w11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPROLDMasked512", argLength: 2, reg: wkw, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPRORD512", argLength: 1, reg: w11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPRORDMasked512", argLength: 2, reg: wkw, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHLDD512", argLength: 2, reg: w21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHLDDMasked512", argLength: 3, reg: w2kw, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHRDD512", argLength: 2, reg: w21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHRDDMasked512", argLength: 3, reg: w2kw, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPCMPDMasked128", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPEXTRD128", argLength: 1, reg: vgp, asm: "VPEXTRD", aux: "Int8", commutative: false, typ: "int32", resultInArg0: false},
+		{name: "VPCMPD128", argLength: 2, reg: w2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPROLD128", argLength: 1, reg: w11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPROLDMasked128", argLength: 2, reg: wkw, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPRORD128", argLength: 1, reg: w11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPRORDMasked128", argLength: 2, reg: wkw, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPINSRD128", argLength: 2, reg: vgpv, asm: "VPINSRD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHLDD128", argLength: 2, reg: w21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHLDDMasked128", argLength: 3, reg: w2kw, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHRDD128", argLength: 2, reg: w21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHRDDMasked128", argLength: 3, reg: w2kw, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPDMasked256", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPD256", argLength: 2, reg: w2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPROLD256", argLength: 1, reg: w11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPROLDMasked256", argLength: 2, reg: wkw, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPRORD256", argLength: 1, reg: w11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPRORDMasked256", argLength: 2, reg: wkw, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHLDD256", argLength: 2, reg: w21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHLDDMasked256", argLength: 3, reg: w2kw, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHRDD256", argLength: 2, reg: w21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHRDDMasked256", argLength: 3, reg: w2kw, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPCMPQMasked128", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPEXTRQ128", argLength: 1, reg: vgp, asm: "VPEXTRQ", aux: "Int8", commutative: false, typ: "int64", resultInArg0: false},
+		{name: "VPCMPQ128", argLength: 2, reg: w2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPROLQ128", argLength: 1, reg: w11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPROLQMasked128", argLength: 2, reg: wkw, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPRORQ128", argLength: 1, reg: w11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPRORQMasked128", argLength: 2, reg: wkw, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPINSRQ128", argLength: 2, reg: vgpv, asm: "VPINSRQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHLDQ128", argLength: 2, reg: w21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHLDQMasked128", argLength: 3, reg: w2kw, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHRDQ128", argLength: 2, reg: w21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPSHRDQMasked128", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPQMasked256", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPQ256", argLength: 2, reg: w2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPROLQ256", argLength: 1, reg: w11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPROLQMasked256", argLength: 2, reg: wkw, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPRORQ256", argLength: 1, reg: w11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPRORQMasked256", argLength: 2, reg: wkw, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHLDQ256", argLength: 2, reg: w21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHLDQMasked256", argLength: 3, reg: w2kw, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHRDQ256", argLength: 2, reg: w21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPSHRDQMasked256", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPCMPQ512", argLength: 2, reg: w2k, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPQMasked512", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPROLQ512", argLength: 1, reg: w11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPROLQMasked512", argLength: 2, reg: wkw, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPRORQ512", argLength: 1, reg: w11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPRORQMasked512", argLength: 2, reg: wkw, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHLDQ512", argLength: 2, reg: w21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHLDQMasked512", argLength: 3, reg: w2kw, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHRDQ512", argLength: 2, reg: w21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPSHRDQMasked512", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VPCMPBMasked128", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPEXTRB128", argLength: 1, reg: wgp, asm: "VPEXTRB", aux: "Int8", commutative: false, typ: "int8", resultInArg0: false},
+		{name: "VPCMPB128", argLength: 2, reg: w2k, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPINSRB128", argLength: 2, reg: vgpv, asm: "VPINSRB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPBMasked256", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VEXTRACTI128128", argLength: 1, reg: v11, asm: "VEXTRACTI128", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPB256", argLength: 2, reg: w2k, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VINSERTI128256", argLength: 2, reg: v21, asm: "VINSERTI128", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPCMPB512", argLength: 2, reg: w2k, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPBMasked512", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUWMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUW256", argLength: 2, reg: w2k, asm: "VPCMPUW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUW512", argLength: 2, reg: w2k, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUWMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUWMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUW128", argLength: 2, reg: w2k, asm: "VPCMPUW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUD512", argLength: 2, reg: w2k, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUDMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUDMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUD128", argLength: 2, reg: w2k, asm: "VPCMPUD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUDMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUD256", argLength: 2, reg: w2k, asm: "VPCMPUD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUQMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUQ128", argLength: 2, reg: w2k, asm: "VPCMPUQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUQMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUQ256", argLength: 2, reg: w2k, asm: "VPCMPUQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUQ512", argLength: 2, reg: w2k, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUQMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUBMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VGF2P8AFFINEQB128", argLength: 2, reg: w21, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VGF2P8AFFINEINVQB128", argLength: 2, reg: w21, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VGF2P8AFFINEINVQBMasked128", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VGF2P8AFFINEQBMasked128", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+		{name: "VPCMPUB128", argLength: 2, reg: w2k, asm: "VPCMPUB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUBMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VGF2P8AFFINEQB256", argLength: 2, reg: w21, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VGF2P8AFFINEINVQB256", argLength: 2, reg: w21, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VGF2P8AFFINEINVQBMasked256", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VGF2P8AFFINEQBMasked256", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+		{name: "VPCMPUB256", argLength: 2, reg: w2k, asm: "VPCMPUB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUB512", argLength: 2, reg: w2k, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VPCMPUBMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+		{name: "VGF2P8AFFINEQB512", argLength: 2, reg: w21, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VGF2P8AFFINEINVQB512", argLength: 2, reg: w21, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VGF2P8AFFINEINVQBMasked512", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+		{name: "VGF2P8AFFINEQBMasked512", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+	}
+}
diff --git a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
new file mode 100644
index 00000000000000..c8fe1e9eeee6d3
--- /dev/null
+++ b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
@@ -0,0 +1,1798 @@
+// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT.
+package main
+
+func simdGenericOps() []opData {
+	return []opData{
+		{name: "AddFloat32x16", argLength: 2, commutative: true},
+		{name: "AddMaskedFloat32x16", argLength: 3, commutative: true},
+		{name: "ApproximateReciprocalFloat32x16", argLength: 1, commutative: false},
+		{name: "ApproximateReciprocalMaskedFloat32x16", argLength: 2, commutative: false},
+		{name: "ApproximateReciprocalOfSqrtFloat32x16", argLength: 1, commutative: false},
+		{name: "ApproximateReciprocalOfSqrtMaskedFloat32x16", argLength: 2, commutative: false},
+		{name: "CompressFloat32x16", argLength: 2, commutative: false},
+		{name: "DivFloat32x16", argLength: 2, commutative: false},
+		{name: "DivMaskedFloat32x16", argLength: 3, commutative: false},
+		{name: "EqualFloat32x16", argLength: 2, commutative: true},
+		{name: "EqualMaskedFloat32x16", argLength: 3, commutative: true},
+		{name: "FusedMultiplyAddFloat32x16", argLength: 3, commutative: false},
+		{name: "FusedMultiplyAddMaskedFloat32x16", argLength: 4, commutative: false},
+		{name: "FusedMultiplyAddSubFloat32x16", argLength: 3, commutative: false},
+		{name: "FusedMultiplyAddSubMaskedFloat32x16", argLength: 4, commutative: false},
+		{name: "FusedMultiplySubAddFloat32x16", argLength: 3, commutative: false},
+		{name: "FusedMultiplySubAddMaskedFloat32x16", argLength: 4, commutative: false},
+		{name: "GreaterFloat32x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualFloat32x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedFloat32x16", argLength: 3, commutative: false},
+		{name: "GreaterMaskedFloat32x16", argLength: 3, commutative: false},
+		{name: "IsNanFloat32x16", argLength: 2, commutative: true},
+		{name: "IsNanMaskedFloat32x16", argLength: 3, commutative: true},
+		{name: "LessFloat32x16", argLength: 2, commutative: false},
+		{name: "LessEqualFloat32x16", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedFloat32x16", argLength: 3, commutative: false},
+		{name: "LessMaskedFloat32x16", argLength: 3, commutative: false},
+		{name: "MaxFloat32x16", argLength: 2, commutative: true},
+		{name: "MaxMaskedFloat32x16", argLength: 3, commutative: true},
+		{name: "MinFloat32x16", argLength: 2, commutative: true},
+		{name: "MinMaskedFloat32x16", argLength: 3, commutative: true},
+		{name: "MulFloat32x16", argLength: 2, commutative: true},
+		{name: "MulByPowOf2Float32x16", argLength: 2, commutative: false},
+		{name: "MulByPowOf2MaskedFloat32x16", argLength: 3, commutative: false},
+		{name: "MulMaskedFloat32x16", argLength: 3, commutative: true},
+		{name: "NotEqualFloat32x16", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedFloat32x16", argLength: 3, commutative: true},
+		{name: "SqrtFloat32x16", argLength: 1, commutative: false},
+		{name: "SqrtMaskedFloat32x16", argLength: 2, commutative: false},
+		{name: "SubFloat32x16", argLength: 2, commutative: false},
+		{name: "SubMaskedFloat32x16", argLength: 3, commutative: false},
+		{name: "AddFloat32x4", argLength: 2, commutative: true},
+		{name: "AddMaskedFloat32x4", argLength: 3, commutative: true},
+		{name: "AddSubFloat32x4", argLength: 2, commutative: false},
+		{name: "ApproximateReciprocalFloat32x4", argLength: 1, commutative: false},
+		{name: "ApproximateReciprocalMaskedFloat32x4", argLength: 2, commutative: false},
+		{name: "ApproximateReciprocalOfSqrtFloat32x4", argLength: 1, commutative: false},
+		{name: "ApproximateReciprocalOfSqrtMaskedFloat32x4", argLength: 2, commutative: false},
+		{name: "CeilFloat32x4", argLength: 1, commutative: false},
+		{name: "CompressFloat32x4", argLength: 2, commutative: false},
+		{name: "DivFloat32x4", argLength: 2, commutative: false},
+		{name: "DivMaskedFloat32x4", argLength: 3, commutative: false},
+		{name: "DotProdBroadcastFloat32x4", argLength: 2, commutative: true},
+		{name: "EqualFloat32x4", argLength: 2, commutative: true},
+		{name: "EqualMaskedFloat32x4", argLength: 3, commutative: true},
+		{name: "FloorFloat32x4", argLength: 1, commutative: false},
+		{name: "FusedMultiplyAddFloat32x4", argLength: 3, commutative: false},
+		{name: "FusedMultiplyAddMaskedFloat32x4", argLength: 4, commutative: false},
+		{name: "FusedMultiplyAddSubFloat32x4", argLength: 3, commutative: false},
+		{name: "FusedMultiplyAddSubMaskedFloat32x4", argLength: 4, commutative: false},
+		{name: "FusedMultiplySubAddFloat32x4", argLength: 3, commutative: false},
+		{name: "FusedMultiplySubAddMaskedFloat32x4", argLength: 4, commutative: false},
+		{name: "GreaterFloat32x4", argLength: 2, commutative: false},
+		{name: "GreaterEqualFloat32x4", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedFloat32x4", argLength: 3, commutative: false},
+		{name: "GreaterMaskedFloat32x4", argLength: 3, commutative: false},
+		{name: "IsNanFloat32x4", argLength: 2, commutative: true},
+		{name: "IsNanMaskedFloat32x4", argLength: 3, commutative: true},
+		{name: "LessFloat32x4", argLength: 2, commutative: false},
+		{name: "LessEqualFloat32x4", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedFloat32x4", argLength: 3, commutative: false},
+		{name: "LessMaskedFloat32x4", argLength: 3, commutative: false},
+		{name: "MaxFloat32x4", argLength: 2, commutative: true},
+		{name: "MaxMaskedFloat32x4", argLength: 3, commutative: true},
+		{name: "MinFloat32x4", argLength: 2, commutative: true},
+		{name: "MinMaskedFloat32x4", argLength: 3, commutative: true},
+		{name: "MulFloat32x4", argLength: 2, commutative: true},
+		{name: "MulByPowOf2Float32x4", argLength: 2, commutative: false},
+		{name: "MulByPowOf2MaskedFloat32x4", argLength: 3, commutative: false},
+		{name: "MulMaskedFloat32x4", argLength: 3, commutative: true},
+		{name: "NotEqualFloat32x4", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedFloat32x4", argLength: 3, commutative: true},
+		{name: "PairwiseAddFloat32x4", argLength: 2, commutative: false},
+		{name: "PairwiseSubFloat32x4", argLength: 2, commutative: false},
+		{name: "RoundFloat32x4", argLength: 1, commutative: false},
+		{name: "SqrtFloat32x4", argLength: 1, commutative: false},
+		{name: "SqrtMaskedFloat32x4", argLength: 2, commutative: false},
+		{name: "SubFloat32x4", argLength: 2, commutative: false},
+		{name: "SubMaskedFloat32x4", argLength: 3, commutative: false},
+		{name: "TruncFloat32x4", argLength: 1, commutative: false},
+		{name: "AddFloat32x8", argLength: 2, commutative: true},
+		{name: "AddMaskedFloat32x8", argLength: 3, commutative: true},
+		{name: "AddSubFloat32x8", argLength: 2, commutative: false},
+		{name: "ApproximateReciprocalFloat32x8", argLength: 1, commutative: false},
+		{name: "ApproximateReciprocalMaskedFloat32x8", argLength: 2, commutative: false},
+		{name: "ApproximateReciprocalOfSqrtFloat32x8", argLength: 1, commutative: false},
+		{name: "ApproximateReciprocalOfSqrtMaskedFloat32x8", argLength: 2, commutative: false},
+		{name: "CeilFloat32x8", argLength: 1, commutative: false},
+		{name: "CompressFloat32x8", argLength: 2, commutative: false},
+		{name: "DivFloat32x8", argLength: 2, commutative: false},
+		{name: "DivMaskedFloat32x8", argLength: 3, commutative: false},
+		{name: "DotProdBroadcastFloat32x8", argLength: 2, commutative: true},
+		{name: "EqualFloat32x8", argLength: 2, commutative: true},
+		{name: "EqualMaskedFloat32x8", argLength: 3, commutative: true},
+		{name: "FloorFloat32x8", argLength: 1, commutative: false},
+		{name: "FusedMultiplyAddFloat32x8", argLength: 3, commutative: false},
+		{name: "FusedMultiplyAddMaskedFloat32x8", argLength: 4, commutative: false},
+		{name: "FusedMultiplyAddSubFloat32x8", argLength: 3, commutative: false},
+		{name: "FusedMultiplyAddSubMaskedFloat32x8", argLength: 4, commutative: false},
+		{name: "FusedMultiplySubAddFloat32x8", argLength: 3, commutative: false},
+		{name: "FusedMultiplySubAddMaskedFloat32x8", argLength: 4, commutative: false},
+		{name: "GreaterFloat32x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualFloat32x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedFloat32x8", argLength: 3, commutative: false},
+		{name: "GreaterMaskedFloat32x8", argLength: 3, commutative: false},
+		{name: "IsNanFloat32x8", argLength: 2, commutative: true},
+		{name: "IsNanMaskedFloat32x8", argLength: 3, commutative: true},
+		{name: "LessFloat32x8", argLength: 2, commutative: false},
+		{name: "LessEqualFloat32x8", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedFloat32x8", argLength: 3, commutative: false},
+		{name: "LessMaskedFloat32x8", argLength: 3, commutative: false},
+		{name: "MaxFloat32x8", argLength: 2, commutative: true},
+		{name: "MaxMaskedFloat32x8", argLength: 3, commutative: true},
+		{name: "MinFloat32x8", argLength: 2, commutative: true},
+		{name: "MinMaskedFloat32x8", argLength: 3, commutative: true},
+		{name: "MulFloat32x8", argLength: 2, commutative: true},
+		{name: "MulByPowOf2Float32x8", argLength: 2, commutative: false},
+		{name: "MulByPowOf2MaskedFloat32x8", argLength: 3, commutative: false},
+		{name: "MulMaskedFloat32x8", argLength: 3, commutative: true},
+		{name: "NotEqualFloat32x8", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedFloat32x8", argLength: 3, commutative: true},
+		{name: "PairwiseAddFloat32x8", argLength: 2, commutative: false},
+		{name: "PairwiseSubFloat32x8", argLength: 2, commutative: false},
+		{name: "RoundFloat32x8", argLength: 1, commutative: false},
+		{name: "SqrtFloat32x8", argLength: 1, commutative: false},
+		{name: "SqrtMaskedFloat32x8", argLength: 2, commutative: false},
+		{name: "SubFloat32x8", argLength: 2, commutative: false},
+		{name: "SubMaskedFloat32x8", argLength: 3, commutative: false},
+		{name: "TruncFloat32x8", argLength: 1, commutative: false},
+		{name: "AddFloat64x2", argLength: 2, commutative: true},
+		{name: "AddMaskedFloat64x2", argLength: 3, commutative: true},
+		{name: "AddSubFloat64x2", argLength: 2, commutative: false},
+		{name: "ApproximateReciprocalFloat64x2", argLength: 1, commutative: false},
+		{name: "ApproximateReciprocalMaskedFloat64x2", argLength: 2, commutative: false},
+		{name: "ApproximateReciprocalOfSqrtFloat64x2", argLength: 1, commutative: false},
+		{name: "ApproximateReciprocalOfSqrtMaskedFloat64x2", argLength: 2, commutative: false},
+		{name: "CeilFloat64x2", argLength: 1, commutative: false},
+		{name: "CompressFloat64x2", argLength: 2, commutative: false},
+		{name: "DivFloat64x2", argLength: 2, commutative: false},
+		{name: "DivMaskedFloat64x2", argLength: 3, commutative: false},
+		{name: "DotProdBroadcastFloat64x2", argLength: 2, commutative: true},
+		{name: "EqualFloat64x2", argLength: 2, commutative: true},
+		{name: "EqualMaskedFloat64x2", argLength: 3, commutative: true},
+		{name: "FloorFloat64x2", argLength: 1, commutative: false},
+		{name: "FusedMultiplyAddFloat64x2", argLength: 3, commutative: false},
+		{name: "FusedMultiplyAddMaskedFloat64x2", argLength: 4, commutative: false},
+		{name: "FusedMultiplyAddSubFloat64x2", argLength: 3, commutative: false},
+		{name: "FusedMultiplyAddSubMaskedFloat64x2", argLength: 4, commutative: false},
+		{name: "FusedMultiplySubAddFloat64x2", argLength: 3, commutative: false},
+		{name: "FusedMultiplySubAddMaskedFloat64x2", argLength: 4, commutative: false},
+		{name: "GreaterFloat64x2", argLength: 2, commutative: false},
+		{name: "GreaterEqualFloat64x2", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedFloat64x2", argLength: 3, commutative: false},
+		{name: "GreaterMaskedFloat64x2", argLength: 3, commutative: false},
+		{name: "IsNanFloat64x2", argLength: 2, commutative: true},
+		{name: "IsNanMaskedFloat64x2", argLength: 3, commutative: true},
+		{name: "LessFloat64x2", argLength: 2, commutative: false},
+		{name: "LessEqualFloat64x2", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedFloat64x2", argLength: 3, commutative: false},
+		{name: "LessMaskedFloat64x2", argLength: 3, commutative: false},
+		{name: "MaxFloat64x2", argLength: 2, commutative: true},
+		{name: "MaxMaskedFloat64x2", argLength: 3, commutative: true},
+		{name: "MinFloat64x2", argLength: 2, commutative: true},
+		{name: "MinMaskedFloat64x2", argLength: 3, commutative: true},
+		{name: "MulFloat64x2", argLength: 2, commutative: true},
+		{name: "MulByPowOf2Float64x2", argLength: 2, commutative: false},
+		{name: "MulByPowOf2MaskedFloat64x2", argLength: 3, commutative: false},
+		{name: "MulMaskedFloat64x2", argLength: 3, commutative: true},
+		{name: "NotEqualFloat64x2", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedFloat64x2", argLength: 3, commutative: true},
+		{name: "PairwiseAddFloat64x2", argLength: 2, commutative: false},
+		{name: "PairwiseSubFloat64x2", argLength: 2, commutative: false},
+		{name: "RoundFloat64x2", argLength: 1, commutative: false},
+		{name: "SqrtFloat64x2", argLength: 1, commutative: false},
+		{name: "SqrtMaskedFloat64x2", argLength: 2, commutative: false},
+		{name: "SubFloat64x2", argLength: 2, commutative: false},
+		{name: "SubMaskedFloat64x2", argLength: 3, commutative: false},
+		{name: "TruncFloat64x2", argLength: 1, commutative: false},
+		{name: "AddFloat64x4", argLength: 2, commutative: true},
+		{name: "AddMaskedFloat64x4", argLength: 3, commutative: true},
+		{name: "AddSubFloat64x4", argLength: 2, commutative: false},
+		{name: "ApproximateReciprocalFloat64x4", argLength: 1, commutative: false},
+		{name: "ApproximateReciprocalMaskedFloat64x4", argLength: 2, commutative: false},
+		{name: "ApproximateReciprocalOfSqrtFloat64x4", argLength: 1, commutative: false},
+		{name: "ApproximateReciprocalOfSqrtMaskedFloat64x4", argLength: 2, commutative: false},
+		{name: "CeilFloat64x4", argLength: 1, commutative: false},
+		{name: "CompressFloat64x4", argLength: 2, commutative: false},
+		{name: "DivFloat64x4", argLength: 2, commutative: false},
+		{name: "DivMaskedFloat64x4", argLength: 3, commutative: false},
+		{name: "EqualFloat64x4", argLength: 2, commutative: true},
+		{name: "EqualMaskedFloat64x4", argLength: 3, commutative: true},
+		{name: "FloorFloat64x4", argLength: 1, commutative: false},
+		{name: "FusedMultiplyAddFloat64x4", argLength: 3, commutative: false},
+		{name: "FusedMultiplyAddMaskedFloat64x4", argLength: 4, commutative: false},
+		{name: "FusedMultiplyAddSubFloat64x4", argLength: 3, commutative: false},
+		{name: "FusedMultiplyAddSubMaskedFloat64x4", argLength: 4, commutative: false},
+		{name: "FusedMultiplySubAddFloat64x4", argLength: 3, commutative: false},
+		{name: "FusedMultiplySubAddMaskedFloat64x4", argLength: 4, commutative: false},
+		{name: "GreaterFloat64x4", argLength: 2, commutative: false},
+		{name: "GreaterEqualFloat64x4", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedFloat64x4", argLength: 3, commutative: false},
+		{name: "GreaterMaskedFloat64x4", argLength: 3, commutative: false},
+		{name: "IsNanFloat64x4", argLength: 2, commutative: true},
+		{name: "IsNanMaskedFloat64x4", argLength: 3, commutative: true},
+		{name: "LessFloat64x4", argLength: 2, commutative: false},
+		{name: "LessEqualFloat64x4", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedFloat64x4", argLength: 3, commutative: false},
+		{name: "LessMaskedFloat64x4", argLength: 3, commutative: false},
+		{name: "MaxFloat64x4", argLength: 2, commutative: true},
+		{name: "MaxMaskedFloat64x4", argLength: 3, commutative: true},
+		{name: "MinFloat64x4", argLength: 2, commutative: true},
+		{name: "MinMaskedFloat64x4", argLength: 3, commutative: true},
+		{name: "MulFloat64x4", argLength: 2, commutative: true},
+		{name: "MulByPowOf2Float64x4", argLength: 2, commutative: false},
+		{name: "MulByPowOf2MaskedFloat64x4", argLength: 3, commutative: false},
+		{name: "MulMaskedFloat64x4", argLength: 3, commutative: true},
+		{name: "NotEqualFloat64x4", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedFloat64x4", argLength: 3, commutative: true},
+		{name: "PairwiseAddFloat64x4", argLength: 2, commutative: false},
+		{name: "PairwiseSubFloat64x4", argLength: 2, commutative: false},
+		{name: "RoundFloat64x4", argLength: 1, commutative: false},
+		{name: "SqrtFloat64x4", argLength: 1, commutative: false},
+		{name: "SqrtMaskedFloat64x4", argLength: 2, commutative: false},
+		{name: "SubFloat64x4", argLength: 2, commutative: false},
+		{name: "SubMaskedFloat64x4", argLength: 3, commutative: false},
+		{name: "TruncFloat64x4", argLength: 1, commutative: false},
+		{name: "AddFloat64x8", argLength: 2, commutative: true},
+		{name: "AddMaskedFloat64x8", argLength: 3, commutative: true},
+		{name: "ApproximateReciprocalFloat64x8", argLength: 1, commutative: false},
+		{name: "ApproximateReciprocalMaskedFloat64x8", argLength: 2, commutative: false},
+		{name: "ApproximateReciprocalOfSqrtFloat64x8", argLength: 1, commutative: false},
+		{name: "ApproximateReciprocalOfSqrtMaskedFloat64x8", argLength: 2, commutative: false},
+		{name: "CompressFloat64x8", argLength: 2, commutative: false},
+		{name: "DivFloat64x8", argLength: 2, commutative: false},
+		{name: "DivMaskedFloat64x8", argLength: 3, commutative: false},
+		{name: "EqualFloat64x8", argLength: 2, commutative: true},
+		{name: "EqualMaskedFloat64x8", argLength: 3, commutative: true},
+		{name: "FusedMultiplyAddFloat64x8", argLength: 3, commutative: false},
+		{name: "FusedMultiplyAddMaskedFloat64x8", argLength: 4, commutative: false},
+		{name: "FusedMultiplyAddSubFloat64x8", argLength: 3, commutative: false},
+		{name: "FusedMultiplyAddSubMaskedFloat64x8", argLength: 4, commutative: false},
+		{name: "FusedMultiplySubAddFloat64x8", argLength: 3, commutative: false},
+		{name: "FusedMultiplySubAddMaskedFloat64x8", argLength: 4, commutative: false},
+		{name: "GreaterFloat64x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualFloat64x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedFloat64x8", argLength: 3, commutative: false},
+		{name: "GreaterMaskedFloat64x8", argLength: 3, commutative: false},
+		{name: "IsNanFloat64x8", argLength: 2, commutative: true},
+		{name: "IsNanMaskedFloat64x8", argLength: 3, commutative: true},
+		{name: "LessFloat64x8", argLength: 2, commutative: false},
+		{name: "LessEqualFloat64x8", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedFloat64x8", argLength: 3, commutative: false},
+		{name: "LessMaskedFloat64x8", argLength: 3, commutative: false},
+		{name: "MaxFloat64x8", argLength: 2, commutative: true},
+		{name: "MaxMaskedFloat64x8", argLength: 3, commutative: true},
+		{name: "MinFloat64x8", argLength: 2, commutative: true},
+		{name: "MinMaskedFloat64x8", argLength: 3, commutative: true},
+		{name: "MulFloat64x8", argLength: 2, commutative: true},
+		{name: "MulByPowOf2Float64x8", argLength: 2, commutative: false},
+		{name: "MulByPowOf2MaskedFloat64x8", argLength: 3, commutative: false},
+		{name: "MulMaskedFloat64x8", argLength: 3, commutative: true},
+		{name: "NotEqualFloat64x8", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedFloat64x8", argLength: 3, commutative: true},
+		{name: "SqrtFloat64x8", argLength: 1, commutative: false},
+		{name: "SqrtMaskedFloat64x8", argLength: 2, commutative: false},
+		{name: "SubFloat64x8", argLength: 2, commutative: false},
+		{name: "SubMaskedFloat64x8", argLength: 3, commutative: false},
+		{name: "AbsoluteInt16x16", argLength: 1, commutative: false},
+		{name: "AbsoluteMaskedInt16x16", argLength: 2, commutative: false},
+		{name: "AddInt16x16", argLength: 2, commutative: true},
+		{name: "AddMaskedInt16x16", argLength: 3, commutative: true},
+		{name: "AndInt16x16", argLength: 2, commutative: true},
+		{name: "AndNotInt16x16", argLength: 2, commutative: false},
+		{name: "CompressInt16x16", argLength: 2, commutative: false},
+		{name: "EqualInt16x16", argLength: 2, commutative: true},
+		{name: "EqualMaskedInt16x16", argLength: 3, commutative: true},
+		{name: "GreaterInt16x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualInt16x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedInt16x16", argLength: 3, commutative: false},
+		{name: "GreaterMaskedInt16x16", argLength: 3, commutative: false},
+		{name: "LessInt16x16", argLength: 2, commutative: false},
+		{name: "LessEqualInt16x16", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedInt16x16", argLength: 3, commutative: false},
+		{name: "LessMaskedInt16x16", argLength: 3, commutative: false},
+		{name: "MaxInt16x16", argLength: 2, commutative: true},
+		{name: "MaxMaskedInt16x16", argLength: 3, commutative: true},
+		{name: "MinInt16x16", argLength: 2, commutative: true},
+		{name: "MinMaskedInt16x16", argLength: 3, commutative: true},
+		{name: "MulHighInt16x16", argLength: 2, commutative: true},
+		{name: "MulHighMaskedInt16x16", argLength: 3, commutative: true},
+		{name: "MulLowInt16x16", argLength: 2, commutative: true},
+		{name: "MulLowMaskedInt16x16", argLength: 3, commutative: true},
+		{name: "NotEqualInt16x16", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedInt16x16", argLength: 3, commutative: true},
+		{name: "OrInt16x16", argLength: 2, commutative: true},
+		{name: "PairDotProdInt16x16", argLength: 2, commutative: false},
+		{name: "PairDotProdMaskedInt16x16", argLength: 3, commutative: false},
+		{name: "PairwiseAddInt16x16", argLength: 2, commutative: false},
+		{name: "PairwiseSubInt16x16", argLength: 2, commutative: false},
+		{name: "PopCountInt16x16", argLength: 1, commutative: false},
+		{name: "PopCountMaskedInt16x16", argLength: 2, commutative: false},
+		{name: "SaturatedAddInt16x16", argLength: 2, commutative: true},
+		{name: "SaturatedAddMaskedInt16x16", argLength: 3, commutative: true},
+		{name: "SaturatedPairwiseAddInt16x16", argLength: 2, commutative: false},
+		{name: "SaturatedPairwiseSubInt16x16", argLength: 2, commutative: false},
+		{name: "SaturatedSubInt16x16", argLength: 2, commutative: false},
+		{name: "SaturatedSubMaskedInt16x16", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftInt16x16", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedInt16x16", argLength: 3, commutative: false},
+		{name: "ShiftAllRightInt16x16", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedInt16x16", argLength: 3, commutative: false},
+		{name: "ShiftLeftInt16x16", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromInt16x16", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedInt16x16", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedInt16x16", argLength: 3, commutative: false},
+		{name: "ShiftRightInt16x16", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromInt16x16", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedInt16x16", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedInt16x16", argLength: 3, commutative: false},
+		{name: "SignInt16x16", argLength: 2, commutative: false},
+		{name: "SubInt16x16", argLength: 2, commutative: false},
+		{name: "SubMaskedInt16x16", argLength: 3, commutative: false},
+		{name: "XorInt16x16", argLength: 2, commutative: true},
+		{name: "AbsoluteInt16x32", argLength: 1, commutative: false},
+		{name: "AbsoluteMaskedInt16x32", argLength: 2, commutative: false},
+		{name: "AddInt16x32", argLength: 2, commutative: true},
+		{name: "AddMaskedInt16x32", argLength: 3, commutative: true},
+		{name: "CompressInt16x32", argLength: 2, commutative: false},
+		{name: "EqualInt16x32", argLength: 2, commutative: true},
+		{name: "EqualMaskedInt16x32", argLength: 3, commutative: true},
+		{name: "GreaterInt16x32", argLength: 2, commutative: false},
+		{name: "GreaterEqualInt16x32", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedInt16x32", argLength: 3, commutative: false},
+		{name: "GreaterMaskedInt16x32", argLength: 3, commutative: false},
+		{name: "LessInt16x32", argLength: 2, commutative: false},
+		{name: "LessEqualInt16x32", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedInt16x32", argLength: 3, commutative: false},
+		{name: "LessMaskedInt16x32", argLength: 3, commutative: false},
+		{name: "MaxInt16x32", argLength: 2, commutative: true},
+		{name: "MaxMaskedInt16x32", argLength: 3, commutative: true},
+		{name: "MinInt16x32", argLength: 2, commutative: true},
+		{name: "MinMaskedInt16x32", argLength: 3, commutative: true},
+		{name: "MulHighInt16x32", argLength: 2, commutative: true},
+		{name: "MulHighMaskedInt16x32", argLength: 3, commutative: true},
+		{name: "MulLowInt16x32", argLength: 2, commutative: true},
+		{name: "MulLowMaskedInt16x32", argLength: 3, commutative: true},
+		{name: "NotEqualInt16x32", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedInt16x32", argLength: 3, commutative: true},
+		{name: "PairDotProdInt16x32", argLength: 2, commutative: false},
+		{name: "PairDotProdMaskedInt16x32", argLength: 3, commutative: false},
+		{name: "PopCountInt16x32", argLength: 1, commutative: false},
+		{name: "PopCountMaskedInt16x32", argLength: 2, commutative: false},
+		{name: "SaturatedAddInt16x32", argLength: 2, commutative: true},
+		{name: "SaturatedAddMaskedInt16x32", argLength: 3, commutative: true},
+		{name: "SaturatedSubInt16x32", argLength: 2, commutative: false},
+		{name: "SaturatedSubMaskedInt16x32", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftInt16x32", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedInt16x32", argLength: 3, commutative: false},
+		{name: "ShiftAllRightInt16x32", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedInt16x32", argLength: 3, commutative: false},
+		{name: "ShiftLeftInt16x32", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromInt16x32", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedInt16x32", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedInt16x32", argLength: 3, commutative: false},
+		{name: "ShiftRightInt16x32", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromInt16x32", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedInt16x32", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedInt16x32", argLength: 3, commutative: false},
+		{name: "SubInt16x32", argLength: 2, commutative: false},
+		{name: "SubMaskedInt16x32", argLength: 3, commutative: false},
+		{name: "AbsoluteInt16x8", argLength: 1, commutative: false},
+		{name: "AbsoluteMaskedInt16x8", argLength: 2, commutative: false},
+		{name: "AddInt16x8", argLength: 2, commutative: true},
+		{name: "AddMaskedInt16x8", argLength: 3, commutative: true},
+		{name: "AndInt16x8", argLength: 2, commutative: true},
+		{name: "AndNotInt16x8", argLength: 2, commutative: false},
+		{name: "CompressInt16x8", argLength: 2, commutative: false},
+		{name: "EqualInt16x8", argLength: 2, commutative: true},
+		{name: "EqualMaskedInt16x8", argLength: 3, commutative: true},
+		{name: "GreaterInt16x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualInt16x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedInt16x8", argLength: 3, commutative: false},
+		{name: "GreaterMaskedInt16x8", argLength: 3, commutative: false},
+		{name: "LessInt16x8", argLength: 2, commutative: false},
+		{name: "LessEqualInt16x8", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedInt16x8", argLength: 3, commutative: false},
+		{name: "LessMaskedInt16x8", argLength: 3, commutative: false},
+		{name: "MaxInt16x8", argLength: 2, commutative: true},
+		{name: "MaxMaskedInt16x8", argLength: 3, commutative: true},
+		{name: "MinInt16x8", argLength: 2, commutative: true},
+		{name: "MinMaskedInt16x8", argLength: 3, commutative: true},
+		{name: "MulHighInt16x8", argLength: 2, commutative: true},
+		{name: "MulHighMaskedInt16x8", argLength: 3, commutative: true},
+		{name: "MulLowInt16x8", argLength: 2, commutative: true},
+		{name: "MulLowMaskedInt16x8", argLength: 3, commutative: true},
+		{name: "NotEqualInt16x8", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedInt16x8", argLength: 3, commutative: true},
+		{name: "OrInt16x8", argLength: 2, commutative: true},
+		{name: "PairDotProdInt16x8", argLength: 2, commutative: false},
+		{name: "PairDotProdMaskedInt16x8", argLength: 3, commutative: false},
+		{name: "PairwiseAddInt16x8", argLength: 2, commutative: false},
+		{name: "PairwiseSubInt16x8", argLength: 2, commutative: false},
+		{name: "PopCountInt16x8", argLength: 1, commutative: false},
+		{name: "PopCountMaskedInt16x8", argLength: 2, commutative: false},
+		{name: "SaturatedAddInt16x8", argLength: 2, commutative: true},
+		{name: "SaturatedAddMaskedInt16x8", argLength: 3, commutative: true},
+		{name: "SaturatedPairwiseAddInt16x8", argLength: 2, commutative: false},
+		{name: "SaturatedPairwiseSubInt16x8", argLength: 2, commutative: false},
+		{name: "SaturatedSubInt16x8", argLength: 2, commutative: false},
+		{name: "SaturatedSubMaskedInt16x8", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftInt16x8", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedInt16x8", argLength: 3, commutative: false},
+		{name: "ShiftAllRightInt16x8", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedInt16x8", argLength: 3, commutative: false},
+		{name: "ShiftLeftInt16x8", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromInt16x8", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedInt16x8", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedInt16x8", argLength: 3, commutative: false},
+		{name: "ShiftRightInt16x8", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromInt16x8", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedInt16x8", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedInt16x8", argLength: 3, commutative: false},
+		{name: "SignInt16x8", argLength: 2, commutative: false},
+		{name: "SubInt16x8", argLength: 2, commutative: false},
+		{name: "SubMaskedInt16x8", argLength: 3, commutative: false},
+		{name: "XorInt16x8", argLength: 2, commutative: true},
+		{name: "AbsoluteInt32x16", argLength: 1, commutative: false},
+		{name: "AbsoluteMaskedInt32x16", argLength: 2, commutative: false},
+		{name: "AddInt32x16", argLength: 2, commutative: true},
+		{name: "AddMaskedInt32x16", argLength: 3, commutative: true},
+		{name: "AndInt32x16", argLength: 2, commutative: true},
+		{name: "AndMaskedInt32x16", argLength: 3, commutative: true},
+		{name: "AndNotInt32x16", argLength: 2, commutative: false},
+		{name: "AndNotMaskedInt32x16", argLength: 3, commutative: false},
+		{name: "CompressInt32x16", argLength: 2, commutative: false},
+		{name: "EqualInt32x16", argLength: 2, commutative: true},
+		{name: "EqualMaskedInt32x16", argLength: 3, commutative: true},
+		{name: "GreaterInt32x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualInt32x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedInt32x16", argLength: 3, commutative: false},
+		{name: "GreaterMaskedInt32x16", argLength: 3, commutative: false},
+		{name: "LessInt32x16", argLength: 2, commutative: false},
+		{name: "LessEqualInt32x16", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedInt32x16", argLength: 3, commutative: false},
+		{name: "LessMaskedInt32x16", argLength: 3, commutative: false},
+		{name: "MaxInt32x16", argLength: 2, commutative: true},
+		{name: "MaxMaskedInt32x16", argLength: 3, commutative: true},
+		{name: "MinInt32x16", argLength: 2, commutative: true},
+		{name: "MinMaskedInt32x16", argLength: 3, commutative: true},
+		{name: "MulLowInt32x16", argLength: 2, commutative: true},
+		{name: "MulLowMaskedInt32x16", argLength: 3, commutative: true},
+		{name: "NotEqualInt32x16", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedInt32x16", argLength: 3, commutative: true},
+		{name: "OrInt32x16", argLength: 2, commutative: true},
+		{name: "OrMaskedInt32x16", argLength: 3, commutative: true},
+		{name: "PairDotProdAccumulateInt32x16", argLength: 3, commutative: false},
+		{name: "PairDotProdAccumulateMaskedInt32x16", argLength: 4, commutative: false},
+		{name: "PopCountInt32x16", argLength: 1, commutative: false},
+		{name: "PopCountMaskedInt32x16", argLength: 2, commutative: false},
+		{name: "RotateLeftInt32x16", argLength: 2, commutative: false},
+		{name: "RotateLeftMaskedInt32x16", argLength: 3, commutative: false},
+		{name: "RotateRightInt32x16", argLength: 2, commutative: false},
+		{name: "RotateRightMaskedInt32x16", argLength: 3, commutative: false},
+		{name: "SaturatedPairDotProdAccumulateInt32x16", argLength: 3, commutative: false},
+		{name: "SaturatedPairDotProdAccumulateMaskedInt32x16", argLength: 4, commutative: false},
+		{name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false},
+		{name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x16", argLength: 4, commutative: false},
+		{name: "ShiftAllLeftInt32x16", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedInt32x16", argLength: 3, commutative: false},
+		{name: "ShiftAllRightInt32x16", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedInt32x16", argLength: 3, commutative: false},
+		{name: "ShiftLeftInt32x16", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromInt32x16", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedInt32x16", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedInt32x16", argLength: 3, commutative: false},
+		{name: "ShiftRightInt32x16", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromInt32x16", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedInt32x16", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedInt32x16", argLength: 3, commutative: false},
+		{name: "SubInt32x16", argLength: 2, commutative: false},
+		{name: "SubMaskedInt32x16", argLength: 3, commutative: false},
+		{name: "UnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false},
+		{name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x16", argLength: 4, commutative: false},
+		{name: "XorInt32x16", argLength: 2, commutative: true},
+		{name: "XorMaskedInt32x16", argLength: 3, commutative: true},
+		{name: "AbsoluteInt32x4", argLength: 1, commutative: false},
+		{name: "AbsoluteMaskedInt32x4", argLength: 2, commutative: false},
+		{name: "AddInt32x4", argLength: 2, commutative: true},
+		{name: "AddMaskedInt32x4", argLength: 3, commutative: true},
+		{name: "AndInt32x4", argLength: 2, commutative: true},
+		{name: "AndMaskedInt32x4", argLength: 3, commutative: true},
+		{name: "AndNotInt32x4", argLength: 2, commutative: false},
+		{name: "AndNotMaskedInt32x4", argLength: 3, commutative: false},
+		{name: "CompressInt32x4", argLength: 2, commutative: false},
+		{name: "EqualInt32x4", argLength: 2, commutative: true},
+		{name: "EqualMaskedInt32x4", argLength: 3, commutative: true},
+		{name: "GreaterInt32x4", argLength: 2, commutative: false},
+		{name: "GreaterEqualInt32x4", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedInt32x4", argLength: 3, commutative: false},
+		{name: "GreaterMaskedInt32x4", argLength: 3, commutative: false},
+		{name: "LessInt32x4", argLength: 2, commutative: false},
+		{name: "LessEqualInt32x4", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedInt32x4", argLength: 3, commutative: false},
+		{name: "LessMaskedInt32x4", argLength: 3, commutative: false},
+		{name: "MaxInt32x4", argLength: 2, commutative: true},
+		{name: "MaxMaskedInt32x4", argLength: 3, commutative: true},
+		{name: "MinInt32x4", argLength: 2, commutative: true},
+		{name: "MinMaskedInt32x4", argLength: 3, commutative: true},
+		{name: "MulEvenWidenInt32x4", argLength: 2, commutative: true},
+		{name: "MulLowInt32x4", argLength: 2, commutative: true},
+		{name: "MulLowMaskedInt32x4", argLength: 3, commutative: true},
+		{name: "NotEqualInt32x4", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedInt32x4", argLength: 3, commutative: true},
+		{name: "OrInt32x4", argLength: 2, commutative: true},
+		{name: "OrMaskedInt32x4", argLength: 3, commutative: true},
+		{name: "PairDotProdAccumulateInt32x4", argLength: 3, commutative: false},
+		{name: "PairDotProdAccumulateMaskedInt32x4", argLength: 4, commutative: false},
+		{name: "PairwiseAddInt32x4", argLength: 2, commutative: false},
+		{name: "PairwiseSubInt32x4", argLength: 2, commutative: false},
+		{name: "PopCountInt32x4", argLength: 1, commutative: false},
+		{name: "PopCountMaskedInt32x4", argLength: 2, commutative: false},
+		{name: "RotateLeftInt32x4", argLength: 2, commutative: false},
+		{name: "RotateLeftMaskedInt32x4", argLength: 3, commutative: false},
+		{name: "RotateRightInt32x4", argLength: 2, commutative: false},
+		{name: "RotateRightMaskedInt32x4", argLength: 3, commutative: false},
+		{name: "SaturatedPairDotProdAccumulateInt32x4", argLength: 3, commutative: false},
+		{name: "SaturatedPairDotProdAccumulateMaskedInt32x4", argLength: 4, commutative: false},
+		{name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false},
+		{name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4", argLength: 4, commutative: false},
+		{name: "ShiftAllLeftInt32x4", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedInt32x4", argLength: 3, commutative: false},
+		{name: "ShiftAllRightInt32x4", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedInt32x4", argLength: 3, commutative: false},
+		{name: "ShiftLeftInt32x4", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromInt32x4", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedInt32x4", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedInt32x4", argLength: 3, commutative: false},
+		{name: "ShiftRightInt32x4", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromInt32x4", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedInt32x4", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedInt32x4", argLength: 3, commutative: false},
+		{name: "SignInt32x4", argLength: 2, commutative: false},
+		{name: "SubInt32x4", argLength: 2, commutative: false},
+		{name: "SubMaskedInt32x4", argLength: 3, commutative: false},
+		{name: "UnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false},
+		{name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x4", argLength: 4, commutative: false},
+		{name: "XorInt32x4", argLength: 2, commutative: true},
+		{name: "XorMaskedInt32x4", argLength: 3, commutative: true},
+		{name: "AbsoluteInt32x8", argLength: 1, commutative: false},
+		{name: "AbsoluteMaskedInt32x8", argLength: 2, commutative: false},
+		{name: "AddInt32x8", argLength: 2, commutative: true},
+		{name: "AddMaskedInt32x8", argLength: 3, commutative: true},
+		{name: "AndInt32x8", argLength: 2, commutative: true},
+		{name: "AndMaskedInt32x8", argLength: 3, commutative: true},
+		{name: "AndNotInt32x8", argLength: 2, commutative: false},
+		{name: "AndNotMaskedInt32x8", argLength: 3, commutative: false},
+		{name: "CompressInt32x8", argLength: 2, commutative: false},
+		{name: "EqualInt32x8", argLength: 2, commutative: true},
+		{name: "EqualMaskedInt32x8", argLength: 3, commutative: true},
+		{name: "GreaterInt32x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualInt32x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedInt32x8", argLength: 3, commutative: false},
+		{name: "GreaterMaskedInt32x8", argLength: 3, commutative: false},
+		{name: "LessInt32x8", argLength: 2, commutative: false},
+		{name: "LessEqualInt32x8", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedInt32x8", argLength: 3, commutative: false},
+		{name: "LessMaskedInt32x8", argLength: 3, commutative: false},
+		{name: "MaxInt32x8", argLength: 2, commutative: true},
+		{name: "MaxMaskedInt32x8", argLength: 3, commutative: true},
+		{name: "MinInt32x8", argLength: 2, commutative: true},
+		{name: "MinMaskedInt32x8", argLength: 3, commutative: true},
+		{name: "MulEvenWidenInt32x8", argLength: 2, commutative: true},
+		{name: "MulLowInt32x8", argLength: 2, commutative: true},
+		{name: "MulLowMaskedInt32x8", argLength: 3, commutative: true},
+		{name: "NotEqualInt32x8", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedInt32x8", argLength: 3, commutative: true},
+		{name: "OrInt32x8", argLength: 2, commutative: true},
+		{name: "OrMaskedInt32x8", argLength: 3, commutative: true},
+		{name: "PairDotProdAccumulateInt32x8", argLength: 3, commutative: false},
+		{name: "PairDotProdAccumulateMaskedInt32x8", argLength: 4, commutative: false},
+		{name: "PairwiseAddInt32x8", argLength: 2, commutative: false},
+		{name: "PairwiseSubInt32x8", argLength: 2, commutative: false},
+		{name: "PopCountInt32x8", argLength: 1, commutative: false},
+		{name: "PopCountMaskedInt32x8", argLength: 2, commutative: false},
+		{name: "RotateLeftInt32x8", argLength: 2, commutative: false},
+		{name: "RotateLeftMaskedInt32x8", argLength: 3, commutative: false},
+		{name: "RotateRightInt32x8", argLength: 2, commutative: false},
+		{name: "RotateRightMaskedInt32x8", argLength: 3, commutative: false},
+		{name: "SaturatedPairDotProdAccumulateInt32x8", argLength: 3, commutative: false},
+		{name: "SaturatedPairDotProdAccumulateMaskedInt32x8", argLength: 4, commutative: false},
+		{name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 3, commutative: false},
+		{name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x8", argLength: 4, commutative: false},
+		{name: "ShiftAllLeftInt32x8", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedInt32x8", argLength: 3, commutative: false},
+		{name: "ShiftAllRightInt32x8", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedInt32x8", argLength: 3, commutative: false},
+		{name: "ShiftLeftInt32x8", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromInt32x8", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedInt32x8", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedInt32x8", argLength: 3, commutative: false},
+		{name: "ShiftRightInt32x8", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromInt32x8", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedInt32x8", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedInt32x8", argLength: 3, commutative: false},
+		{name: "SignInt32x8", argLength: 2, commutative: false},
+		{name: "SubInt32x8", argLength: 2, commutative: false},
+		{name: "SubMaskedInt32x8", argLength: 3, commutative: false},
+		{name: "UnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 3, commutative: false},
+		{name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x8", argLength: 4, commutative: false},
+		{name: "XorInt32x8", argLength: 2, commutative: true},
+		{name: "XorMaskedInt32x8", argLength: 3, commutative: true},
+		{name: "AbsoluteInt64x2", argLength: 1, commutative: false},
+		{name: "AbsoluteMaskedInt64x2", argLength: 2, commutative: false},
+		{name: "AddInt64x2", argLength: 2, commutative: true},
+		{name: "AddMaskedInt64x2", argLength: 3, commutative: true},
+		{name: "AndInt64x2", argLength: 2, commutative: true},
+		{name: "AndMaskedInt64x2", argLength: 3, commutative: true},
+		{name: "AndNotInt64x2", argLength: 2, commutative: false},
+		{name: "AndNotMaskedInt64x2", argLength: 3, commutative: false},
+		{name: "CompressInt64x2", argLength: 2, commutative: false},
+		{name: "EqualInt64x2", argLength: 2, commutative: true},
+		{name: "EqualMaskedInt64x2", argLength: 3, commutative: true},
+		{name: "GreaterInt64x2", argLength: 2, commutative: false},
+		{name: "GreaterEqualInt64x2", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedInt64x2", argLength: 3, commutative: false},
+		{name: "GreaterMaskedInt64x2", argLength: 3, commutative: false},
+		{name: "LessInt64x2", argLength: 2, commutative: false},
+		{name: "LessEqualInt64x2", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedInt64x2", argLength: 3, commutative: false},
+		{name: "LessMaskedInt64x2", argLength: 3, commutative: false},
+		{name: "MaxInt64x2", argLength: 2, commutative: true},
+		{name: "MaxMaskedInt64x2", argLength: 3, commutative: true},
+		{name: "MinInt64x2", argLength: 2, commutative: true},
+		{name: "MinMaskedInt64x2", argLength: 3, commutative: true},
+		{name: "MulEvenWidenInt64x2", argLength: 2, commutative: true},
+		{name: "MulEvenWidenMaskedInt64x2", argLength: 3, commutative: true},
+		{name: "MulLowInt64x2", argLength: 2, commutative: true},
+		{name: "MulLowMaskedInt64x2", argLength: 3, commutative: true},
+		{name: "NotEqualInt64x2", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedInt64x2", argLength: 3, commutative: true},
+		{name: "OrInt64x2", argLength: 2, commutative: true},
+		{name: "OrMaskedInt64x2", argLength: 3, commutative: true},
+		{name: "PopCountInt64x2", argLength: 1, commutative: false},
+		{name: "PopCountMaskedInt64x2", argLength: 2, commutative: false},
+		{name: "RotateLeftInt64x2", argLength: 2, commutative: false},
+		{name: "RotateLeftMaskedInt64x2", argLength: 3, commutative: false},
+		{name: "RotateRightInt64x2", argLength: 2, commutative: false},
+		{name: "RotateRightMaskedInt64x2", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftInt64x2", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedInt64x2", argLength: 3, commutative: false},
+		{name: "ShiftAllRightInt64x2", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedInt64x2", argLength: 3, commutative: false},
+		{name: "ShiftLeftInt64x2", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromInt64x2", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedInt64x2", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedInt64x2", argLength: 3, commutative: false},
+		{name: "ShiftRightInt64x2", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromInt64x2", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedInt64x2", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedInt64x2", argLength: 3, commutative: false},
+		{name: "SubInt64x2", argLength: 2, commutative: false},
+		{name: "SubMaskedInt64x2", argLength: 3, commutative: false},
+		{name: "XorInt64x2", argLength: 2, commutative: true},
+		{name: "XorMaskedInt64x2", argLength: 3, commutative: true},
+		{name: "AbsoluteInt64x4", argLength: 1, commutative: false},
+		{name: "AbsoluteMaskedInt64x4", argLength: 2, commutative: false},
+		{name: "AddInt64x4", argLength: 2, commutative: true},
+		{name: "AddMaskedInt64x4", argLength: 3, commutative: true},
+		{name: "AndInt64x4", argLength: 2, commutative: true},
+		{name: "AndMaskedInt64x4", argLength: 3, commutative: true},
+		{name: "AndNotInt64x4", argLength: 2, commutative: false},
+		{name: "AndNotMaskedInt64x4", argLength: 3, commutative: false},
+		{name: "CompressInt64x4", argLength: 2, commutative: false},
+		{name: "EqualInt64x4", argLength: 2, commutative: true},
+		{name: "EqualMaskedInt64x4", argLength: 3, commutative: true},
+		{name: "GreaterInt64x4", argLength: 2, commutative: false},
+		{name: "GreaterEqualInt64x4", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedInt64x4", argLength: 3, commutative: false},
+		{name: "GreaterMaskedInt64x4", argLength: 3, commutative: false},
+		{name: "LessInt64x4", argLength: 2, commutative: false},
+		{name: "LessEqualInt64x4", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedInt64x4", argLength: 3, commutative: false},
+		{name: "LessMaskedInt64x4", argLength: 3, commutative: false},
+		{name: "MaxInt64x4", argLength: 2, commutative: true},
+		{name: "MaxMaskedInt64x4", argLength: 3, commutative: true},
+		{name: "MinInt64x4", argLength: 2, commutative: true},
+		{name: "MinMaskedInt64x4", argLength: 3, commutative: true},
+		{name: "MulEvenWidenInt64x4", argLength: 2, commutative: true},
+		{name: "MulEvenWidenMaskedInt64x4", argLength: 3, commutative: true},
+		{name: "MulLowInt64x4", argLength: 2, commutative: true},
+		{name: "MulLowMaskedInt64x4", argLength: 3, commutative: true},
+		{name: "NotEqualInt64x4", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedInt64x4", argLength: 3, commutative: true},
+		{name: "OrInt64x4", argLength: 2, commutative: true},
+		{name: "OrMaskedInt64x4", argLength: 3, commutative: true},
+		{name: "PopCountInt64x4", argLength: 1, commutative: false},
+		{name: "PopCountMaskedInt64x4", argLength: 2, commutative: false},
+		{name: "RotateLeftInt64x4", argLength: 2, commutative: false},
+		{name: "RotateLeftMaskedInt64x4", argLength: 3, commutative: false},
+		{name: "RotateRightInt64x4", argLength: 2, commutative: false},
+		{name: "RotateRightMaskedInt64x4", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftInt64x4", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedInt64x4", argLength: 3, commutative: false},
+		{name: "ShiftAllRightInt64x4", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedInt64x4", argLength: 3, commutative: false},
+		{name: "ShiftLeftInt64x4", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromInt64x4", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedInt64x4", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedInt64x4", argLength: 3, commutative: false},
+		{name: "ShiftRightInt64x4", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromInt64x4", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedInt64x4", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedInt64x4", argLength: 3, commutative: false},
+		{name: "SubInt64x4", argLength: 2, commutative: false},
+		{name: "SubMaskedInt64x4", argLength: 3, commutative: false},
+		{name: "XorInt64x4", argLength: 2, commutative: true},
+		{name: "XorMaskedInt64x4", argLength: 3, commutative: true},
+		{name: "AbsoluteInt64x8", argLength: 1, commutative: false},
+		{name: "AbsoluteMaskedInt64x8", argLength: 2, commutative: false},
+		{name: "AddInt64x8", argLength: 2, commutative: true},
+		{name: "AddMaskedInt64x8", argLength: 3, commutative: true},
+		{name: "AndInt64x8", argLength: 2, commutative: true},
+		{name: "AndMaskedInt64x8", argLength: 3, commutative: true},
+		{name: "AndNotInt64x8", argLength: 2, commutative: false},
+		{name: "AndNotMaskedInt64x8", argLength: 3, commutative: false},
+		{name: "CompressInt64x8", argLength: 2, commutative: false},
+		{name: "EqualInt64x8", argLength: 2, commutative: true},
+		{name: "EqualMaskedInt64x8", argLength: 3, commutative: true},
+		{name: "GreaterInt64x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualInt64x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedInt64x8", argLength: 3, commutative: false},
+		{name: "GreaterMaskedInt64x8", argLength: 3, commutative: false},
+		{name: "LessInt64x8", argLength: 2, commutative: false},
+		{name: "LessEqualInt64x8", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedInt64x8", argLength: 3, commutative: false},
+		{name: "LessMaskedInt64x8", argLength: 3, commutative: false},
+		{name: "MaxInt64x8", argLength: 2, commutative: true},
+		{name: "MaxMaskedInt64x8", argLength: 3, commutative: true},
+		{name: "MinInt64x8", argLength: 2, commutative: true},
+		{name: "MinMaskedInt64x8", argLength: 3, commutative: true},
+		{name: "MulEvenWidenInt64x8", argLength: 2, commutative: true},
+		{name: "MulEvenWidenMaskedInt64x8", argLength: 3, commutative: true},
+		{name: "MulLowInt64x8", argLength: 2, commutative: true},
+		{name: "MulLowMaskedInt64x8", argLength: 3, commutative: true},
+		{name: "NotEqualInt64x8", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedInt64x8", argLength: 3, commutative: true},
+		{name: "OrInt64x8", argLength: 2, commutative: true},
+		{name: "OrMaskedInt64x8", argLength: 3, commutative: true},
+		{name: "PopCountInt64x8", argLength: 1, commutative: false},
+		{name: "PopCountMaskedInt64x8", argLength: 2, commutative: false},
+		{name: "RotateLeftInt64x8", argLength: 2, commutative: false},
+		{name: "RotateLeftMaskedInt64x8", argLength: 3, commutative: false},
+		{name: "RotateRightInt64x8", argLength: 2, commutative: false},
+		{name: "RotateRightMaskedInt64x8", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftInt64x8", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedInt64x8", argLength: 3, commutative: false},
+		{name: "ShiftAllRightInt64x8", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedInt64x8", argLength: 3, commutative: false},
+		{name: "ShiftLeftInt64x8", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromInt64x8", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedInt64x8", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedInt64x8", argLength: 3, commutative: false},
+		{name: "ShiftRightInt64x8", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromInt64x8", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedInt64x8", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedInt64x8", argLength: 3, commutative: false},
+		{name: "SubInt64x8", argLength: 2, commutative: false},
+		{name: "SubMaskedInt64x8", argLength: 3, commutative: false},
+		{name: "XorInt64x8", argLength: 2, commutative: true},
+		{name: "XorMaskedInt64x8", argLength: 3, commutative: true},
+		{name: "AbsoluteInt8x16", argLength: 1, commutative: false},
+		{name: "AbsoluteMaskedInt8x16", argLength: 2, commutative: false},
+		{name: "AddInt8x16", argLength: 2, commutative: true},
+		{name: "AddMaskedInt8x16", argLength: 3, commutative: true},
+		{name: "AndInt8x16", argLength: 2, commutative: true},
+		{name: "AndNotInt8x16", argLength: 2, commutative: false},
+		{name: "CompressInt8x16", argLength: 2, commutative: false},
+		{name: "EqualInt8x16", argLength: 2, commutative: true},
+		{name: "EqualMaskedInt8x16", argLength: 3, commutative: true},
+		{name: "GreaterInt8x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualInt8x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedInt8x16", argLength: 3, commutative: false},
+		{name: "GreaterMaskedInt8x16", argLength: 3, commutative: false},
+		{name: "LessInt8x16", argLength: 2, commutative: false},
+		{name: "LessEqualInt8x16", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedInt8x16", argLength: 3, commutative: false},
+		{name: "LessMaskedInt8x16", argLength: 3, commutative: false},
+		{name: "MaxInt8x16", argLength: 2, commutative: true},
+		{name: "MaxMaskedInt8x16", argLength: 3, commutative: true},
+		{name: "MinInt8x16", argLength: 2, commutative: true},
+		{name: "MinMaskedInt8x16", argLength: 3, commutative: true},
+		{name: "NotEqualInt8x16", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedInt8x16", argLength: 3, commutative: true},
+		{name: "OrInt8x16", argLength: 2, commutative: true},
+		{name: "PopCountInt8x16", argLength: 1, commutative: false},
+		{name: "PopCountMaskedInt8x16", argLength: 2, commutative: false},
+		{name: "SaturatedAddInt8x16", argLength: 2, commutative: true},
+		{name: "SaturatedAddMaskedInt8x16", argLength: 3, commutative: true},
+		{name: "SaturatedSubInt8x16", argLength: 2, commutative: false},
+		{name: "SaturatedSubMaskedInt8x16", argLength: 3, commutative: false},
+		{name: "SignInt8x16", argLength: 2, commutative: false},
+		{name: "SubInt8x16", argLength: 2, commutative: false},
+		{name: "SubMaskedInt8x16", argLength: 3, commutative: false},
+		{name: "XorInt8x16", argLength: 2, commutative: true},
+		{name: "AbsoluteInt8x32", argLength: 1, commutative: false},
+		{name: "AbsoluteMaskedInt8x32", argLength: 2, commutative: false},
+		{name: "AddInt8x32", argLength: 2, commutative: true},
+		{name: "AddMaskedInt8x32", argLength: 3, commutative: true},
+		{name: "AndInt8x32", argLength: 2, commutative: true},
+		{name: "AndNotInt8x32", argLength: 2, commutative: false},
+		{name: "CompressInt8x32", argLength: 2, commutative: false},
+		{name: "EqualInt8x32", argLength: 2, commutative: true},
+		{name: "EqualMaskedInt8x32", argLength: 3, commutative: true},
+		{name: "GreaterInt8x32", argLength: 2, commutative: false},
+		{name: "GreaterEqualInt8x32", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedInt8x32", argLength: 3, commutative: false},
+		{name: "GreaterMaskedInt8x32", argLength: 3, commutative: false},
+		{name: "LessInt8x32", argLength: 2, commutative: false},
+		{name: "LessEqualInt8x32", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedInt8x32", argLength: 3, commutative: false},
+		{name: "LessMaskedInt8x32", argLength: 3, commutative: false},
+		{name: "MaxInt8x32", argLength: 2, commutative: true},
+		{name: "MaxMaskedInt8x32", argLength: 3, commutative: true},
+		{name: "MinInt8x32", argLength: 2, commutative: true},
+		{name: "MinMaskedInt8x32", argLength: 3, commutative: true},
+		{name: "NotEqualInt8x32", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedInt8x32", argLength: 3, commutative: true},
+		{name: "OrInt8x32", argLength: 2, commutative: true},
+		{name: "PopCountInt8x32", argLength: 1, commutative: false},
+		{name: "PopCountMaskedInt8x32", argLength: 2, commutative: false},
+		{name: "SaturatedAddInt8x32", argLength: 2, commutative: true},
+		{name: "SaturatedAddMaskedInt8x32", argLength: 3, commutative: true},
+		{name: "SaturatedSubInt8x32", argLength: 2, commutative: false},
+		{name: "SaturatedSubMaskedInt8x32", argLength: 3, commutative: false},
+		{name: "SignInt8x32", argLength: 2, commutative: false},
+		{name: "SubInt8x32", argLength: 2, commutative: false},
+		{name: "SubMaskedInt8x32", argLength: 3, commutative: false},
+		{name: "XorInt8x32", argLength: 2, commutative: true},
+		{name: "AbsoluteInt8x64", argLength: 1, commutative: false},
+		{name: "AbsoluteMaskedInt8x64", argLength: 2, commutative: false},
+		{name: "AddInt8x64", argLength: 2, commutative: true},
+		{name: "AddMaskedInt8x64", argLength: 3, commutative: true},
+		{name: "CompressInt8x64", argLength: 2, commutative: false},
+		{name: "EqualInt8x64", argLength: 2, commutative: true},
+		{name: "EqualMaskedInt8x64", argLength: 3, commutative: true},
+		{name: "GreaterInt8x64", argLength: 2, commutative: false},
+		{name: "GreaterEqualInt8x64", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedInt8x64", argLength: 3, commutative: false},
+		{name: "GreaterMaskedInt8x64", argLength: 3, commutative: false},
+		{name: "LessInt8x64", argLength: 2, commutative: false},
+		{name: "LessEqualInt8x64", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedInt8x64", argLength: 3, commutative: false},
+		{name: "LessMaskedInt8x64", argLength: 3, commutative: false},
+		{name: "MaxInt8x64", argLength: 2, commutative: true},
+		{name: "MaxMaskedInt8x64", argLength: 3, commutative: true},
+		{name: "MinInt8x64", argLength: 2, commutative: true},
+		{name: "MinMaskedInt8x64", argLength: 3, commutative: true},
+		{name: "NotEqualInt8x64", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedInt8x64", argLength: 3, commutative: true},
+		{name: "PopCountInt8x64", argLength: 1, commutative: false},
+		{name: "PopCountMaskedInt8x64", argLength: 2, commutative: false},
+		{name: "SaturatedAddInt8x64", argLength: 2, commutative: true},
+		{name: "SaturatedAddMaskedInt8x64", argLength: 3, commutative: true},
+		{name: "SaturatedSubInt8x64", argLength: 2, commutative: false},
+		{name: "SaturatedSubMaskedInt8x64", argLength: 3, commutative: false},
+		{name: "SubInt8x64", argLength: 2, commutative: false},
+		{name: "SubMaskedInt8x64", argLength: 3, commutative: false},
+		{name: "AddUint16x16", argLength: 2, commutative: true},
+		{name: "AddMaskedUint16x16", argLength: 3, commutative: true},
+		{name: "AndUint16x16", argLength: 2, commutative: true},
+		{name: "AndNotUint16x16", argLength: 2, commutative: false},
+		{name: "AverageUint16x16", argLength: 2, commutative: true},
+		{name: "AverageMaskedUint16x16", argLength: 3, commutative: true},
+		{name: "CompressUint16x16", argLength: 2, commutative: false},
+		{name: "EqualUint16x16", argLength: 2, commutative: true},
+		{name: "EqualMaskedUint16x16", argLength: 3, commutative: true},
+		{name: "GreaterUint16x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualUint16x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedUint16x16", argLength: 3, commutative: false},
+		{name: "GreaterMaskedUint16x16", argLength: 3, commutative: false},
+		{name: "LessUint16x16", argLength: 2, commutative: false},
+		{name: "LessEqualUint16x16", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedUint16x16", argLength: 3, commutative: false},
+		{name: "LessMaskedUint16x16", argLength: 3, commutative: false},
+		{name: "MaxUint16x16", argLength: 2, commutative: true},
+		{name: "MaxMaskedUint16x16", argLength: 3, commutative: true},
+		{name: "MinUint16x16", argLength: 2, commutative: true},
+		{name: "MinMaskedUint16x16", argLength: 3, commutative: true},
+		{name: "MulHighUint16x16", argLength: 2, commutative: true},
+		{name: "MulHighMaskedUint16x16", argLength: 3, commutative: true},
+		{name: "NotEqualUint16x16", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedUint16x16", argLength: 3, commutative: true},
+		{name: "OrUint16x16", argLength: 2, commutative: true},
+		{name: "PairwiseAddUint16x16", argLength: 2, commutative: false},
+		{name: "PairwiseSubUint16x16", argLength: 2, commutative: false},
+		{name: "PermuteInt16x16", argLength: 2, commutative: false},
+		{name: "PermuteUint16x16", argLength: 2, commutative: false},
+		{name: "Permute2Uint16x16", argLength: 3, commutative: false},
+		{name: "Permute2Int16x16", argLength: 3, commutative: false},
+		{name: "Permute2MaskedInt16x16", argLength: 4, commutative: false},
+		{name: "Permute2MaskedUint16x16", argLength: 4, commutative: false},
+		{name: "PermuteMaskedUint16x16", argLength: 3, commutative: false},
+		{name: "PermuteMaskedInt16x16", argLength: 3, commutative: false},
+		{name: "PopCountUint16x16", argLength: 1, commutative: false},
+		{name: "PopCountMaskedUint16x16", argLength: 2, commutative: false},
+		{name: "SaturatedAddUint16x16", argLength: 2, commutative: true},
+		{name: "SaturatedAddMaskedUint16x16", argLength: 3, commutative: true},
+		{name: "SaturatedSubUint16x16", argLength: 2, commutative: false},
+		{name: "SaturatedSubMaskedUint16x16", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftUint16x16", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedUint16x16", argLength: 3, commutative: false},
+		{name: "ShiftAllRightUint16x16", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedUint16x16", argLength: 3, commutative: false},
+		{name: "ShiftLeftUint16x16", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromUint16x16", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedUint16x16", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedUint16x16", argLength: 3, commutative: false},
+		{name: "ShiftRightUint16x16", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromUint16x16", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedUint16x16", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedUint16x16", argLength: 3, commutative: false},
+		{name: "SubUint16x16", argLength: 2, commutative: false},
+		{name: "SubMaskedUint16x16", argLength: 3, commutative: false},
+		{name: "XorUint16x16", argLength: 2, commutative: true},
+		{name: "AddUint16x32", argLength: 2, commutative: true},
+		{name: "AddMaskedUint16x32", argLength: 3, commutative: true},
+		{name: "AverageUint16x32", argLength: 2, commutative: true},
+		{name: "AverageMaskedUint16x32", argLength: 3, commutative: true},
+		{name: "CompressUint16x32", argLength: 2, commutative: false},
+		{name: "EqualUint16x32", argLength: 2, commutative: true},
+		{name: "EqualMaskedUint16x32", argLength: 3, commutative: true},
+		{name: "GreaterUint16x32", argLength: 2, commutative: false},
+		{name: "GreaterEqualUint16x32", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedUint16x32", argLength: 3, commutative: false},
+		{name: "GreaterMaskedUint16x32", argLength: 3, commutative: false},
+		{name: "LessUint16x32", argLength: 2, commutative: false},
+		{name: "LessEqualUint16x32", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedUint16x32", argLength: 3, commutative: false},
+		{name: "LessMaskedUint16x32", argLength: 3, commutative: false},
+		{name: "MaxUint16x32", argLength: 2, commutative: true},
+		{name: "MaxMaskedUint16x32", argLength: 3, commutative: true},
+		{name: "MinUint16x32", argLength: 2, commutative: true},
+		{name: "MinMaskedUint16x32", argLength: 3, commutative: true},
+		{name: "MulHighUint16x32", argLength: 2, commutative: true},
+		{name: "MulHighMaskedUint16x32", argLength: 3, commutative: true},
+		{name: "NotEqualUint16x32", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedUint16x32", argLength: 3, commutative: true},
+		{name: "PermuteUint16x32", argLength: 2, commutative: false},
+		{name: "PermuteInt16x32", argLength: 2, commutative: false},
+		{name: "Permute2Uint16x32", argLength: 3, commutative: false},
+		{name: "Permute2Int16x32", argLength: 3, commutative: false},
+		{name: "Permute2MaskedUint16x32", argLength: 4, commutative: false},
+		{name: "Permute2MaskedInt16x32", argLength: 4, commutative: false},
+		{name: "PermuteMaskedUint16x32", argLength: 3, commutative: false},
+		{name: "PermuteMaskedInt16x32", argLength: 3, commutative: false},
+		{name: "PopCountUint16x32", argLength: 1, commutative: false},
+		{name: "PopCountMaskedUint16x32", argLength: 2, commutative: false},
+		{name: "SaturatedAddUint16x32", argLength: 2, commutative: true},
+		{name: "SaturatedAddMaskedUint16x32", argLength: 3, commutative: true},
+		{name: "SaturatedSubUint16x32", argLength: 2, commutative: false},
+		{name: "SaturatedSubMaskedUint16x32", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftUint16x32", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedUint16x32", argLength: 3, commutative: false},
+		{name: "ShiftAllRightUint16x32", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedUint16x32", argLength: 3, commutative: false},
+		{name: "ShiftLeftUint16x32", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromUint16x32", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedUint16x32", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedUint16x32", argLength: 3, commutative: false},
+		{name: "ShiftRightUint16x32", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromUint16x32", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedUint16x32", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedUint16x32", argLength: 3, commutative: false},
+		{name: "SubUint16x32", argLength: 2, commutative: false},
+		{name: "SubMaskedUint16x32", argLength: 3, commutative: false},
+		{name: "AddUint16x8", argLength: 2, commutative: true},
+		{name: "AddMaskedUint16x8", argLength: 3, commutative: true},
+		{name: "AndUint16x8", argLength: 2, commutative: true},
+		{name: "AndNotUint16x8", argLength: 2, commutative: false},
+		{name: "AverageUint16x8", argLength: 2, commutative: true},
+		{name: "AverageMaskedUint16x8", argLength: 3, commutative: true},
+		{name: "CompressUint16x8", argLength: 2, commutative: false},
+		{name: "EqualUint16x8", argLength: 2, commutative: true},
+		{name: "EqualMaskedUint16x8", argLength: 3, commutative: true},
+		{name: "GreaterUint16x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualUint16x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedUint16x8", argLength: 3, commutative: false},
+		{name: "GreaterMaskedUint16x8", argLength: 3, commutative: false},
+		{name: "LessUint16x8", argLength: 2, commutative: false},
+		{name: "LessEqualUint16x8", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedUint16x8", argLength: 3, commutative: false},
+		{name: "LessMaskedUint16x8", argLength: 3, commutative: false},
+		{name: "MaxUint16x8", argLength: 2, commutative: true},
+		{name: "MaxMaskedUint16x8", argLength: 3, commutative: true},
+		{name: "MinUint16x8", argLength: 2, commutative: true},
+		{name: "MinMaskedUint16x8", argLength: 3, commutative: true},
+		{name: "MulHighUint16x8", argLength: 2, commutative: true},
+		{name: "MulHighMaskedUint16x8", argLength: 3, commutative: true},
+		{name: "NotEqualUint16x8", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedUint16x8", argLength: 3, commutative: true},
+		{name: "OrUint16x8", argLength: 2, commutative: true},
+		{name: "PairwiseAddUint16x8", argLength: 2, commutative: false},
+		{name: "PairwiseSubUint16x8", argLength: 2, commutative: false},
+		{name: "PermuteInt16x8", argLength: 2, commutative: false},
+		{name: "PermuteUint16x8", argLength: 2, commutative: false},
+		{name: "Permute2Int16x8", argLength: 3, commutative: false},
+		{name: "Permute2Uint16x8", argLength: 3, commutative: false},
+		{name: "Permute2MaskedInt16x8", argLength: 4, commutative: false},
+		{name: "Permute2MaskedUint16x8", argLength: 4, commutative: false},
+		{name: "PermuteMaskedUint16x8", argLength: 3, commutative: false},
+		{name: "PermuteMaskedInt16x8", argLength: 3, commutative: false},
+		{name: "PopCountUint16x8", argLength: 1, commutative: false},
+		{name: "PopCountMaskedUint16x8", argLength: 2, commutative: false},
+		{name: "SaturatedAddUint16x8", argLength: 2, commutative: true},
+		{name: "SaturatedAddMaskedUint16x8", argLength: 3, commutative: true},
+		{name: "SaturatedSubUint16x8", argLength: 2, commutative: false},
+		{name: "SaturatedSubMaskedUint16x8", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftUint16x8", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedUint16x8", argLength: 3, commutative: false},
+		{name: "ShiftAllRightUint16x8", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedUint16x8", argLength: 3, commutative: false},
+		{name: "ShiftLeftUint16x8", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromUint16x8", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedUint16x8", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedUint16x8", argLength: 3, commutative: false},
+		{name: "ShiftRightUint16x8", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromUint16x8", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedUint16x8", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedUint16x8", argLength: 3, commutative: false},
+		{name: "SubUint16x8", argLength: 2, commutative: false},
+		{name: "SubMaskedUint16x8", argLength: 3, commutative: false},
+		{name: "XorUint16x8", argLength: 2, commutative: true},
+		{name: "AddUint32x16", argLength: 2, commutative: true},
+		{name: "AddMaskedUint32x16", argLength: 3, commutative: true},
+		{name: "AndUint32x16", argLength: 2, commutative: true},
+		{name: "AndMaskedUint32x16", argLength: 3, commutative: true},
+		{name: "AndNotUint32x16", argLength: 2, commutative: false},
+		{name: "AndNotMaskedUint32x16", argLength: 3, commutative: false},
+		{name: "CompressUint32x16", argLength: 2, commutative: false},
+		{name: "EqualUint32x16", argLength: 2, commutative: true},
+		{name: "EqualMaskedUint32x16", argLength: 3, commutative: true},
+		{name: "GreaterUint32x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualUint32x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedUint32x16", argLength: 3, commutative: false},
+		{name: "GreaterMaskedUint32x16", argLength: 3, commutative: false},
+		{name: "LessUint32x16", argLength: 2, commutative: false},
+		{name: "LessEqualUint32x16", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedUint32x16", argLength: 3, commutative: false},
+		{name: "LessMaskedUint32x16", argLength: 3, commutative: false},
+		{name: "MaxUint32x16", argLength: 2, commutative: true},
+		{name: "MaxMaskedUint32x16", argLength: 3, commutative: true},
+		{name: "MinUint32x16", argLength: 2, commutative: true},
+		{name: "MinMaskedUint32x16", argLength: 3, commutative: true},
+		{name: "NotEqualUint32x16", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedUint32x16", argLength: 3, commutative: true},
+		{name: "OrUint32x16", argLength: 2, commutative: true},
+		{name: "OrMaskedUint32x16", argLength: 3, commutative: true},
+		{name: "PermuteFloat32x16", argLength: 2, commutative: false},
+		{name: "PermuteInt32x16", argLength: 2, commutative: false},
+		{name: "PermuteUint32x16", argLength: 2, commutative: false},
+		{name: "Permute2Uint32x16", argLength: 3, commutative: false},
+		{name: "Permute2Float32x16", argLength: 3, commutative: false},
+		{name: "Permute2Int32x16", argLength: 3, commutative: false},
+		{name: "Permute2MaskedInt32x16", argLength: 4, commutative: false},
+		{name: "Permute2MaskedFloat32x16", argLength: 4, commutative: false},
+		{name: "Permute2MaskedUint32x16", argLength: 4, commutative: false},
+		{name: "PermuteMaskedInt32x16", argLength: 3, commutative: false},
+		{name: "PermuteMaskedFloat32x16", argLength: 3, commutative: false},
+		{name: "PermuteMaskedUint32x16", argLength: 3, commutative: false},
+		{name: "PopCountUint32x16", argLength: 1, commutative: false},
+		{name: "PopCountMaskedUint32x16", argLength: 2, commutative: false},
+		{name: "RotateLeftUint32x16", argLength: 2, commutative: false},
+		{name: "RotateLeftMaskedUint32x16", argLength: 3, commutative: false},
+		{name: "RotateRightUint32x16", argLength: 2, commutative: false},
+		{name: "RotateRightMaskedUint32x16", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftUint32x16", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedUint32x16", argLength: 3, commutative: false},
+		{name: "ShiftAllRightUint32x16", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedUint32x16", argLength: 3, commutative: false},
+		{name: "ShiftLeftUint32x16", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromUint32x16", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedUint32x16", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedUint32x16", argLength: 3, commutative: false},
+		{name: "ShiftRightUint32x16", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromUint32x16", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedUint32x16", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedUint32x16", argLength: 3, commutative: false},
+		{name: "SubUint32x16", argLength: 2, commutative: false},
+		{name: "SubMaskedUint32x16", argLength: 3, commutative: false},
+		{name: "XorUint32x16", argLength: 2, commutative: true},
+		{name: "XorMaskedUint32x16", argLength: 3, commutative: true},
+		{name: "AddUint32x4", argLength: 2, commutative: true},
+		{name: "AddMaskedUint32x4", argLength: 3, commutative: true},
+		{name: "AndUint32x4", argLength: 2, commutative: true},
+		{name: "AndMaskedUint32x4", argLength: 3, commutative: true},
+		{name: "AndNotUint32x4", argLength: 2, commutative: false},
+		{name: "AndNotMaskedUint32x4", argLength: 3, commutative: false},
+		{name: "CompressUint32x4", argLength: 2, commutative: false},
+		{name: "EqualUint32x4", argLength: 2, commutative: true},
+		{name: "EqualMaskedUint32x4", argLength: 3, commutative: true},
+		{name: "GreaterUint32x4", argLength: 2, commutative: false},
+		{name: "GreaterEqualUint32x4", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedUint32x4", argLength: 3, commutative: false},
+		{name: "GreaterMaskedUint32x4", argLength: 3, commutative: false},
+		{name: "LessUint32x4", argLength: 2, commutative: false},
+		{name: "LessEqualUint32x4", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedUint32x4", argLength: 3, commutative: false},
+		{name: "LessMaskedUint32x4", argLength: 3, commutative: false},
+		{name: "MaxUint32x4", argLength: 2, commutative: true},
+		{name: "MaxMaskedUint32x4", argLength: 3, commutative: true},
+		{name: "MinUint32x4", argLength: 2, commutative: true},
+		{name: "MinMaskedUint32x4", argLength: 3, commutative: true},
+		{name: "MulEvenWidenUint32x4", argLength: 2, commutative: true},
+		{name: "NotEqualUint32x4", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedUint32x4", argLength: 3, commutative: true},
+		{name: "OrUint32x4", argLength: 2, commutative: true},
+		{name: "OrMaskedUint32x4", argLength: 3, commutative: true},
+		{name: "PairwiseAddUint32x4", argLength: 2, commutative: false},
+		{name: "PairwiseSubUint32x4", argLength: 2, commutative: false},
+		{name: "Permute2Float32x4", argLength: 3, commutative: false},
+		{name: "Permute2Uint32x4", argLength: 3, commutative: false},
+		{name: "Permute2Int32x4", argLength: 3, commutative: false},
+		{name: "Permute2MaskedInt32x4", argLength: 4, commutative: false},
+		{name: "Permute2MaskedUint32x4", argLength: 4, commutative: false},
+		{name: "Permute2MaskedFloat32x4", argLength: 4, commutative: false},
+		{name: "PopCountUint32x4", argLength: 1, commutative: false},
+		{name: "PopCountMaskedUint32x4", argLength: 2, commutative: false},
+		{name: "RotateLeftUint32x4", argLength: 2, commutative: false},
+		{name: "RotateLeftMaskedUint32x4", argLength: 3, commutative: false},
+		{name: "RotateRightUint32x4", argLength: 2, commutative: false},
+		{name: "RotateRightMaskedUint32x4", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftUint32x4", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedUint32x4", argLength: 3, commutative: false},
+		{name: "ShiftAllRightUint32x4", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedUint32x4", argLength: 3, commutative: false},
+		{name: "ShiftLeftUint32x4", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromUint32x4", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedUint32x4", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedUint32x4", argLength: 3, commutative: false},
+		{name: "ShiftRightUint32x4", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromUint32x4", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedUint32x4", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedUint32x4", argLength: 3, commutative: false},
+		{name: "SubUint32x4", argLength: 2, commutative: false},
+		{name: "SubMaskedUint32x4", argLength: 3, commutative: false},
+		{name: "XorUint32x4", argLength: 2, commutative: true},
+		{name: "XorMaskedUint32x4", argLength: 3, commutative: true},
+		{name: "AddUint32x8", argLength: 2, commutative: true},
+		{name: "AddMaskedUint32x8", argLength: 3, commutative: true},
+		{name: "AndUint32x8", argLength: 2, commutative: true},
+		{name: "AndMaskedUint32x8", argLength: 3, commutative: true},
+		{name: "AndNotUint32x8", argLength: 2, commutative: false},
+		{name: "AndNotMaskedUint32x8", argLength: 3, commutative: false},
+		{name: "CompressUint32x8", argLength: 2, commutative: false},
+		{name: "EqualUint32x8", argLength: 2, commutative: true},
+		{name: "EqualMaskedUint32x8", argLength: 3, commutative: true},
+		{name: "GreaterUint32x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualUint32x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedUint32x8", argLength: 3, commutative: false},
+		{name: "GreaterMaskedUint32x8", argLength: 3, commutative: false},
+		{name: "LessUint32x8", argLength: 2, commutative: false},
+		{name: "LessEqualUint32x8", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedUint32x8", argLength: 3, commutative: false},
+		{name: "LessMaskedUint32x8", argLength: 3, commutative: false},
+		{name: "MaxUint32x8", argLength: 2, commutative: true},
+		{name: "MaxMaskedUint32x8", argLength: 3, commutative: true},
+		{name: "MinUint32x8", argLength: 2, commutative: true},
+		{name: "MinMaskedUint32x8", argLength: 3, commutative: true},
+		{name: "MulEvenWidenUint32x8", argLength: 2, commutative: true},
+		{name: "NotEqualUint32x8", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedUint32x8", argLength: 3, commutative: true},
+		{name: "OrUint32x8", argLength: 2, commutative: true},
+		{name: "OrMaskedUint32x8", argLength: 3, commutative: true},
+		{name: "PairwiseAddUint32x8", argLength: 2, commutative: false},
+		{name: "PairwiseSubUint32x8", argLength: 2, commutative: false},
+		{name: "PermuteUint32x8", argLength: 2, commutative: false},
+		{name: "PermuteFloat32x8", argLength: 2, commutative: false},
+		{name: "PermuteInt32x8", argLength: 2, commutative: false},
+		{name: "Permute2Int32x8", argLength: 3, commutative: false},
+		{name: "Permute2Float32x8", argLength: 3, commutative: false},
+		{name: "Permute2Uint32x8", argLength: 3, commutative: false},
+		{name: "Permute2MaskedFloat32x8", argLength: 4, commutative: false},
+		{name: "Permute2MaskedUint32x8", argLength: 4, commutative: false},
+		{name: "Permute2MaskedInt32x8", argLength: 4, commutative: false},
+		{name: "PermuteMaskedInt32x8", argLength: 3, commutative: false},
+		{name: "PermuteMaskedUint32x8", argLength: 3, commutative: false},
+		{name: "PermuteMaskedFloat32x8", argLength: 3, commutative: false},
+		{name: "PopCountUint32x8", argLength: 1, commutative: false},
+		{name: "PopCountMaskedUint32x8", argLength: 2, commutative: false},
+		{name: "RotateLeftUint32x8", argLength: 2, commutative: false},
+		{name: "RotateLeftMaskedUint32x8", argLength: 3, commutative: false},
+		{name: "RotateRightUint32x8", argLength: 2, commutative: false},
+		{name: "RotateRightMaskedUint32x8", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftUint32x8", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedUint32x8", argLength: 3, commutative: false},
+		{name: "ShiftAllRightUint32x8", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedUint32x8", argLength: 3, commutative: false},
+		{name: "ShiftLeftUint32x8", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromUint32x8", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedUint32x8", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedUint32x8", argLength: 3, commutative: false},
+		{name: "ShiftRightUint32x8", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromUint32x8", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedUint32x8", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedUint32x8", argLength: 3, commutative: false},
+		{name: "SubUint32x8", argLength: 2, commutative: false},
+		{name: "SubMaskedUint32x8", argLength: 3, commutative: false},
+		{name: "XorUint32x8", argLength: 2, commutative: true},
+		{name: "XorMaskedUint32x8", argLength: 3, commutative: true},
+		{name: "AddUint64x2", argLength: 2, commutative: true},
+		{name: "AddMaskedUint64x2", argLength: 3, commutative: true},
+		{name: "AndUint64x2", argLength: 2, commutative: true},
+		{name: "AndMaskedUint64x2", argLength: 3, commutative: true},
+		{name: "AndNotUint64x2", argLength: 2, commutative: false},
+		{name: "AndNotMaskedUint64x2", argLength: 3, commutative: false},
+		{name: "CompressUint64x2", argLength: 2, commutative: false},
+		{name: "EqualUint64x2", argLength: 2, commutative: true},
+		{name: "EqualMaskedUint64x2", argLength: 3, commutative: true},
+		{name: "GreaterUint64x2", argLength: 2, commutative: false},
+		{name: "GreaterEqualUint64x2", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedUint64x2", argLength: 3, commutative: false},
+		{name: "GreaterMaskedUint64x2", argLength: 3, commutative: false},
+		{name: "LessUint64x2", argLength: 2, commutative: false},
+		{name: "LessEqualUint64x2", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedUint64x2", argLength: 3, commutative: false},
+		{name: "LessMaskedUint64x2", argLength: 3, commutative: false},
+		{name: "MaxUint64x2", argLength: 2, commutative: true},
+		{name: "MaxMaskedUint64x2", argLength: 3, commutative: true},
+		{name: "MinUint64x2", argLength: 2, commutative: true},
+		{name: "MinMaskedUint64x2", argLength: 3, commutative: true},
+		{name: "MulEvenWidenUint64x2", argLength: 2, commutative: true},
+		{name: "MulEvenWidenMaskedUint64x2", argLength: 3, commutative: true},
+		{name: "NotEqualUint64x2", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedUint64x2", argLength: 3, commutative: true},
+		{name: "OrUint64x2", argLength: 2, commutative: true},
+		{name: "OrMaskedUint64x2", argLength: 3, commutative: true},
+		{name: "Permute2Float64x2", argLength: 3, commutative: false},
+		{name: "Permute2Uint64x2", argLength: 3, commutative: false},
+		{name: "Permute2Int64x2", argLength: 3, commutative: false},
+		{name: "Permute2MaskedInt64x2", argLength: 4, commutative: false},
+		{name: "Permute2MaskedFloat64x2", argLength: 4, commutative: false},
+		{name: "Permute2MaskedUint64x2", argLength: 4, commutative: false},
+		{name: "PopCountUint64x2", argLength: 1, commutative: false},
+		{name: "PopCountMaskedUint64x2", argLength: 2, commutative: false},
+		{name: "RotateLeftUint64x2", argLength: 2, commutative: false},
+		{name: "RotateLeftMaskedUint64x2", argLength: 3, commutative: false},
+		{name: "RotateRightUint64x2", argLength: 2, commutative: false},
+		{name: "RotateRightMaskedUint64x2", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftUint64x2", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedUint64x2", argLength: 3, commutative: false},
+		{name: "ShiftAllRightUint64x2", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedUint64x2", argLength: 3, commutative: false},
+		{name: "ShiftLeftUint64x2", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromUint64x2", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedUint64x2", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedUint64x2", argLength: 3, commutative: false},
+		{name: "ShiftRightUint64x2", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromUint64x2", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedUint64x2", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedUint64x2", argLength: 3, commutative: false},
+		{name: "SubUint64x2", argLength: 2, commutative: false},
+		{name: "SubMaskedUint64x2", argLength: 3, commutative: false},
+		{name: "XorUint64x2", argLength: 2, commutative: true},
+		{name: "XorMaskedUint64x2", argLength: 3, commutative: true},
+		{name: "AddUint64x4", argLength: 2, commutative: true},
+		{name: "AddMaskedUint64x4", argLength: 3, commutative: true},
+		{name: "AndUint64x4", argLength: 2, commutative: true},
+		{name: "AndMaskedUint64x4", argLength: 3, commutative: true},
+		{name: "AndNotUint64x4", argLength: 2, commutative: false},
+		{name: "AndNotMaskedUint64x4", argLength: 3, commutative: false},
+		{name: "CompressUint64x4", argLength: 2, commutative: false},
+		{name: "EqualUint64x4", argLength: 2, commutative: true},
+		{name: "EqualMaskedUint64x4", argLength: 3, commutative: true},
+		{name: "GreaterUint64x4", argLength: 2, commutative: false},
+		{name: "GreaterEqualUint64x4", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedUint64x4", argLength: 3, commutative: false},
+		{name: "GreaterMaskedUint64x4", argLength: 3, commutative: false},
+		{name: "LessUint64x4", argLength: 2, commutative: false},
+		{name: "LessEqualUint64x4", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedUint64x4", argLength: 3, commutative: false},
+		{name: "LessMaskedUint64x4", argLength: 3, commutative: false},
+		{name: "MaxUint64x4", argLength: 2, commutative: true},
+		{name: "MaxMaskedUint64x4", argLength: 3, commutative: true},
+		{name: "MinUint64x4", argLength: 2, commutative: true},
+		{name: "MinMaskedUint64x4", argLength: 3, commutative: true},
+		{name: "MulEvenWidenUint64x4", argLength: 2, commutative: true},
+		{name: "MulEvenWidenMaskedUint64x4", argLength: 3, commutative: true},
+		{name: "NotEqualUint64x4", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedUint64x4", argLength: 3, commutative: true},
+		{name: "OrUint64x4", argLength: 2, commutative: true},
+		{name: "OrMaskedUint64x4", argLength: 3, commutative: true},
+		{name: "PermuteUint64x4", argLength: 2, commutative: false},
+		{name: "PermuteInt64x4", argLength: 2, commutative: false},
+		{name: "PermuteFloat64x4", argLength: 2, commutative: false},
+		{name: "Permute2Float64x4", argLength: 3, commutative: false},
+		{name: "Permute2Int64x4", argLength: 3, commutative: false},
+		{name: "Permute2Uint64x4", argLength: 3, commutative: false},
+		{name: "Permute2MaskedFloat64x4", argLength: 4, commutative: false},
+		{name: "Permute2MaskedUint64x4", argLength: 4, commutative: false},
+		{name: "Permute2MaskedInt64x4", argLength: 4, commutative: false},
+		{name: "PermuteMaskedFloat64x4", argLength: 3, commutative: false},
+		{name: "PermuteMaskedInt64x4", argLength: 3, commutative: false},
+		{name: "PermuteMaskedUint64x4", argLength: 3, commutative: false},
+		{name: "PopCountUint64x4", argLength: 1, commutative: false},
+		{name: "PopCountMaskedUint64x4", argLength: 2, commutative: false},
+		{name: "RotateLeftUint64x4", argLength: 2, commutative: false},
+		{name: "RotateLeftMaskedUint64x4", argLength: 3, commutative: false},
+		{name: "RotateRightUint64x4", argLength: 2, commutative: false},
+		{name: "RotateRightMaskedUint64x4", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftUint64x4", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedUint64x4", argLength: 3, commutative: false},
+		{name: "ShiftAllRightUint64x4", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedUint64x4", argLength: 3, commutative: false},
+		{name: "ShiftLeftUint64x4", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromUint64x4", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedUint64x4", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedUint64x4", argLength: 3, commutative: false},
+		{name: "ShiftRightUint64x4", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromUint64x4", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedUint64x4", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedUint64x4", argLength: 3, commutative: false},
+		{name: "SubUint64x4", argLength: 2, commutative: false},
+		{name: "SubMaskedUint64x4", argLength: 3, commutative: false},
+		{name: "XorUint64x4", argLength: 2, commutative: true},
+		{name: "XorMaskedUint64x4", argLength: 3, commutative: true},
+		{name: "AddUint64x8", argLength: 2, commutative: true},
+		{name: "AddMaskedUint64x8", argLength: 3, commutative: true},
+		{name: "AndUint64x8", argLength: 2, commutative: true},
+		{name: "AndMaskedUint64x8", argLength: 3, commutative: true},
+		{name: "AndNotUint64x8", argLength: 2, commutative: false},
+		{name: "AndNotMaskedUint64x8", argLength: 3, commutative: false},
+		{name: "CompressUint64x8", argLength: 2, commutative: false},
+		{name: "EqualUint64x8", argLength: 2, commutative: true},
+		{name: "EqualMaskedUint64x8", argLength: 3, commutative: true},
+		{name: "GreaterUint64x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualUint64x8", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedUint64x8", argLength: 3, commutative: false},
+		{name: "GreaterMaskedUint64x8", argLength: 3, commutative: false},
+		{name: "LessUint64x8", argLength: 2, commutative: false},
+		{name: "LessEqualUint64x8", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedUint64x8", argLength: 3, commutative: false},
+		{name: "LessMaskedUint64x8", argLength: 3, commutative: false},
+		{name: "MaxUint64x8", argLength: 2, commutative: true},
+		{name: "MaxMaskedUint64x8", argLength: 3, commutative: true},
+		{name: "MinUint64x8", argLength: 2, commutative: true},
+		{name: "MinMaskedUint64x8", argLength: 3, commutative: true},
+		{name: "MulEvenWidenUint64x8", argLength: 2, commutative: true},
+		{name: "MulEvenWidenMaskedUint64x8", argLength: 3, commutative: true},
+		{name: "NotEqualUint64x8", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedUint64x8", argLength: 3, commutative: true},
+		{name: "OrUint64x8", argLength: 2, commutative: true},
+		{name: "OrMaskedUint64x8", argLength: 3, commutative: true},
+		{name: "PermuteFloat64x8", argLength: 2, commutative: false},
+		{name: "PermuteInt64x8", argLength: 2, commutative: false},
+		{name: "PermuteUint64x8", argLength: 2, commutative: false},
+		{name: "Permute2Int64x8", argLength: 3, commutative: false},
+		{name: "Permute2Float64x8", argLength: 3, commutative: false},
+		{name: "Permute2Uint64x8", argLength: 3, commutative: false},
+		{name: "Permute2MaskedUint64x8", argLength: 4, commutative: false},
+		{name: "Permute2MaskedInt64x8", argLength: 4, commutative: false},
+		{name: "Permute2MaskedFloat64x8", argLength: 4, commutative: false},
+		{name: "PermuteMaskedUint64x8", argLength: 3, commutative: false},
+		{name: "PermuteMaskedFloat64x8", argLength: 3, commutative: false},
+		{name: "PermuteMaskedInt64x8", argLength: 3, commutative: false},
+		{name: "PopCountUint64x8", argLength: 1, commutative: false},
+		{name: "PopCountMaskedUint64x8", argLength: 2, commutative: false},
+		{name: "RotateLeftUint64x8", argLength: 2, commutative: false},
+		{name: "RotateLeftMaskedUint64x8", argLength: 3, commutative: false},
+		{name: "RotateRightUint64x8", argLength: 2, commutative: false},
+		{name: "RotateRightMaskedUint64x8", argLength: 3, commutative: false},
+		{name: "ShiftAllLeftUint64x8", argLength: 2, commutative: false},
+		{name: "ShiftAllLeftMaskedUint64x8", argLength: 3, commutative: false},
+		{name: "ShiftAllRightUint64x8", argLength: 2, commutative: false},
+		{name: "ShiftAllRightMaskedUint64x8", argLength: 3, commutative: false},
+		{name: "ShiftLeftUint64x8", argLength: 2, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromUint64x8", argLength: 3, commutative: false},
+		{name: "ShiftLeftAndFillUpperFromMaskedUint64x8", argLength: 4, commutative: false},
+		{name: "ShiftLeftMaskedUint64x8", argLength: 3, commutative: false},
+		{name: "ShiftRightUint64x8", argLength: 2, commutative: false},
+		{name: "ShiftRightAndFillUpperFromUint64x8", argLength: 3, commutative: false},
+		{name: "ShiftRightAndFillUpperFromMaskedUint64x8", argLength: 4, commutative: false},
+		{name: "ShiftRightMaskedUint64x8", argLength: 3, commutative: false},
+		{name: "SubUint64x8", argLength: 2, commutative: false},
+		{name: "SubMaskedUint64x8", argLength: 3, commutative: false},
+		{name: "XorUint64x8", argLength: 2, commutative: true},
+		{name: "XorMaskedUint64x8", argLength: 3, commutative: true},
+		{name: "AddUint8x16", argLength: 2, commutative: true},
+		{name: "AddMaskedUint8x16", argLength: 3, commutative: true},
+		{name: "AndUint8x16", argLength: 2, commutative: true},
+		{name: "AndNotUint8x16", argLength: 2, commutative: false},
+		{name: "AverageUint8x16", argLength: 2, commutative: true},
+		{name: "AverageMaskedUint8x16", argLength: 3, commutative: true},
+		{name: "CompressUint8x16", argLength: 2, commutative: false},
+		{name: "EqualUint8x16", argLength: 2, commutative: true},
+		{name: "EqualMaskedUint8x16", argLength: 3, commutative: true},
+		{name: "GaloisFieldMulUint8x16", argLength: 2, commutative: false},
+		{name: "GaloisFieldMulMaskedUint8x16", argLength: 3, commutative: false},
+		{name: "GreaterUint8x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualUint8x16", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedUint8x16", argLength: 3, commutative: false},
+		{name: "GreaterMaskedUint8x16", argLength: 3, commutative: false},
+		{name: "LessUint8x16", argLength: 2, commutative: false},
+		{name: "LessEqualUint8x16", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedUint8x16", argLength: 3, commutative: false},
+		{name: "LessMaskedUint8x16", argLength: 3, commutative: false},
+		{name: "MaxUint8x16", argLength: 2, commutative: true},
+		{name: "MaxMaskedUint8x16", argLength: 3, commutative: true},
+		{name: "MinUint8x16", argLength: 2, commutative: true},
+		{name: "MinMaskedUint8x16", argLength: 3, commutative: true},
+		{name: "NotEqualUint8x16", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedUint8x16", argLength: 3, commutative: true},
+		{name: "OrUint8x16", argLength: 2, commutative: true},
+		{name: "PermuteUint8x16", argLength: 2, commutative: false},
+		{name: "PermuteInt8x16", argLength: 2, commutative: false},
+		{name: "Permute2Uint8x16", argLength: 3, commutative: false},
+		{name: "Permute2Int8x16", argLength: 3, commutative: false},
+		{name: "Permute2MaskedInt8x16", argLength: 4, commutative: false},
+		{name: "Permute2MaskedUint8x16", argLength: 4, commutative: false},
+		{name: "PermuteMaskedUint8x16", argLength: 3, commutative: false},
+		{name: "PermuteMaskedInt8x16", argLength: 3, commutative: false},
+		{name: "PopCountUint8x16", argLength: 1, commutative: false},
+		{name: "PopCountMaskedUint8x16", argLength: 2, commutative: false},
+		{name: "SaturatedAddUint8x16", argLength: 2, commutative: true},
+		{name: "SaturatedAddMaskedUint8x16", argLength: 3, commutative: true},
+		{name: "SaturatedSubUint8x16", argLength: 2, commutative: false},
+		{name: "SaturatedSubMaskedUint8x16", argLength: 3, commutative: false},
+		{name: "SaturatedUnsignedSignedPairDotProdUint8x16", argLength: 2, commutative: false},
+		{name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x16", argLength: 3, commutative: false},
+		{name: "SubUint8x16", argLength: 2, commutative: false},
+		{name: "SubMaskedUint8x16", argLength: 3, commutative: false},
+		{name: "XorUint8x16", argLength: 2, commutative: true},
+		{name: "AddUint8x32", argLength: 2, commutative: true},
+		{name: "AddMaskedUint8x32", argLength: 3, commutative: true},
+		{name: "AndUint8x32", argLength: 2, commutative: true},
+		{name: "AndNotUint8x32", argLength: 2, commutative: false},
+		{name: "AverageUint8x32", argLength: 2, commutative: true},
+		{name: "AverageMaskedUint8x32", argLength: 3, commutative: true},
+		{name: "CompressUint8x32", argLength: 2, commutative: false},
+		{name: "EqualUint8x32", argLength: 2, commutative: true},
+		{name: "EqualMaskedUint8x32", argLength: 3, commutative: true},
+		{name: "GaloisFieldMulUint8x32", argLength: 2, commutative: false},
+		{name: "GaloisFieldMulMaskedUint8x32", argLength: 3, commutative: false},
+		{name: "GreaterUint8x32", argLength: 2, commutative: false},
+		{name: "GreaterEqualUint8x32", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedUint8x32", argLength: 3, commutative: false},
+		{name: "GreaterMaskedUint8x32", argLength: 3, commutative: false},
+		{name: "LessUint8x32", argLength: 2, commutative: false},
+		{name: "LessEqualUint8x32", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedUint8x32", argLength: 3, commutative: false},
+		{name: "LessMaskedUint8x32", argLength: 3, commutative: false},
+		{name: "MaxUint8x32", argLength: 2, commutative: true},
+		{name: "MaxMaskedUint8x32", argLength: 3, commutative: true},
+		{name: "MinUint8x32", argLength: 2, commutative: true},
+		{name: "MinMaskedUint8x32", argLength: 3, commutative: true},
+		{name: "NotEqualUint8x32", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedUint8x32", argLength: 3, commutative: true},
+		{name: "OrUint8x32", argLength: 2, commutative: true},
+		{name: "PermuteUint8x32", argLength: 2, commutative: false},
+		{name: "PermuteInt8x32", argLength: 2, commutative: false},
+		{name: "Permute2Int8x32", argLength: 3, commutative: false},
+		{name: "Permute2Uint8x32", argLength: 3, commutative: false},
+		{name: "Permute2MaskedUint8x32", argLength: 4, commutative: false},
+		{name: "Permute2MaskedInt8x32", argLength: 4, commutative: false},
+		{name: "PermuteMaskedUint8x32", argLength: 3, commutative: false},
+		{name: "PermuteMaskedInt8x32", argLength: 3, commutative: false},
+		{name: "PopCountUint8x32", argLength: 1, commutative: false},
+		{name: "PopCountMaskedUint8x32", argLength: 2, commutative: false},
+		{name: "SaturatedAddUint8x32", argLength: 2, commutative: true},
+		{name: "SaturatedAddMaskedUint8x32", argLength: 3, commutative: true},
+		{name: "SaturatedSubUint8x32", argLength: 2, commutative: false},
+		{name: "SaturatedSubMaskedUint8x32", argLength: 3, commutative: false},
+		{name: "SaturatedUnsignedSignedPairDotProdUint8x32", argLength: 2, commutative: false},
+		{name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x32", argLength: 3, commutative: false},
+		{name: "SubUint8x32", argLength: 2, commutative: false},
+		{name: "SubMaskedUint8x32", argLength: 3, commutative: false},
+		{name: "XorUint8x32", argLength: 2, commutative: true},
+		{name: "AddUint8x64", argLength: 2, commutative: true},
+		{name: "AddMaskedUint8x64", argLength: 3, commutative: true},
+		{name: "AverageUint8x64", argLength: 2, commutative: true},
+		{name: "AverageMaskedUint8x64", argLength: 3, commutative: true},
+		{name: "CompressUint8x64", argLength: 2, commutative: false},
+		{name: "EqualUint8x64", argLength: 2, commutative: true},
+		{name: "EqualMaskedUint8x64", argLength: 3, commutative: true},
+		{name: "GaloisFieldMulUint8x64", argLength: 2, commutative: false},
+		{name: "GaloisFieldMulMaskedUint8x64", argLength: 3, commutative: false},
+		{name: "GreaterUint8x64", argLength: 2, commutative: false},
+		{name: "GreaterEqualUint8x64", argLength: 2, commutative: false},
+		{name: "GreaterEqualMaskedUint8x64", argLength: 3, commutative: false},
+		{name: "GreaterMaskedUint8x64", argLength: 3, commutative: false},
+		{name: "LessUint8x64", argLength: 2, commutative: false},
+		{name: "LessEqualUint8x64", argLength: 2, commutative: false},
+		{name: "LessEqualMaskedUint8x64", argLength: 3, commutative: false},
+		{name: "LessMaskedUint8x64", argLength: 3, commutative: false},
+		{name: "MaxUint8x64", argLength: 2, commutative: true},
+		{name: "MaxMaskedUint8x64", argLength: 3, commutative: true},
+		{name: "MinUint8x64", argLength: 2, commutative: true},
+		{name: "MinMaskedUint8x64", argLength: 3, commutative: true},
+		{name: "NotEqualUint8x64", argLength: 2, commutative: true},
+		{name: "NotEqualMaskedUint8x64", argLength: 3, commutative: true},
+		{name: "PermuteInt8x64", argLength: 2, commutative: false},
+		{name: "PermuteUint8x64", argLength: 2, commutative: false},
+		{name: "Permute2Uint8x64", argLength: 3, commutative: false},
+		{name: "Permute2Int8x64", argLength: 3, commutative: false},
+		{name: "Permute2MaskedUint8x64", argLength: 4, commutative: false},
+		{name: "Permute2MaskedInt8x64", argLength: 4, commutative: false},
+		{name: "PermuteMaskedUint8x64", argLength: 3, commutative: false},
+		{name: "PermuteMaskedInt8x64", argLength: 3, commutative: false},
+		{name: "PopCountUint8x64", argLength: 1, commutative: false},
+		{name: "PopCountMaskedUint8x64", argLength: 2, commutative: false},
+		{name: "SaturatedAddUint8x64", argLength: 2, commutative: true},
+		{name: "SaturatedAddMaskedUint8x64", argLength: 3, commutative: true},
+		{name: "SaturatedSubUint8x64", argLength: 2, commutative: false},
+		{name: "SaturatedSubMaskedUint8x64", argLength: 3, commutative: false},
+		{name: "SaturatedUnsignedSignedPairDotProdUint8x64", argLength: 2, commutative: false},
+		{name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x64", argLength: 3, commutative: false},
+		{name: "SubUint8x64", argLength: 2, commutative: false},
+		{name: "SubMaskedUint8x64", argLength: 3, commutative: false},
+		{name: "CeilWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "CeilWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithCeilWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithCeilWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithFloorWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithFloorWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithRoundWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithRoundWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithTruncWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithTruncWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "FloorWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "FloorWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RoundWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RoundWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "TruncWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "TruncWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "CeilWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "CeilWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithCeilWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithCeilWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithFloorWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithFloorWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithRoundWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithRoundWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithTruncWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithTruncWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "FloorWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "FloorWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RoundWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RoundWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "TruncWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "TruncWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "CeilWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "CeilWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithCeilWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithCeilWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithFloorWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithFloorWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithRoundWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithRoundWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithTruncWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithTruncWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "FloorWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "FloorWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "Get128Float32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RoundWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RoundWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "Set128Float32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "TruncWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "TruncWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "CeilWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "CeilWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithCeilWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithCeilWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithFloorWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithFloorWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithRoundWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithRoundWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithTruncWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithTruncWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "FloorWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "FloorWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RoundWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RoundWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "TruncWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "TruncWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "CeilWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "CeilWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithCeilWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithCeilWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithFloorWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithFloorWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithRoundWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithRoundWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithTruncWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithTruncWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "FloorWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "FloorWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "Get128Float64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RoundWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RoundWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "Set128Float64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "TruncWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "TruncWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "CeilWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "CeilWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithCeilWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithCeilWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithFloorWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithFloorWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithRoundWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithRoundWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "DiffWithTruncWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "DiffWithTruncWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "FloorWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "FloorWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RoundWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RoundWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "TruncWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "TruncWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "Get128Int16x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "Set128Int16x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromInt16x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedInt16x16", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromInt16x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedInt16x16", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromInt16x32", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedInt16x32", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromInt16x32", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedInt16x32", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "GetElemInt16x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "SetElemInt16x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromInt16x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedInt16x8", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromInt16x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedInt16x8", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftInt32x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftMaskedInt32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightInt32x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightMaskedInt32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromInt32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedInt32x16", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromInt32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedInt32x16", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "GetElemInt32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftInt32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftMaskedInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightInt32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightMaskedInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "SetElemInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedInt32x4", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedInt32x4", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "Get128Int32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftInt32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftMaskedInt32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightInt32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightMaskedInt32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "Set128Int32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromInt32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedInt32x8", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromInt32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedInt32x8", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "GetElemInt64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftInt64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftMaskedInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightInt64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightMaskedInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "SetElemInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedInt64x2", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedInt64x2", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "Get128Int64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftInt64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftMaskedInt64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightInt64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightMaskedInt64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "Set128Int64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromInt64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedInt64x4", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromInt64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedInt64x4", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftInt64x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftMaskedInt64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightInt64x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightMaskedInt64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromInt64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedInt64x8", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromInt64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedInt64x8", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "GetElemInt8x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "SetElemInt8x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "Get128Int8x32", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "Set128Int8x32", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "Get128Uint16x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "Set128Uint16x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromUint16x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedUint16x16", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromUint16x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedUint16x16", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromUint16x32", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedUint16x32", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromUint16x32", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedUint16x32", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "GetElemUint16x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "SetElemUint16x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromUint16x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedUint16x8", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromUint16x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedUint16x8", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftUint32x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftMaskedUint32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightUint32x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightMaskedUint32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromUint32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedUint32x16", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromUint32x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedUint32x16", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "GetElemUint32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftUint32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftMaskedUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightUint32x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightMaskedUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "SetElemUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedUint32x4", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedUint32x4", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "Get128Uint32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftUint32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftMaskedUint32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightUint32x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightMaskedUint32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "Set128Uint32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromUint32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedUint32x8", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromUint32x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedUint32x8", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "GetElemUint64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftUint64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftMaskedUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightUint64x2", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightMaskedUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "SetElemUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedUint64x2", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedUint64x2", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "Get128Uint64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftUint64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftMaskedUint64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightUint64x4", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightMaskedUint64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "Set128Uint64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromUint64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedUint64x4", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromUint64x4", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedUint64x4", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftUint64x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllLeftMaskedUint64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightUint64x8", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "RotateAllRightMaskedUint64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromUint64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllLeftAndFillUpperFromMaskedUint64x8", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromUint64x8", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "ShiftAllRightAndFillUpperFromMaskedUint64x8", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "GaloisFieldAffineTransformUint8x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "GaloisFieldAffineTransformInverseUint8x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "GaloisFieldAffineTransformInverseMaskedUint8x16", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "GaloisFieldAffineTransformMaskedUint8x16", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "GetElemUint8x16", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "SetElemUint8x16", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "GaloisFieldAffineTransformUint8x32", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "GaloisFieldAffineTransformInverseUint8x32", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "GaloisFieldAffineTransformInverseMaskedUint8x32", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "GaloisFieldAffineTransformMaskedUint8x32", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "Get128Uint8x32", argLength: 1, commutative: false, aux: "Int8"},
+		{name: "Set128Uint8x32", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "GaloisFieldAffineTransformUint8x64", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "GaloisFieldAffineTransformInverseUint8x64", argLength: 2, commutative: false, aux: "Int8"},
+		{name: "GaloisFieldAffineTransformInverseMaskedUint8x64", argLength: 3, commutative: false, aux: "Int8"},
+		{name: "GaloisFieldAffineTransformMaskedUint8x64", argLength: 3, commutative: false, aux: "Int8"},
+	}
+}
diff --git a/src/cmd/compile/internal/ssa/config.go b/src/cmd/compile/internal/ssa/config.go
index d4cd32a0d7b5b6..0299e808c6d365 100644
--- a/src/cmd/compile/internal/ssa/config.go
+++ b/src/cmd/compile/internal/ssa/config.go
@@ -89,6 +89,10 @@ type Types struct {
 	Float32Ptr *types.Type
 	Float64Ptr *types.Type
 	BytePtrPtr *types.Type
+	Vec128     *types.Type
+	Vec256     *types.Type
+	Vec512     *types.Type
+	Mask       *types.Type
 }
 
 // NewTypes creates and populates a Types.
@@ -123,6 +127,10 @@ func (t *Types) SetTypPtrs() {
 	t.Float32Ptr = types.NewPtr(types.Types[types.TFLOAT32])
 	t.Float64Ptr = types.NewPtr(types.Types[types.TFLOAT64])
 	t.BytePtrPtr = types.NewPtr(types.NewPtr(types.Types[types.TUINT8]))
+	t.Vec128 = types.TypeVec128
+	t.Vec256 = types.TypeVec256
+	t.Vec512 = types.TypeVec512
+	t.Mask = types.TypeMask
 }
 
 type Logger interface {
diff --git a/src/cmd/compile/internal/ssa/decompose.go b/src/cmd/compile/internal/ssa/decompose.go
index cf9285741ed085..c3d9997793ef05 100644
--- a/src/cmd/compile/internal/ssa/decompose.go
+++ b/src/cmd/compile/internal/ssa/decompose.go
@@ -100,7 +100,7 @@ func decomposeBuiltIn(f *Func) {
 			}
 		case t.IsFloat():
 			// floats are never decomposed, even ones bigger than RegSize
-		case t.Size() > f.Config.RegSize:
+		case t.Size() > f.Config.RegSize && !t.IsSIMD():
 			f.Fatalf("undecomposed named type %s %v", name, t)
 		}
 	}
@@ -135,7 +135,7 @@ func decomposeBuiltInPhi(v *Value) {
 		decomposeInterfacePhi(v)
 	case v.Type.IsFloat():
 		// floats are never decomposed, even ones bigger than RegSize
-	case v.Type.Size() > v.Block.Func.Config.RegSize:
+	case v.Type.Size() > v.Block.Func.Config.RegSize && !v.Type.IsSIMD():
 		v.Fatalf("%v undecomposed type %v", v, v.Type)
 	}
 }
@@ -248,7 +248,7 @@ func decomposeUser(f *Func) {
 	for _, name := range f.Names {
 		t := name.Type
 		switch {
-		case t.IsStruct():
+		case isStructNotSIMD(t):
 			newNames = decomposeUserStructInto(f, name, newNames)
 		case t.IsArray():
 			newNames = decomposeUserArrayInto(f, name, newNames)
@@ -293,7 +293,7 @@ func decomposeUserArrayInto(f *Func, name *LocalSlot, slots []*LocalSlot) []*Loc
 
 	if t.Elem().IsArray() {
 		return decomposeUserArrayInto(f, elemName, slots)
-	} else if t.Elem().IsStruct() {
+	} else if isStructNotSIMD(t.Elem()) {
 		return decomposeUserStructInto(f, elemName, slots)
 	}
 
@@ -313,7 +313,7 @@ func decomposeUserStructInto(f *Func, name *LocalSlot, slots []*LocalSlot) []*Lo
 		fnames = append(fnames, fs)
 		// arrays and structs will be decomposed further, so
 		// there's no need to record a name
-		if !fs.Type.IsArray() && !fs.Type.IsStruct() {
+		if !fs.Type.IsArray() && !isStructNotSIMD(fs.Type) {
 			slots = maybeAppend(f, slots, fs)
 		}
 	}
@@ -339,7 +339,7 @@ func decomposeUserStructInto(f *Func, name *LocalSlot, slots []*LocalSlot) []*Lo
 	// now that this f.NamedValues contains values for the struct
 	// fields, recurse into nested structs
 	for i := 0; i < n; i++ {
-		if name.Type.FieldType(i).IsStruct() {
+		if isStructNotSIMD(name.Type.FieldType(i)) {
 			slots = decomposeUserStructInto(f, fnames[i], slots)
 			delete(f.NamedValues, *fnames[i])
 		} else if name.Type.FieldType(i).IsArray() {
@@ -351,7 +351,7 @@ func decomposeUserStructInto(f *Func, name *LocalSlot, slots []*LocalSlot) []*Lo
 }
 func decomposeUserPhi(v *Value) {
 	switch {
-	case v.Type.IsStruct():
+	case isStructNotSIMD(v.Type):
 		decomposeStructPhi(v)
 	case v.Type.IsArray():
 		decomposeArrayPhi(v)
@@ -458,3 +458,7 @@ func deleteNamedVals(f *Func, toDelete []namedVal) {
 	}
 	f.Names = f.Names[:end]
 }
+
+func isStructNotSIMD(t *types.Type) bool {
+	return t.IsStruct() && !t.IsSIMD()
+}
diff --git a/src/cmd/compile/internal/ssa/expand_calls.go b/src/cmd/compile/internal/ssa/expand_calls.go
index fb281f2f8452cb..9e46182a4cd9ae 100644
--- a/src/cmd/compile/internal/ssa/expand_calls.go
+++ b/src/cmd/compile/internal/ssa/expand_calls.go
@@ -399,6 +399,9 @@ func (x *expandState) decomposeAsNecessary(pos src.XPos, b *Block, a, m0 *Value,
 		return mem
 
 	case types.TSTRUCT:
+		if at.IsSIMD() {
+			break // XXX
+		}
 		for i := 0; i < at.NumFields(); i++ {
 			et := at.Field(i).Type // might need to read offsets from the fields
 			e := b.NewValue1I(pos, OpStructSelect, et, int64(i), a)
@@ -547,6 +550,9 @@ func (x *expandState) rewriteSelectOrArg(pos src.XPos, b *Block, container, a, m
 
 	case types.TSTRUCT:
 		// Assume ssagen/ssa.go (in buildssa) spills large aggregates so they won't appear here.
+		if at.IsSIMD() {
+			break // XXX
+		}
 		for i := 0; i < at.NumFields(); i++ {
 			et := at.Field(i).Type
 			e := x.rewriteSelectOrArg(pos, b, container, nil, m0, et, rc.next(et))
@@ -713,6 +719,9 @@ func (x *expandState) rewriteWideSelectToStores(pos src.XPos, b *Block, containe
 
 	case types.TSTRUCT:
 		// Assume ssagen/ssa.go (in buildssa) spills large aggregates so they won't appear here.
+		if at.IsSIMD() {
+			break // XXX
+		}
 		for i := 0; i < at.NumFields(); i++ {
 			et := at.Field(i).Type
 			m0 = x.rewriteWideSelectToStores(pos, b, container, m0, et, rc.next(et))
@@ -859,7 +868,7 @@ func (c *registerCursor) at(t *types.Type, i int) registerCursor {
 		rc.nextSlice += Abi1RO(i * w)
 		return rc
 	}
-	if t.IsStruct() {
+	if isStructNotSIMD(t) {
 		for j := 0; j < i; j++ {
 			rc.next(t.FieldType(j))
 		}
@@ -973,7 +982,7 @@ func (x *expandState) regOffset(t *types.Type, i int) Abi1RO {
 	if t.IsArray() {
 		return Abi1RO(i) * x.regWidth(t.Elem())
 	}
-	if t.IsStruct() {
+	if isStructNotSIMD(t) {
 		k := Abi1RO(0)
 		for j := 0; j < i; j++ {
 			k += x.regWidth(t.FieldType(j))
diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 5d13f81841482d..29058f0b193bc0 100644
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -1162,6 +1162,1021 @@ const (
 	OpAMD64PSIGNB
 	OpAMD64PCMPEQB
 	OpAMD64PMOVMSKB
+	OpAMD64VPADDD4
+	OpAMD64VMOVDQUload128
+	OpAMD64VMOVDQUstore128
+	OpAMD64VMOVDQUload256
+	OpAMD64VMOVDQUstore256
+	OpAMD64VMOVDQUload512
+	OpAMD64VMOVDQUstore512
+	OpAMD64VPMOVMToVec8x16
+	OpAMD64VPMOVMToVec8x32
+	OpAMD64VPMOVMToVec8x64
+	OpAMD64VPMOVMToVec16x8
+	OpAMD64VPMOVMToVec16x16
+	OpAMD64VPMOVMToVec16x32
+	OpAMD64VPMOVMToVec32x4
+	OpAMD64VPMOVMToVec32x8
+	OpAMD64VPMOVMToVec32x16
+	OpAMD64VPMOVMToVec64x2
+	OpAMD64VPMOVMToVec64x4
+	OpAMD64VPMOVMToVec64x8
+	OpAMD64VPMOVVec8x16ToM
+	OpAMD64VPMOVVec8x32ToM
+	OpAMD64VPMOVVec8x64ToM
+	OpAMD64VPMOVVec16x8ToM
+	OpAMD64VPMOVVec16x16ToM
+	OpAMD64VPMOVVec16x32ToM
+	OpAMD64VPMOVVec32x4ToM
+	OpAMD64VPMOVVec32x8ToM
+	OpAMD64VPMOVVec32x16ToM
+	OpAMD64VPMOVVec64x2ToM
+	OpAMD64VPMOVVec64x4ToM
+	OpAMD64VPMOVVec64x8ToM
+	OpAMD64Zero128
+	OpAMD64Zero256
+	OpAMD64Zero512
+	OpAMD64VZEROUPPER
+	OpAMD64VZEROALL
+	OpAMD64VADDPS512
+	OpAMD64VADDPSMasked512
+	OpAMD64VRCP14PS512
+	OpAMD64VRCP14PSMasked512
+	OpAMD64VRSQRT14PS512
+	OpAMD64VRSQRT14PSMasked512
+	OpAMD64VCOMPRESSPSMasked512
+	OpAMD64VDIVPS512
+	OpAMD64VDIVPSMasked512
+	OpAMD64VFMADD213PS512
+	OpAMD64VFMADD213PSMasked512
+	OpAMD64VFMADDSUB213PS512
+	OpAMD64VFMADDSUB213PSMasked512
+	OpAMD64VFMSUBADD213PS512
+	OpAMD64VFMSUBADD213PSMasked512
+	OpAMD64VMAXPS512
+	OpAMD64VMAXPSMasked512
+	OpAMD64VMINPS512
+	OpAMD64VMINPSMasked512
+	OpAMD64VMULPS512
+	OpAMD64VSCALEFPS512
+	OpAMD64VSCALEFPSMasked512
+	OpAMD64VMULPSMasked512
+	OpAMD64VSQRTPS512
+	OpAMD64VSQRTPSMasked512
+	OpAMD64VSUBPS512
+	OpAMD64VSUBPSMasked512
+	OpAMD64VADDPS128
+	OpAMD64VADDPSMasked128
+	OpAMD64VADDSUBPS128
+	OpAMD64VRCP14PS128
+	OpAMD64VRCP14PSMasked128
+	OpAMD64VRSQRTPS128
+	OpAMD64VRSQRT14PSMasked128
+	OpAMD64VCOMPRESSPSMasked128
+	OpAMD64VDIVPS128
+	OpAMD64VDIVPSMasked128
+	OpAMD64VFMADD213PS128
+	OpAMD64VFMADD213PSMasked128
+	OpAMD64VFMADDSUB213PS128
+	OpAMD64VFMADDSUB213PSMasked128
+	OpAMD64VFMSUBADD213PS128
+	OpAMD64VFMSUBADD213PSMasked128
+	OpAMD64VMAXPS128
+	OpAMD64VMAXPSMasked128
+	OpAMD64VMINPS128
+	OpAMD64VMINPSMasked128
+	OpAMD64VMULPS128
+	OpAMD64VSCALEFPS128
+	OpAMD64VSCALEFPSMasked128
+	OpAMD64VMULPSMasked128
+	OpAMD64VHADDPS128
+	OpAMD64VHSUBPS128
+	OpAMD64VSQRTPS128
+	OpAMD64VSQRTPSMasked128
+	OpAMD64VSUBPS128
+	OpAMD64VSUBPSMasked128
+	OpAMD64VADDPS256
+	OpAMD64VADDPSMasked256
+	OpAMD64VADDSUBPS256
+	OpAMD64VRCP14PS256
+	OpAMD64VRCP14PSMasked256
+	OpAMD64VRSQRTPS256
+	OpAMD64VRSQRT14PSMasked256
+	OpAMD64VCOMPRESSPSMasked256
+	OpAMD64VDIVPS256
+	OpAMD64VDIVPSMasked256
+	OpAMD64VFMADD213PS256
+	OpAMD64VFMADD213PSMasked256
+	OpAMD64VFMADDSUB213PS256
+	OpAMD64VFMADDSUB213PSMasked256
+	OpAMD64VFMSUBADD213PS256
+	OpAMD64VFMSUBADD213PSMasked256
+	OpAMD64VMAXPS256
+	OpAMD64VMAXPSMasked256
+	OpAMD64VMINPS256
+	OpAMD64VMINPSMasked256
+	OpAMD64VMULPS256
+	OpAMD64VSCALEFPS256
+	OpAMD64VSCALEFPSMasked256
+	OpAMD64VMULPSMasked256
+	OpAMD64VHADDPS256
+	OpAMD64VHSUBPS256
+	OpAMD64VSQRTPS256
+	OpAMD64VSQRTPSMasked256
+	OpAMD64VSUBPS256
+	OpAMD64VSUBPSMasked256
+	OpAMD64VADDPD128
+	OpAMD64VADDPDMasked128
+	OpAMD64VADDSUBPD128
+	OpAMD64VRCP14PD128
+	OpAMD64VRCP14PDMasked128
+	OpAMD64VRSQRT14PD128
+	OpAMD64VRSQRT14PDMasked128
+	OpAMD64VCOMPRESSPDMasked128
+	OpAMD64VDIVPD128
+	OpAMD64VDIVPDMasked128
+	OpAMD64VFMADD213PD128
+	OpAMD64VFMADD213PDMasked128
+	OpAMD64VFMADDSUB213PD128
+	OpAMD64VFMADDSUB213PDMasked128
+	OpAMD64VFMSUBADD213PD128
+	OpAMD64VFMSUBADD213PDMasked128
+	OpAMD64VMAXPD128
+	OpAMD64VMAXPDMasked128
+	OpAMD64VMINPD128
+	OpAMD64VMINPDMasked128
+	OpAMD64VMULPD128
+	OpAMD64VSCALEFPD128
+	OpAMD64VSCALEFPDMasked128
+	OpAMD64VMULPDMasked128
+	OpAMD64VHADDPD128
+	OpAMD64VHSUBPD128
+	OpAMD64VSQRTPD128
+	OpAMD64VSQRTPDMasked128
+	OpAMD64VSUBPD128
+	OpAMD64VSUBPDMasked128
+	OpAMD64VADDPD256
+	OpAMD64VADDPDMasked256
+	OpAMD64VADDSUBPD256
+	OpAMD64VRCP14PD256
+	OpAMD64VRCP14PDMasked256
+	OpAMD64VRSQRT14PD256
+	OpAMD64VRSQRT14PDMasked256
+	OpAMD64VCOMPRESSPDMasked256
+	OpAMD64VDIVPD256
+	OpAMD64VDIVPDMasked256
+	OpAMD64VFMADD213PD256
+	OpAMD64VFMADD213PDMasked256
+	OpAMD64VFMADDSUB213PD256
+	OpAMD64VFMADDSUB213PDMasked256
+	OpAMD64VFMSUBADD213PD256
+	OpAMD64VFMSUBADD213PDMasked256
+	OpAMD64VMAXPD256
+	OpAMD64VMAXPDMasked256
+	OpAMD64VMINPD256
+	OpAMD64VMINPDMasked256
+	OpAMD64VMULPD256
+	OpAMD64VSCALEFPD256
+	OpAMD64VSCALEFPDMasked256
+	OpAMD64VMULPDMasked256
+	OpAMD64VHADDPD256
+	OpAMD64VHSUBPD256
+	OpAMD64VSQRTPD256
+	OpAMD64VSQRTPDMasked256
+	OpAMD64VSUBPD256
+	OpAMD64VSUBPDMasked256
+	OpAMD64VADDPD512
+	OpAMD64VADDPDMasked512
+	OpAMD64VRCP14PD512
+	OpAMD64VRCP14PDMasked512
+	OpAMD64VRSQRT14PD512
+	OpAMD64VRSQRT14PDMasked512
+	OpAMD64VCOMPRESSPDMasked512
+	OpAMD64VDIVPD512
+	OpAMD64VDIVPDMasked512
+	OpAMD64VFMADD213PD512
+	OpAMD64VFMADD213PDMasked512
+	OpAMD64VFMADDSUB213PD512
+	OpAMD64VFMADDSUB213PDMasked512
+	OpAMD64VFMSUBADD213PD512
+	OpAMD64VFMSUBADD213PDMasked512
+	OpAMD64VMAXPD512
+	OpAMD64VMAXPDMasked512
+	OpAMD64VMINPD512
+	OpAMD64VMINPDMasked512
+	OpAMD64VMULPD512
+	OpAMD64VSCALEFPD512
+	OpAMD64VSCALEFPDMasked512
+	OpAMD64VMULPDMasked512
+	OpAMD64VSQRTPD512
+	OpAMD64VSQRTPDMasked512
+	OpAMD64VSUBPD512
+	OpAMD64VSUBPDMasked512
+	OpAMD64VPABSW256
+	OpAMD64VPABSWMasked256
+	OpAMD64VPADDW256
+	OpAMD64VPADDWMasked256
+	OpAMD64VPCOMPRESSWMasked256
+	OpAMD64VPCMPEQW256
+	OpAMD64VPCMPGTW256
+	OpAMD64VPMAXSW256
+	OpAMD64VPMAXSWMasked256
+	OpAMD64VPMINSW256
+	OpAMD64VPMINSWMasked256
+	OpAMD64VPMULHW256
+	OpAMD64VPMULHWMasked256
+	OpAMD64VPMULLW256
+	OpAMD64VPMULLWMasked256
+	OpAMD64VPMADDWD256
+	OpAMD64VPMADDWDMasked256
+	OpAMD64VPHADDW256
+	OpAMD64VPHSUBW256
+	OpAMD64VPOPCNTW256
+	OpAMD64VPOPCNTWMasked256
+	OpAMD64VPADDSW256
+	OpAMD64VPADDSWMasked256
+	OpAMD64VPHADDSW256
+	OpAMD64VPHSUBSW256
+	OpAMD64VPSUBSW256
+	OpAMD64VPSUBSWMasked256
+	OpAMD64VPSLLW256
+	OpAMD64VPSLLWMasked256
+	OpAMD64VPSRAW256
+	OpAMD64VPSRAWMasked256
+	OpAMD64VPSLLVW256
+	OpAMD64VPSHLDVW256
+	OpAMD64VPSHLDVWMasked256
+	OpAMD64VPSLLVWMasked256
+	OpAMD64VPSRAVW256
+	OpAMD64VPSHRDVW256
+	OpAMD64VPSHRDVWMasked256
+	OpAMD64VPSRAVWMasked256
+	OpAMD64VPSIGNW256
+	OpAMD64VPSUBW256
+	OpAMD64VPSUBWMasked256
+	OpAMD64VPABSW512
+	OpAMD64VPABSWMasked512
+	OpAMD64VPADDW512
+	OpAMD64VPADDWMasked512
+	OpAMD64VPCOMPRESSWMasked512
+	OpAMD64VPMAXSW512
+	OpAMD64VPMAXSWMasked512
+	OpAMD64VPMINSW512
+	OpAMD64VPMINSWMasked512
+	OpAMD64VPMULHW512
+	OpAMD64VPMULHWMasked512
+	OpAMD64VPMULLW512
+	OpAMD64VPMULLWMasked512
+	OpAMD64VPMADDWD512
+	OpAMD64VPMADDWDMasked512
+	OpAMD64VPOPCNTW512
+	OpAMD64VPOPCNTWMasked512
+	OpAMD64VPADDSW512
+	OpAMD64VPADDSWMasked512
+	OpAMD64VPSUBSW512
+	OpAMD64VPSUBSWMasked512
+	OpAMD64VPSLLW512
+	OpAMD64VPSLLWMasked512
+	OpAMD64VPSRAW512
+	OpAMD64VPSRAWMasked512
+	OpAMD64VPSLLVW512
+	OpAMD64VPSHLDVW512
+	OpAMD64VPSHLDVWMasked512
+	OpAMD64VPSLLVWMasked512
+	OpAMD64VPSRAVW512
+	OpAMD64VPSHRDVW512
+	OpAMD64VPSHRDVWMasked512
+	OpAMD64VPSRAVWMasked512
+	OpAMD64VPSUBW512
+	OpAMD64VPSUBWMasked512
+	OpAMD64VPABSW128
+	OpAMD64VPABSWMasked128
+	OpAMD64VPADDW128
+	OpAMD64VPADDWMasked128
+	OpAMD64VPCOMPRESSWMasked128
+	OpAMD64VPCMPEQW128
+	OpAMD64VPCMPGTW128
+	OpAMD64VPMAXSW128
+	OpAMD64VPMAXSWMasked128
+	OpAMD64VPMINSW128
+	OpAMD64VPMINSWMasked128
+	OpAMD64VPMULHW128
+	OpAMD64VPMULHWMasked128
+	OpAMD64VPMULLW128
+	OpAMD64VPMULLWMasked128
+	OpAMD64VPMADDWD128
+	OpAMD64VPMADDWDMasked128
+	OpAMD64VPHADDW128
+	OpAMD64VPHSUBW128
+	OpAMD64VPOPCNTW128
+	OpAMD64VPOPCNTWMasked128
+	OpAMD64VPADDSW128
+	OpAMD64VPADDSWMasked128
+	OpAMD64VPHADDSW128
+	OpAMD64VPHSUBSW128
+	OpAMD64VPSUBSW128
+	OpAMD64VPSUBSWMasked128
+	OpAMD64VPSLLW128
+	OpAMD64VPSLLWMasked128
+	OpAMD64VPSRAW128
+	OpAMD64VPSRAWMasked128
+	OpAMD64VPSLLVW128
+	OpAMD64VPSHLDVW128
+	OpAMD64VPSHLDVWMasked128
+	OpAMD64VPSLLVWMasked128
+	OpAMD64VPSRAVW128
+	OpAMD64VPSHRDVW128
+	OpAMD64VPSHRDVWMasked128
+	OpAMD64VPSRAVWMasked128
+	OpAMD64VPSIGNW128
+	OpAMD64VPSUBW128
+	OpAMD64VPSUBWMasked128
+	OpAMD64VPABSD512
+	OpAMD64VPABSDMasked512
+	OpAMD64VPADDD512
+	OpAMD64VPADDDMasked512
+	OpAMD64VPANDD512
+	OpAMD64VPANDDMasked512
+	OpAMD64VPANDND512
+	OpAMD64VPANDNDMasked512
+	OpAMD64VPCOMPRESSDMasked512
+	OpAMD64VPMAXSD512
+	OpAMD64VPMAXSDMasked512
+	OpAMD64VPMINSD512
+	OpAMD64VPMINSDMasked512
+	OpAMD64VPMULLD512
+	OpAMD64VPMULLDMasked512
+	OpAMD64VPORD512
+	OpAMD64VPORDMasked512
+	OpAMD64VPDPWSSD512
+	OpAMD64VPDPWSSDMasked512
+	OpAMD64VPOPCNTD512
+	OpAMD64VPOPCNTDMasked512
+	OpAMD64VPROLVD512
+	OpAMD64VPROLVDMasked512
+	OpAMD64VPRORVD512
+	OpAMD64VPRORVDMasked512
+	OpAMD64VPDPWSSDS512
+	OpAMD64VPDPWSSDSMasked512
+	OpAMD64VPDPBUSDS512
+	OpAMD64VPDPBUSDSMasked512
+	OpAMD64VPSLLD512
+	OpAMD64VPSLLDMasked512
+	OpAMD64VPSRAD512
+	OpAMD64VPSRADMasked512
+	OpAMD64VPSLLVD512
+	OpAMD64VPSHLDVD512
+	OpAMD64VPSHLDVDMasked512
+	OpAMD64VPSLLVDMasked512
+	OpAMD64VPSRAVD512
+	OpAMD64VPSHRDVD512
+	OpAMD64VPSHRDVDMasked512
+	OpAMD64VPSRAVDMasked512
+	OpAMD64VPSUBD512
+	OpAMD64VPSUBDMasked512
+	OpAMD64VPDPBUSD512
+	OpAMD64VPDPBUSDMasked512
+	OpAMD64VPXORD512
+	OpAMD64VPXORDMasked512
+	OpAMD64VPABSD128
+	OpAMD64VPABSDMasked128
+	OpAMD64VPADDD128
+	OpAMD64VPADDDMasked128
+	OpAMD64VPANDDMasked128
+	OpAMD64VPANDNDMasked128
+	OpAMD64VPCOMPRESSDMasked128
+	OpAMD64VPCMPEQD128
+	OpAMD64VPCMPGTD128
+	OpAMD64VPMAXSD128
+	OpAMD64VPMAXSDMasked128
+	OpAMD64VPMINSD128
+	OpAMD64VPMINSDMasked128
+	OpAMD64VPMULDQ128
+	OpAMD64VPMULLD128
+	OpAMD64VPMULLDMasked128
+	OpAMD64VPORDMasked128
+	OpAMD64VPDPWSSD128
+	OpAMD64VPDPWSSDMasked128
+	OpAMD64VPHADDD128
+	OpAMD64VPHSUBD128
+	OpAMD64VPOPCNTD128
+	OpAMD64VPOPCNTDMasked128
+	OpAMD64VPROLVD128
+	OpAMD64VPROLVDMasked128
+	OpAMD64VPRORVD128
+	OpAMD64VPRORVDMasked128
+	OpAMD64VPDPWSSDS128
+	OpAMD64VPDPWSSDSMasked128
+	OpAMD64VPDPBUSDS128
+	OpAMD64VPDPBUSDSMasked128
+	OpAMD64VPSLLD128
+	OpAMD64VPSLLDMasked128
+	OpAMD64VPSRAD128
+	OpAMD64VPSRADMasked128
+	OpAMD64VPSLLVD128
+	OpAMD64VPSHLDVD128
+	OpAMD64VPSHLDVDMasked128
+	OpAMD64VPSLLVDMasked128
+	OpAMD64VPSRAVD128
+	OpAMD64VPSHRDVD128
+	OpAMD64VPSHRDVDMasked128
+	OpAMD64VPSRAVDMasked128
+	OpAMD64VPSIGND128
+	OpAMD64VPSUBD128
+	OpAMD64VPSUBDMasked128
+	OpAMD64VPDPBUSD128
+	OpAMD64VPDPBUSDMasked128
+	OpAMD64VPXORDMasked128
+	OpAMD64VPABSD256
+	OpAMD64VPABSDMasked256
+	OpAMD64VPADDD256
+	OpAMD64VPADDDMasked256
+	OpAMD64VPANDDMasked256
+	OpAMD64VPANDNDMasked256
+	OpAMD64VPCOMPRESSDMasked256
+	OpAMD64VPCMPEQD256
+	OpAMD64VPCMPGTD256
+	OpAMD64VPMAXSD256
+	OpAMD64VPMAXSDMasked256
+	OpAMD64VPMINSD256
+	OpAMD64VPMINSDMasked256
+	OpAMD64VPMULDQ256
+	OpAMD64VPMULLD256
+	OpAMD64VPMULLDMasked256
+	OpAMD64VPORDMasked256
+	OpAMD64VPDPWSSD256
+	OpAMD64VPDPWSSDMasked256
+	OpAMD64VPHADDD256
+	OpAMD64VPHSUBD256
+	OpAMD64VPOPCNTD256
+	OpAMD64VPOPCNTDMasked256
+	OpAMD64VPROLVD256
+	OpAMD64VPROLVDMasked256
+	OpAMD64VPRORVD256
+	OpAMD64VPRORVDMasked256
+	OpAMD64VPDPWSSDS256
+	OpAMD64VPDPWSSDSMasked256
+	OpAMD64VPDPBUSDS256
+	OpAMD64VPDPBUSDSMasked256
+	OpAMD64VPSLLD256
+	OpAMD64VPSLLDMasked256
+	OpAMD64VPSRAD256
+	OpAMD64VPSRADMasked256
+	OpAMD64VPSLLVD256
+	OpAMD64VPSHLDVD256
+	OpAMD64VPSHLDVDMasked256
+	OpAMD64VPSLLVDMasked256
+	OpAMD64VPSRAVD256
+	OpAMD64VPSHRDVD256
+	OpAMD64VPSHRDVDMasked256
+	OpAMD64VPSRAVDMasked256
+	OpAMD64VPSIGND256
+	OpAMD64VPSUBD256
+	OpAMD64VPSUBDMasked256
+	OpAMD64VPDPBUSD256
+	OpAMD64VPDPBUSDMasked256
+	OpAMD64VPXORDMasked256
+	OpAMD64VPABSQ128
+	OpAMD64VPABSQMasked128
+	OpAMD64VPADDQ128
+	OpAMD64VPADDQMasked128
+	OpAMD64VPANDQMasked128
+	OpAMD64VPANDNQMasked128
+	OpAMD64VPCOMPRESSQMasked128
+	OpAMD64VPCMPEQQ128
+	OpAMD64VPCMPGTQ128
+	OpAMD64VPMAXSQ128
+	OpAMD64VPMAXSQMasked128
+	OpAMD64VPMINSQ128
+	OpAMD64VPMINSQMasked128
+	OpAMD64VPMULDQMasked128
+	OpAMD64VPMULLQ128
+	OpAMD64VPMULLQMasked128
+	OpAMD64VPORQMasked128
+	OpAMD64VPOPCNTQ128
+	OpAMD64VPOPCNTQMasked128
+	OpAMD64VPROLVQ128
+	OpAMD64VPROLVQMasked128
+	OpAMD64VPRORVQ128
+	OpAMD64VPRORVQMasked128
+	OpAMD64VPSLLQ128
+	OpAMD64VPSLLQMasked128
+	OpAMD64VPSRAQ128
+	OpAMD64VPSRAQMasked128
+	OpAMD64VPSLLVQ128
+	OpAMD64VPSHLDVQ128
+	OpAMD64VPSHLDVQMasked128
+	OpAMD64VPSLLVQMasked128
+	OpAMD64VPSRAVQ128
+	OpAMD64VPSHRDVQ128
+	OpAMD64VPSHRDVQMasked128
+	OpAMD64VPSRAVQMasked128
+	OpAMD64VPSUBQ128
+	OpAMD64VPSUBQMasked128
+	OpAMD64VPXORQMasked128
+	OpAMD64VPABSQ256
+	OpAMD64VPABSQMasked256
+	OpAMD64VPADDQ256
+	OpAMD64VPADDQMasked256
+	OpAMD64VPANDQMasked256
+	OpAMD64VPANDNQMasked256
+	OpAMD64VPCOMPRESSQMasked256
+	OpAMD64VPCMPEQQ256
+	OpAMD64VPCMPGTQ256
+	OpAMD64VPMAXSQ256
+	OpAMD64VPMAXSQMasked256
+	OpAMD64VPMINSQ256
+	OpAMD64VPMINSQMasked256
+	OpAMD64VPMULDQMasked256
+	OpAMD64VPMULLQ256
+	OpAMD64VPMULLQMasked256
+	OpAMD64VPORQMasked256
+	OpAMD64VPOPCNTQ256
+	OpAMD64VPOPCNTQMasked256
+	OpAMD64VPROLVQ256
+	OpAMD64VPROLVQMasked256
+	OpAMD64VPRORVQ256
+	OpAMD64VPRORVQMasked256
+	OpAMD64VPSLLQ256
+	OpAMD64VPSLLQMasked256
+	OpAMD64VPSRAQ256
+	OpAMD64VPSRAQMasked256
+	OpAMD64VPSLLVQ256
+	OpAMD64VPSHLDVQ256
+	OpAMD64VPSHLDVQMasked256
+	OpAMD64VPSLLVQMasked256
+	OpAMD64VPSRAVQ256
+	OpAMD64VPSHRDVQ256
+	OpAMD64VPSHRDVQMasked256
+	OpAMD64VPSRAVQMasked256
+	OpAMD64VPSUBQ256
+	OpAMD64VPSUBQMasked256
+	OpAMD64VPXORQMasked256
+	OpAMD64VPABSQ512
+	OpAMD64VPABSQMasked512
+	OpAMD64VPADDQ512
+	OpAMD64VPADDQMasked512
+	OpAMD64VPANDQ512
+	OpAMD64VPANDQMasked512
+	OpAMD64VPANDNQ512
+	OpAMD64VPANDNQMasked512
+	OpAMD64VPCOMPRESSQMasked512
+	OpAMD64VPMAXSQ512
+	OpAMD64VPMAXSQMasked512
+	OpAMD64VPMINSQ512
+	OpAMD64VPMINSQMasked512
+	OpAMD64VPMULDQ512
+	OpAMD64VPMULDQMasked512
+	OpAMD64VPMULLQ512
+	OpAMD64VPMULLQMasked512
+	OpAMD64VPORQ512
+	OpAMD64VPORQMasked512
+	OpAMD64VPOPCNTQ512
+	OpAMD64VPOPCNTQMasked512
+	OpAMD64VPROLVQ512
+	OpAMD64VPROLVQMasked512
+	OpAMD64VPRORVQ512
+	OpAMD64VPRORVQMasked512
+	OpAMD64VPSLLQ512
+	OpAMD64VPSLLQMasked512
+	OpAMD64VPSRAQ512
+	OpAMD64VPSRAQMasked512
+	OpAMD64VPSLLVQ512
+	OpAMD64VPSHLDVQ512
+	OpAMD64VPSHLDVQMasked512
+	OpAMD64VPSLLVQMasked512
+	OpAMD64VPSRAVQ512
+	OpAMD64VPSHRDVQ512
+	OpAMD64VPSHRDVQMasked512
+	OpAMD64VPSRAVQMasked512
+	OpAMD64VPSUBQ512
+	OpAMD64VPSUBQMasked512
+	OpAMD64VPXORQ512
+	OpAMD64VPXORQMasked512
+	OpAMD64VPABSB128
+	OpAMD64VPABSBMasked128
+	OpAMD64VPADDB128
+	OpAMD64VPADDBMasked128
+	OpAMD64VPAND128
+	OpAMD64VPANDN128
+	OpAMD64VPCOMPRESSBMasked128
+	OpAMD64VPCMPEQB128
+	OpAMD64VPCMPGTB128
+	OpAMD64VPMAXSB128
+	OpAMD64VPMAXSBMasked128
+	OpAMD64VPMINSB128
+	OpAMD64VPMINSBMasked128
+	OpAMD64VPOR128
+	OpAMD64VPOPCNTB128
+	OpAMD64VPOPCNTBMasked128
+	OpAMD64VPADDSB128
+	OpAMD64VPADDSBMasked128
+	OpAMD64VPSUBSB128
+	OpAMD64VPSUBSBMasked128
+	OpAMD64VPSIGNB128
+	OpAMD64VPSUBB128
+	OpAMD64VPSUBBMasked128
+	OpAMD64VPXOR128
+	OpAMD64VPABSB256
+	OpAMD64VPABSBMasked256
+	OpAMD64VPADDB256
+	OpAMD64VPADDBMasked256
+	OpAMD64VPAND256
+	OpAMD64VPANDN256
+	OpAMD64VPCOMPRESSBMasked256
+	OpAMD64VPCMPEQB256
+	OpAMD64VPCMPGTB256
+	OpAMD64VPMAXSB256
+	OpAMD64VPMAXSBMasked256
+	OpAMD64VPMINSB256
+	OpAMD64VPMINSBMasked256
+	OpAMD64VPOR256
+	OpAMD64VPOPCNTB256
+	OpAMD64VPOPCNTBMasked256
+	OpAMD64VPADDSB256
+	OpAMD64VPADDSBMasked256
+	OpAMD64VPSUBSB256
+	OpAMD64VPSUBSBMasked256
+	OpAMD64VPSIGNB256
+	OpAMD64VPSUBB256
+	OpAMD64VPSUBBMasked256
+	OpAMD64VPXOR256
+	OpAMD64VPABSB512
+	OpAMD64VPABSBMasked512
+	OpAMD64VPADDB512
+	OpAMD64VPADDBMasked512
+	OpAMD64VPCOMPRESSBMasked512
+	OpAMD64VPMAXSB512
+	OpAMD64VPMAXSBMasked512
+	OpAMD64VPMINSB512
+	OpAMD64VPMINSBMasked512
+	OpAMD64VPOPCNTB512
+	OpAMD64VPOPCNTBMasked512
+	OpAMD64VPADDSB512
+	OpAMD64VPADDSBMasked512
+	OpAMD64VPSUBSB512
+	OpAMD64VPSUBSBMasked512
+	OpAMD64VPSUBB512
+	OpAMD64VPSUBBMasked512
+	OpAMD64VPAVGW256
+	OpAMD64VPAVGWMasked256
+	OpAMD64VPMAXUW256
+	OpAMD64VPMAXUWMasked256
+	OpAMD64VPMINUW256
+	OpAMD64VPMINUWMasked256
+	OpAMD64VPMULHUW256
+	OpAMD64VPMULHUWMasked256
+	OpAMD64VPERMW256
+	OpAMD64VPERMI2W256
+	OpAMD64VPERMI2WMasked256
+	OpAMD64VPERMWMasked256
+	OpAMD64VPSRLW256
+	OpAMD64VPSRLWMasked256
+	OpAMD64VPSRLVW256
+	OpAMD64VPSRLVWMasked256
+	OpAMD64VPAVGW512
+	OpAMD64VPAVGWMasked512
+	OpAMD64VPMAXUW512
+	OpAMD64VPMAXUWMasked512
+	OpAMD64VPMINUW512
+	OpAMD64VPMINUWMasked512
+	OpAMD64VPMULHUW512
+	OpAMD64VPMULHUWMasked512
+	OpAMD64VPERMW512
+	OpAMD64VPERMI2W512
+	OpAMD64VPERMI2WMasked512
+	OpAMD64VPERMWMasked512
+	OpAMD64VPSRLW512
+	OpAMD64VPSRLWMasked512
+	OpAMD64VPSRLVW512
+	OpAMD64VPSRLVWMasked512
+	OpAMD64VPAVGW128
+	OpAMD64VPAVGWMasked128
+	OpAMD64VPMAXUW128
+	OpAMD64VPMAXUWMasked128
+	OpAMD64VPMINUW128
+	OpAMD64VPMINUWMasked128
+	OpAMD64VPMULHUW128
+	OpAMD64VPMULHUWMasked128
+	OpAMD64VPERMW128
+	OpAMD64VPERMI2W128
+	OpAMD64VPERMI2WMasked128
+	OpAMD64VPERMWMasked128
+	OpAMD64VPSRLW128
+	OpAMD64VPSRLWMasked128
+	OpAMD64VPSRLVW128
+	OpAMD64VPSRLVWMasked128
+	OpAMD64VPMAXUD512
+	OpAMD64VPMAXUDMasked512
+	OpAMD64VPMINUD512
+	OpAMD64VPMINUDMasked512
+	OpAMD64VPERMD512
+	OpAMD64VPERMPS512
+	OpAMD64VPERMI2PS512
+	OpAMD64VPERMI2D512
+	OpAMD64VPERMI2PSMasked512
+	OpAMD64VPERMI2DMasked512
+	OpAMD64VPERMPSMasked512
+	OpAMD64VPERMDMasked512
+	OpAMD64VPSRLD512
+	OpAMD64VPSRLDMasked512
+	OpAMD64VPSRLVD512
+	OpAMD64VPSRLVDMasked512
+	OpAMD64VPMAXUD128
+	OpAMD64VPMAXUDMasked128
+	OpAMD64VPMINUD128
+	OpAMD64VPMINUDMasked128
+	OpAMD64VPMULUDQ128
+	OpAMD64VPERMI2D128
+	OpAMD64VPERMI2PS128
+	OpAMD64VPERMI2PSMasked128
+	OpAMD64VPERMI2DMasked128
+	OpAMD64VPSRLD128
+	OpAMD64VPSRLDMasked128
+	OpAMD64VPSRLVD128
+	OpAMD64VPSRLVDMasked128
+	OpAMD64VPMAXUD256
+	OpAMD64VPMAXUDMasked256
+	OpAMD64VPMINUD256
+	OpAMD64VPMINUDMasked256
+	OpAMD64VPMULUDQ256
+	OpAMD64VPERMPS256
+	OpAMD64VPERMD256
+	OpAMD64VPERMI2D256
+	OpAMD64VPERMI2PS256
+	OpAMD64VPERMI2DMasked256
+	OpAMD64VPERMI2PSMasked256
+	OpAMD64VPERMPSMasked256
+	OpAMD64VPERMDMasked256
+	OpAMD64VPSRLD256
+	OpAMD64VPSRLDMasked256
+	OpAMD64VPSRLVD256
+	OpAMD64VPSRLVDMasked256
+	OpAMD64VPMAXUQ128
+	OpAMD64VPMAXUQMasked128
+	OpAMD64VPMINUQ128
+	OpAMD64VPMINUQMasked128
+	OpAMD64VPMULUDQMasked128
+	OpAMD64VPERMI2PD128
+	OpAMD64VPERMI2Q128
+	OpAMD64VPERMI2PDMasked128
+	OpAMD64VPERMI2QMasked128
+	OpAMD64VPSRLQ128
+	OpAMD64VPSRLQMasked128
+	OpAMD64VPSRLVQ128
+	OpAMD64VPSRLVQMasked128
+	OpAMD64VPMAXUQ256
+	OpAMD64VPMAXUQMasked256
+	OpAMD64VPMINUQ256
+	OpAMD64VPMINUQMasked256
+	OpAMD64VPMULUDQMasked256
+	OpAMD64VPERMQ256
+	OpAMD64VPERMPD256
+	OpAMD64VPERMI2Q256
+	OpAMD64VPERMI2PD256
+	OpAMD64VPERMI2PDMasked256
+	OpAMD64VPERMI2QMasked256
+	OpAMD64VPERMQMasked256
+	OpAMD64VPERMPDMasked256
+	OpAMD64VPSRLQ256
+	OpAMD64VPSRLQMasked256
+	OpAMD64VPSRLVQ256
+	OpAMD64VPSRLVQMasked256
+	OpAMD64VPMAXUQ512
+	OpAMD64VPMAXUQMasked512
+	OpAMD64VPMINUQ512
+	OpAMD64VPMINUQMasked512
+	OpAMD64VPMULUDQ512
+	OpAMD64VPMULUDQMasked512
+	OpAMD64VPERMPD512
+	OpAMD64VPERMQ512
+	OpAMD64VPERMI2Q512
+	OpAMD64VPERMI2PD512
+	OpAMD64VPERMI2QMasked512
+	OpAMD64VPERMI2PDMasked512
+	OpAMD64VPERMQMasked512
+	OpAMD64VPERMPDMasked512
+	OpAMD64VPSRLQ512
+	OpAMD64VPSRLQMasked512
+	OpAMD64VPSRLVQ512
+	OpAMD64VPSRLVQMasked512
+	OpAMD64VPAVGB128
+	OpAMD64VPAVGBMasked128
+	OpAMD64VGF2P8MULB128
+	OpAMD64VGF2P8MULBMasked128
+	OpAMD64VPMAXUB128
+	OpAMD64VPMAXUBMasked128
+	OpAMD64VPMINUB128
+	OpAMD64VPMINUBMasked128
+	OpAMD64VPERMB128
+	OpAMD64VPERMI2B128
+	OpAMD64VPERMI2BMasked128
+	OpAMD64VPERMBMasked128
+	OpAMD64VPMADDUBSW128
+	OpAMD64VPMADDUBSWMasked128
+	OpAMD64VPAVGB256
+	OpAMD64VPAVGBMasked256
+	OpAMD64VGF2P8MULB256
+	OpAMD64VGF2P8MULBMasked256
+	OpAMD64VPMAXUB256
+	OpAMD64VPMAXUBMasked256
+	OpAMD64VPMINUB256
+	OpAMD64VPMINUBMasked256
+	OpAMD64VPERMB256
+	OpAMD64VPERMI2B256
+	OpAMD64VPERMI2BMasked256
+	OpAMD64VPERMBMasked256
+	OpAMD64VPMADDUBSW256
+	OpAMD64VPMADDUBSWMasked256
+	OpAMD64VPAVGB512
+	OpAMD64VPAVGBMasked512
+	OpAMD64VGF2P8MULB512
+	OpAMD64VGF2P8MULBMasked512
+	OpAMD64VPMAXUB512
+	OpAMD64VPMAXUBMasked512
+	OpAMD64VPMINUB512
+	OpAMD64VPMINUBMasked512
+	OpAMD64VPERMB512
+	OpAMD64VPERMI2B512
+	OpAMD64VPERMI2BMasked512
+	OpAMD64VPERMBMasked512
+	OpAMD64VPMADDUBSW512
+	OpAMD64VPMADDUBSWMasked512
+	OpAMD64VRNDSCALEPS512
+	OpAMD64VRNDSCALEPSMasked512
+	OpAMD64VREDUCEPS512
+	OpAMD64VREDUCEPSMasked512
+	OpAMD64VCMPPS512
+	OpAMD64VCMPPSMasked512
+	OpAMD64VROUNDPS128
+	OpAMD64VRNDSCALEPS128
+	OpAMD64VRNDSCALEPSMasked128
+	OpAMD64VREDUCEPS128
+	OpAMD64VREDUCEPSMasked128
+	OpAMD64VDPPS128
+	OpAMD64VCMPPS128
+	OpAMD64VCMPPSMasked128
+	OpAMD64VROUNDPS256
+	OpAMD64VRNDSCALEPS256
+	OpAMD64VRNDSCALEPSMasked256
+	OpAMD64VREDUCEPS256
+	OpAMD64VREDUCEPSMasked256
+	OpAMD64VDPPS256
+	OpAMD64VCMPPS256
+	OpAMD64VCMPPSMasked256
+	OpAMD64VEXTRACTF128128
+	OpAMD64VINSERTF128256
+	OpAMD64VROUNDPD128
+	OpAMD64VRNDSCALEPD128
+	OpAMD64VRNDSCALEPDMasked128
+	OpAMD64VREDUCEPD128
+	OpAMD64VREDUCEPDMasked128
+	OpAMD64VDPPD128
+	OpAMD64VCMPPD128
+	OpAMD64VCMPPDMasked128
+	OpAMD64VROUNDPD256
+	OpAMD64VRNDSCALEPD256
+	OpAMD64VRNDSCALEPDMasked256
+	OpAMD64VREDUCEPD256
+	OpAMD64VREDUCEPDMasked256
+	OpAMD64VCMPPD256
+	OpAMD64VCMPPDMasked256
+	OpAMD64VRNDSCALEPD512
+	OpAMD64VRNDSCALEPDMasked512
+	OpAMD64VREDUCEPD512
+	OpAMD64VREDUCEPDMasked512
+	OpAMD64VCMPPD512
+	OpAMD64VCMPPDMasked512
+	OpAMD64VPCMPWMasked256
+	OpAMD64VPCMPW256
+	OpAMD64VPSHLDW256
+	OpAMD64VPSHLDWMasked256
+	OpAMD64VPSHRDW256
+	OpAMD64VPSHRDWMasked256
+	OpAMD64VPCMPW512
+	OpAMD64VPCMPWMasked512
+	OpAMD64VPSHLDW512
+	OpAMD64VPSHLDWMasked512
+	OpAMD64VPSHRDW512
+	OpAMD64VPSHRDWMasked512
+	OpAMD64VPCMPWMasked128
+	OpAMD64VPEXTRW128
+	OpAMD64VPCMPW128
+	OpAMD64VPINSRW128
+	OpAMD64VPSHLDW128
+	OpAMD64VPSHLDWMasked128
+	OpAMD64VPSHRDW128
+	OpAMD64VPSHRDWMasked128
+	OpAMD64VPCMPD512
+	OpAMD64VPCMPDMasked512
+	OpAMD64VPROLD512
+	OpAMD64VPROLDMasked512
+	OpAMD64VPRORD512
+	OpAMD64VPRORDMasked512
+	OpAMD64VPSHLDD512
+	OpAMD64VPSHLDDMasked512
+	OpAMD64VPSHRDD512
+	OpAMD64VPSHRDDMasked512
+	OpAMD64VPCMPDMasked128
+	OpAMD64VPEXTRD128
+	OpAMD64VPCMPD128
+	OpAMD64VPROLD128
+	OpAMD64VPROLDMasked128
+	OpAMD64VPRORD128
+	OpAMD64VPRORDMasked128
+	OpAMD64VPINSRD128
+	OpAMD64VPSHLDD128
+	OpAMD64VPSHLDDMasked128
+	OpAMD64VPSHRDD128
+	OpAMD64VPSHRDDMasked128
+	OpAMD64VPCMPDMasked256
+	OpAMD64VPCMPD256
+	OpAMD64VPROLD256
+	OpAMD64VPROLDMasked256
+	OpAMD64VPRORD256
+	OpAMD64VPRORDMasked256
+	OpAMD64VPSHLDD256
+	OpAMD64VPSHLDDMasked256
+	OpAMD64VPSHRDD256
+	OpAMD64VPSHRDDMasked256
+	OpAMD64VPCMPQMasked128
+	OpAMD64VPEXTRQ128
+	OpAMD64VPCMPQ128
+	OpAMD64VPROLQ128
+	OpAMD64VPROLQMasked128
+	OpAMD64VPRORQ128
+	OpAMD64VPRORQMasked128
+	OpAMD64VPINSRQ128
+	OpAMD64VPSHLDQ128
+	OpAMD64VPSHLDQMasked128
+	OpAMD64VPSHRDQ128
+	OpAMD64VPSHRDQMasked128
+	OpAMD64VPCMPQMasked256
+	OpAMD64VPCMPQ256
+	OpAMD64VPROLQ256
+	OpAMD64VPROLQMasked256
+	OpAMD64VPRORQ256
+	OpAMD64VPRORQMasked256
+	OpAMD64VPSHLDQ256
+	OpAMD64VPSHLDQMasked256
+	OpAMD64VPSHRDQ256
+	OpAMD64VPSHRDQMasked256
+	OpAMD64VPCMPQ512
+	OpAMD64VPCMPQMasked512
+	OpAMD64VPROLQ512
+	OpAMD64VPROLQMasked512
+	OpAMD64VPRORQ512
+	OpAMD64VPRORQMasked512
+	OpAMD64VPSHLDQ512
+	OpAMD64VPSHLDQMasked512
+	OpAMD64VPSHRDQ512
+	OpAMD64VPSHRDQMasked512
+	OpAMD64VPCMPBMasked128
+	OpAMD64VPEXTRB128
+	OpAMD64VPCMPB128
+	OpAMD64VPINSRB128
+	OpAMD64VPCMPBMasked256
+	OpAMD64VEXTRACTI128128
+	OpAMD64VPCMPB256
+	OpAMD64VINSERTI128256
+	OpAMD64VPCMPB512
+	OpAMD64VPCMPBMasked512
+	OpAMD64VPCMPUWMasked256
+	OpAMD64VPCMPUW256
+	OpAMD64VPCMPUW512
+	OpAMD64VPCMPUWMasked512
+	OpAMD64VPCMPUWMasked128
+	OpAMD64VPCMPUW128
+	OpAMD64VPCMPUD512
+	OpAMD64VPCMPUDMasked512
+	OpAMD64VPCMPUDMasked128
+	OpAMD64VPCMPUD128
+	OpAMD64VPCMPUDMasked256
+	OpAMD64VPCMPUD256
+	OpAMD64VPCMPUQMasked128
+	OpAMD64VPCMPUQ128
+	OpAMD64VPCMPUQMasked256
+	OpAMD64VPCMPUQ256
+	OpAMD64VPCMPUQ512
+	OpAMD64VPCMPUQMasked512
+	OpAMD64VPCMPUBMasked128
+	OpAMD64VGF2P8AFFINEQB128
+	OpAMD64VGF2P8AFFINEINVQB128
+	OpAMD64VGF2P8AFFINEINVQBMasked128
+	OpAMD64VGF2P8AFFINEQBMasked128
+	OpAMD64VPCMPUB128
+	OpAMD64VPCMPUBMasked256
+	OpAMD64VGF2P8AFFINEQB256
+	OpAMD64VGF2P8AFFINEINVQB256
+	OpAMD64VGF2P8AFFINEINVQBMasked256
+	OpAMD64VGF2P8AFFINEQBMasked256
+	OpAMD64VPCMPUB256
+	OpAMD64VPCMPUB512
+	OpAMD64VPCMPUBMasked512
+	OpAMD64VGF2P8AFFINEQB512
+	OpAMD64VGF2P8AFFINEINVQB512
+	OpAMD64VGF2P8AFFINEINVQBMasked512
+	OpAMD64VGF2P8AFFINEQBMasked512
 
 	OpARMADD
 	OpARMADDconst
@@ -3386,6 +4401,1799 @@ const (
 	OpClobberReg
 	OpPrefetchCache
 	OpPrefetchCacheStreamed
+	OpAdd32x4
+	OpZeroSIMD
+	OpAddFloat32x16
+	OpAddMaskedFloat32x16
+	OpApproximateReciprocalFloat32x16
+	OpApproximateReciprocalMaskedFloat32x16
+	OpApproximateReciprocalOfSqrtFloat32x16
+	OpApproximateReciprocalOfSqrtMaskedFloat32x16
+	OpCompressFloat32x16
+	OpDivFloat32x16
+	OpDivMaskedFloat32x16
+	OpEqualFloat32x16
+	OpEqualMaskedFloat32x16
+	OpFusedMultiplyAddFloat32x16
+	OpFusedMultiplyAddMaskedFloat32x16
+	OpFusedMultiplyAddSubFloat32x16
+	OpFusedMultiplyAddSubMaskedFloat32x16
+	OpFusedMultiplySubAddFloat32x16
+	OpFusedMultiplySubAddMaskedFloat32x16
+	OpGreaterFloat32x16
+	OpGreaterEqualFloat32x16
+	OpGreaterEqualMaskedFloat32x16
+	OpGreaterMaskedFloat32x16
+	OpIsNanFloat32x16
+	OpIsNanMaskedFloat32x16
+	OpLessFloat32x16
+	OpLessEqualFloat32x16
+	OpLessEqualMaskedFloat32x16
+	OpLessMaskedFloat32x16
+	OpMaxFloat32x16
+	OpMaxMaskedFloat32x16
+	OpMinFloat32x16
+	OpMinMaskedFloat32x16
+	OpMulFloat32x16
+	OpMulByPowOf2Float32x16
+	OpMulByPowOf2MaskedFloat32x16
+	OpMulMaskedFloat32x16
+	OpNotEqualFloat32x16
+	OpNotEqualMaskedFloat32x16
+	OpSqrtFloat32x16
+	OpSqrtMaskedFloat32x16
+	OpSubFloat32x16
+	OpSubMaskedFloat32x16
+	OpAddFloat32x4
+	OpAddMaskedFloat32x4
+	OpAddSubFloat32x4
+	OpApproximateReciprocalFloat32x4
+	OpApproximateReciprocalMaskedFloat32x4
+	OpApproximateReciprocalOfSqrtFloat32x4
+	OpApproximateReciprocalOfSqrtMaskedFloat32x4
+	OpCeilFloat32x4
+	OpCompressFloat32x4
+	OpDivFloat32x4
+	OpDivMaskedFloat32x4
+	OpDotProdBroadcastFloat32x4
+	OpEqualFloat32x4
+	OpEqualMaskedFloat32x4
+	OpFloorFloat32x4
+	OpFusedMultiplyAddFloat32x4
+	OpFusedMultiplyAddMaskedFloat32x4
+	OpFusedMultiplyAddSubFloat32x4
+	OpFusedMultiplyAddSubMaskedFloat32x4
+	OpFusedMultiplySubAddFloat32x4
+	OpFusedMultiplySubAddMaskedFloat32x4
+	OpGreaterFloat32x4
+	OpGreaterEqualFloat32x4
+	OpGreaterEqualMaskedFloat32x4
+	OpGreaterMaskedFloat32x4
+	OpIsNanFloat32x4
+	OpIsNanMaskedFloat32x4
+	OpLessFloat32x4
+	OpLessEqualFloat32x4
+	OpLessEqualMaskedFloat32x4
+	OpLessMaskedFloat32x4
+	OpMaxFloat32x4
+	OpMaxMaskedFloat32x4
+	OpMinFloat32x4
+	OpMinMaskedFloat32x4
+	OpMulFloat32x4
+	OpMulByPowOf2Float32x4
+	OpMulByPowOf2MaskedFloat32x4
+	OpMulMaskedFloat32x4
+	OpNotEqualFloat32x4
+	OpNotEqualMaskedFloat32x4
+	OpPairwiseAddFloat32x4
+	OpPairwiseSubFloat32x4
+	OpRoundFloat32x4
+	OpSqrtFloat32x4
+	OpSqrtMaskedFloat32x4
+	OpSubFloat32x4
+	OpSubMaskedFloat32x4
+	OpTruncFloat32x4
+	OpAddFloat32x8
+	OpAddMaskedFloat32x8
+	OpAddSubFloat32x8
+	OpApproximateReciprocalFloat32x8
+	OpApproximateReciprocalMaskedFloat32x8
+	OpApproximateReciprocalOfSqrtFloat32x8
+	OpApproximateReciprocalOfSqrtMaskedFloat32x8
+	OpCeilFloat32x8
+	OpCompressFloat32x8
+	OpDivFloat32x8
+	OpDivMaskedFloat32x8
+	OpDotProdBroadcastFloat32x8
+	OpEqualFloat32x8
+	OpEqualMaskedFloat32x8
+	OpFloorFloat32x8
+	OpFusedMultiplyAddFloat32x8
+	OpFusedMultiplyAddMaskedFloat32x8
+	OpFusedMultiplyAddSubFloat32x8
+	OpFusedMultiplyAddSubMaskedFloat32x8
+	OpFusedMultiplySubAddFloat32x8
+	OpFusedMultiplySubAddMaskedFloat32x8
+	OpGreaterFloat32x8
+	OpGreaterEqualFloat32x8
+	OpGreaterEqualMaskedFloat32x8
+	OpGreaterMaskedFloat32x8
+	OpIsNanFloat32x8
+	OpIsNanMaskedFloat32x8
+	OpLessFloat32x8
+	OpLessEqualFloat32x8
+	OpLessEqualMaskedFloat32x8
+	OpLessMaskedFloat32x8
+	OpMaxFloat32x8
+	OpMaxMaskedFloat32x8
+	OpMinFloat32x8
+	OpMinMaskedFloat32x8
+	OpMulFloat32x8
+	OpMulByPowOf2Float32x8
+	OpMulByPowOf2MaskedFloat32x8
+	OpMulMaskedFloat32x8
+	OpNotEqualFloat32x8
+	OpNotEqualMaskedFloat32x8
+	OpPairwiseAddFloat32x8
+	OpPairwiseSubFloat32x8
+	OpRoundFloat32x8
+	OpSqrtFloat32x8
+	OpSqrtMaskedFloat32x8
+	OpSubFloat32x8
+	OpSubMaskedFloat32x8
+	OpTruncFloat32x8
+	OpAddFloat64x2
+	OpAddMaskedFloat64x2
+	OpAddSubFloat64x2
+	OpApproximateReciprocalFloat64x2
+	OpApproximateReciprocalMaskedFloat64x2
+	OpApproximateReciprocalOfSqrtFloat64x2
+	OpApproximateReciprocalOfSqrtMaskedFloat64x2
+	OpCeilFloat64x2
+	OpCompressFloat64x2
+	OpDivFloat64x2
+	OpDivMaskedFloat64x2
+	OpDotProdBroadcastFloat64x2
+	OpEqualFloat64x2
+	OpEqualMaskedFloat64x2
+	OpFloorFloat64x2
+	OpFusedMultiplyAddFloat64x2
+	OpFusedMultiplyAddMaskedFloat64x2
+	OpFusedMultiplyAddSubFloat64x2
+	OpFusedMultiplyAddSubMaskedFloat64x2
+	OpFusedMultiplySubAddFloat64x2
+	OpFusedMultiplySubAddMaskedFloat64x2
+	OpGreaterFloat64x2
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+	OpSubInt8x16
+	OpSubMaskedInt8x16
+	OpXorInt8x16
+	OpAbsoluteInt8x32
+	OpAbsoluteMaskedInt8x32
+	OpAddInt8x32
+	OpAddMaskedInt8x32
+	OpAndInt8x32
+	OpAndNotInt8x32
+	OpCompressInt8x32
+	OpEqualInt8x32
+	OpEqualMaskedInt8x32
+	OpGreaterInt8x32
+	OpGreaterEqualInt8x32
+	OpGreaterEqualMaskedInt8x32
+	OpGreaterMaskedInt8x32
+	OpLessInt8x32
+	OpLessEqualInt8x32
+	OpLessEqualMaskedInt8x32
+	OpLessMaskedInt8x32
+	OpMaxInt8x32
+	OpMaxMaskedInt8x32
+	OpMinInt8x32
+	OpMinMaskedInt8x32
+	OpNotEqualInt8x32
+	OpNotEqualMaskedInt8x32
+	OpOrInt8x32
+	OpPopCountInt8x32
+	OpPopCountMaskedInt8x32
+	OpSaturatedAddInt8x32
+	OpSaturatedAddMaskedInt8x32
+	OpSaturatedSubInt8x32
+	OpSaturatedSubMaskedInt8x32
+	OpSignInt8x32
+	OpSubInt8x32
+	OpSubMaskedInt8x32
+	OpXorInt8x32
+	OpAbsoluteInt8x64
+	OpAbsoluteMaskedInt8x64
+	OpAddInt8x64
+	OpAddMaskedInt8x64
+	OpCompressInt8x64
+	OpEqualInt8x64
+	OpEqualMaskedInt8x64
+	OpGreaterInt8x64
+	OpGreaterEqualInt8x64
+	OpGreaterEqualMaskedInt8x64
+	OpGreaterMaskedInt8x64
+	OpLessInt8x64
+	OpLessEqualInt8x64
+	OpLessEqualMaskedInt8x64
+	OpLessMaskedInt8x64
+	OpMaxInt8x64
+	OpMaxMaskedInt8x64
+	OpMinInt8x64
+	OpMinMaskedInt8x64
+	OpNotEqualInt8x64
+	OpNotEqualMaskedInt8x64
+	OpPopCountInt8x64
+	OpPopCountMaskedInt8x64
+	OpSaturatedAddInt8x64
+	OpSaturatedAddMaskedInt8x64
+	OpSaturatedSubInt8x64
+	OpSaturatedSubMaskedInt8x64
+	OpSubInt8x64
+	OpSubMaskedInt8x64
+	OpAddUint16x16
+	OpAddMaskedUint16x16
+	OpAndUint16x16
+	OpAndNotUint16x16
+	OpAverageUint16x16
+	OpAverageMaskedUint16x16
+	OpCompressUint16x16
+	OpEqualUint16x16
+	OpEqualMaskedUint16x16
+	OpGreaterUint16x16
+	OpGreaterEqualUint16x16
+	OpGreaterEqualMaskedUint16x16
+	OpGreaterMaskedUint16x16
+	OpLessUint16x16
+	OpLessEqualUint16x16
+	OpLessEqualMaskedUint16x16
+	OpLessMaskedUint16x16
+	OpMaxUint16x16
+	OpMaxMaskedUint16x16
+	OpMinUint16x16
+	OpMinMaskedUint16x16
+	OpMulHighUint16x16
+	OpMulHighMaskedUint16x16
+	OpNotEqualUint16x16
+	OpNotEqualMaskedUint16x16
+	OpOrUint16x16
+	OpPairwiseAddUint16x16
+	OpPairwiseSubUint16x16
+	OpPermuteInt16x16
+	OpPermuteUint16x16
+	OpPermute2Uint16x16
+	OpPermute2Int16x16
+	OpPermute2MaskedInt16x16
+	OpPermute2MaskedUint16x16
+	OpPermuteMaskedUint16x16
+	OpPermuteMaskedInt16x16
+	OpPopCountUint16x16
+	OpPopCountMaskedUint16x16
+	OpSaturatedAddUint16x16
+	OpSaturatedAddMaskedUint16x16
+	OpSaturatedSubUint16x16
+	OpSaturatedSubMaskedUint16x16
+	OpShiftAllLeftUint16x16
+	OpShiftAllLeftMaskedUint16x16
+	OpShiftAllRightUint16x16
+	OpShiftAllRightMaskedUint16x16
+	OpShiftLeftUint16x16
+	OpShiftLeftAndFillUpperFromUint16x16
+	OpShiftLeftAndFillUpperFromMaskedUint16x16
+	OpShiftLeftMaskedUint16x16
+	OpShiftRightUint16x16
+	OpShiftRightAndFillUpperFromUint16x16
+	OpShiftRightAndFillUpperFromMaskedUint16x16
+	OpShiftRightMaskedUint16x16
+	OpSubUint16x16
+	OpSubMaskedUint16x16
+	OpXorUint16x16
+	OpAddUint16x32
+	OpAddMaskedUint16x32
+	OpAverageUint16x32
+	OpAverageMaskedUint16x32
+	OpCompressUint16x32
+	OpEqualUint16x32
+	OpEqualMaskedUint16x32
+	OpGreaterUint16x32
+	OpGreaterEqualUint16x32
+	OpGreaterEqualMaskedUint16x32
+	OpGreaterMaskedUint16x32
+	OpLessUint16x32
+	OpLessEqualUint16x32
+	OpLessEqualMaskedUint16x32
+	OpLessMaskedUint16x32
+	OpMaxUint16x32
+	OpMaxMaskedUint16x32
+	OpMinUint16x32
+	OpMinMaskedUint16x32
+	OpMulHighUint16x32
+	OpMulHighMaskedUint16x32
+	OpNotEqualUint16x32
+	OpNotEqualMaskedUint16x32
+	OpPermuteUint16x32
+	OpPermuteInt16x32
+	OpPermute2Uint16x32
+	OpPermute2Int16x32
+	OpPermute2MaskedUint16x32
+	OpPermute2MaskedInt16x32
+	OpPermuteMaskedUint16x32
+	OpPermuteMaskedInt16x32
+	OpPopCountUint16x32
+	OpPopCountMaskedUint16x32
+	OpSaturatedAddUint16x32
+	OpSaturatedAddMaskedUint16x32
+	OpSaturatedSubUint16x32
+	OpSaturatedSubMaskedUint16x32
+	OpShiftAllLeftUint16x32
+	OpShiftAllLeftMaskedUint16x32
+	OpShiftAllRightUint16x32
+	OpShiftAllRightMaskedUint16x32
+	OpShiftLeftUint16x32
+	OpShiftLeftAndFillUpperFromUint16x32
+	OpShiftLeftAndFillUpperFromMaskedUint16x32
+	OpShiftLeftMaskedUint16x32
+	OpShiftRightUint16x32
+	OpShiftRightAndFillUpperFromUint16x32
+	OpShiftRightAndFillUpperFromMaskedUint16x32
+	OpShiftRightMaskedUint16x32
+	OpSubUint16x32
+	OpSubMaskedUint16x32
+	OpAddUint16x8
+	OpAddMaskedUint16x8
+	OpAndUint16x8
+	OpAndNotUint16x8
+	OpAverageUint16x8
+	OpAverageMaskedUint16x8
+	OpCompressUint16x8
+	OpEqualUint16x8
+	OpEqualMaskedUint16x8
+	OpGreaterUint16x8
+	OpGreaterEqualUint16x8
+	OpGreaterEqualMaskedUint16x8
+	OpGreaterMaskedUint16x8
+	OpLessUint16x8
+	OpLessEqualUint16x8
+	OpLessEqualMaskedUint16x8
+	OpLessMaskedUint16x8
+	OpMaxUint16x8
+	OpMaxMaskedUint16x8
+	OpMinUint16x8
+	OpMinMaskedUint16x8
+	OpMulHighUint16x8
+	OpMulHighMaskedUint16x8
+	OpNotEqualUint16x8
+	OpNotEqualMaskedUint16x8
+	OpOrUint16x8
+	OpPairwiseAddUint16x8
+	OpPairwiseSubUint16x8
+	OpPermuteInt16x8
+	OpPermuteUint16x8
+	OpPermute2Int16x8
+	OpPermute2Uint16x8
+	OpPermute2MaskedInt16x8
+	OpPermute2MaskedUint16x8
+	OpPermuteMaskedUint16x8
+	OpPermuteMaskedInt16x8
+	OpPopCountUint16x8
+	OpPopCountMaskedUint16x8
+	OpSaturatedAddUint16x8
+	OpSaturatedAddMaskedUint16x8
+	OpSaturatedSubUint16x8
+	OpSaturatedSubMaskedUint16x8
+	OpShiftAllLeftUint16x8
+	OpShiftAllLeftMaskedUint16x8
+	OpShiftAllRightUint16x8
+	OpShiftAllRightMaskedUint16x8
+	OpShiftLeftUint16x8
+	OpShiftLeftAndFillUpperFromUint16x8
+	OpShiftLeftAndFillUpperFromMaskedUint16x8
+	OpShiftLeftMaskedUint16x8
+	OpShiftRightUint16x8
+	OpShiftRightAndFillUpperFromUint16x8
+	OpShiftRightAndFillUpperFromMaskedUint16x8
+	OpShiftRightMaskedUint16x8
+	OpSubUint16x8
+	OpSubMaskedUint16x8
+	OpXorUint16x8
+	OpAddUint32x16
+	OpAddMaskedUint32x16
+	OpAndUint32x16
+	OpAndMaskedUint32x16
+	OpAndNotUint32x16
+	OpAndNotMaskedUint32x16
+	OpCompressUint32x16
+	OpEqualUint32x16
+	OpEqualMaskedUint32x16
+	OpGreaterUint32x16
+	OpGreaterEqualUint32x16
+	OpGreaterEqualMaskedUint32x16
+	OpGreaterMaskedUint32x16
+	OpLessUint32x16
+	OpLessEqualUint32x16
+	OpLessEqualMaskedUint32x16
+	OpLessMaskedUint32x16
+	OpMaxUint32x16
+	OpMaxMaskedUint32x16
+	OpMinUint32x16
+	OpMinMaskedUint32x16
+	OpNotEqualUint32x16
+	OpNotEqualMaskedUint32x16
+	OpOrUint32x16
+	OpOrMaskedUint32x16
+	OpPermuteFloat32x16
+	OpPermuteInt32x16
+	OpPermuteUint32x16
+	OpPermute2Uint32x16
+	OpPermute2Float32x16
+	OpPermute2Int32x16
+	OpPermute2MaskedInt32x16
+	OpPermute2MaskedFloat32x16
+	OpPermute2MaskedUint32x16
+	OpPermuteMaskedInt32x16
+	OpPermuteMaskedFloat32x16
+	OpPermuteMaskedUint32x16
+	OpPopCountUint32x16
+	OpPopCountMaskedUint32x16
+	OpRotateLeftUint32x16
+	OpRotateLeftMaskedUint32x16
+	OpRotateRightUint32x16
+	OpRotateRightMaskedUint32x16
+	OpShiftAllLeftUint32x16
+	OpShiftAllLeftMaskedUint32x16
+	OpShiftAllRightUint32x16
+	OpShiftAllRightMaskedUint32x16
+	OpShiftLeftUint32x16
+	OpShiftLeftAndFillUpperFromUint32x16
+	OpShiftLeftAndFillUpperFromMaskedUint32x16
+	OpShiftLeftMaskedUint32x16
+	OpShiftRightUint32x16
+	OpShiftRightAndFillUpperFromUint32x16
+	OpShiftRightAndFillUpperFromMaskedUint32x16
+	OpShiftRightMaskedUint32x16
+	OpSubUint32x16
+	OpSubMaskedUint32x16
+	OpXorUint32x16
+	OpXorMaskedUint32x16
+	OpAddUint32x4
+	OpAddMaskedUint32x4
+	OpAndUint32x4
+	OpAndMaskedUint32x4
+	OpAndNotUint32x4
+	OpAndNotMaskedUint32x4
+	OpCompressUint32x4
+	OpEqualUint32x4
+	OpEqualMaskedUint32x4
+	OpGreaterUint32x4
+	OpGreaterEqualUint32x4
+	OpGreaterEqualMaskedUint32x4
+	OpGreaterMaskedUint32x4
+	OpLessUint32x4
+	OpLessEqualUint32x4
+	OpLessEqualMaskedUint32x4
+	OpLessMaskedUint32x4
+	OpMaxUint32x4
+	OpMaxMaskedUint32x4
+	OpMinUint32x4
+	OpMinMaskedUint32x4
+	OpMulEvenWidenUint32x4
+	OpNotEqualUint32x4
+	OpNotEqualMaskedUint32x4
+	OpOrUint32x4
+	OpOrMaskedUint32x4
+	OpPairwiseAddUint32x4
+	OpPairwiseSubUint32x4
+	OpPermute2Float32x4
+	OpPermute2Uint32x4
+	OpPermute2Int32x4
+	OpPermute2MaskedInt32x4
+	OpPermute2MaskedUint32x4
+	OpPermute2MaskedFloat32x4
+	OpPopCountUint32x4
+	OpPopCountMaskedUint32x4
+	OpRotateLeftUint32x4
+	OpRotateLeftMaskedUint32x4
+	OpRotateRightUint32x4
+	OpRotateRightMaskedUint32x4
+	OpShiftAllLeftUint32x4
+	OpShiftAllLeftMaskedUint32x4
+	OpShiftAllRightUint32x4
+	OpShiftAllRightMaskedUint32x4
+	OpShiftLeftUint32x4
+	OpShiftLeftAndFillUpperFromUint32x4
+	OpShiftLeftAndFillUpperFromMaskedUint32x4
+	OpShiftLeftMaskedUint32x4
+	OpShiftRightUint32x4
+	OpShiftRightAndFillUpperFromUint32x4
+	OpShiftRightAndFillUpperFromMaskedUint32x4
+	OpShiftRightMaskedUint32x4
+	OpSubUint32x4
+	OpSubMaskedUint32x4
+	OpXorUint32x4
+	OpXorMaskedUint32x4
+	OpAddUint32x8
+	OpAddMaskedUint32x8
+	OpAndUint32x8
+	OpAndMaskedUint32x8
+	OpAndNotUint32x8
+	OpAndNotMaskedUint32x8
+	OpCompressUint32x8
+	OpEqualUint32x8
+	OpEqualMaskedUint32x8
+	OpGreaterUint32x8
+	OpGreaterEqualUint32x8
+	OpGreaterEqualMaskedUint32x8
+	OpGreaterMaskedUint32x8
+	OpLessUint32x8
+	OpLessEqualUint32x8
+	OpLessEqualMaskedUint32x8
+	OpLessMaskedUint32x8
+	OpMaxUint32x8
+	OpMaxMaskedUint32x8
+	OpMinUint32x8
+	OpMinMaskedUint32x8
+	OpMulEvenWidenUint32x8
+	OpNotEqualUint32x8
+	OpNotEqualMaskedUint32x8
+	OpOrUint32x8
+	OpOrMaskedUint32x8
+	OpPairwiseAddUint32x8
+	OpPairwiseSubUint32x8
+	OpPermuteUint32x8
+	OpPermuteFloat32x8
+	OpPermuteInt32x8
+	OpPermute2Int32x8
+	OpPermute2Float32x8
+	OpPermute2Uint32x8
+	OpPermute2MaskedFloat32x8
+	OpPermute2MaskedUint32x8
+	OpPermute2MaskedInt32x8
+	OpPermuteMaskedInt32x8
+	OpPermuteMaskedUint32x8
+	OpPermuteMaskedFloat32x8
+	OpPopCountUint32x8
+	OpPopCountMaskedUint32x8
+	OpRotateLeftUint32x8
+	OpRotateLeftMaskedUint32x8
+	OpRotateRightUint32x8
+	OpRotateRightMaskedUint32x8
+	OpShiftAllLeftUint32x8
+	OpShiftAllLeftMaskedUint32x8
+	OpShiftAllRightUint32x8
+	OpShiftAllRightMaskedUint32x8
+	OpShiftLeftUint32x8
+	OpShiftLeftAndFillUpperFromUint32x8
+	OpShiftLeftAndFillUpperFromMaskedUint32x8
+	OpShiftLeftMaskedUint32x8
+	OpShiftRightUint32x8
+	OpShiftRightAndFillUpperFromUint32x8
+	OpShiftRightAndFillUpperFromMaskedUint32x8
+	OpShiftRightMaskedUint32x8
+	OpSubUint32x8
+	OpSubMaskedUint32x8
+	OpXorUint32x8
+	OpXorMaskedUint32x8
+	OpAddUint64x2
+	OpAddMaskedUint64x2
+	OpAndUint64x2
+	OpAndMaskedUint64x2
+	OpAndNotUint64x2
+	OpAndNotMaskedUint64x2
+	OpCompressUint64x2
+	OpEqualUint64x2
+	OpEqualMaskedUint64x2
+	OpGreaterUint64x2
+	OpGreaterEqualUint64x2
+	OpGreaterEqualMaskedUint64x2
+	OpGreaterMaskedUint64x2
+	OpLessUint64x2
+	OpLessEqualUint64x2
+	OpLessEqualMaskedUint64x2
+	OpLessMaskedUint64x2
+	OpMaxUint64x2
+	OpMaxMaskedUint64x2
+	OpMinUint64x2
+	OpMinMaskedUint64x2
+	OpMulEvenWidenUint64x2
+	OpMulEvenWidenMaskedUint64x2
+	OpNotEqualUint64x2
+	OpNotEqualMaskedUint64x2
+	OpOrUint64x2
+	OpOrMaskedUint64x2
+	OpPermute2Float64x2
+	OpPermute2Uint64x2
+	OpPermute2Int64x2
+	OpPermute2MaskedInt64x2
+	OpPermute2MaskedFloat64x2
+	OpPermute2MaskedUint64x2
+	OpPopCountUint64x2
+	OpPopCountMaskedUint64x2
+	OpRotateLeftUint64x2
+	OpRotateLeftMaskedUint64x2
+	OpRotateRightUint64x2
+	OpRotateRightMaskedUint64x2
+	OpShiftAllLeftUint64x2
+	OpShiftAllLeftMaskedUint64x2
+	OpShiftAllRightUint64x2
+	OpShiftAllRightMaskedUint64x2
+	OpShiftLeftUint64x2
+	OpShiftLeftAndFillUpperFromUint64x2
+	OpShiftLeftAndFillUpperFromMaskedUint64x2
+	OpShiftLeftMaskedUint64x2
+	OpShiftRightUint64x2
+	OpShiftRightAndFillUpperFromUint64x2
+	OpShiftRightAndFillUpperFromMaskedUint64x2
+	OpShiftRightMaskedUint64x2
+	OpSubUint64x2
+	OpSubMaskedUint64x2
+	OpXorUint64x2
+	OpXorMaskedUint64x2
+	OpAddUint64x4
+	OpAddMaskedUint64x4
+	OpAndUint64x4
+	OpAndMaskedUint64x4
+	OpAndNotUint64x4
+	OpAndNotMaskedUint64x4
+	OpCompressUint64x4
+	OpEqualUint64x4
+	OpEqualMaskedUint64x4
+	OpGreaterUint64x4
+	OpGreaterEqualUint64x4
+	OpGreaterEqualMaskedUint64x4
+	OpGreaterMaskedUint64x4
+	OpLessUint64x4
+	OpLessEqualUint64x4
+	OpLessEqualMaskedUint64x4
+	OpLessMaskedUint64x4
+	OpMaxUint64x4
+	OpMaxMaskedUint64x4
+	OpMinUint64x4
+	OpMinMaskedUint64x4
+	OpMulEvenWidenUint64x4
+	OpMulEvenWidenMaskedUint64x4
+	OpNotEqualUint64x4
+	OpNotEqualMaskedUint64x4
+	OpOrUint64x4
+	OpOrMaskedUint64x4
+	OpPermuteUint64x4
+	OpPermuteInt64x4
+	OpPermuteFloat64x4
+	OpPermute2Float64x4
+	OpPermute2Int64x4
+	OpPermute2Uint64x4
+	OpPermute2MaskedFloat64x4
+	OpPermute2MaskedUint64x4
+	OpPermute2MaskedInt64x4
+	OpPermuteMaskedFloat64x4
+	OpPermuteMaskedInt64x4
+	OpPermuteMaskedUint64x4
+	OpPopCountUint64x4
+	OpPopCountMaskedUint64x4
+	OpRotateLeftUint64x4
+	OpRotateLeftMaskedUint64x4
+	OpRotateRightUint64x4
+	OpRotateRightMaskedUint64x4
+	OpShiftAllLeftUint64x4
+	OpShiftAllLeftMaskedUint64x4
+	OpShiftAllRightUint64x4
+	OpShiftAllRightMaskedUint64x4
+	OpShiftLeftUint64x4
+	OpShiftLeftAndFillUpperFromUint64x4
+	OpShiftLeftAndFillUpperFromMaskedUint64x4
+	OpShiftLeftMaskedUint64x4
+	OpShiftRightUint64x4
+	OpShiftRightAndFillUpperFromUint64x4
+	OpShiftRightAndFillUpperFromMaskedUint64x4
+	OpShiftRightMaskedUint64x4
+	OpSubUint64x4
+	OpSubMaskedUint64x4
+	OpXorUint64x4
+	OpXorMaskedUint64x4
+	OpAddUint64x8
+	OpAddMaskedUint64x8
+	OpAndUint64x8
+	OpAndMaskedUint64x8
+	OpAndNotUint64x8
+	OpAndNotMaskedUint64x8
+	OpCompressUint64x8
+	OpEqualUint64x8
+	OpEqualMaskedUint64x8
+	OpGreaterUint64x8
+	OpGreaterEqualUint64x8
+	OpGreaterEqualMaskedUint64x8
+	OpGreaterMaskedUint64x8
+	OpLessUint64x8
+	OpLessEqualUint64x8
+	OpLessEqualMaskedUint64x8
+	OpLessMaskedUint64x8
+	OpMaxUint64x8
+	OpMaxMaskedUint64x8
+	OpMinUint64x8
+	OpMinMaskedUint64x8
+	OpMulEvenWidenUint64x8
+	OpMulEvenWidenMaskedUint64x8
+	OpNotEqualUint64x8
+	OpNotEqualMaskedUint64x8
+	OpOrUint64x8
+	OpOrMaskedUint64x8
+	OpPermuteFloat64x8
+	OpPermuteInt64x8
+	OpPermuteUint64x8
+	OpPermute2Int64x8
+	OpPermute2Float64x8
+	OpPermute2Uint64x8
+	OpPermute2MaskedUint64x8
+	OpPermute2MaskedInt64x8
+	OpPermute2MaskedFloat64x8
+	OpPermuteMaskedUint64x8
+	OpPermuteMaskedFloat64x8
+	OpPermuteMaskedInt64x8
+	OpPopCountUint64x8
+	OpPopCountMaskedUint64x8
+	OpRotateLeftUint64x8
+	OpRotateLeftMaskedUint64x8
+	OpRotateRightUint64x8
+	OpRotateRightMaskedUint64x8
+	OpShiftAllLeftUint64x8
+	OpShiftAllLeftMaskedUint64x8
+	OpShiftAllRightUint64x8
+	OpShiftAllRightMaskedUint64x8
+	OpShiftLeftUint64x8
+	OpShiftLeftAndFillUpperFromUint64x8
+	OpShiftLeftAndFillUpperFromMaskedUint64x8
+	OpShiftLeftMaskedUint64x8
+	OpShiftRightUint64x8
+	OpShiftRightAndFillUpperFromUint64x8
+	OpShiftRightAndFillUpperFromMaskedUint64x8
+	OpShiftRightMaskedUint64x8
+	OpSubUint64x8
+	OpSubMaskedUint64x8
+	OpXorUint64x8
+	OpXorMaskedUint64x8
+	OpAddUint8x16
+	OpAddMaskedUint8x16
+	OpAndUint8x16
+	OpAndNotUint8x16
+	OpAverageUint8x16
+	OpAverageMaskedUint8x16
+	OpCompressUint8x16
+	OpEqualUint8x16
+	OpEqualMaskedUint8x16
+	OpGaloisFieldMulUint8x16
+	OpGaloisFieldMulMaskedUint8x16
+	OpGreaterUint8x16
+	OpGreaterEqualUint8x16
+	OpGreaterEqualMaskedUint8x16
+	OpGreaterMaskedUint8x16
+	OpLessUint8x16
+	OpLessEqualUint8x16
+	OpLessEqualMaskedUint8x16
+	OpLessMaskedUint8x16
+	OpMaxUint8x16
+	OpMaxMaskedUint8x16
+	OpMinUint8x16
+	OpMinMaskedUint8x16
+	OpNotEqualUint8x16
+	OpNotEqualMaskedUint8x16
+	OpOrUint8x16
+	OpPermuteUint8x16
+	OpPermuteInt8x16
+	OpPermute2Uint8x16
+	OpPermute2Int8x16
+	OpPermute2MaskedInt8x16
+	OpPermute2MaskedUint8x16
+	OpPermuteMaskedUint8x16
+	OpPermuteMaskedInt8x16
+	OpPopCountUint8x16
+	OpPopCountMaskedUint8x16
+	OpSaturatedAddUint8x16
+	OpSaturatedAddMaskedUint8x16
+	OpSaturatedSubUint8x16
+	OpSaturatedSubMaskedUint8x16
+	OpSaturatedUnsignedSignedPairDotProdUint8x16
+	OpSaturatedUnsignedSignedPairDotProdMaskedUint8x16
+	OpSubUint8x16
+	OpSubMaskedUint8x16
+	OpXorUint8x16
+	OpAddUint8x32
+	OpAddMaskedUint8x32
+	OpAndUint8x32
+	OpAndNotUint8x32
+	OpAverageUint8x32
+	OpAverageMaskedUint8x32
+	OpCompressUint8x32
+	OpEqualUint8x32
+	OpEqualMaskedUint8x32
+	OpGaloisFieldMulUint8x32
+	OpGaloisFieldMulMaskedUint8x32
+	OpGreaterUint8x32
+	OpGreaterEqualUint8x32
+	OpGreaterEqualMaskedUint8x32
+	OpGreaterMaskedUint8x32
+	OpLessUint8x32
+	OpLessEqualUint8x32
+	OpLessEqualMaskedUint8x32
+	OpLessMaskedUint8x32
+	OpMaxUint8x32
+	OpMaxMaskedUint8x32
+	OpMinUint8x32
+	OpMinMaskedUint8x32
+	OpNotEqualUint8x32
+	OpNotEqualMaskedUint8x32
+	OpOrUint8x32
+	OpPermuteUint8x32
+	OpPermuteInt8x32
+	OpPermute2Int8x32
+	OpPermute2Uint8x32
+	OpPermute2MaskedUint8x32
+	OpPermute2MaskedInt8x32
+	OpPermuteMaskedUint8x32
+	OpPermuteMaskedInt8x32
+	OpPopCountUint8x32
+	OpPopCountMaskedUint8x32
+	OpSaturatedAddUint8x32
+	OpSaturatedAddMaskedUint8x32
+	OpSaturatedSubUint8x32
+	OpSaturatedSubMaskedUint8x32
+	OpSaturatedUnsignedSignedPairDotProdUint8x32
+	OpSaturatedUnsignedSignedPairDotProdMaskedUint8x32
+	OpSubUint8x32
+	OpSubMaskedUint8x32
+	OpXorUint8x32
+	OpAddUint8x64
+	OpAddMaskedUint8x64
+	OpAverageUint8x64
+	OpAverageMaskedUint8x64
+	OpCompressUint8x64
+	OpEqualUint8x64
+	OpEqualMaskedUint8x64
+	OpGaloisFieldMulUint8x64
+	OpGaloisFieldMulMaskedUint8x64
+	OpGreaterUint8x64
+	OpGreaterEqualUint8x64
+	OpGreaterEqualMaskedUint8x64
+	OpGreaterMaskedUint8x64
+	OpLessUint8x64
+	OpLessEqualUint8x64
+	OpLessEqualMaskedUint8x64
+	OpLessMaskedUint8x64
+	OpMaxUint8x64
+	OpMaxMaskedUint8x64
+	OpMinUint8x64
+	OpMinMaskedUint8x64
+	OpNotEqualUint8x64
+	OpNotEqualMaskedUint8x64
+	OpPermuteInt8x64
+	OpPermuteUint8x64
+	OpPermute2Uint8x64
+	OpPermute2Int8x64
+	OpPermute2MaskedUint8x64
+	OpPermute2MaskedInt8x64
+	OpPermuteMaskedUint8x64
+	OpPermuteMaskedInt8x64
+	OpPopCountUint8x64
+	OpPopCountMaskedUint8x64
+	OpSaturatedAddUint8x64
+	OpSaturatedAddMaskedUint8x64
+	OpSaturatedSubUint8x64
+	OpSaturatedSubMaskedUint8x64
+	OpSaturatedUnsignedSignedPairDotProdUint8x64
+	OpSaturatedUnsignedSignedPairDotProdMaskedUint8x64
+	OpSubUint8x64
+	OpSubMaskedUint8x64
+	OpCeilWithPrecisionFloat32x16
+	OpCeilWithPrecisionMaskedFloat32x16
+	OpDiffWithCeilWithPrecisionFloat32x16
+	OpDiffWithCeilWithPrecisionMaskedFloat32x16
+	OpDiffWithFloorWithPrecisionFloat32x16
+	OpDiffWithFloorWithPrecisionMaskedFloat32x16
+	OpDiffWithRoundWithPrecisionFloat32x16
+	OpDiffWithRoundWithPrecisionMaskedFloat32x16
+	OpDiffWithTruncWithPrecisionFloat32x16
+	OpDiffWithTruncWithPrecisionMaskedFloat32x16
+	OpFloorWithPrecisionFloat32x16
+	OpFloorWithPrecisionMaskedFloat32x16
+	OpRoundWithPrecisionFloat32x16
+	OpRoundWithPrecisionMaskedFloat32x16
+	OpTruncWithPrecisionFloat32x16
+	OpTruncWithPrecisionMaskedFloat32x16
+	OpCeilWithPrecisionFloat32x4
+	OpCeilWithPrecisionMaskedFloat32x4
+	OpDiffWithCeilWithPrecisionFloat32x4
+	OpDiffWithCeilWithPrecisionMaskedFloat32x4
+	OpDiffWithFloorWithPrecisionFloat32x4
+	OpDiffWithFloorWithPrecisionMaskedFloat32x4
+	OpDiffWithRoundWithPrecisionFloat32x4
+	OpDiffWithRoundWithPrecisionMaskedFloat32x4
+	OpDiffWithTruncWithPrecisionFloat32x4
+	OpDiffWithTruncWithPrecisionMaskedFloat32x4
+	OpFloorWithPrecisionFloat32x4
+	OpFloorWithPrecisionMaskedFloat32x4
+	OpRoundWithPrecisionFloat32x4
+	OpRoundWithPrecisionMaskedFloat32x4
+	OpTruncWithPrecisionFloat32x4
+	OpTruncWithPrecisionMaskedFloat32x4
+	OpCeilWithPrecisionFloat32x8
+	OpCeilWithPrecisionMaskedFloat32x8
+	OpDiffWithCeilWithPrecisionFloat32x8
+	OpDiffWithCeilWithPrecisionMaskedFloat32x8
+	OpDiffWithFloorWithPrecisionFloat32x8
+	OpDiffWithFloorWithPrecisionMaskedFloat32x8
+	OpDiffWithRoundWithPrecisionFloat32x8
+	OpDiffWithRoundWithPrecisionMaskedFloat32x8
+	OpDiffWithTruncWithPrecisionFloat32x8
+	OpDiffWithTruncWithPrecisionMaskedFloat32x8
+	OpFloorWithPrecisionFloat32x8
+	OpFloorWithPrecisionMaskedFloat32x8
+	OpGet128Float32x8
+	OpRoundWithPrecisionFloat32x8
+	OpRoundWithPrecisionMaskedFloat32x8
+	OpSet128Float32x8
+	OpTruncWithPrecisionFloat32x8
+	OpTruncWithPrecisionMaskedFloat32x8
+	OpCeilWithPrecisionFloat64x2
+	OpCeilWithPrecisionMaskedFloat64x2
+	OpDiffWithCeilWithPrecisionFloat64x2
+	OpDiffWithCeilWithPrecisionMaskedFloat64x2
+	OpDiffWithFloorWithPrecisionFloat64x2
+	OpDiffWithFloorWithPrecisionMaskedFloat64x2
+	OpDiffWithRoundWithPrecisionFloat64x2
+	OpDiffWithRoundWithPrecisionMaskedFloat64x2
+	OpDiffWithTruncWithPrecisionFloat64x2
+	OpDiffWithTruncWithPrecisionMaskedFloat64x2
+	OpFloorWithPrecisionFloat64x2
+	OpFloorWithPrecisionMaskedFloat64x2
+	OpRoundWithPrecisionFloat64x2
+	OpRoundWithPrecisionMaskedFloat64x2
+	OpTruncWithPrecisionFloat64x2
+	OpTruncWithPrecisionMaskedFloat64x2
+	OpCeilWithPrecisionFloat64x4
+	OpCeilWithPrecisionMaskedFloat64x4
+	OpDiffWithCeilWithPrecisionFloat64x4
+	OpDiffWithCeilWithPrecisionMaskedFloat64x4
+	OpDiffWithFloorWithPrecisionFloat64x4
+	OpDiffWithFloorWithPrecisionMaskedFloat64x4
+	OpDiffWithRoundWithPrecisionFloat64x4
+	OpDiffWithRoundWithPrecisionMaskedFloat64x4
+	OpDiffWithTruncWithPrecisionFloat64x4
+	OpDiffWithTruncWithPrecisionMaskedFloat64x4
+	OpFloorWithPrecisionFloat64x4
+	OpFloorWithPrecisionMaskedFloat64x4
+	OpGet128Float64x4
+	OpRoundWithPrecisionFloat64x4
+	OpRoundWithPrecisionMaskedFloat64x4
+	OpSet128Float64x4
+	OpTruncWithPrecisionFloat64x4
+	OpTruncWithPrecisionMaskedFloat64x4
+	OpCeilWithPrecisionFloat64x8
+	OpCeilWithPrecisionMaskedFloat64x8
+	OpDiffWithCeilWithPrecisionFloat64x8
+	OpDiffWithCeilWithPrecisionMaskedFloat64x8
+	OpDiffWithFloorWithPrecisionFloat64x8
+	OpDiffWithFloorWithPrecisionMaskedFloat64x8
+	OpDiffWithRoundWithPrecisionFloat64x8
+	OpDiffWithRoundWithPrecisionMaskedFloat64x8
+	OpDiffWithTruncWithPrecisionFloat64x8
+	OpDiffWithTruncWithPrecisionMaskedFloat64x8
+	OpFloorWithPrecisionFloat64x8
+	OpFloorWithPrecisionMaskedFloat64x8
+	OpRoundWithPrecisionFloat64x8
+	OpRoundWithPrecisionMaskedFloat64x8
+	OpTruncWithPrecisionFloat64x8
+	OpTruncWithPrecisionMaskedFloat64x8
+	OpGet128Int16x16
+	OpSet128Int16x16
+	OpShiftAllLeftAndFillUpperFromInt16x16
+	OpShiftAllLeftAndFillUpperFromMaskedInt16x16
+	OpShiftAllRightAndFillUpperFromInt16x16
+	OpShiftAllRightAndFillUpperFromMaskedInt16x16
+	OpShiftAllLeftAndFillUpperFromInt16x32
+	OpShiftAllLeftAndFillUpperFromMaskedInt16x32
+	OpShiftAllRightAndFillUpperFromInt16x32
+	OpShiftAllRightAndFillUpperFromMaskedInt16x32
+	OpGetElemInt16x8
+	OpSetElemInt16x8
+	OpShiftAllLeftAndFillUpperFromInt16x8
+	OpShiftAllLeftAndFillUpperFromMaskedInt16x8
+	OpShiftAllRightAndFillUpperFromInt16x8
+	OpShiftAllRightAndFillUpperFromMaskedInt16x8
+	OpRotateAllLeftInt32x16
+	OpRotateAllLeftMaskedInt32x16
+	OpRotateAllRightInt32x16
+	OpRotateAllRightMaskedInt32x16
+	OpShiftAllLeftAndFillUpperFromInt32x16
+	OpShiftAllLeftAndFillUpperFromMaskedInt32x16
+	OpShiftAllRightAndFillUpperFromInt32x16
+	OpShiftAllRightAndFillUpperFromMaskedInt32x16
+	OpGetElemInt32x4
+	OpRotateAllLeftInt32x4
+	OpRotateAllLeftMaskedInt32x4
+	OpRotateAllRightInt32x4
+	OpRotateAllRightMaskedInt32x4
+	OpSetElemInt32x4
+	OpShiftAllLeftAndFillUpperFromInt32x4
+	OpShiftAllLeftAndFillUpperFromMaskedInt32x4
+	OpShiftAllRightAndFillUpperFromInt32x4
+	OpShiftAllRightAndFillUpperFromMaskedInt32x4
+	OpGet128Int32x8
+	OpRotateAllLeftInt32x8
+	OpRotateAllLeftMaskedInt32x8
+	OpRotateAllRightInt32x8
+	OpRotateAllRightMaskedInt32x8
+	OpSet128Int32x8
+	OpShiftAllLeftAndFillUpperFromInt32x8
+	OpShiftAllLeftAndFillUpperFromMaskedInt32x8
+	OpShiftAllRightAndFillUpperFromInt32x8
+	OpShiftAllRightAndFillUpperFromMaskedInt32x8
+	OpGetElemInt64x2
+	OpRotateAllLeftInt64x2
+	OpRotateAllLeftMaskedInt64x2
+	OpRotateAllRightInt64x2
+	OpRotateAllRightMaskedInt64x2
+	OpSetElemInt64x2
+	OpShiftAllLeftAndFillUpperFromInt64x2
+	OpShiftAllLeftAndFillUpperFromMaskedInt64x2
+	OpShiftAllRightAndFillUpperFromInt64x2
+	OpShiftAllRightAndFillUpperFromMaskedInt64x2
+	OpGet128Int64x4
+	OpRotateAllLeftInt64x4
+	OpRotateAllLeftMaskedInt64x4
+	OpRotateAllRightInt64x4
+	OpRotateAllRightMaskedInt64x4
+	OpSet128Int64x4
+	OpShiftAllLeftAndFillUpperFromInt64x4
+	OpShiftAllLeftAndFillUpperFromMaskedInt64x4
+	OpShiftAllRightAndFillUpperFromInt64x4
+	OpShiftAllRightAndFillUpperFromMaskedInt64x4
+	OpRotateAllLeftInt64x8
+	OpRotateAllLeftMaskedInt64x8
+	OpRotateAllRightInt64x8
+	OpRotateAllRightMaskedInt64x8
+	OpShiftAllLeftAndFillUpperFromInt64x8
+	OpShiftAllLeftAndFillUpperFromMaskedInt64x8
+	OpShiftAllRightAndFillUpperFromInt64x8
+	OpShiftAllRightAndFillUpperFromMaskedInt64x8
+	OpGetElemInt8x16
+	OpSetElemInt8x16
+	OpGet128Int8x32
+	OpSet128Int8x32
+	OpGet128Uint16x16
+	OpSet128Uint16x16
+	OpShiftAllLeftAndFillUpperFromUint16x16
+	OpShiftAllLeftAndFillUpperFromMaskedUint16x16
+	OpShiftAllRightAndFillUpperFromUint16x16
+	OpShiftAllRightAndFillUpperFromMaskedUint16x16
+	OpShiftAllLeftAndFillUpperFromUint16x32
+	OpShiftAllLeftAndFillUpperFromMaskedUint16x32
+	OpShiftAllRightAndFillUpperFromUint16x32
+	OpShiftAllRightAndFillUpperFromMaskedUint16x32
+	OpGetElemUint16x8
+	OpSetElemUint16x8
+	OpShiftAllLeftAndFillUpperFromUint16x8
+	OpShiftAllLeftAndFillUpperFromMaskedUint16x8
+	OpShiftAllRightAndFillUpperFromUint16x8
+	OpShiftAllRightAndFillUpperFromMaskedUint16x8
+	OpRotateAllLeftUint32x16
+	OpRotateAllLeftMaskedUint32x16
+	OpRotateAllRightUint32x16
+	OpRotateAllRightMaskedUint32x16
+	OpShiftAllLeftAndFillUpperFromUint32x16
+	OpShiftAllLeftAndFillUpperFromMaskedUint32x16
+	OpShiftAllRightAndFillUpperFromUint32x16
+	OpShiftAllRightAndFillUpperFromMaskedUint32x16
+	OpGetElemUint32x4
+	OpRotateAllLeftUint32x4
+	OpRotateAllLeftMaskedUint32x4
+	OpRotateAllRightUint32x4
+	OpRotateAllRightMaskedUint32x4
+	OpSetElemUint32x4
+	OpShiftAllLeftAndFillUpperFromUint32x4
+	OpShiftAllLeftAndFillUpperFromMaskedUint32x4
+	OpShiftAllRightAndFillUpperFromUint32x4
+	OpShiftAllRightAndFillUpperFromMaskedUint32x4
+	OpGet128Uint32x8
+	OpRotateAllLeftUint32x8
+	OpRotateAllLeftMaskedUint32x8
+	OpRotateAllRightUint32x8
+	OpRotateAllRightMaskedUint32x8
+	OpSet128Uint32x8
+	OpShiftAllLeftAndFillUpperFromUint32x8
+	OpShiftAllLeftAndFillUpperFromMaskedUint32x8
+	OpShiftAllRightAndFillUpperFromUint32x8
+	OpShiftAllRightAndFillUpperFromMaskedUint32x8
+	OpGetElemUint64x2
+	OpRotateAllLeftUint64x2
+	OpRotateAllLeftMaskedUint64x2
+	OpRotateAllRightUint64x2
+	OpRotateAllRightMaskedUint64x2
+	OpSetElemUint64x2
+	OpShiftAllLeftAndFillUpperFromUint64x2
+	OpShiftAllLeftAndFillUpperFromMaskedUint64x2
+	OpShiftAllRightAndFillUpperFromUint64x2
+	OpShiftAllRightAndFillUpperFromMaskedUint64x2
+	OpGet128Uint64x4
+	OpRotateAllLeftUint64x4
+	OpRotateAllLeftMaskedUint64x4
+	OpRotateAllRightUint64x4
+	OpRotateAllRightMaskedUint64x4
+	OpSet128Uint64x4
+	OpShiftAllLeftAndFillUpperFromUint64x4
+	OpShiftAllLeftAndFillUpperFromMaskedUint64x4
+	OpShiftAllRightAndFillUpperFromUint64x4
+	OpShiftAllRightAndFillUpperFromMaskedUint64x4
+	OpRotateAllLeftUint64x8
+	OpRotateAllLeftMaskedUint64x8
+	OpRotateAllRightUint64x8
+	OpRotateAllRightMaskedUint64x8
+	OpShiftAllLeftAndFillUpperFromUint64x8
+	OpShiftAllLeftAndFillUpperFromMaskedUint64x8
+	OpShiftAllRightAndFillUpperFromUint64x8
+	OpShiftAllRightAndFillUpperFromMaskedUint64x8
+	OpGaloisFieldAffineTransformUint8x16
+	OpGaloisFieldAffineTransformInverseUint8x16
+	OpGaloisFieldAffineTransformInverseMaskedUint8x16
+	OpGaloisFieldAffineTransformMaskedUint8x16
+	OpGetElemUint8x16
+	OpSetElemUint8x16
+	OpGaloisFieldAffineTransformUint8x32
+	OpGaloisFieldAffineTransformInverseUint8x32
+	OpGaloisFieldAffineTransformInverseMaskedUint8x32
+	OpGaloisFieldAffineTransformMaskedUint8x32
+	OpGet128Uint8x32
+	OpSet128Uint8x32
+	OpGaloisFieldAffineTransformUint8x64
+	OpGaloisFieldAffineTransformInverseUint8x64
+	OpGaloisFieldAffineTransformInverseMaskedUint8x64
+	OpGaloisFieldAffineTransformMaskedUint8x64
 )
 
 var opcodeTable = [...]opInfo{
@@ -6856,7 +9664,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVSS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -6872,7 +9680,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -6912,8 +9720,8 @@ var opcodeTable = [...]opInfo{
 		scale:     1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -6929,8 +9737,8 @@ var opcodeTable = [...]opInfo{
 		scale:     4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -6946,8 +9754,8 @@ var opcodeTable = [...]opInfo{
 		scale:     1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -6963,8 +9771,8 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -6980,8 +9788,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVSS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 		},
 	},
@@ -6994,8 +9802,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 		},
 	},
@@ -7008,9 +9816,9 @@ var opcodeTable = [...]opInfo{
 		scale:     1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 		},
 	},
@@ -7023,9 +9831,9 @@ var opcodeTable = [...]opInfo{
 		scale:     4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 		},
 	},
@@ -7038,9 +9846,9 @@ var opcodeTable = [...]opInfo{
 		scale:     1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 		},
 	},
@@ -7053,9 +9861,9 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 		},
 	},
@@ -7069,8 +9877,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AADDSS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7087,8 +9895,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AADDSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7105,8 +9913,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASUBSS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7123,8 +9931,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASUBSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7141,8 +9949,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMULSS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7159,8 +9967,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMULSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7177,8 +9985,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ADIVSS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7195,8 +10003,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ADIVSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7213,9 +10021,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7232,9 +10040,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7251,9 +10059,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7270,9 +10078,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7289,9 +10097,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7308,9 +10116,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7327,9 +10135,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7346,9 +10154,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7365,9 +10173,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7384,9 +10192,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7403,9 +10211,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7422,9 +10230,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7441,9 +10249,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7460,9 +10268,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7479,9 +10287,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7498,9 +10306,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -7579,7 +10387,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AADDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -7593,7 +10401,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AADDL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8227,7 +11035,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AANDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8241,7 +11049,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AANDL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8321,7 +11129,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8335,7 +11143,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AORL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8415,7 +11223,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AXORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8429,7 +11237,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AXORL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8530,8 +11338,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ACMPQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8544,8 +11352,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ACMPL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8558,8 +11366,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ACMPW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8572,8 +11380,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ACMPB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8586,7 +11394,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ACMPQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8599,7 +11407,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ACMPL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8612,7 +11420,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ACMPW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8625,7 +11433,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ACMPB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8638,9 +11446,9 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8654,9 +11462,9 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8669,9 +11477,9 @@ var opcodeTable = [...]opInfo{
 		scale:     4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8685,9 +11493,9 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8700,9 +11508,9 @@ var opcodeTable = [...]opInfo{
 		scale:     2,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8716,9 +11524,9 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8732,9 +11540,9 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8747,8 +11555,8 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8762,8 +11570,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8776,8 +11584,8 @@ var opcodeTable = [...]opInfo{
 		scale:     4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8791,8 +11599,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8805,8 +11613,8 @@ var opcodeTable = [...]opInfo{
 		scale:     2,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8820,8 +11628,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -8835,8 +11643,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -9060,7 +11868,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ABTSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -9074,7 +11882,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ABTRQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -9088,7 +11896,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ABTCQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -9741,8 +12549,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AADDL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -9760,8 +12568,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AADDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -9779,8 +12587,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASUBQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -9798,8 +12606,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASUBL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -9817,8 +12625,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AANDL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -9836,8 +12644,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AANDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -9855,8 +12663,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -9874,8 +12682,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AORL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -9893,8 +12701,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AXORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -9912,8 +12720,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AXORL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -9931,9 +12739,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -9951,9 +12759,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -9971,9 +12779,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -9991,9 +12799,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10011,9 +12819,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10031,9 +12839,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10051,9 +12859,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10071,9 +12879,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10091,9 +12899,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10111,9 +12919,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10131,9 +12939,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10151,9 +12959,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10171,9 +12979,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10191,9 +12999,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10211,9 +13019,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10231,9 +13039,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10251,9 +13059,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10271,9 +13079,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10291,9 +13099,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10311,9 +13119,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10331,9 +13139,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10351,9 +13159,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10371,9 +13179,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10391,9 +13199,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10411,9 +13219,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -10430,8 +13238,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AADDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10445,8 +13253,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASUBQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10460,8 +13268,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AANDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10475,8 +13283,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10490,8 +13298,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AXORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10505,8 +13313,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AADDL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10520,8 +13328,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASUBL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10535,8 +13343,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AANDL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10550,8 +13358,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AORL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10565,8 +13373,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AXORL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10580,9 +13388,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10596,9 +13404,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10612,9 +13420,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10628,9 +13436,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10644,9 +13452,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10660,9 +13468,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10676,9 +13484,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10692,9 +13500,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10708,9 +13516,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10724,9 +13532,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10740,9 +13548,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10756,9 +13564,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10772,9 +13580,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10788,9 +13596,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10804,9 +13612,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10820,9 +13628,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10836,9 +13644,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10852,9 +13660,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10868,9 +13676,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10884,9 +13692,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10900,9 +13708,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10916,9 +13724,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10932,9 +13740,9 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10948,9 +13756,9 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10964,9 +13772,9 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10980,8 +13788,8 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -10995,8 +13803,8 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11010,8 +13818,8 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11025,8 +13833,8 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11040,8 +13848,8 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11055,8 +13863,8 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11070,8 +13878,8 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11085,8 +13893,8 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11100,8 +13908,8 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11115,8 +13923,8 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11130,8 +13938,8 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11145,8 +13953,8 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11160,8 +13968,8 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11175,8 +13983,8 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11190,8 +13998,8 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11205,8 +14013,8 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11220,8 +14028,8 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11235,8 +14043,8 @@ var opcodeTable = [...]opInfo{
 		scale:        1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11250,8 +14058,8 @@ var opcodeTable = [...]opInfo{
 		scale:        4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -11265,8 +14073,8 @@ var opcodeTable = [...]opInfo{
 		scale:        8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12342,7 +15150,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASETEQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12355,7 +15163,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASETNE,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12368,7 +15176,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASETLT,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12381,7 +15189,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASETLE,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12394,7 +15202,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASETGT,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12407,7 +15215,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASETGE,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12420,7 +15228,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASETCS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12433,7 +15241,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASETLS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12446,7 +15254,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASETHI,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12459,7 +15267,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASETCC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12473,8 +15281,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12488,8 +15296,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12503,8 +15311,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12518,8 +15326,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12533,8 +15341,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12548,8 +15356,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12563,8 +15371,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12578,8 +15386,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12593,8 +15401,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12608,8 +15416,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -12998,7 +15806,7 @@ var opcodeTable = [...]opInfo{
 		asm:               x86.ALEAQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13014,7 +15822,7 @@ var opcodeTable = [...]opInfo{
 		asm:               x86.ALEAL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13030,7 +15838,7 @@ var opcodeTable = [...]opInfo{
 		asm:               x86.ALEAW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13047,8 +15855,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13065,8 +15873,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13083,8 +15891,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13100,8 +15908,8 @@ var opcodeTable = [...]opInfo{
 		scale:     2,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13117,8 +15925,8 @@ var opcodeTable = [...]opInfo{
 		scale:     2,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13134,8 +15942,8 @@ var opcodeTable = [...]opInfo{
 		scale:     2,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13151,8 +15959,8 @@ var opcodeTable = [...]opInfo{
 		scale:     4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13168,8 +15976,8 @@ var opcodeTable = [...]opInfo{
 		scale:     4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13185,8 +15993,8 @@ var opcodeTable = [...]opInfo{
 		scale:     4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13202,8 +16010,8 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13219,8 +16027,8 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13236,8 +16044,8 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13253,7 +16061,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVBLZX,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13269,7 +16077,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVBQSX,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13285,7 +16093,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVWLZX,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13301,7 +16109,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVWQSX,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13317,7 +16125,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13333,7 +16141,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVLQSX,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13349,7 +16157,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13365,8 +16173,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13379,8 +16187,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13393,8 +16201,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13407,8 +16215,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13421,7 +16229,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVUPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -13437,8 +16245,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVUPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 		},
 	},
@@ -13452,8 +16260,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13470,8 +16278,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13487,8 +16295,8 @@ var opcodeTable = [...]opInfo{
 		scale:     2,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13505,8 +16313,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13522,8 +16330,8 @@ var opcodeTable = [...]opInfo{
 		scale:     4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13539,8 +16347,8 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13557,8 +16365,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13574,8 +16382,8 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -13592,9 +16400,9 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13608,9 +16416,9 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13623,9 +16431,9 @@ var opcodeTable = [...]opInfo{
 		scale:     2,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13639,9 +16447,9 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13654,9 +16462,9 @@ var opcodeTable = [...]opInfo{
 		scale:     4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13669,9 +16477,9 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13685,9 +16493,9 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13700,9 +16508,9 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13715,7 +16523,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13728,7 +16536,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13741,7 +16549,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13754,7 +16562,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13767,7 +16575,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVUPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13781,8 +16589,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13796,8 +16604,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13810,8 +16618,8 @@ var opcodeTable = [...]opInfo{
 		scale:     2,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13825,8 +16633,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13839,8 +16647,8 @@ var opcodeTable = [...]opInfo{
 		scale:     4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13854,8 +16662,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -13868,8 +16676,8 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14124,7 +16932,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14140,7 +16948,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14156,7 +16964,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14174,8 +16982,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AXCHGB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14193,8 +17001,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AXCHGL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14212,8 +17020,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AXCHGQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14232,8 +17040,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AXADDL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14252,8 +17060,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AXADDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14325,8 +17133,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AANDB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14341,8 +17149,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AANDL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14357,8 +17165,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AANDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14373,8 +17181,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AORB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14389,8 +17197,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AORL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14405,8 +17213,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14509,7 +17317,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.APREFETCHT0,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14520,7 +17328,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.APREFETCHNTA,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14703,8 +17511,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVBEW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14717,7 +17525,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVBEL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14733,8 +17541,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVBEL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14747,7 +17555,7 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVBEQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14763,8 +17571,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.AMOVBEQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14778,8 +17586,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14795,8 +17603,8 @@ var opcodeTable = [...]opInfo{
 		scale:     4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14812,8 +17620,8 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14830,8 +17638,8 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14847,8 +17655,8 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -14865,9 +17673,9 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14880,9 +17688,9 @@ var opcodeTable = [...]opInfo{
 		scale:     2,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14896,9 +17704,9 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14911,9 +17719,9 @@ var opcodeTable = [...]opInfo{
 		scale:     4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14926,9 +17734,9 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14942,9 +17750,9 @@ var opcodeTable = [...]opInfo{
 		scale:       1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -14957,9 +17765,9 @@ var opcodeTable = [...]opInfo{
 		scale:     8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{2, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 		},
 	},
@@ -15056,8 +17864,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASARXL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15073,8 +17881,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASARXQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15090,8 +17898,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASHLXL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15107,8 +17915,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASHLXQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15124,8 +17932,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASHRXL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15141,8 +17949,8 @@ var opcodeTable = [...]opInfo{
 		asm:            x86.ASHRXQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{1, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15159,9 +17967,9 @@ var opcodeTable = [...]opInfo{
 		scale:          1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15178,9 +17986,9 @@ var opcodeTable = [...]opInfo{
 		scale:          4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15197,9 +18005,9 @@ var opcodeTable = [...]opInfo{
 		scale:          8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15216,9 +18024,9 @@ var opcodeTable = [...]opInfo{
 		scale:          1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15235,9 +18043,9 @@ var opcodeTable = [...]opInfo{
 		scale:          8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15254,9 +18062,9 @@ var opcodeTable = [...]opInfo{
 		scale:          1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15273,9 +18081,9 @@ var opcodeTable = [...]opInfo{
 		scale:          4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15292,9 +18100,9 @@ var opcodeTable = [...]opInfo{
 		scale:          8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15311,9 +18119,9 @@ var opcodeTable = [...]opInfo{
 		scale:          1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15330,9 +18138,9 @@ var opcodeTable = [...]opInfo{
 		scale:          8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15349,9 +18157,9 @@ var opcodeTable = [...]opInfo{
 		scale:          1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15368,9 +18176,9 @@ var opcodeTable = [...]opInfo{
 		scale:          4,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15387,9 +18195,9 @@ var opcodeTable = [...]opInfo{
 		scale:          8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15406,9 +18214,9 @@ var opcodeTable = [...]opInfo{
 		scale:          1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15425,9 +18233,9 @@ var opcodeTable = [...]opInfo{
 		scale:          8,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
-				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
+				{2, 49135},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{1, 49151},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 72057594037993471}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
 			},
 			outputs: []outputInfo{
 				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
@@ -15534,17473 +18342,18816 @@ var opcodeTable = [...]opInfo{
 			},
 		},
 	},
-
 	{
-		name:        "ADD",
+		name:        "VPADDD4",
 		argLen:      2,
 		commutative: true,
-		asm:         arm.AADD,
+		asm:         x86.AVPADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.AADD,
+		name:           "VMOVDQUload128",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            x86.AVMOVDQU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SUB",
-		argLen: 2,
-		asm:    arm.ASUB,
+		name:           "VMOVDQUstore128",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            x86.AVMOVDQU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-			},
-			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 		},
 	},
 	{
-		name:    "SUBconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ASUB,
+		name:           "VMOVDQUload256",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            x86.AVMOVDQU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "RSB",
-		argLen: 2,
-		asm:    arm.ARSB,
+		name:           "VMOVDQUstore256",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            x86.AVMOVDQU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-			},
-			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 		},
 	},
 	{
-		name:    "RSBconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ARSB,
+		name:           "VMOVDQUload512",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            x86.AVMOVDQU64,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MUL",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.AMUL,
+		name:           "VMOVDQUstore512",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            x86.AVMOVDQU64,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-			},
-			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 			},
 		},
 	},
 	{
-		name:        "HMUL",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.AMULL,
+		name:   "VPMOVMToVec8x16",
+		argLen: 1,
+		asm:    x86.AVPMOVM2B,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "HMULU",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.AMULLU,
+		name:   "VPMOVMToVec8x32",
+		argLen: 1,
+		asm:    x86.AVPMOVM2B,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "CALLudiv",
-		argLen:       2,
-		clobberFlags: true,
+		name:   "VPMOVMToVec8x64",
+		argLen: 1,
+		asm:    x86.AVPMOVM2B,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2}, // R1
-				{1, 1}, // R0
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
-			clobbers: 20492, // R2 R3 R12 R14
 			outputs: []outputInfo{
-				{0, 1}, // R0
-				{1, 2}, // R1
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "ADDS",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.AADD,
+		name:   "VPMOVMToVec16x8",
+		argLen: 1,
+		asm:    x86.AVPMOVM2W,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDSconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.AADD,
+		name:   "VPMOVMToVec16x16",
+		argLen: 1,
+		asm:    x86.AVPMOVM2W,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "ADC",
-		argLen:      3,
-		commutative: true,
-		asm:         arm.AADC,
+		name:   "VPMOVMToVec16x32",
+		argLen: 1,
+		asm:    x86.AVPMOVM2W,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "ADCconst",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AADC,
+		name:   "VPMOVMToVec32x4",
+		argLen: 1,
+		asm:    x86.AVPMOVM2D,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SUBS",
-		argLen: 2,
-		asm:    arm.ASUB,
+		name:   "VPMOVMToVec32x8",
+		argLen: 1,
+		asm:    x86.AVPMOVM2D,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SUBSconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ASUB,
+		name:   "VPMOVMToVec32x16",
+		argLen: 1,
+		asm:    x86.AVPMOVM2D,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "RSBSconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ARSB,
+		name:   "VPMOVMToVec64x2",
+		argLen: 1,
+		asm:    x86.AVPMOVM2Q,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SBC",
-		argLen: 3,
-		asm:    arm.ASBC,
+		name:   "VPMOVMToVec64x4",
+		argLen: 1,
+		asm:    x86.AVPMOVM2Q,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SBCconst",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ASBC,
+		name:   "VPMOVMToVec64x8",
+		argLen: 1,
+		asm:    x86.AVPMOVM2Q,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "RSCconst",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ARSC,
+		name:   "VPMOVVec8x16ToM",
+		argLen: 1,
+		asm:    x86.AVPMOVB2M,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:        "MULLU",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.AMULLU,
+		name:   "VPMOVVec8x32ToM",
+		argLen: 1,
+		asm:    x86.AVPMOVB2M,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MULA",
-		argLen: 3,
-		asm:    arm.AMULA,
+		name:   "VPMOVVec8x64ToM",
+		argLen: 1,
+		asm:    x86.AVPMOVB2M,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MULS",
-		argLen: 3,
-		asm:    arm.AMULS,
+		name:   "VPMOVVec16x8ToM",
+		argLen: 1,
+		asm:    x86.AVPMOVW2M,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:        "ADDF",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.AADDF,
+		name:   "VPMOVVec16x16ToM",
+		argLen: 1,
+		asm:    x86.AVPMOVW2M,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:        "ADDD",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.AADDD,
+		name:   "VPMOVVec16x32ToM",
+		argLen: 1,
+		asm:    x86.AVPMOVW2M,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "SUBF",
-		argLen: 2,
-		asm:    arm.ASUBF,
+		name:   "VPMOVVec32x4ToM",
+		argLen: 1,
+		asm:    x86.AVPMOVD2M,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "SUBD",
-		argLen: 2,
-		asm:    arm.ASUBD,
+		name:   "VPMOVVec32x8ToM",
+		argLen: 1,
+		asm:    x86.AVPMOVD2M,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:        "MULF",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.AMULF,
+		name:   "VPMOVVec32x16ToM",
+		argLen: 1,
+		asm:    x86.AVPMOVD2M,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:        "MULD",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.AMULD,
+		name:   "VPMOVVec64x2ToM",
+		argLen: 1,
+		asm:    x86.AVPMOVQ2M,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:        "NMULF",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.ANMULF,
+		name:   "VPMOVVec64x4ToM",
+		argLen: 1,
+		asm:    x86.AVPMOVQ2M,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:        "NMULD",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.ANMULD,
+		name:   "VPMOVVec64x8ToM",
+		argLen: 1,
+		asm:    x86.AVPMOVQ2M,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "DIVF",
-		argLen: 2,
-		asm:    arm.ADIVF,
+		name:   "Zero128",
+		argLen: 0,
+		asm:    x86.AVPXOR,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "DIVD",
-		argLen: 2,
-		asm:    arm.ADIVD,
+		name:   "Zero256",
+		argLen: 0,
+		asm:    x86.AVPXOR,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "MULAF",
-		argLen:       3,
-		resultInArg0: true,
-		asm:          arm.AMULAF,
+		name:   "Zero512",
+		argLen: 0,
+		asm:    x86.AVPXORQ,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:         "MULAD",
-		argLen:       3,
-		resultInArg0: true,
-		asm:          arm.AMULAD,
+		name:   "VZEROUPPER",
+		argLen: 0,
+		asm:    x86.AVZEROUPPER,
+		reg:    regInfo{},
+	},
+	{
+		name:   "VZEROALL",
+		argLen: 0,
+		asm:    x86.AVZEROALL,
+		reg:    regInfo{},
+	},
+	{
+		name:        "VADDPS512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVADDPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:         "MULSF",
-		argLen:       3,
-		resultInArg0: true,
-		asm:          arm.AMULSF,
+		name:        "VADDPSMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVADDPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "MULSD",
-		argLen:       3,
-		resultInArg0: true,
-		asm:          arm.AMULSD,
+		name:   "VRCP14PS512",
+		argLen: 1,
+		asm:    x86.AVRCP14PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:         "FMULAD",
-		argLen:       3,
-		resultInArg0: true,
-		asm:          arm.AFMULAD,
+		name:   "VRCP14PSMasked512",
+		argLen: 2,
+		asm:    x86.AVRCP14PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "AND",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.AAND,
+		name:   "VRSQRT14PS512",
+		argLen: 1,
+		asm:    x86.AVRSQRT14PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "ANDconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.AAND,
+		name:   "VRSQRT14PSMasked512",
+		argLen: 2,
+		asm:    x86.AVRSQRT14PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "OR",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.AORR,
+		name:   "VCOMPRESSPSMasked512",
+		argLen: 2,
+		asm:    x86.AVCOMPRESSPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ORconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.AORR,
+		name:   "VDIVPS512",
+		argLen: 2,
+		asm:    x86.AVDIVPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "XOR",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.AEOR,
+		name:   "VDIVPSMasked512",
+		argLen: 3,
+		asm:    x86.AVDIVPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "XORconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.AEOR,
+		name:         "VFMADD213PS512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMADD213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "BIC",
-		argLen: 2,
-		asm:    arm.ABIC,
+		name:         "VFMADD213PSMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMADD213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "BICconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ABIC,
+		name:         "VFMADDSUB213PS512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMADDSUB213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "BFX",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ABFX,
+		name:         "VFMADDSUB213PSMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMADDSUB213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "BFXU",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ABFXU,
+		name:         "VFMSUBADD213PS512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMSUBADD213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MVN",
-		argLen: 1,
-		asm:    arm.AMVN,
+		name:         "VFMSUBADD213PSMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMSUBADD213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NEGF",
-		argLen: 1,
-		asm:    arm.ANEGF,
+		name:        "VMAXPS512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMAXPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "NEGD",
-		argLen: 1,
-		asm:    arm.ANEGD,
+		name:        "VMAXPSMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMAXPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SQRTD",
-		argLen: 1,
-		asm:    arm.ASQRTD,
+		name:        "VMINPS512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMINPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SQRTF",
-		argLen: 1,
-		asm:    arm.ASQRTF,
+		name:        "VMINPSMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMINPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ABSD",
-		argLen: 1,
-		asm:    arm.AABSD,
+		name:        "VMULPS512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMULPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "CLZ",
-		argLen: 1,
-		asm:    arm.ACLZ,
+		name:   "VSCALEFPS512",
+		argLen: 2,
+		asm:    x86.AVSCALEFPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "REV",
-		argLen: 1,
-		asm:    arm.AREV,
+		name:   "VSCALEFPSMasked512",
+		argLen: 3,
+		asm:    x86.AVSCALEFPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "REV16",
-		argLen: 1,
-		asm:    arm.AREV16,
+		name:        "VMULPSMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMULPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "RBIT",
+		name:   "VSQRTPS512",
 		argLen: 1,
-		asm:    arm.ARBIT,
+		asm:    x86.AVSQRTPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SLL",
+		name:   "VSQRTPSMasked512",
 		argLen: 2,
-		asm:    arm.ASLL,
+		asm:    x86.AVSQRTPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SLLconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ASLL,
+		name:   "VSUBPS512",
+		argLen: 2,
+		asm:    x86.AVSUBPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SRL",
-		argLen: 2,
-		asm:    arm.ASRL,
+		name:   "VSUBPSMasked512",
+		argLen: 3,
+		asm:    x86.AVSUBPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SRLconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ASRL,
+		name:        "VADDPS128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVADDPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SRA",
-		argLen: 2,
-		asm:    arm.ASRA,
+		name:        "VADDPSMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVADDPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SRAconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ASRA,
+		name:   "VADDSUBPS128",
+		argLen: 2,
+		asm:    x86.AVADDSUBPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SRR",
-		argLen: 2,
+		name:   "VRCP14PS128",
+		argLen: 1,
+		asm:    x86.AVRCP14PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "SRRconst",
-		auxType: auxInt32,
-		argLen:  1,
+		name:   "VRCP14PSMasked128",
+		argLen: 2,
+		asm:    x86.AVRCP14PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AADD,
+		name:   "VRSQRTPS128",
+		argLen: 1,
+		asm:    x86.AVRSQRTPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AADD,
+		name:   "VRSQRT14PSMasked128",
+		argLen: 2,
+		asm:    x86.AVRSQRT14PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AADD,
+		name:   "VCOMPRESSPSMasked128",
+		argLen: 2,
+		asm:    x86.AVCOMPRESSPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SUBshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ASUB,
+		name:   "VDIVPS128",
+		argLen: 2,
+		asm:    x86.AVDIVPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SUBshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ASUB,
+		name:   "VDIVPSMasked128",
+		argLen: 3,
+		asm:    x86.AVDIVPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SUBshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ASUB,
+		name:         "VFMADD213PS128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMADD213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "RSBshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ARSB,
+		name:         "VFMADD213PSMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMADD213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "RSBshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ARSB,
+		name:         "VFMADDSUB213PS128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMADDSUB213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "RSBshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ARSB,
+		name:         "VFMADDSUB213PSMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMADDSUB213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ANDshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AAND,
+		name:         "VFMSUBADD213PS128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMSUBADD213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ANDshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AAND,
+		name:         "VFMSUBADD213PSMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMSUBADD213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ANDshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AAND,
+		name:        "VMAXPS128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMAXPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ORshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AORR,
+		name:        "VMAXPSMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMAXPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ORshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AORR,
+		name:        "VMINPS128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMINPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ORshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AORR,
+		name:        "VMINPSMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMINPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "XORshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AEOR,
+		name:        "VMULPS128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMULPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "XORshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AEOR,
+		name:   "VSCALEFPS128",
+		argLen: 2,
+		asm:    x86.AVSCALEFPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "XORshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AEOR,
+		name:   "VSCALEFPSMasked128",
+		argLen: 3,
+		asm:    x86.AVSCALEFPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "XORshiftRR",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AEOR,
+		name:        "VMULPSMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMULPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "BICshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ABIC,
+		name:   "VHADDPS128",
+		argLen: 2,
+		asm:    x86.AVHADDPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "BICshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ABIC,
+		name:   "VHSUBPS128",
+		argLen: 2,
+		asm:    x86.AVHSUBPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "BICshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ABIC,
+		name:   "VSQRTPS128",
+		argLen: 1,
+		asm:    x86.AVSQRTPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "MVNshiftLL",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.AMVN,
+		name:   "VSQRTPSMasked128",
+		argLen: 2,
+		asm:    x86.AVSQRTPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "MVNshiftRL",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.AMVN,
+		name:   "VSUBPS128",
+		argLen: 2,
+		asm:    x86.AVSUBPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "MVNshiftRA",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.AMVN,
+		name:   "VSUBPSMasked128",
+		argLen: 3,
+		asm:    x86.AVSUBPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADCshiftLL",
-		auxType: auxInt32,
-		argLen:  3,
-		asm:     arm.AADC,
+		name:        "VADDPS256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVADDPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADCshiftRL",
-		auxType: auxInt32,
-		argLen:  3,
-		asm:     arm.AADC,
+		name:        "VADDPSMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVADDPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADCshiftRA",
-		auxType: auxInt32,
-		argLen:  3,
-		asm:     arm.AADC,
+		name:   "VADDSUBPS256",
+		argLen: 2,
+		asm:    x86.AVADDSUBPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SBCshiftLL",
-		auxType: auxInt32,
-		argLen:  3,
-		asm:     arm.ASBC,
+		name:   "VRCP14PS256",
+		argLen: 1,
+		asm:    x86.AVRCP14PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "SBCshiftRL",
-		auxType: auxInt32,
-		argLen:  3,
-		asm:     arm.ASBC,
+		name:   "VRCP14PSMasked256",
+		argLen: 2,
+		asm:    x86.AVRCP14PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SBCshiftRA",
-		auxType: auxInt32,
-		argLen:  3,
-		asm:     arm.ASBC,
+		name:   "VRSQRTPS256",
+		argLen: 1,
+		asm:    x86.AVRSQRTPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "RSCshiftLL",
-		auxType: auxInt32,
-		argLen:  3,
-		asm:     arm.ARSC,
+		name:   "VRSQRT14PSMasked256",
+		argLen: 2,
+		asm:    x86.AVRSQRT14PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "RSCshiftRL",
-		auxType: auxInt32,
-		argLen:  3,
-		asm:     arm.ARSC,
+		name:   "VCOMPRESSPSMasked256",
+		argLen: 2,
+		asm:    x86.AVCOMPRESSPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "RSCshiftRA",
-		auxType: auxInt32,
-		argLen:  3,
-		asm:     arm.ARSC,
+		name:   "VDIVPS256",
+		argLen: 2,
+		asm:    x86.AVDIVPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDSshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AADD,
+		name:   "VDIVPSMasked256",
+		argLen: 3,
+		asm:    x86.AVDIVPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDSshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AADD,
+		name:         "VFMADD213PS256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMADD213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDSshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.AADD,
+		name:         "VFMADD213PSMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMADD213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SUBSshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ASUB,
+		name:         "VFMADDSUB213PS256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMADDSUB213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SUBSshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ASUB,
+		name:         "VFMADDSUB213PSMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMADDSUB213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SUBSshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ASUB,
+		name:         "VFMSUBADD213PS256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMSUBADD213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "RSBSshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ARSB,
+		name:         "VFMSUBADD213PSMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMSUBADD213PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "RSBSshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ARSB,
+		name:        "VMAXPS256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMAXPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "RSBSshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ARSB,
+		name:        "VMAXPSMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMAXPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ADDshiftLLreg",
-		argLen: 3,
-		asm:    arm.AADD,
+		name:        "VMINPS256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMINPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ADDshiftRLreg",
-		argLen: 3,
-		asm:    arm.AADD,
+		name:        "VMINPSMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMINPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ADDshiftRAreg",
-		argLen: 3,
-		asm:    arm.AADD,
+		name:        "VMULPS256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMULPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SUBshiftLLreg",
-		argLen: 3,
-		asm:    arm.ASUB,
+		name:   "VSCALEFPS256",
+		argLen: 2,
+		asm:    x86.AVSCALEFPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SUBshiftRLreg",
+		name:   "VSCALEFPSMasked256",
 		argLen: 3,
-		asm:    arm.ASUB,
+		asm:    x86.AVSCALEFPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SUBshiftRAreg",
-		argLen: 3,
-		asm:    arm.ASUB,
+		name:        "VMULPSMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMULPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "RSBshiftLLreg",
-		argLen: 3,
-		asm:    arm.ARSB,
+		name:   "VHADDPS256",
+		argLen: 2,
+		asm:    x86.AVHADDPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "RSBshiftRLreg",
-		argLen: 3,
-		asm:    arm.ARSB,
+		name:   "VHSUBPS256",
+		argLen: 2,
+		asm:    x86.AVHSUBPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "RSBshiftRAreg",
-		argLen: 3,
-		asm:    arm.ARSB,
+		name:   "VSQRTPS256",
+		argLen: 1,
+		asm:    x86.AVSQRTPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ANDshiftLLreg",
-		argLen: 3,
-		asm:    arm.AAND,
+		name:   "VSQRTPSMasked256",
+		argLen: 2,
+		asm:    x86.AVSQRTPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ANDshiftRLreg",
-		argLen: 3,
-		asm:    arm.AAND,
+		name:   "VSUBPS256",
+		argLen: 2,
+		asm:    x86.AVSUBPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ANDshiftRAreg",
+		name:   "VSUBPSMasked256",
 		argLen: 3,
-		asm:    arm.AAND,
+		asm:    x86.AVSUBPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ORshiftLLreg",
-		argLen: 3,
-		asm:    arm.AORR,
+		name:        "VADDPD128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVADDPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ORshiftRLreg",
-		argLen: 3,
-		asm:    arm.AORR,
+		name:        "VADDPDMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVADDPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ORshiftRAreg",
-		argLen: 3,
-		asm:    arm.AORR,
+		name:   "VADDSUBPD128",
+		argLen: 2,
+		asm:    x86.AVADDSUBPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "XORshiftLLreg",
-		argLen: 3,
-		asm:    arm.AEOR,
+		name:   "VRCP14PD128",
+		argLen: 1,
+		asm:    x86.AVRCP14PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "XORshiftRLreg",
-		argLen: 3,
-		asm:    arm.AEOR,
+		name:   "VRCP14PDMasked128",
+		argLen: 2,
+		asm:    x86.AVRCP14PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "XORshiftRAreg",
-		argLen: 3,
-		asm:    arm.AEOR,
+		name:   "VRSQRT14PD128",
+		argLen: 1,
+		asm:    x86.AVRSQRT14PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "BICshiftLLreg",
-		argLen: 3,
-		asm:    arm.ABIC,
+		name:   "VRSQRT14PDMasked128",
+		argLen: 2,
+		asm:    x86.AVRSQRT14PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "BICshiftRLreg",
-		argLen: 3,
-		asm:    arm.ABIC,
+		name:   "VCOMPRESSPDMasked128",
+		argLen: 2,
+		asm:    x86.AVCOMPRESSPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "BICshiftRAreg",
-		argLen: 3,
-		asm:    arm.ABIC,
+		name:   "VDIVPD128",
+		argLen: 2,
+		asm:    x86.AVDIVPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MVNshiftLLreg",
-		argLen: 2,
-		asm:    arm.AMVN,
+		name:   "VDIVPDMasked128",
+		argLen: 3,
+		asm:    x86.AVDIVPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MVNshiftRLreg",
-		argLen: 2,
-		asm:    arm.AMVN,
+		name:         "VFMADD213PD128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMADD213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MVNshiftRAreg",
-		argLen: 2,
-		asm:    arm.AMVN,
+		name:         "VFMADD213PDMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMADD213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ADCshiftLLreg",
-		argLen: 4,
-		asm:    arm.AADC,
+		name:         "VFMADDSUB213PD128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMADDSUB213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ADCshiftRLreg",
-		argLen: 4,
-		asm:    arm.AADC,
+		name:         "VFMADDSUB213PDMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMADDSUB213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ADCshiftRAreg",
-		argLen: 4,
-		asm:    arm.AADC,
+		name:         "VFMSUBADD213PD128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMSUBADD213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SBCshiftLLreg",
-		argLen: 4,
-		asm:    arm.ASBC,
+		name:         "VFMSUBADD213PDMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMSUBADD213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SBCshiftRLreg",
-		argLen: 4,
-		asm:    arm.ASBC,
+		name:        "VMAXPD128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMAXPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SBCshiftRAreg",
-		argLen: 4,
-		asm:    arm.ASBC,
+		name:        "VMAXPDMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMAXPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "RSCshiftLLreg",
-		argLen: 4,
-		asm:    arm.ARSC,
+		name:        "VMINPD128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMINPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "RSCshiftRLreg",
-		argLen: 4,
-		asm:    arm.ARSC,
+		name:        "VMINPDMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMINPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "RSCshiftRAreg",
-		argLen: 4,
-		asm:    arm.ARSC,
+		name:        "VMULPD128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMULPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ADDSshiftLLreg",
-		argLen: 3,
-		asm:    arm.AADD,
+		name:   "VSCALEFPD128",
+		argLen: 2,
+		asm:    x86.AVSCALEFPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "ADDSshiftRLreg",
+		name:   "VSCALEFPDMasked128",
 		argLen: 3,
-		asm:    arm.AADD,
+		asm:    x86.AVSCALEFPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ADDSshiftRAreg",
-		argLen: 3,
-		asm:    arm.AADD,
+		name:        "VMULPDMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMULPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SUBSshiftLLreg",
-		argLen: 3,
-		asm:    arm.ASUB,
+		name:   "VHADDPD128",
+		argLen: 2,
+		asm:    x86.AVHADDPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SUBSshiftRLreg",
-		argLen: 3,
-		asm:    arm.ASUB,
+		name:   "VHSUBPD128",
+		argLen: 2,
+		asm:    x86.AVHSUBPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SUBSshiftRAreg",
-		argLen: 3,
-		asm:    arm.ASUB,
+		name:   "VSQRTPD128",
+		argLen: 1,
+		asm:    x86.AVSQRTPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "RSBSshiftLLreg",
-		argLen: 3,
-		asm:    arm.ARSB,
+		name:   "VSQRTPDMasked128",
+		argLen: 2,
+		asm:    x86.AVSQRTPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "RSBSshiftRLreg",
-		argLen: 3,
-		asm:    arm.ARSB,
+		name:   "VSUBPD128",
+		argLen: 2,
+		asm:    x86.AVSUBPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "RSBSshiftRAreg",
+		name:   "VSUBPDMasked128",
 		argLen: 3,
-		asm:    arm.ARSB,
+		asm:    x86.AVSUBPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMP",
-		argLen: 2,
-		asm:    arm.ACMP,
+		name:        "VADDPD256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVADDPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMPconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ACMP,
+		name:        "VADDPDMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVADDPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "CMN",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.ACMN,
+		name:   "VADDSUBPD256",
+		argLen: 2,
+		asm:    x86.AVADDSUBPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMNconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ACMN,
+		name:   "VRCP14PD256",
+		argLen: 1,
+		asm:    x86.AVRCP14PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "TST",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.ATST,
+		name:   "VRCP14PDMasked256",
+		argLen: 2,
+		asm:    x86.AVRCP14PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "TSTconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ATST,
+		name:   "VRSQRT14PD256",
+		argLen: 1,
+		asm:    x86.AVRSQRT14PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "TEQ",
-		argLen:      2,
-		commutative: true,
-		asm:         arm.ATEQ,
+		name:   "VRSQRT14PDMasked256",
+		argLen: 2,
+		asm:    x86.AVRSQRT14PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "TEQconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm.ATEQ,
+		name:   "VCOMPRESSPDMasked256",
+		argLen: 2,
+		asm:    x86.AVCOMPRESSPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPF",
+		name:   "VDIVPD256",
 		argLen: 2,
-		asm:    arm.ACMPF,
+		asm:    x86.AVDIVPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPD",
-		argLen: 2,
-		asm:    arm.ACMPD,
+		name:   "VDIVPDMasked256",
+		argLen: 3,
+		asm:    x86.AVDIVPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMPshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ACMP,
+		name:         "VFMADD213PD256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMADD213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMPshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ACMP,
+		name:         "VFMADD213PDMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMADD213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMPshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ACMP,
+		name:         "VFMADDSUB213PD256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMADDSUB213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMNshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ACMN,
+		name:         "VFMADDSUB213PDMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMADDSUB213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMNshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ACMN,
+		name:         "VFMSUBADD213PD256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMSUBADD213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMNshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ACMN,
+		name:         "VFMSUBADD213PDMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMSUBADD213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "TSTshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ATST,
+		name:        "VMAXPD256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMAXPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "TSTshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ATST,
+		name:        "VMAXPDMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMAXPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "TSTshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ATST,
+		name:        "VMINPD256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMINPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "TEQshiftLL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ATEQ,
+		name:        "VMINPDMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMINPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "TEQshiftRL",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ATEQ,
+		name:        "VMULPD256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMULPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "TEQshiftRA",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     arm.ATEQ,
+		name:   "VSCALEFPD256",
+		argLen: 2,
+		asm:    x86.AVSCALEFPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "CMPshiftLLreg",
+		name:   "VSCALEFPDMasked256",
 		argLen: 3,
-		asm:    arm.ACMP,
+		asm:    x86.AVSCALEFPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPshiftRLreg",
-		argLen: 3,
-		asm:    arm.ACMP,
+		name:        "VMULPDMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMULPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPshiftRAreg",
-		argLen: 3,
-		asm:    arm.ACMP,
+		name:   "VHADDPD256",
+		argLen: 2,
+		asm:    x86.AVHADDPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMNshiftLLreg",
-		argLen: 3,
-		asm:    arm.ACMN,
+		name:   "VHSUBPD256",
+		argLen: 2,
+		asm:    x86.AVHSUBPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMNshiftRLreg",
-		argLen: 3,
-		asm:    arm.ACMN,
+		name:   "VSQRTPD256",
+		argLen: 1,
+		asm:    x86.AVSQRTPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMNshiftRAreg",
-		argLen: 3,
-		asm:    arm.ACMN,
+		name:   "VSQRTPDMasked256",
+		argLen: 2,
+		asm:    x86.AVSQRTPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "TSTshiftLLreg",
-		argLen: 3,
-		asm:    arm.ATST,
+		name:   "VSUBPD256",
+		argLen: 2,
+		asm:    x86.AVSUBPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "TSTshiftRLreg",
+		name:   "VSUBPDMasked256",
 		argLen: 3,
-		asm:    arm.ATST,
+		asm:    x86.AVSUBPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "TSTshiftRAreg",
-		argLen: 3,
-		asm:    arm.ATST,
+		name:        "VADDPD512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVADDPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "TEQshiftLLreg",
-		argLen: 3,
-		asm:    arm.ATEQ,
+		name:        "VADDPDMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVADDPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "TEQshiftRLreg",
-		argLen: 3,
-		asm:    arm.ATEQ,
+		name:   "VRCP14PD512",
+		argLen: 1,
+		asm:    x86.AVRCP14PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "TEQshiftRAreg",
-		argLen: 3,
-		asm:    arm.ATEQ,
+		name:   "VRCP14PDMasked512",
+		argLen: 2,
+		asm:    x86.AVRCP14PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPF0",
+		name:   "VRSQRT14PD512",
 		argLen: 1,
-		asm:    arm.ACMPF,
+		asm:    x86.AVRSQRT14PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "CMPD0",
-		argLen: 1,
-		asm:    arm.ACMPD,
+		name:   "VRSQRT14PDMasked512",
+		argLen: 2,
+		asm:    x86.AVRSQRT14PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:              "MOVWconst",
-		auxType:           auxInt32,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               arm.AMOVW,
+		name:   "VCOMPRESSPDMasked512",
+		argLen: 2,
+		asm:    x86.AVCOMPRESSPD,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:              "MOVFconst",
-		auxType:           auxFloat64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               arm.AMOVF,
+		name:   "VDIVPD512",
+		argLen: 2,
+		asm:    x86.AVDIVPD,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:              "MOVDconst",
-		auxType:           auxFloat64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               arm.AMOVD,
+		name:   "VDIVPDMasked512",
+		argLen: 3,
+		asm:    x86.AVDIVPD,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:              "MOVWaddr",
-		auxType:           auxSymOff,
-		argLen:            1,
-		rematerializeable: true,
-		symEffect:         SymAddr,
-		asm:               arm.AMOVW,
+		name:         "VFMADD213PD512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMADD213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294975488}, // SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVBload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm.AMOVB,
+		name:         "VFMADD213PDMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMADD213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVBUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm.AMOVBU,
+		name:         "VFMADDSUB213PD512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMADDSUB213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVHload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm.AMOVH,
+		name:         "VFMADDSUB213PDMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMADDSUB213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVHUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm.AMOVHU,
+		name:         "VFMSUBADD213PD512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVFMSUBADD213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVWload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm.AMOVW,
+		name:         "VFMSUBADD213PDMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVFMSUBADD213PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVFload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm.AMOVF,
+		name:        "VMAXPD512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMAXPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVDload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm.AMOVD,
+		name:        "VMAXPDMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMAXPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVBstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm.AMOVB,
+		name:        "VMINPD512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMINPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVHstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm.AMOVH,
+		name:        "VMINPDMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMINPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVWstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm.AMOVW,
+		name:        "VMULPD512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVMULPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVFstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm.AMOVF,
+		name:   "VSCALEFPD512",
+		argLen: 2,
+		asm:    x86.AVSCALEFPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVDstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm.AMOVD,
+		name:   "VSCALEFPDMasked512",
+		argLen: 3,
+		asm:    x86.AVSCALEFPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWloadidx",
-		argLen: 3,
-		asm:    arm.AMOVW,
+		name:        "VMULPDMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVMULPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "MOVWloadshiftLL",
-		auxType: auxInt32,
-		argLen:  3,
-		asm:     arm.AMOVW,
+		name:   "VSQRTPD512",
+		argLen: 1,
+		asm:    x86.AVSQRTPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "MOVWloadshiftRL",
-		auxType: auxInt32,
-		argLen:  3,
-		asm:     arm.AMOVW,
+		name:   "VSQRTPDMasked512",
+		argLen: 2,
+		asm:    x86.AVSQRTPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "MOVWloadshiftRA",
-		auxType: auxInt32,
-		argLen:  3,
-		asm:     arm.AMOVW,
+		name:   "VSUBPD512",
+		argLen: 2,
+		asm:    x86.AVSUBPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVBUloadidx",
+		name:   "VSUBPDMasked512",
 		argLen: 3,
-		asm:    arm.AMOVBU,
+		asm:    x86.AVSUBPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVBloadidx",
-		argLen: 3,
-		asm:    arm.AMOVB,
+		name:   "VPABSW256",
+		argLen: 1,
+		asm:    x86.AVPABSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHUloadidx",
-		argLen: 3,
-		asm:    arm.AMOVHU,
+		name:   "VPABSWMasked256",
+		argLen: 2,
+		asm:    x86.AVPABSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHloadidx",
-		argLen: 3,
-		asm:    arm.AMOVH,
+		name:        "VPADDW256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWstoreidx",
-		argLen: 4,
-		asm:    arm.AMOVW,
+		name:        "VPADDWMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "MOVWstoreshiftLL",
-		auxType: auxInt32,
-		argLen:  4,
-		asm:     arm.AMOVW,
+		name:   "VPCOMPRESSWMasked256",
+		argLen: 2,
+		asm:    x86.AVPCOMPRESSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "MOVWstoreshiftRL",
-		auxType: auxInt32,
-		argLen:  4,
-		asm:     arm.AMOVW,
+		name:        "VPCMPEQW256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPEQW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "MOVWstoreshiftRA",
-		auxType: auxInt32,
-		argLen:  4,
-		asm:     arm.AMOVW,
+		name:   "VPCMPGTW256",
+		argLen: 2,
+		asm:    x86.AVPCMPGTW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVBstoreidx",
-		argLen: 4,
-		asm:    arm.AMOVB,
+		name:        "VPMAXSW256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHstoreidx",
-		argLen: 4,
-		asm:    arm.AMOVH,
+		name:        "VPMAXSWMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVBreg",
-		argLen: 1,
-		asm:    arm.AMOVBS,
+		name:        "VPMINSW256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVBUreg",
-		argLen: 1,
-		asm:    arm.AMOVBU,
+		name:        "VPMINSWMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHreg",
-		argLen: 1,
-		asm:    arm.AMOVHS,
+		name:        "VPMULHW256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULHW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHUreg",
-		argLen: 1,
-		asm:    arm.AMOVHU,
+		name:        "VPMULHWMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULHW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWreg",
-		argLen: 1,
-		asm:    arm.AMOVW,
+		name:        "VPMULLW256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "MOVWnop",
-		argLen:       1,
-		resultInArg0: true,
+		name:        "VPMULLWMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWF",
-		argLen: 1,
-		asm:    arm.AMOVWF,
+		name:   "VPMADDWD256",
+		argLen: 2,
+		asm:    x86.AVPMADDWD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 2147483648, // F15
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWD",
-		argLen: 1,
-		asm:    arm.AMOVWD,
+		name:   "VPMADDWDMasked256",
+		argLen: 3,
+		asm:    x86.AVPMADDWD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 2147483648, // F15
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWUF",
-		argLen: 1,
-		asm:    arm.AMOVWF,
+		name:   "VPHADDW256",
+		argLen: 2,
+		asm:    x86.AVPHADDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 2147483648, // F15
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWUD",
-		argLen: 1,
-		asm:    arm.AMOVWD,
+		name:   "VPHSUBW256",
+		argLen: 2,
+		asm:    x86.AVPHSUBW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 2147483648, // F15
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVFW",
+		name:   "VPOPCNTW256",
 		argLen: 1,
-		asm:    arm.AMOVFW,
+		asm:    x86.AVPOPCNTW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-			clobbers: 2147483648, // F15
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVDW",
-		argLen: 1,
-		asm:    arm.AMOVDW,
+		name:   "VPOPCNTWMasked256",
+		argLen: 2,
+		asm:    x86.AVPOPCNTW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 2147483648, // F15
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVFWU",
-		argLen: 1,
-		asm:    arm.AMOVFW,
+		name:        "VPADDSW256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 2147483648, // F15
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVDWU",
-		argLen: 1,
-		asm:    arm.AMOVDW,
+		name:        "VPADDSWMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 2147483648, // F15
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVFD",
-		argLen: 1,
-		asm:    arm.AMOVFD,
+		name:   "VPHADDSW256",
+		argLen: 2,
+		asm:    x86.AVPHADDSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVDF",
-		argLen: 1,
-		asm:    arm.AMOVDF,
+		name:   "VPHSUBSW256",
+		argLen: 2,
+		asm:    x86.AVPHSUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "CMOVWHSconst",
-		auxType:      auxInt32,
-		argLen:       2,
-		resultInArg0: true,
-		asm:          arm.AMOVW,
+		name:   "VPSUBSW256",
+		argLen: 2,
+		asm:    x86.AVPSUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "CMOVWLSconst",
-		auxType:      auxInt32,
-		argLen:       2,
-		resultInArg0: true,
-		asm:          arm.AMOVW,
+		name:   "VPSUBSWMasked256",
+		argLen: 3,
+		asm:    x86.AVPSUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SRAcond",
-		argLen: 3,
-		asm:    arm.ASRA,
+		name:   "VPSLLW256",
+		argLen: 2,
+		asm:    x86.AVPSLLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "CALLstatic",
-		auxType:      auxCallOff,
-		argLen:       1,
-		clobberFlags: true,
-		call:         true,
+		name:   "VPSLLWMasked256",
+		argLen: 3,
+		asm:    x86.AVPSLLW,
 		reg: regInfo{
-			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 		},
 	},
 	{
-		name:         "CALLtail",
-		auxType:      auxCallOff,
-		argLen:       1,
-		clobberFlags: true,
-		call:         true,
-		tailCall:     true,
+		name:   "VPSRAW256",
+		argLen: 2,
+		asm:    x86.AVPSRAW,
 		reg: regInfo{
-			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 		},
 	},
 	{
-		name:         "CALLclosure",
-		auxType:      auxCallOff,
-		argLen:       3,
-		clobberFlags: true,
-		call:         true,
+		name:   "VPSRAWMasked256",
+		argLen: 3,
+		asm:    x86.AVPSRAW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 128},   // R7
-				{0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 		},
 	},
 	{
-		name:         "CALLinter",
-		auxType:      auxCallOff,
-		argLen:       2,
-		clobberFlags: true,
-		call:         true,
+		name:   "VPSLLVW256",
+		argLen: 2,
+		asm:    x86.AVPSLLVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 		},
 	},
 	{
-		name:           "LoweredNilCheck",
-		argLen:         2,
-		nilCheck:       true,
-		faultOnNilArg0: true,
+		name:         "VPSHLDVW256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "Equal",
-		argLen: 1,
+		name:         "VPSHLDVWMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NotEqual",
-		argLen: 1,
+		name:   "VPSLLVWMasked256",
+		argLen: 3,
+		asm:    x86.AVPSLLVW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "LessThan",
-		argLen: 1,
+		name:   "VPSRAVW256",
+		argLen: 2,
+		asm:    x86.AVPSRAVW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "LessEqual",
-		argLen: 1,
+		name:         "VPSHRDVW256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "GreaterThan",
-		argLen: 1,
+		name:         "VPSHRDVWMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "GreaterEqual",
-		argLen: 1,
+		name:   "VPSRAVWMasked256",
+		argLen: 3,
+		asm:    x86.AVPSRAVW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "LessThanU",
-		argLen: 1,
+		name:   "VPSIGNW256",
+		argLen: 2,
+		asm:    x86.AVPSIGNW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "LessEqualU",
-		argLen: 1,
+		name:   "VPSUBW256",
+		argLen: 2,
+		asm:    x86.AVPSUBW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "GreaterThanU",
-		argLen: 1,
+		name:   "VPSUBWMasked256",
+		argLen: 3,
+		asm:    x86.AVPSUBW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "GreaterEqualU",
+		name:   "VPABSW512",
 		argLen: 1,
+		asm:    x86.AVPABSW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "DUFFZERO",
-		auxType:        auxInt64,
-		argLen:         3,
-		faultOnNilArg0: true,
+		name:   "VPABSWMasked512",
+		argLen: 2,
+		asm:    x86.AVPABSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2}, // R1
-				{1, 1}, // R0
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 20482, // R1 R12 R14
 		},
 	},
 	{
-		name:           "DUFFCOPY",
-		auxType:        auxInt64,
-		argLen:         3,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
+		name:        "VPADDW512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4}, // R2
-				{1, 2}, // R1
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-			clobbers: 20487, // R0 R1 R2 R12 R14
 		},
 	},
 	{
-		name:           "LoweredZero",
-		auxType:        auxInt64,
-		argLen:         4,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
+		name:        "VPADDWMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2},     // R1
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 2, // R1
 		},
 	},
 	{
-		name:           "LoweredMove",
-		auxType:        auxInt64,
-		argLen:         4,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
+		name:   "VPCOMPRESSWMasked512",
+		argLen: 2,
+		asm:    x86.AVPCOMPRESSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4},     // R2
-				{1, 2},     // R1
-				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 6, // R1 R2
 		},
 	},
 	{
-		name:      "LoweredGetClosurePtr",
-		argLen:    0,
-		zeroWidth: true,
+		name:        "VPMAXSW512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXSW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 128}, // R7
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerSP",
-		argLen:            1,
-		rematerializeable: true,
+		name:        "VPMAXSWMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXSW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerPC",
-		argLen:            0,
-		rematerializeable: true,
+		name:        "VPMINSW512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINSW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsA",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:        "VPMINSWMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4}, // R2
-				{1, 8}, // R3
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsB",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:        "VPMULHW512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULHW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2}, // R1
-				{1, 4}, // R2
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsC",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:        "VPMULHWMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULHW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1}, // R0
-				{1, 2}, // R1
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicExtendA",
-		auxType: auxInt64,
-		argLen:  4,
-		call:    true,
+		name:        "VPMULLW512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 16}, // R4
-				{1, 4},  // R2
-				{2, 8},  // R3
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicExtendB",
-		auxType: auxInt64,
-		argLen:  4,
-		call:    true,
+		name:        "VPMULLWMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 16}, // R4
-				{1, 2},  // R1
-				{2, 4},  // R2
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicExtendC",
-		auxType: auxInt64,
-		argLen:  4,
-		call:    true,
+		name:   "VPMADDWD512",
+		argLen: 2,
+		asm:    x86.AVPMADDWD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 16}, // R4
-				{1, 1},  // R0
-				{2, 2},  // R1
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "FlagConstant",
-		auxType: auxFlagConstant,
-		argLen:  0,
-		reg:     regInfo{},
+		name:   "VPMADDWDMasked512",
+		argLen: 3,
+		asm:    x86.AVPMADDWD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+		},
 	},
 	{
-		name:   "InvertFlags",
+		name:   "VPOPCNTW512",
 		argLen: 1,
-		reg:    regInfo{},
-	},
-	{
-		name:         "LoweredWB",
-		auxType:      auxInt64,
-		argLen:       1,
-		clobberFlags: true,
+		asm:    x86.AVPOPCNTW,
 		reg: regInfo{
-			clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 256}, // R8
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
-
 	{
-		name:        "ADCSflags",
-		argLen:      3,
-		commutative: true,
-		asm:         arm64.AADCS,
+		name:   "VPOPCNTWMasked512",
+		argLen: 2,
+		asm:    x86.AVPOPCNTW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ADCzerocarry",
-		argLen: 1,
-		asm:    arm64.AADC,
+		name:        "VPADDSW512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDSW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "ADD",
-		argLen:      2,
+		name:        "VPADDSWMasked512",
+		argLen:      3,
 		commutative: true,
-		asm:         arm64.AADD,
+		asm:         x86.AVPADDSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.AADD,
+		name:   "VPSUBSW512",
+		argLen: 2,
+		asm:    x86.AVPSUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1476395007}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "ADDSconstflags",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.AADDS,
+		name:   "VPSUBSWMasked512",
+		argLen: 3,
+		asm:    x86.AVPSUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "ADDSflags",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.AADDS,
+		name:   "VPSLLW512",
+		argLen: 2,
+		asm:    x86.AVPSLLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 2147418112},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SUB",
-		argLen: 2,
-		asm:    arm64.ASUB,
+		name:   "VPSLLWMasked512",
+		argLen: 3,
+		asm:    x86.AVPSLLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "SUBconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.ASUB,
+		name:   "VPSRAW512",
+		argLen: 2,
+		asm:    x86.AVPSRAW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 2147418112},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SBCSflags",
+		name:   "VPSRAWMasked512",
 		argLen: 3,
-		asm:    arm64.ASBCS,
+		asm:    x86.AVPSRAW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SUBSflags",
+		name:   "VPSLLVW512",
 		argLen: 2,
-		asm:    arm64.ASUBS,
+		asm:    x86.AVPSLLVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "MUL",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.AMUL,
+		name:         "VPSHLDVW512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MULW",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.AMULW,
+		name:         "VPSHLDVWMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MNEG",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.AMNEG,
+		name:   "VPSLLVWMasked512",
+		argLen: 3,
+		asm:    x86.AVPSLLVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MNEGW",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.AMNEGW,
+		name:   "VPSRAVW512",
+		argLen: 2,
+		asm:    x86.AVPSRAVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "MULH",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.ASMULH,
+		name:         "VPSHRDVW512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "UMULH",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.AUMULH,
+		name:         "VPSHRDVWMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MULL",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.ASMULL,
+		name:   "VPSRAVWMasked512",
+		argLen: 3,
+		asm:    x86.AVPSRAVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "UMULL",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.AUMULL,
+		name:   "VPSUBW512",
+		argLen: 2,
+		asm:    x86.AVPSUBW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "DIV",
-		argLen: 2,
-		asm:    arm64.ASDIV,
+		name:   "VPSUBWMasked512",
+		argLen: 3,
+		asm:    x86.AVPSUBW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "UDIV",
-		argLen: 2,
-		asm:    arm64.AUDIV,
+		name:   "VPABSW128",
+		argLen: 1,
+		asm:    x86.AVPABSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "DIVW",
+		name:   "VPABSWMasked128",
 		argLen: 2,
-		asm:    arm64.ASDIVW,
+		asm:    x86.AVPABSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "UDIVW",
-		argLen: 2,
-		asm:    arm64.AUDIVW,
+		name:        "VPADDW128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOD",
-		argLen: 2,
-		asm:    arm64.AREM,
+		name:        "VPADDWMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "UMOD",
+		name:   "VPCOMPRESSWMasked128",
 		argLen: 2,
-		asm:    arm64.AUREM,
+		asm:    x86.AVPCOMPRESSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MODW",
-		argLen: 2,
-		asm:    arm64.AREMW,
+		name:        "VPCMPEQW128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPEQW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "UMODW",
+		name:   "VPCMPGTW128",
 		argLen: 2,
-		asm:    arm64.AUREMW,
+		asm:    x86.AVPCMPGTW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "FADDS",
+		name:        "VPMAXSW128",
 		argLen:      2,
 		commutative: true,
-		asm:         arm64.AFADDS,
+		asm:         x86.AVPMAXSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "FADDD",
-		argLen:      2,
+		name:        "VPMAXSWMasked128",
+		argLen:      3,
 		commutative: true,
-		asm:         arm64.AFADDD,
+		asm:         x86.AVPMAXSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FSUBS",
-		argLen: 2,
-		asm:    arm64.AFSUBS,
+		name:        "VPMINSW128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FSUBD",
-		argLen: 2,
-		asm:    arm64.AFSUBD,
+		name:        "VPMINSWMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "FMULS",
+		name:        "VPMULHW128",
 		argLen:      2,
 		commutative: true,
-		asm:         arm64.AFMULS,
+		asm:         x86.AVPMULHW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "FMULD",
-		argLen:      2,
+		name:        "VPMULHWMasked128",
+		argLen:      3,
 		commutative: true,
-		asm:         arm64.AFMULD,
+		asm:         x86.AVPMULHW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "FNMULS",
+		name:        "VPMULLW128",
 		argLen:      2,
 		commutative: true,
-		asm:         arm64.AFNMULS,
+		asm:         x86.AVPMULLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "FNMULD",
-		argLen:      2,
+		name:        "VPMULLWMasked128",
+		argLen:      3,
 		commutative: true,
-		asm:         arm64.AFNMULD,
+		asm:         x86.AVPMULLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FDIVS",
+		name:   "VPMADDWD128",
 		argLen: 2,
-		asm:    arm64.AFDIVS,
+		asm:    x86.AVPMADDWD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FDIVD",
-		argLen: 2,
-		asm:    arm64.AFDIVD,
+		name:   "VPMADDWDMasked128",
+		argLen: 3,
+		asm:    x86.AVPMADDWD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "AND",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.AAND,
+		name:   "VPHADDW128",
+		argLen: 2,
+		asm:    x86.AVPHADDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ANDconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.AAND,
+		name:   "VPHSUBW128",
+		argLen: 2,
+		asm:    x86.AVPHSUBW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "OR",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.AORR,
+		name:   "VPOPCNTW128",
+		argLen: 1,
+		asm:    x86.AVPOPCNTW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "ORconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.AORR,
+		name:   "VPOPCNTWMasked128",
+		argLen: 2,
+		asm:    x86.AVPOPCNTW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "XOR",
+		name:        "VPADDSW128",
 		argLen:      2,
 		commutative: true,
-		asm:         arm64.AEOR,
+		asm:         x86.AVPADDSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "XORconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.AEOR,
+		name:        "VPADDSWMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "BIC",
+		name:   "VPHADDSW128",
 		argLen: 2,
-		asm:    arm64.ABIC,
+		asm:    x86.AVPHADDSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "EON",
+		name:   "VPHSUBSW128",
 		argLen: 2,
-		asm:    arm64.AEON,
+		asm:    x86.AVPHSUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ORN",
+		name:   "VPSUBSW128",
 		argLen: 2,
-		asm:    arm64.AORN,
+		asm:    x86.AVPSUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MVN",
-		argLen: 1,
-		asm:    arm64.AMVN,
+		name:   "VPSUBSWMasked128",
+		argLen: 3,
+		asm:    x86.AVPSUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NEG",
-		argLen: 1,
-		asm:    arm64.ANEG,
+		name:   "VPSLLW128",
+		argLen: 2,
+		asm:    x86.AVPSLLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NEGSflags",
-		argLen: 1,
-		asm:    arm64.ANEGS,
+		name:   "VPSLLWMasked128",
+		argLen: 3,
+		asm:    x86.AVPSLLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "NGCzerocarry",
-		argLen: 1,
-		asm:    arm64.ANGC,
+		name:   "VPSRAW128",
+		argLen: 2,
+		asm:    x86.AVPSRAW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FABSD",
-		argLen: 1,
-		asm:    arm64.AFABSD,
+		name:   "VPSRAWMasked128",
+		argLen: 3,
+		asm:    x86.AVPSRAW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FNEGS",
-		argLen: 1,
-		asm:    arm64.AFNEGS,
+		name:   "VPSLLVW128",
+		argLen: 2,
+		asm:    x86.AVPSLLVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FNEGD",
-		argLen: 1,
-		asm:    arm64.AFNEGD,
+		name:         "VPSHLDVW128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FSQRTD",
-		argLen: 1,
-		asm:    arm64.AFSQRTD,
+		name:         "VPSHLDVWMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FSQRTS",
-		argLen: 1,
-		asm:    arm64.AFSQRTS,
+		name:   "VPSLLVWMasked128",
+		argLen: 3,
+		asm:    x86.AVPSLLVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMIND",
+		name:   "VPSRAVW128",
 		argLen: 2,
-		asm:    arm64.AFMIND,
+		asm:    x86.AVPSRAVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FMINS",
-		argLen: 2,
-		asm:    arm64.AFMINS,
+		name:         "VPSHRDVW128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMAXD",
-		argLen: 2,
-		asm:    arm64.AFMAXD,
+		name:         "VPSHRDVWMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMAXS",
-		argLen: 2,
-		asm:    arm64.AFMAXS,
+		name:   "VPSRAVWMasked128",
+		argLen: 3,
+		asm:    x86.AVPSRAVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "REV",
-		argLen: 1,
-		asm:    arm64.AREV,
+		name:   "VPSIGNW128",
+		argLen: 2,
+		asm:    x86.AVPSIGNW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "REVW",
-		argLen: 1,
-		asm:    arm64.AREVW,
+		name:   "VPSUBW128",
+		argLen: 2,
+		asm:    x86.AVPSUBW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "REV16",
-		argLen: 1,
-		asm:    arm64.AREV16,
+		name:   "VPSUBWMasked128",
+		argLen: 3,
+		asm:    x86.AVPSUBW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "REV16W",
+		name:   "VPABSD512",
 		argLen: 1,
-		asm:    arm64.AREV16W,
+		asm:    x86.AVPABSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "RBIT",
-		argLen: 1,
-		asm:    arm64.ARBIT,
+		name:   "VPABSDMasked512",
+		argLen: 2,
+		asm:    x86.AVPABSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "RBITW",
-		argLen: 1,
-		asm:    arm64.ARBITW,
+		name:        "VPADDD512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "CLZ",
-		argLen: 1,
-		asm:    arm64.ACLZ,
+		name:        "VPADDDMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CLZW",
-		argLen: 1,
-		asm:    arm64.ACLZW,
+		name:        "VPANDD512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPANDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "VCNT",
-		argLen: 1,
-		asm:    arm64.AVCNT,
+		name:        "VPANDDMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPANDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "VUADDLV",
-		argLen: 1,
-		asm:    arm64.AVUADDLV,
+		name:   "VPANDND512",
+		argLen: 2,
+		asm:    x86.AVPANDND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:         "LoweredRound32F",
-		argLen:       1,
-		resultInArg0: true,
-		zeroWidth:    true,
+		name:   "VPANDNDMasked512",
+		argLen: 3,
+		asm:    x86.AVPANDND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "LoweredRound64F",
-		argLen:       1,
-		resultInArg0: true,
-		zeroWidth:    true,
+		name:   "VPCOMPRESSDMasked512",
+		argLen: 2,
+		asm:    x86.AVPCOMPRESSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMADDS",
-		argLen: 3,
-		asm:    arm64.AFMADDS,
+		name:        "VPMAXSD512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FMADDD",
-		argLen: 3,
-		asm:    arm64.AFMADDD,
+		name:        "VPMAXSDMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FNMADDS",
-		argLen: 3,
-		asm:    arm64.AFNMADDS,
+		name:        "VPMINSD512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FNMADDD",
-		argLen: 3,
-		asm:    arm64.AFNMADDD,
+		name:        "VPMINSDMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMSUBS",
-		argLen: 3,
-		asm:    arm64.AFMSUBS,
+		name:        "VPMULLD512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FMSUBD",
-		argLen: 3,
-		asm:    arm64.AFMSUBD,
+		name:        "VPMULLDMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FNMSUBS",
-		argLen: 3,
-		asm:    arm64.AFNMSUBS,
+		name:        "VPORD512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FNMSUBD",
-		argLen: 3,
-		asm:    arm64.AFNMSUBD,
+		name:        "VPORDMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MADD",
-		argLen: 3,
-		asm:    arm64.AMADD,
+		name:         "VPDPWSSD512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPDPWSSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MADDW",
-		argLen: 3,
-		asm:    arm64.AMADDW,
+		name:         "VPDPWSSDMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPDPWSSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MSUB",
-		argLen: 3,
-		asm:    arm64.AMSUB,
+		name:   "VPOPCNTD512",
+		argLen: 1,
+		asm:    x86.AVPOPCNTD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MSUBW",
-		argLen: 3,
-		asm:    arm64.AMSUBW,
+		name:   "VPOPCNTDMasked512",
+		argLen: 2,
+		asm:    x86.AVPOPCNTD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SLL",
+		name:   "VPROLVD512",
 		argLen: 2,
-		asm:    arm64.ALSL,
+		asm:    x86.AVPROLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "SLLconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.ALSL,
+		name:   "VPROLVDMasked512",
+		argLen: 3,
+		asm:    x86.AVPROLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SRL",
+		name:   "VPRORVD512",
 		argLen: 2,
-		asm:    arm64.ALSR,
+		asm:    x86.AVPRORVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "SRLconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.ALSR,
+		name:   "VPRORVDMasked512",
+		argLen: 3,
+		asm:    x86.AVPRORVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SRA",
-		argLen: 2,
-		asm:    arm64.AASR,
+		name:         "VPDPWSSDS512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPDPWSSDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SRAconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.AASR,
+		name:         "VPDPWSSDSMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPDPWSSDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ROR",
-		argLen: 2,
-		asm:    arm64.AROR,
+		name:         "VPDPBUSDS512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPDPBUSDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "RORW",
-		argLen: 2,
-		asm:    arm64.ARORW,
+		name:         "VPDPBUSDSMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPDPBUSDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "RORconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.AROR,
+		name:   "VPSLLD512",
+		argLen: 2,
+		asm:    x86.AVPSLLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 2147418112},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "RORWconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.ARORW,
+		name:   "VPSLLDMasked512",
+		argLen: 3,
+		asm:    x86.AVPSLLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "EXTRconst",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AEXTR,
+		name:   "VPSRAD512",
+		argLen: 2,
+		asm:    x86.AVPSRAD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 2147418112},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "EXTRWconst",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AEXTRW,
+		name:   "VPSRADMasked512",
+		argLen: 3,
+		asm:    x86.AVPSRAD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "CMP",
+		name:   "VPSLLVD512",
 		argLen: 2,
-		asm:    arm64.ACMP,
+		asm:    x86.AVPSLLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "CMPconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.ACMP,
+		name:         "VPSHLDVD512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPW",
-		argLen: 2,
-		asm:    arm64.ACMPW,
+		name:         "VPSHLDVDMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMPWconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm64.ACMPW,
+		name:   "VPSLLVDMasked512",
+		argLen: 3,
+		asm:    x86.AVPSLLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "CMN",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.ACMN,
+		name:   "VPSRAVD512",
+		argLen: 2,
+		asm:    x86.AVPSRAVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "CMNconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.ACMN,
+		name:         "VPSHRDVD512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "CMNW",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.ACMNW,
+		name:         "VPSHRDVDMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMNWconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm64.ACMNW,
+		name:   "VPSRAVDMasked512",
+		argLen: 3,
+		asm:    x86.AVPSRAVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "TST",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.ATST,
+		name:   "VPSUBD512",
+		argLen: 2,
+		asm:    x86.AVPSUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "TSTconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.ATST,
+		name:   "VPSUBDMasked512",
+		argLen: 3,
+		asm:    x86.AVPSUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-		},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+		},
 	},
 	{
-		name:        "TSTW",
-		argLen:      2,
-		commutative: true,
-		asm:         arm64.ATSTW,
+		name:         "VPDPBUSD512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPDPBUSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "TSTWconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     arm64.ATSTW,
+		name:         "VPDPBUSDMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPDPBUSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FCMPS",
-		argLen: 2,
-		asm:    arm64.AFCMPS,
+		name:        "VPXORD512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPXORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FCMPD",
-		argLen: 2,
-		asm:    arm64.AFCMPD,
+		name:        "VPXORDMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPXORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FCMPS0",
+		name:   "VPABSD128",
 		argLen: 1,
-		asm:    arm64.AFCMPS,
+		asm:    x86.AVPABSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FCMPD0",
-		argLen: 1,
-		asm:    arm64.AFCMPD,
+		name:   "VPABSDMasked128",
+		argLen: 2,
+		asm:    x86.AVPABSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "MVNshiftLL",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.AMVN,
+		name:        "VPADDD128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "MVNshiftRL",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.AMVN,
+		name:        "VPADDDMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "MVNshiftRA",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.AMVN,
+		name:        "VPANDDMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPANDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "MVNshiftRO",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.AMVN,
+		name:   "VPANDNDMasked128",
+		argLen: 3,
+		asm:    x86.AVPANDND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "NEGshiftLL",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.ANEG,
+		name:   "VPCOMPRESSDMasked128",
+		argLen: 2,
+		asm:    x86.AVPCOMPRESSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "NEGshiftRL",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.ANEG,
+		name:        "VPCMPEQD128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPEQD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "NEGshiftRA",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     arm64.ANEG,
+		name:   "VPCMPGTD128",
+		argLen: 2,
+		asm:    x86.AVPCMPGTD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDshiftLL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AADD,
+		name:        "VPMAXSD128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDshiftRL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AADD,
+		name:        "VPMAXSDMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDshiftRA",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AADD,
+		name:        "VPMINSD128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SUBshiftLL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ASUB,
+		name:        "VPMINSDMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SUBshiftRL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ASUB,
+		name:        "VPMULDQ128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SUBshiftRA",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ASUB,
+		name:        "VPMULLD128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ANDshiftLL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AAND,
+		name:        "VPMULLDMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ANDshiftRL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AAND,
+		name:        "VPORDMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ANDshiftRA",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AAND,
+		name:         "VPDPWSSD128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPDPWSSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ANDshiftRO",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AAND,
+		name:         "VPDPWSSDMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPDPWSSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ORshiftLL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AORR,
+		name:   "VPHADDD128",
+		argLen: 2,
+		asm:    x86.AVPHADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ORshiftRL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AORR,
+		name:   "VPHSUBD128",
+		argLen: 2,
+		asm:    x86.AVPHSUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ORshiftRA",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AORR,
+		name:   "VPOPCNTD128",
+		argLen: 1,
+		asm:    x86.AVPOPCNTD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "ORshiftRO",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AORR,
+		name:   "VPOPCNTDMasked128",
+		argLen: 2,
+		asm:    x86.AVPOPCNTD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "XORshiftLL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AEOR,
+		name:   "VPROLVD128",
+		argLen: 2,
+		asm:    x86.AVPROLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "XORshiftRL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AEOR,
+		name:   "VPROLVDMasked128",
+		argLen: 3,
+		asm:    x86.AVPROLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "XORshiftRA",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AEOR,
+		name:   "VPRORVD128",
+		argLen: 2,
+		asm:    x86.AVPRORVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "XORshiftRO",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AEOR,
+		name:   "VPRORVDMasked128",
+		argLen: 3,
+		asm:    x86.AVPRORVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "BICshiftLL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ABIC,
+		name:         "VPDPWSSDS128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPDPWSSDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "BICshiftRL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ABIC,
+		name:         "VPDPWSSDSMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPDPWSSDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "BICshiftRA",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ABIC,
+		name:         "VPDPBUSDS128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPDPBUSDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "BICshiftRO",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ABIC,
+		name:         "VPDPBUSDSMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPDPBUSDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "EONshiftLL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AEON,
+		name:   "VPSLLD128",
+		argLen: 2,
+		asm:    x86.AVPSLLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "EONshiftRL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AEON,
+		name:   "VPSLLDMasked128",
+		argLen: 3,
+		asm:    x86.AVPSLLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "EONshiftRA",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AEON,
+		name:   "VPSRAD128",
+		argLen: 2,
+		asm:    x86.AVPSRAD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "EONshiftRO",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AEON,
+		name:   "VPSRADMasked128",
+		argLen: 3,
+		asm:    x86.AVPSRAD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "ORNshiftLL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AORN,
+		name:   "VPSLLVD128",
+		argLen: 2,
+		asm:    x86.AVPSLLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ORNshiftRL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AORN,
+		name:         "VPSHLDVD128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ORNshiftRA",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AORN,
+		name:         "VPSHLDVDMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ORNshiftRO",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.AORN,
+		name:   "VPSLLVDMasked128",
+		argLen: 3,
+		asm:    x86.AVPSLLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMPshiftLL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ACMP,
+		name:   "VPSRAVD128",
+		argLen: 2,
+		asm:    x86.AVPSRAVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMPshiftRL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ACMP,
+		name:         "VPSHRDVD128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMPshiftRA",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ACMP,
+		name:         "VPSHRDVDMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMNshiftLL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ACMN,
+		name:   "VPSRAVDMasked128",
+		argLen: 3,
+		asm:    x86.AVPSRAVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMNshiftRL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ACMN,
+		name:   "VPSIGND128",
+		argLen: 2,
+		asm:    x86.AVPSIGND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CMNshiftRA",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ACMN,
+		name:   "VPSUBD128",
+		argLen: 2,
+		asm:    x86.AVPSUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "TSTshiftLL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ATST,
+		name:   "VPSUBDMasked128",
+		argLen: 3,
+		asm:    x86.AVPSUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "TSTshiftRL",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ATST,
+		name:         "VPDPBUSD128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPDPBUSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "TSTshiftRA",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ATST,
+		name:         "VPDPBUSDMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPDPBUSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "TSTshiftRO",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     arm64.ATST,
+		name:        "VPXORDMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPXORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "BFI",
-		auxType:      auxARM64BitField,
-		argLen:       2,
-		resultInArg0: true,
-		asm:          arm64.ABFI,
+		name:   "VPABSD256",
+		argLen: 1,
+		asm:    x86.AVPABSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "BFXIL",
-		auxType:      auxARM64BitField,
-		argLen:       2,
-		resultInArg0: true,
-		asm:          arm64.ABFXIL,
+		name:   "VPABSDMasked256",
+		argLen: 2,
+		asm:    x86.AVPABSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SBFIZ",
-		auxType: auxARM64BitField,
-		argLen:  1,
-		asm:     arm64.ASBFIZ,
+		name:        "VPADDD256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SBFX",
-		auxType: auxARM64BitField,
-		argLen:  1,
-		asm:     arm64.ASBFX,
+		name:        "VPADDDMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "UBFIZ",
-		auxType: auxARM64BitField,
-		argLen:  1,
-		asm:     arm64.AUBFIZ,
+		name:        "VPANDDMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPANDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "UBFX",
-		auxType: auxARM64BitField,
-		argLen:  1,
-		asm:     arm64.AUBFX,
+		name:   "VPANDNDMasked256",
+		argLen: 3,
+		asm:    x86.AVPANDND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:              "MOVDconst",
-		auxType:           auxInt64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               arm64.AMOVD,
+		name:   "VPCOMPRESSDMasked256",
+		argLen: 2,
+		asm:    x86.AVPCOMPRESSD,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:              "FMOVSconst",
-		auxType:           auxFloat64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               arm64.AFMOVS,
+		name:        "VPCMPEQD256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPEQD,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:              "FMOVDconst",
-		auxType:           auxFloat64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               arm64.AFMOVD,
+		name:   "VPCMPGTD256",
+		argLen: 2,
+		asm:    x86.AVPCMPGTD,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:              "MOVDaddr",
-		auxType:           auxSymOff,
-		argLen:            1,
-		rematerializeable: true,
-		symEffect:         SymAddr,
-		asm:               arm64.AMOVD,
+		name:        "VPMAXSD256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037928517632}, // SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVBload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.AMOVB,
+		name:        "VPMAXSDMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVBUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.AMOVBU,
+		name:        "VPMINSD256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVHload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.AMOVH,
+		name:        "VPMINSDMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVHUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.AMOVHU,
+		name:        "VPMULDQ256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVWload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.AMOVW,
+		name:        "VPMULLD256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVWUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.AMOVWU,
+		name:        "VPMULLDMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVDload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.AMOVD,
+		name:        "VPORDMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "FMOVSload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.AFMOVS,
+		name:         "VPDPWSSD256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPDPWSSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "FMOVDload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.AFMOVD,
+		name:         "VPDPWSSDMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPDPWSSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LDP",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.ALDP,
+		name:   "VPHADDD256",
+		argLen: 2,
+		asm:    x86.AVPHADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LDPW",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.ALDPW,
+		name:   "VPHSUBD256",
+		argLen: 2,
+		asm:    x86.AVPHSUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LDPSW",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.ALDPSW,
+		name:   "VPOPCNTD256",
+		argLen: 1,
+		asm:    x86.AVPOPCNTD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "FLDPD",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.AFLDPD,
+		name:   "VPOPCNTDMasked256",
+		argLen: 2,
+		asm:    x86.AVPOPCNTD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "FLDPS",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            arm64.AFLDPS,
+		name:   "VPROLVD256",
+		argLen: 2,
+		asm:    x86.AVPROLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVDloadidx",
+		name:   "VPROLVDMasked256",
 		argLen: 3,
-		asm:    arm64.AMOVD,
+		asm:    x86.AVPROLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWloadidx",
-		argLen: 3,
-		asm:    arm64.AMOVW,
+		name:   "VPRORVD256",
+		argLen: 2,
+		asm:    x86.AVPRORVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVWUloadidx",
+		name:   "VPRORVDMasked256",
 		argLen: 3,
-		asm:    arm64.AMOVWU,
+		asm:    x86.AVPRORVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHloadidx",
-		argLen: 3,
-		asm:    arm64.AMOVH,
+		name:         "VPDPWSSDS256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPDPWSSDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHUloadidx",
-		argLen: 3,
-		asm:    arm64.AMOVHU,
+		name:         "VPDPWSSDSMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPDPWSSDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVBloadidx",
-		argLen: 3,
-		asm:    arm64.AMOVB,
+		name:         "VPDPBUSDS256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPDPBUSDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVBUloadidx",
-		argLen: 3,
-		asm:    arm64.AMOVBU,
+		name:         "VPDPBUSDSMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPDPBUSDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMOVSloadidx",
-		argLen: 3,
-		asm:    arm64.AFMOVS,
+		name:   "VPSLLD256",
+		argLen: 2,
+		asm:    x86.AVPSLLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMOVDloadidx",
+		name:   "VPSLLDMasked256",
 		argLen: 3,
-		asm:    arm64.AFMOVD,
+		asm:    x86.AVPSLLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVHloadidx2",
-		argLen: 3,
-		asm:    arm64.AMOVH,
+		name:   "VPSRAD256",
+		argLen: 2,
+		asm:    x86.AVPSRAD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHUloadidx2",
+		name:   "VPSRADMasked256",
 		argLen: 3,
-		asm:    arm64.AMOVHU,
+		asm:    x86.AVPSRAD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVWloadidx4",
-		argLen: 3,
-		asm:    arm64.AMOVW,
+		name:   "VPSLLVD256",
+		argLen: 2,
+		asm:    x86.AVPSLLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWUloadidx4",
-		argLen: 3,
-		asm:    arm64.AMOVWU,
+		name:         "VPSHLDVD256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVDloadidx8",
-		argLen: 3,
-		asm:    arm64.AMOVD,
+		name:         "VPSHLDVDMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMOVSloadidx4",
+		name:   "VPSLLVDMasked256",
 		argLen: 3,
-		asm:    arm64.AFMOVS,
+		asm:    x86.AVPSLLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMOVDloadidx8",
-		argLen: 3,
-		asm:    arm64.AFMOVD,
+		name:   "VPSRAVD256",
+		argLen: 2,
+		asm:    x86.AVPSRAVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVBstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm64.AMOVB,
+		name:         "VPSHRDVD256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVHstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm64.AMOVH,
+		name:         "VPSHRDVDMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVWstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm64.AMOVW,
+		name:   "VPSRAVDMasked256",
+		argLen: 3,
+		asm:    x86.AVPSRAVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVDstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm64.AMOVD,
+		name:   "VPSIGND256",
+		argLen: 2,
+		asm:    x86.AVPSIGND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "FMOVSstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm64.AFMOVS,
+		name:   "VPSUBD256",
+		argLen: 2,
+		asm:    x86.AVPSUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "FMOVDstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm64.AFMOVD,
+		name:   "VPSUBDMasked256",
+		argLen: 3,
+		asm:    x86.AVPSUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "STP",
-		auxType:        auxSymOff,
-		argLen:         4,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm64.ASTP,
+		name:         "VPDPBUSD256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPDPBUSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "STPW",
-		auxType:        auxSymOff,
-		argLen:         4,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm64.ASTPW,
+		name:         "VPDPBUSDMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPDPBUSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "FSTPD",
-		auxType:        auxSymOff,
-		argLen:         4,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm64.AFSTPD,
+		name:        "VPXORDMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPXORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "FSTPS",
-		auxType:        auxSymOff,
-		argLen:         4,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            arm64.AFSTPS,
+		name:   "VPABSQ128",
+		argLen: 1,
+		asm:    x86.AVPABSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVBstoreidx",
-		argLen: 4,
-		asm:    arm64.AMOVB,
+		name:   "VPABSQMasked128",
+		argLen: 2,
+		asm:    x86.AVPABSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHstoreidx",
-		argLen: 4,
-		asm:    arm64.AMOVH,
+		name:        "VPADDQ128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWstoreidx",
-		argLen: 4,
-		asm:    arm64.AMOVW,
+		name:        "VPADDQMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVDstoreidx",
-		argLen: 4,
-		asm:    arm64.AMOVD,
+		name:        "VPANDQMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPANDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMOVSstoreidx",
-		argLen: 4,
-		asm:    arm64.AFMOVS,
+		name:   "VPANDNQMasked128",
+		argLen: 3,
+		asm:    x86.AVPANDNQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMOVDstoreidx",
-		argLen: 4,
-		asm:    arm64.AFMOVD,
+		name:   "VPCOMPRESSQMasked128",
+		argLen: 2,
+		asm:    x86.AVPCOMPRESSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHstoreidx2",
-		argLen: 4,
-		asm:    arm64.AMOVH,
+		name:        "VPCMPEQQ128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPEQQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWstoreidx4",
-		argLen: 4,
-		asm:    arm64.AMOVW,
+		name:   "VPCMPGTQ128",
+		argLen: 2,
+		asm:    x86.AVPCMPGTQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVDstoreidx8",
-		argLen: 4,
-		asm:    arm64.AMOVD,
+		name:        "VPMAXSQ128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FMOVSstoreidx4",
-		argLen: 4,
-		asm:    arm64.AFMOVS,
+		name:        "VPMAXSQMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMOVDstoreidx8",
-		argLen: 4,
-		asm:    arm64.AFMOVD,
+		name:        "VPMINSQ128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FMOVDgpfp",
-		argLen: 1,
-		asm:    arm64.AFMOVD,
+		name:        "VPMINSQMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMOVDfpgp",
-		argLen: 1,
-		asm:    arm64.AFMOVD,
+		name:        "VPMULDQMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FMOVSgpfp",
-		argLen: 1,
-		asm:    arm64.AFMOVS,
+		name:        "VPMULLQ128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FMOVSfpgp",
-		argLen: 1,
-		asm:    arm64.AFMOVS,
+		name:        "VPMULLQMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVBreg",
-		argLen: 1,
-		asm:    arm64.AMOVB,
+		name:        "VPORQMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVBUreg",
+		name:   "VPOPCNTQ128",
 		argLen: 1,
-		asm:    arm64.AMOVBU,
+		asm:    x86.AVPOPCNTQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVHreg",
-		argLen: 1,
-		asm:    arm64.AMOVH,
+		name:   "VPOPCNTQMasked128",
+		argLen: 2,
+		asm:    x86.AVPOPCNTQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHUreg",
-		argLen: 1,
-		asm:    arm64.AMOVHU,
+		name:   "VPROLVQ128",
+		argLen: 2,
+		asm:    x86.AVPROLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVWreg",
-		argLen: 1,
-		asm:    arm64.AMOVW,
+		name:   "VPROLVQMasked128",
+		argLen: 3,
+		asm:    x86.AVPROLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWUreg",
-		argLen: 1,
-		asm:    arm64.AMOVWU,
+		name:   "VPRORVQ128",
+		argLen: 2,
+		asm:    x86.AVPRORVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVDreg",
-		argLen: 1,
-		asm:    arm64.AMOVD,
+		name:   "VPRORVQMasked128",
+		argLen: 3,
+		asm:    x86.AVPRORVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "MOVDnop",
-		argLen:       1,
-		resultInArg0: true,
+		name:   "VPSLLQ128",
+		argLen: 2,
+		asm:    x86.AVPSLLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SCVTFWS",
-		argLen: 1,
-		asm:    arm64.ASCVTFWS,
+		name:   "VPSLLQMasked128",
+		argLen: 3,
+		asm:    x86.AVPSLLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SCVTFWD",
-		argLen: 1,
-		asm:    arm64.ASCVTFWD,
+		name:   "VPSRAQ128",
+		argLen: 2,
+		asm:    x86.AVPSRAQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 2147418112},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "UCVTFWS",
-		argLen: 1,
-		asm:    arm64.AUCVTFWS,
+		name:   "VPSRAQMasked128",
+		argLen: 3,
+		asm:    x86.AVPSRAQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "UCVTFWD",
-		argLen: 1,
-		asm:    arm64.AUCVTFWD,
+		name:   "VPSLLVQ128",
+		argLen: 2,
+		asm:    x86.AVPSLLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SCVTFS",
-		argLen: 1,
-		asm:    arm64.ASCVTFS,
+		name:         "VPSHLDVQ128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SCVTFD",
-		argLen: 1,
-		asm:    arm64.ASCVTFD,
+		name:         "VPSHLDVQMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "UCVTFS",
-		argLen: 1,
-		asm:    arm64.AUCVTFS,
+		name:   "VPSLLVQMasked128",
+		argLen: 3,
+		asm:    x86.AVPSLLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "UCVTFD",
-		argLen: 1,
-		asm:    arm64.AUCVTFD,
+		name:   "VPSRAVQ128",
+		argLen: 2,
+		asm:    x86.AVPSRAVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FCVTZSSW",
-		argLen: 1,
-		asm:    arm64.AFCVTZSSW,
+		name:         "VPSHRDVQ128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FCVTZSDW",
-		argLen: 1,
-		asm:    arm64.AFCVTZSDW,
+		name:         "VPSHRDVQMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FCVTZUSW",
-		argLen: 1,
-		asm:    arm64.AFCVTZUSW,
+		name:   "VPSRAVQMasked128",
+		argLen: 3,
+		asm:    x86.AVPSRAVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FCVTZUDW",
-		argLen: 1,
-		asm:    arm64.AFCVTZUDW,
+		name:   "VPSUBQ128",
+		argLen: 2,
+		asm:    x86.AVPSUBQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FCVTZSS",
-		argLen: 1,
-		asm:    arm64.AFCVTZSS,
+		name:   "VPSUBQMasked128",
+		argLen: 3,
+		asm:    x86.AVPSUBQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FCVTZSD",
-		argLen: 1,
-		asm:    arm64.AFCVTZSD,
+		name:        "VPXORQMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPXORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FCVTZUS",
+		name:   "VPABSQ256",
 		argLen: 1,
-		asm:    arm64.AFCVTZUS,
+		asm:    x86.AVPABSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FCVTZUD",
-		argLen: 1,
-		asm:    arm64.AFCVTZUD,
+		name:   "VPABSQMasked256",
+		argLen: 2,
+		asm:    x86.AVPABSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FCVTSD",
-		argLen: 1,
-		asm:    arm64.AFCVTSD,
+		name:        "VPADDQ256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FCVTDS",
-		argLen: 1,
-		asm:    arm64.AFCVTDS,
+		name:        "VPADDQMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FRINTAD",
-		argLen: 1,
-		asm:    arm64.AFRINTAD,
+		name:        "VPANDQMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPANDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FRINTMD",
-		argLen: 1,
-		asm:    arm64.AFRINTMD,
+		name:   "VPANDNQMasked256",
+		argLen: 3,
+		asm:    x86.AVPANDNQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FRINTND",
-		argLen: 1,
-		asm:    arm64.AFRINTND,
+		name:   "VPCOMPRESSQMasked256",
+		argLen: 2,
+		asm:    x86.AVPCOMPRESSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FRINTPD",
-		argLen: 1,
-		asm:    arm64.AFRINTPD,
+		name:        "VPCMPEQQ256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPEQQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FRINTZD",
-		argLen: 1,
-		asm:    arm64.AFRINTZD,
+		name:   "VPCMPGTQ256",
+		argLen: 2,
+		asm:    x86.AVPCMPGTQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CSEL",
-		auxType: auxCCop,
-		argLen:  3,
-		asm:     arm64.ACSEL,
+		name:        "VPMAXSQ256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "CSEL0",
-		auxType: auxCCop,
-		argLen:  2,
-		asm:     arm64.ACSEL,
+		name:        "VPMAXSQMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CSINC",
-		auxType: auxCCop,
-		argLen:  3,
-		asm:     arm64.ACSINC,
+		name:        "VPMINSQ256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "CSINV",
-		auxType: auxCCop,
-		argLen:  3,
-		asm:     arm64.ACSINV,
+		name:        "VPMINSQMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CSNEG",
-		auxType: auxCCop,
-		argLen:  3,
-		asm:     arm64.ACSNEG,
+		name:        "VPMULDQMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "CSETM",
-		auxType: auxCCop,
-		argLen:  1,
-		asm:     arm64.ACSETM,
+		name:        "VPMULLQ256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULLQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:         "CALLstatic",
-		auxType:      auxCallOff,
-		argLen:       -1,
-		clobberFlags: true,
-		call:         true,
+		name:        "VPMULLQMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULLQ,
 		reg: regInfo{
-			clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 		},
 	},
 	{
-		name:         "CALLtail",
-		auxType:      auxCallOff,
-		argLen:       -1,
-		clobberFlags: true,
-		call:         true,
-		tailCall:     true,
+		name:        "VPORQMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPORQ,
 		reg: regInfo{
-			clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 		},
 	},
 	{
-		name:         "CALLclosure",
-		auxType:      auxCallOff,
-		argLen:       -1,
-		clobberFlags: true,
-		call:         true,
+		name:   "VPOPCNTQ256",
+		argLen: 1,
+		asm:    x86.AVPOPCNTQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 33554432},   // R26
-				{0, 1409286143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-			clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:         "CALLinter",
-		auxType:      auxCallOff,
-		argLen:       -1,
-		clobberFlags: true,
-		call:         true,
+		name:   "VPOPCNTQMasked256",
+		argLen: 2,
+		asm:    x86.AVPOPCNTQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:           "LoweredNilCheck",
-		argLen:         2,
-		nilCheck:       true,
-		faultOnNilArg0: true,
+		name:   "VPROLVQ256",
+		argLen: 2,
+		asm:    x86.AVPROLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "Equal",
-		argLen: 1,
+		name:   "VPROLVQMasked256",
+		argLen: 3,
+		asm:    x86.AVPROLVQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NotEqual",
-		argLen: 1,
+		name:   "VPRORVQ256",
+		argLen: 2,
+		asm:    x86.AVPRORVQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "LessThan",
-		argLen: 1,
+		name:   "VPRORVQMasked256",
+		argLen: 3,
+		asm:    x86.AVPRORVQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "LessEqual",
-		argLen: 1,
+		name:   "VPSLLQ256",
+		argLen: 2,
+		asm:    x86.AVPSLLQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "GreaterThan",
-		argLen: 1,
+		name:   "VPSLLQMasked256",
+		argLen: 3,
+		asm:    x86.AVPSLLQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "GreaterEqual",
-		argLen: 1,
+		name:   "VPSRAQ256",
+		argLen: 2,
+		asm:    x86.AVPSRAQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 2147418112},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "LessThanU",
-		argLen: 1,
+		name:   "VPSRAQMasked256",
+		argLen: 3,
+		asm:    x86.AVPSRAQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "LessEqualU",
-		argLen: 1,
+		name:   "VPSLLVQ256",
+		argLen: 2,
+		asm:    x86.AVPSLLVQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "GreaterThanU",
-		argLen: 1,
+		name:         "VPSHLDVQ256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "GreaterEqualU",
-		argLen: 1,
+		name:         "VPSHLDVQMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "LessThanF",
-		argLen: 1,
+		name:   "VPSLLVQMasked256",
+		argLen: 3,
+		asm:    x86.AVPSLLVQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "LessEqualF",
-		argLen: 1,
+		name:   "VPSRAVQ256",
+		argLen: 2,
+		asm:    x86.AVPSRAVQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "GreaterThanF",
-		argLen: 1,
+		name:         "VPSHRDVQ256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "GreaterEqualF",
-		argLen: 1,
+		name:         "VPSHRDVQMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NotLessThanF",
-		argLen: 1,
+		name:   "VPSRAVQMasked256",
+		argLen: 3,
+		asm:    x86.AVPSRAVQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NotLessEqualF",
-		argLen: 1,
+		name:   "VPSUBQ256",
+		argLen: 2,
+		asm:    x86.AVPSUBQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NotGreaterThanF",
-		argLen: 1,
+		name:   "VPSUBQMasked256",
+		argLen: 3,
+		asm:    x86.AVPSUBQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NotGreaterEqualF",
-		argLen: 1,
+		name:        "VPXORQMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPXORQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "LessThanNoov",
+		name:   "VPABSQ512",
 		argLen: 1,
+		asm:    x86.AVPABSQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "GreaterEqualNoov",
-		argLen: 1,
+		name:   "VPABSQMasked512",
+		argLen: 2,
+		asm:    x86.AVPABSQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "DUFFZERO",
-		auxType:     auxInt64,
+		name:        "VPADDQ512",
 		argLen:      2,
-		unsafePoint: true,
+		commutative: true,
+		asm:         x86.AVPADDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 524288}, // R20
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-			clobbers: 269156352, // R16 R17 R20 R30
 		},
 	},
 	{
-		name:           "LoweredZero",
-		argLen:         3,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
+		name:        "VPADDQMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 65536},     // R16
-				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 65536, // R16
 		},
 	},
 	{
-		name:        "DUFFCOPY",
-		auxType:     auxInt64,
-		argLen:      3,
-		unsafePoint: true,
+		name:        "VPANDQ512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPANDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1048576}, // R21
-				{1, 524288},  // R20
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-			clobbers: 303759360, // R16 R17 R20 R21 R26 R30
 		},
 	},
 	{
-		name:           "LoweredMove",
-		argLen:         4,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
+		name:        "VPANDQMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPANDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 131072},    // R17
-				{1, 65536},     // R16
-				{2, 318767103}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 16973824, // R16 R17 R25
 		},
 	},
 	{
-		name:      "LoweredGetClosurePtr",
-		argLen:    0,
-		zeroWidth: true,
+		name:   "VPANDNQ512",
+		argLen: 2,
+		asm:    x86.AVPANDNQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 33554432}, // R26
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerSP",
-		argLen:            1,
-		rematerializeable: true,
+		name:   "VPANDNQMasked512",
+		argLen: 3,
+		asm:    x86.AVPANDNQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerPC",
-		argLen:            0,
-		rematerializeable: true,
+		name:   "VPCOMPRESSQMasked512",
+		argLen: 2,
+		asm:    x86.AVPCOMPRESSQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "FlagConstant",
-		auxType: auxFlagConstant,
-		argLen:  0,
-		reg:     regInfo{},
-	},
-	{
-		name:   "InvertFlags",
-		argLen: 1,
-		reg:    regInfo{},
+		name:        "VPMAXSQ512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXSQ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+		},
 	},
 	{
-		name:           "LDAR",
-		argLen:         2,
-		faultOnNilArg0: true,
-		asm:            arm64.ALDAR,
+		name:        "VPMAXSQMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LDARB",
-		argLen:         2,
-		faultOnNilArg0: true,
-		asm:            arm64.ALDARB,
+		name:        "VPMINSQ512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "LDARW",
-		argLen:         2,
-		faultOnNilArg0: true,
-		asm:            arm64.ALDARW,
+		name:        "VPMINSQMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINSQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "STLRB",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		asm:            arm64.ASTLRB,
+		name:        "VPMULDQ512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "STLR",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		asm:            arm64.ASTLR,
+		name:        "VPMULDQMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "STLRW",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		asm:            arm64.ASTLRW,
+		name:        "VPMULLQ512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange64",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:        "VPMULLQMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange32",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:        "VPORQ512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange8",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:        "VPORQMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange64Variant",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "VPOPCNTQ512",
+		argLen: 1,
+		asm:    x86.AVPOPCNTQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange32Variant",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "VPOPCNTQMasked512",
+		argLen: 2,
+		asm:    x86.AVPOPCNTQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange8Variant",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:   "VPROLVQ512",
+		argLen: 2,
+		asm:    x86.AVPROLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAdd64",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:   "VPROLVQMasked512",
+		argLen: 3,
+		asm:    x86.AVPROLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAdd32",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:   "VPRORVQ512",
+		argLen: 2,
+		asm:    x86.AVPRORVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAdd64Variant",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "VPRORVQMasked512",
+		argLen: 3,
+		asm:    x86.AVPRORVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAdd32Variant",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "VPSLLQ512",
+		argLen: 2,
+		asm:    x86.AVPSLLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{1, 2147418112},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas64",
-		argLen:          4,
-		resultNotInArgs: true,
-		clobberFlags:    true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:   "VPSLLQMasked512",
+		argLen: 3,
+		asm:    x86.AVPSLLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas32",
-		argLen:          4,
-		resultNotInArgs: true,
-		clobberFlags:    true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:   "VPSRAQ512",
+		argLen: 2,
+		asm:    x86.AVPSRAQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{1, 2147418112},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas64Variant",
-		argLen:          4,
-		resultNotInArgs: true,
-		clobberFlags:    true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:   "VPSRAQMasked512",
+		argLen: 3,
+		asm:    x86.AVPSRAQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas32Variant",
-		argLen:          4,
-		resultNotInArgs: true,
-		clobberFlags:    true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:   "VPSLLVQ512",
+		argLen: 2,
+		asm:    x86.AVPSLLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAnd8",
-		argLen:          3,
-		resultNotInArgs: true,
-		needIntTemp:     true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
-		asm:             arm64.AAND,
+		name:         "VPSHLDVQ512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicOr8",
-		argLen:          3,
-		resultNotInArgs: true,
-		needIntTemp:     true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
-		asm:             arm64.AORR,
+		name:         "VPSHLDVQMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHLDVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAnd64",
-		argLen:          3,
-		resultNotInArgs: true,
-		needIntTemp:     true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
-		asm:             arm64.AAND,
+		name:   "VPSLLVQMasked512",
+		argLen: 3,
+		asm:    x86.AVPSLLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicOr64",
-		argLen:          3,
-		resultNotInArgs: true,
-		needIntTemp:     true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
-		asm:             arm64.AORR,
+		name:   "VPSRAVQ512",
+		argLen: 2,
+		asm:    x86.AVPSRAVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAnd32",
-		argLen:          3,
-		resultNotInArgs: true,
-		needIntTemp:     true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
-		asm:             arm64.AAND,
+		name:         "VPSHRDVQ512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicOr32",
-		argLen:          3,
-		resultNotInArgs: true,
-		needIntTemp:     true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
-		asm:             arm64.AORR,
+		name:         "VPSHRDVQMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPSHRDVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAnd8Variant",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:   "VPSRAVQMasked512",
+		argLen: 3,
+		asm:    x86.AVPSRAVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicOr8Variant",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "VPSUBQ512",
+		argLen: 2,
+		asm:    x86.AVPSUBQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAnd64Variant",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:   "VPSUBQMasked512",
+		argLen: 3,
+		asm:    x86.AVPSUBQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicOr64Variant",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:        "VPXORQ512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPXORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAnd32Variant",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:        "VPXORQMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPXORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicOr32Variant",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "VPABSB128",
+		argLen: 1,
+		asm:    x86.AVPABSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "LoweredWB",
-		auxType:      auxInt64,
-		argLen:       1,
-		clobberFlags: true,
+		name:   "VPABSBMasked128",
+		argLen: 2,
+		asm:    x86.AVPABSB,
 		reg: regInfo{
-			clobbers: 9223372034975924224, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			inputs: []inputInfo{
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 16777216}, // R25
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsA",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:        "VPADDB128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4}, // R2
-				{1, 8}, // R3
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-		},
-	},
-	{
-		name:    "LoweredPanicBoundsB",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 2}, // R1
-				{1, 4}, // R2
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsC",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:        "VPADDBMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1}, // R0
-				{1, 2}, // R1
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-		},
-	},
-	{
-		name:           "PRFM",
-		auxType:        auxInt64,
-		argLen:         2,
-		hasSideEffects: true,
-		asm:            arm64.APRFM,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "DMB",
-		auxType:        auxInt64,
-		argLen:         1,
-		hasSideEffects: true,
-		asm:            arm64.ADMB,
-		reg:            regInfo{},
-	},
-	{
-		name:      "ZERO",
-		argLen:    0,
-		zeroWidth: true,
-		fixedReg:  true,
-		reg:       regInfo{},
-	},
-
-	{
-		name:   "NEGV",
-		argLen: 1,
+		name:        "VPAND128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NEGF",
-		argLen: 1,
-		asm:    loong64.ANEGF,
+		name:   "VPANDN128",
+		argLen: 2,
+		asm:    x86.AVPANDN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NEGD",
-		argLen: 1,
-		asm:    loong64.ANEGD,
+		name:   "VPCOMPRESSBMasked128",
+		argLen: 2,
+		asm:    x86.AVPCOMPRESSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SQRTD",
-		argLen: 1,
-		asm:    loong64.ASQRTD,
+		name:        "VPCMPEQB128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPEQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SQRTF",
-		argLen: 1,
-		asm:    loong64.ASQRTF,
+		name:   "VPCMPGTB128",
+		argLen: 2,
+		asm:    x86.AVPCMPGTB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ABSD",
-		argLen: 1,
-		asm:    loong64.AABSD,
+		name:        "VPMAXSB128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CLZW",
-		argLen: 1,
-		asm:    loong64.ACLZW,
+		name:        "VPMAXSBMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CLZV",
-		argLen: 1,
-		asm:    loong64.ACLZV,
+		name:        "VPMINSB128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CTZW",
-		argLen: 1,
-		asm:    loong64.ACTZW,
+		name:        "VPMINSBMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CTZV",
-		argLen: 1,
-		asm:    loong64.ACTZV,
+		name:        "VPOR128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "REVB2H",
+		name:   "VPOPCNTB128",
 		argLen: 1,
-		asm:    loong64.AREVB2H,
+		asm:    x86.AVPOPCNTB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "REVB2W",
-		argLen: 1,
-		asm:    loong64.AREVB2W,
+		name:   "VPOPCNTBMasked128",
+		argLen: 2,
+		asm:    x86.AVPOPCNTB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "REVBV",
-		argLen: 1,
-		asm:    loong64.AREVBV,
+		name:        "VPADDSB128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "BITREV4B",
-		argLen: 1,
-		asm:    loong64.ABITREV4B,
+		name:        "VPADDSBMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "BITREVW",
-		argLen: 1,
-		asm:    loong64.ABITREVW,
+		name:   "VPSUBSB128",
+		argLen: 2,
+		asm:    x86.AVPSUBSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "BITREVV",
-		argLen: 1,
-		asm:    loong64.ABITREVV,
+		name:   "VPSUBSBMasked128",
+		argLen: 3,
+		asm:    x86.AVPSUBSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "VPCNT64",
-		argLen: 1,
-		asm:    loong64.AVPCNTV,
+		name:   "VPSIGNB128",
+		argLen: 2,
+		asm:    x86.AVPSIGNB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "VPCNT32",
-		argLen: 1,
-		asm:    loong64.AVPCNTW,
+		name:   "VPSUBB128",
+		argLen: 2,
+		asm:    x86.AVPSUBB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "VPCNT16",
-		argLen: 1,
-		asm:    loong64.AVPCNTH,
+		name:   "VPSUBBMasked128",
+		argLen: 3,
+		asm:    x86.AVPSUBB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "ADDV",
+		name:        "VPXOR128",
 		argLen:      2,
 		commutative: true,
-		asm:         loong64.AADDVU,
+		asm:         x86.AVPXOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDVconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.AADDVU,
+		name:   "VPABSB256",
+		argLen: 1,
+		asm:    x86.AVPABSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SUBV",
+		name:   "VPABSBMasked256",
 		argLen: 2,
-		asm:    loong64.ASUBVU,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-			},
-			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
-			},
-		},
-	},
-	{
-		name:    "SUBVconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.ASUBVU,
+		asm:    x86.AVPABSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MULV",
+		name:        "VPADDB256",
 		argLen:      2,
 		commutative: true,
-		asm:         loong64.AMULV,
+		asm:         x86.AVPADDB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MULHV",
-		argLen:      2,
+		name:        "VPADDBMasked256",
+		argLen:      3,
 		commutative: true,
-		asm:         loong64.AMULHV,
+		asm:         x86.AVPADDB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MULHVU",
+		name:        "VPAND256",
 		argLen:      2,
 		commutative: true,
-		asm:         loong64.AMULHVU,
+		asm:         x86.AVPAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "DIVV",
+		name:   "VPANDN256",
 		argLen: 2,
-		asm:    loong64.ADIVV,
+		asm:    x86.AVPANDN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "DIVVU",
+		name:   "VPCOMPRESSBMasked256",
 		argLen: 2,
-		asm:    loong64.ADIVVU,
+		asm:    x86.AVPCOMPRESSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "REMV",
-		argLen: 2,
-		asm:    loong64.AREMV,
+		name:        "VPCMPEQB256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPEQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "REMVU",
+		name:   "VPCMPGTB256",
 		argLen: 2,
-		asm:    loong64.AREMVU,
+		asm:    x86.AVPCMPGTB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "ADDF",
+		name:        "VPMAXSB256",
 		argLen:      2,
 		commutative: true,
-		asm:         loong64.AADDF,
+		asm:         x86.AVPMAXSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "ADDD",
-		argLen:      2,
+		name:        "VPMAXSBMasked256",
+		argLen:      3,
 		commutative: true,
-		asm:         loong64.AADDD,
+		asm:         x86.AVPMAXSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SUBF",
-		argLen: 2,
-		asm:    loong64.ASUBF,
+		name:        "VPMINSB256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SUBD",
-		argLen: 2,
-		asm:    loong64.ASUBD,
+		name:        "VPMINSBMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MULF",
+		name:        "VPOR256",
 		argLen:      2,
 		commutative: true,
-		asm:         loong64.AMULF,
+		asm:         x86.AVPOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MULD",
-		argLen:      2,
-		commutative: true,
-		asm:         loong64.AMULD,
+		name:   "VPOPCNTB256",
+		argLen: 1,
+		asm:    x86.AVPOPCNTB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "DIVF",
+		name:   "VPOPCNTBMasked256",
 		argLen: 2,
-		asm:    loong64.ADIVF,
+		asm:    x86.AVPOPCNTB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "DIVD",
-		argLen: 2,
-		asm:    loong64.ADIVD,
+		name:        "VPADDSB256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "AND",
-		argLen:      2,
+		name:        "VPADDSBMasked256",
+		argLen:      3,
 		commutative: true,
-		asm:         loong64.AAND,
+		asm:         x86.AVPADDSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ANDconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.AAND,
+		name:   "VPSUBSB256",
+		argLen: 2,
+		asm:    x86.AVPSUBSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "OR",
-		argLen:      2,
-		commutative: true,
-		asm:         loong64.AOR,
+		name:   "VPSUBSBMasked256",
+		argLen: 3,
+		asm:    x86.AVPSUBSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ORconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.AOR,
+		name:   "VPSIGNB256",
+		argLen: 2,
+		asm:    x86.AVPSIGNB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "XOR",
-		argLen:      2,
-		commutative: true,
-		asm:         loong64.AXOR,
+		name:   "VPSUBB256",
+		argLen: 2,
+		asm:    x86.AVPSUBB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "XORconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.AXOR,
+		name:   "VPSUBBMasked256",
+		argLen: 3,
+		asm:    x86.AVPSUBB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "NOR",
+		name:        "VPXOR256",
 		argLen:      2,
 		commutative: true,
-		asm:         loong64.ANOR,
+		asm:         x86.AVPXOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "NORconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.ANOR,
+		name:   "VPABSB512",
+		argLen: 1,
+		asm:    x86.AVPABSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "ANDN",
+		name:   "VPABSBMasked512",
 		argLen: 2,
-		asm:    loong64.AANDN,
+		asm:    x86.AVPABSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ORN",
-		argLen: 2,
-		asm:    loong64.AORN,
+		name:        "VPADDB512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "FMADDF",
+		name:        "VPADDBMasked512",
 		argLen:      3,
 		commutative: true,
-		asm:         loong64.AFMADDF,
+		asm:         x86.AVPADDB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "FMADDD",
-		argLen:      3,
-		commutative: true,
-		asm:         loong64.AFMADDD,
+		name:   "VPCOMPRESSBMasked512",
+		argLen: 2,
+		asm:    x86.AVPCOMPRESSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "FMSUBF",
-		argLen:      3,
+		name:        "VPMAXSB512",
+		argLen:      2,
 		commutative: true,
-		asm:         loong64.AFMSUBF,
+		asm:         x86.AVPMAXSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "FMSUBD",
+		name:        "VPMAXSBMasked512",
 		argLen:      3,
 		commutative: true,
-		asm:         loong64.AFMSUBD,
+		asm:         x86.AVPMAXSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "FNMADDF",
-		argLen:      3,
+		name:        "VPMINSB512",
+		argLen:      2,
 		commutative: true,
-		asm:         loong64.AFNMADDF,
+		asm:         x86.AVPMINSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "FNMADDD",
+		name:        "VPMINSBMasked512",
 		argLen:      3,
 		commutative: true,
-		asm:         loong64.AFNMADDD,
+		asm:         x86.AVPMINSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "FNMSUBF",
-		argLen:      3,
-		commutative: true,
-		asm:         loong64.AFNMSUBF,
+		name:   "VPOPCNTB512",
+		argLen: 1,
+		asm:    x86.AVPOPCNTB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "FNMSUBD",
-		argLen:      3,
-		commutative: true,
-		asm:         loong64.AFNMSUBD,
+		name:   "VPOPCNTBMasked512",
+		argLen: 2,
+		asm:    x86.AVPOPCNTB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "FMINF",
-		argLen:          2,
-		commutative:     true,
-		resultNotInArgs: true,
-		asm:             loong64.AFMINF,
+		name:        "VPADDSB512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPADDSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "FMIND",
-		argLen:          2,
-		commutative:     true,
-		resultNotInArgs: true,
-		asm:             loong64.AFMIND,
+		name:        "VPADDSBMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPADDSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "FMAXF",
-		argLen:          2,
-		commutative:     true,
-		resultNotInArgs: true,
-		asm:             loong64.AFMAXF,
+		name:   "VPSUBSB512",
+		argLen: 2,
+		asm:    x86.AVPSUBSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "FMAXD",
-		argLen:          2,
-		commutative:     true,
-		resultNotInArgs: true,
-		asm:             loong64.AFMAXD,
+		name:   "VPSUBSBMasked512",
+		argLen: 3,
+		asm:    x86.AVPSUBSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MASKEQZ",
+		name:   "VPSUBB512",
 		argLen: 2,
-		asm:    loong64.AMASKEQZ,
+		asm:    x86.AVPSUBB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MASKNEZ",
-		argLen: 2,
-		asm:    loong64.AMASKNEZ,
+		name:   "VPSUBBMasked512",
+		argLen: 3,
+		asm:    x86.AVPSUBB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FCOPYSGD",
-		argLen: 2,
-		asm:    loong64.AFCOPYSGD,
+		name:        "VPAVGW256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPAVGW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SLL",
-		argLen: 2,
-		asm:    loong64.ASLL,
+		name:        "VPAVGWMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPAVGW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SLLV",
-		argLen: 2,
-		asm:    loong64.ASLLV,
+		name:        "VPMAXUW256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SLLconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.ASLL,
+		name:        "VPMAXUWMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SLLVconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.ASLLV,
+		name:        "VPMINUW256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SRL",
-		argLen: 2,
-		asm:    loong64.ASRL,
+		name:        "VPMINUWMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SRLV",
-		argLen: 2,
-		asm:    loong64.ASRLV,
+		name:        "VPMULHUW256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULHUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SRLconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.ASRL,
+		name:        "VPMULHUWMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULHUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SRLVconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.ASRLV,
+		name:   "VPERMW256",
+		argLen: 2,
+		asm:    x86.AVPERMW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SRA",
-		argLen: 2,
-		asm:    loong64.ASRA,
+		name:         "VPERMI2W256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2W,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SRAV",
-		argLen: 2,
-		asm:    loong64.ASRAV,
+		name:         "VPERMI2WMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2W,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SRAconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.ASRA,
+		name:   "VPERMWMasked256",
+		argLen: 3,
+		asm:    x86.AVPERMW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SRAVconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.ASRAV,
+		name:   "VPSRLW256",
+		argLen: 2,
+		asm:    x86.AVPSRLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "ROTR",
-		argLen: 2,
-		asm:    loong64.AROTR,
+		name:   "VPSRLWMasked256",
+		argLen: 3,
+		asm:    x86.AVPSRLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "ROTRV",
+		name:   "VPSRLVW256",
 		argLen: 2,
-		asm:    loong64.AROTRV,
+		asm:    x86.AVPSRLVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "ROTRconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.AROTR,
+		name:   "VPSRLVWMasked256",
+		argLen: 3,
+		asm:    x86.AVPSRLVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ROTRVconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.AROTRV,
+		name:        "VPAVGW512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPAVGW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SGT",
-		argLen: 2,
-		asm:    loong64.ASGT,
+		name:        "VPAVGWMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPAVGW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SGTconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.ASGT,
+		name:        "VPMAXUW512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SGTU",
-		argLen: 2,
-		asm:    loong64.ASGTU,
+		name:        "VPMAXUWMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SGTUconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.ASGTU,
+		name:        "VPMINUW512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "CMPEQF",
-		argLen: 2,
-		asm:    loong64.ACMPEQF,
+		name:        "VPMINUWMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPEQD",
-		argLen: 2,
-		asm:    loong64.ACMPEQD,
+		name:        "VPMULHUW512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULHUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "CMPGEF",
-		argLen: 2,
-		asm:    loong64.ACMPGEF,
+		name:        "VPMULHUWMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULHUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPGED",
+		name:   "VPERMW512",
 		argLen: 2,
-		asm:    loong64.ACMPGED,
+		asm:    x86.AVPERMW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "CMPGTF",
-		argLen: 2,
-		asm:    loong64.ACMPGTF,
+		name:         "VPERMI2W512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2W,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPGTD",
-		argLen: 2,
-		asm:    loong64.ACMPGTD,
+		name:         "VPERMI2WMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2W,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "BSTRPICKW",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.ABSTRPICKW,
+		name:   "VPERMWMasked512",
+		argLen: 3,
+		asm:    x86.AVPERMW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "BSTRPICKV",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     loong64.ABSTRPICKV,
+		name:   "VPSRLW512",
+		argLen: 2,
+		asm:    x86.AVPSRLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 2147418112},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:              "MOVVconst",
-		auxType:           auxInt64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               loong64.AMOVV,
+		name:   "VPSRLWMasked512",
+		argLen: 3,
+		asm:    x86.AVPSRLW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:              "MOVFconst",
-		auxType:           auxFloat64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               loong64.AMOVF,
+		name:   "VPSRLVW512",
+		argLen: 2,
+		asm:    x86.AVPSRLVW,
 		reg: regInfo{
-			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-		},
-	},
-	{
-		name:              "MOVDconst",
-		auxType:           auxFloat64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               loong64.AMOVD,
-		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:              "MOVVaddr",
-		auxType:           auxSymOff,
-		argLen:            1,
-		rematerializeable: true,
-		symEffect:         SymAddr,
-		asm:               loong64.AMOVV,
+		name:   "VPSRLVWMasked512",
+		argLen: 3,
+		asm:    x86.AVPSRLVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018427387908}, // SP SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVBload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            loong64.AMOVB,
+		name:        "VPAVGW128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPAVGW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVBUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            loong64.AMOVBU,
+		name:        "VPAVGWMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPAVGW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVHload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            loong64.AMOVH,
+		name:        "VPMAXUW128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVHUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            loong64.AMOVHU,
+		name:        "VPMAXUWMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVWload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            loong64.AMOVW,
+		name:        "VPMINUW128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVWUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            loong64.AMOVWU,
+		name:        "VPMINUWMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVVload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            loong64.AMOVV,
+		name:        "VPMULHUW128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULHUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVFload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            loong64.AMOVF,
+		name:        "VPMULHUWMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULHUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVDload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            loong64.AMOVD,
+		name:   "VPERMW128",
+		argLen: 2,
+		asm:    x86.AVPERMW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVVloadidx",
-		argLen: 3,
-		asm:    loong64.AMOVV,
+		name:         "VPERMI2W128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2W,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWloadidx",
-		argLen: 3,
-		asm:    loong64.AMOVW,
+		name:         "VPERMI2WMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2W,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWUloadidx",
+		name:   "VPERMWMasked128",
 		argLen: 3,
-		asm:    loong64.AMOVWU,
+		asm:    x86.AVPERMW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHloadidx",
-		argLen: 3,
-		asm:    loong64.AMOVH,
+		name:   "VPSRLW128",
+		argLen: 2,
+		asm:    x86.AVPSRLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHUloadidx",
+		name:   "VPSRLWMasked128",
 		argLen: 3,
-		asm:    loong64.AMOVHU,
+		asm:    x86.AVPSRLW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVBloadidx",
-		argLen: 3,
-		asm:    loong64.AMOVB,
+		name:   "VPSRLVW128",
+		argLen: 2,
+		asm:    x86.AVPSRLVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVBUloadidx",
+		name:   "VPSRLVWMasked128",
 		argLen: 3,
-		asm:    loong64.AMOVBU,
+		asm:    x86.AVPSRLVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVFloadidx",
-		argLen: 3,
-		asm:    loong64.AMOVF,
+		name:        "VPMAXUD512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVDloadidx",
-		argLen: 3,
-		asm:    loong64.AMOVD,
+		name:        "VPMAXUDMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVBstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            loong64.AMOVB,
+		name:        "VPMINUD512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVHstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            loong64.AMOVH,
+		name:        "VPMINUDMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVWstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            loong64.AMOVW,
+		name:   "VPERMD512",
+		argLen: 2,
+		asm:    x86.AVPERMD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVVstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            loong64.AMOVV,
+		name:   "VPERMPS512",
+		argLen: 2,
+		asm:    x86.AVPERMPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVFstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            loong64.AMOVF,
+		name:         "VPERMI2PS512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVDstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            loong64.AMOVD,
+		name:         "VPERMI2D512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2D,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVBstoreidx",
-		argLen: 4,
-		asm:    loong64.AMOVB,
+		name:         "VPERMI2PSMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHstoreidx",
-		argLen: 4,
-		asm:    loong64.AMOVH,
+		name:         "VPERMI2DMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2D,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWstoreidx",
-		argLen: 4,
-		asm:    loong64.AMOVW,
+		name:   "VPERMPSMasked512",
+		argLen: 3,
+		asm:    x86.AVPERMPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVVstoreidx",
-		argLen: 4,
-		asm:    loong64.AMOVV,
+		name:   "VPERMDMasked512",
+		argLen: 3,
+		asm:    x86.AVPERMD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVFstoreidx",
-		argLen: 4,
-		asm:    loong64.AMOVF,
+		name:   "VPSRLD512",
+		argLen: 2,
+		asm:    x86.AVPSRLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 2147418112},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVDstoreidx",
-		argLen: 4,
-		asm:    loong64.AMOVD,
+		name:   "VPSRLDMasked512",
+		argLen: 3,
+		asm:    x86.AVPSRLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVBstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            loong64.AMOVB,
+		name:   "VPSRLVD512",
+		argLen: 2,
+		asm:    x86.AVPSRLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVHstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            loong64.AMOVH,
+		name:   "VPSRLVDMasked512",
+		argLen: 3,
+		asm:    x86.AVPSRLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVWstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            loong64.AMOVW,
+		name:        "VPMAXUD128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVVstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            loong64.AMOVV,
+		name:        "VPMAXUDMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVBstorezeroidx",
-		argLen: 3,
-		asm:    loong64.AMOVB,
+		name:        "VPMINUD128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHstorezeroidx",
-		argLen: 3,
-		asm:    loong64.AMOVH,
+		name:        "VPMINUDMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWstorezeroidx",
-		argLen: 3,
-		asm:    loong64.AMOVW,
+		name:        "VPMULUDQ128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULUDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVVstorezeroidx",
-		argLen: 3,
-		asm:    loong64.AMOVV,
+		name:         "VPERMI2D128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2D,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWfpgp",
-		argLen: 1,
-		asm:    loong64.AMOVW,
+		name:         "VPERMI2PS128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWgpfp",
-		argLen: 1,
-		asm:    loong64.AMOVW,
+		name:         "VPERMI2PSMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVVfpgp",
-		argLen: 1,
-		asm:    loong64.AMOVV,
+		name:         "VPERMI2DMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2D,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVVgpfp",
-		argLen: 1,
-		asm:    loong64.AMOVV,
+		name:   "VPSRLD128",
+		argLen: 2,
+		asm:    x86.AVPSRLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVBreg",
-		argLen: 1,
-		asm:    loong64.AMOVB,
+		name:   "VPSRLDMasked128",
+		argLen: 3,
+		asm:    x86.AVPSRLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVBUreg",
-		argLen: 1,
-		asm:    loong64.AMOVBU,
+		name:   "VPSRLVD128",
+		argLen: 2,
+		asm:    x86.AVPSRLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHreg",
-		argLen: 1,
-		asm:    loong64.AMOVH,
+		name:   "VPSRLVDMasked128",
+		argLen: 3,
+		asm:    x86.AVPSRLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHUreg",
-		argLen: 1,
-		asm:    loong64.AMOVHU,
+		name:        "VPMAXUD256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWreg",
-		argLen: 1,
-		asm:    loong64.AMOVW,
+		name:        "VPMAXUDMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWUreg",
-		argLen: 1,
-		asm:    loong64.AMOVWU,
-		reg: regInfo{
+		name:        "VPMINUD256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINUD,
+		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVVreg",
-		argLen: 1,
-		asm:    loong64.AMOVV,
+		name:        "VPMINUDMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "MOVVnop",
-		argLen:       1,
-		resultInArg0: true,
+		name:        "VPMULUDQ256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULUDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWF",
-		argLen: 1,
-		asm:    loong64.AMOVWF,
+		name:   "VPERMPS256",
+		argLen: 2,
+		asm:    x86.AVPERMPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWD",
-		argLen: 1,
-		asm:    loong64.AMOVWD,
+		name:   "VPERMD256",
+		argLen: 2,
+		asm:    x86.AVPERMD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVVF",
-		argLen: 1,
-		asm:    loong64.AMOVVF,
+		name:         "VPERMI2D256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2D,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVVD",
-		argLen: 1,
-		asm:    loong64.AMOVVD,
+		name:         "VPERMI2PS256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "TRUNCFW",
-		argLen: 1,
-		asm:    loong64.ATRUNCFW,
+		name:         "VPERMI2DMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2D,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "TRUNCDW",
-		argLen: 1,
-		asm:    loong64.ATRUNCDW,
+		name:         "VPERMI2PSMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2PS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "TRUNCFV",
-		argLen: 1,
-		asm:    loong64.ATRUNCFV,
+		name:   "VPERMPSMasked256",
+		argLen: 3,
+		asm:    x86.AVPERMPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "TRUNCDV",
-		argLen: 1,
-		asm:    loong64.ATRUNCDV,
+		name:   "VPERMDMasked256",
+		argLen: 3,
+		asm:    x86.AVPERMD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVFD",
-		argLen: 1,
-		asm:    loong64.AMOVFD,
+		name:   "VPSRLD256",
+		argLen: 2,
+		asm:    x86.AVPSRLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVDF",
-		argLen: 1,
-		asm:    loong64.AMOVDF,
+		name:   "VPSRLDMasked256",
+		argLen: 3,
+		asm:    x86.AVPSRLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:         "LoweredRound32F",
-		argLen:       1,
-		resultInArg0: true,
+		name:   "VPSRLVD256",
+		argLen: 2,
+		asm:    x86.AVPSRLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "LoweredRound64F",
-		argLen:       1,
-		resultInArg0: true,
+		name:   "VPSRLVDMasked256",
+		argLen: 3,
+		asm:    x86.AVPSRLVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "CALLstatic",
-		auxType:      auxCallOff,
-		argLen:       -1,
-		clobberFlags: true,
-		call:         true,
-		reg: regInfo{
-			clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-		},
-	},
-	{
-		name:         "CALLtail",
-		auxType:      auxCallOff,
-		argLen:       -1,
-		clobberFlags: true,
-		call:         true,
-		tailCall:     true,
+		name:        "VPMAXUQ128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXUQ,
 		reg: regInfo{
-			clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 		},
 	},
 	{
-		name:         "CALLclosure",
-		auxType:      auxCallOff,
-		argLen:       -1,
-		clobberFlags: true,
-		call:         true,
+		name:        "VPMAXUQMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 268435456},  // R29
-				{0, 1071644668}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:         "CALLinter",
-		auxType:      auxCallOff,
-		argLen:       -1,
-		clobberFlags: true,
-		call:         true,
+		name:        "VPMINUQ128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-			clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:           "DUFFZERO",
-		auxType:        auxInt64,
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:        "VPMINUQMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 524288}, // R20
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 524290, // R1 R20
 		},
 	},
 	{
-		name:           "DUFFCOPY",
-		auxType:        auxInt64,
-		argLen:         3,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
+		name:        "VPMULUDQMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULUDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1048576}, // R21
-				{1, 524288},  // R20
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 1572866, // R1 R20 R21
 		},
 	},
 	{
-		name:           "LoweredZero",
-		auxType:        auxInt64,
-		argLen:         3,
-		faultOnNilArg0: true,
+		name:         "VPERMI2PD128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 524288},     // R20
-				{1, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 524288, // R20
 		},
 	},
 	{
-		name:           "LoweredMove",
-		auxType:        auxInt64,
-		argLen:         4,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
+		name:         "VPERMI2Q128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2Q,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1048576},    // R21
-				{1, 524288},     // R20
-				{2, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 1572864, // R20 R21
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad8",
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:         "VPERMI2PDMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad32",
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:         "VPERMI2QMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2Q,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad64",
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:   "VPSRLQ128",
+		argLen: 2,
+		asm:    x86.AVPSRLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore8",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:   "VPSRLQMasked128",
+		argLen: 3,
+		asm:    x86.AVPSRLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore32",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:   "VPSRLVQ128",
+		argLen: 2,
+		asm:    x86.AVPSRLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore64",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:   "VPSRLVQMasked128",
+		argLen: 3,
+		asm:    x86.AVPSRLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore8Variant",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:        "VPMAXUQ256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore32Variant",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:        "VPMAXUQMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore64Variant",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:        "VPMINUQ256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange32",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:        "VPMINUQMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange64",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:        "VPMULUDQMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULUDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange8Variant",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "VPERMQ256",
+		argLen: 2,
+		asm:    x86.AVPERMQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAdd32",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "VPERMPD256",
+		argLen: 2,
+		asm:    x86.AVPERMPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAdd64",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:         "VPERMI2Q256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2Q,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas32",
-		argLen:          4,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:         "VPERMI2PD256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas64",
-		argLen:          4,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:         "VPERMI2PDMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas64Variant",
-		argLen:          4,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:         "VPERMI2QMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2Q,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas32Variant",
-		argLen:          4,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:   "VPERMQMasked256",
+		argLen: 3,
+		asm:    x86.AVPERMQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAnd32",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		asm:             loong64.AAMANDDBW,
+		name:   "VPERMPDMasked256",
+		argLen: 3,
+		asm:    x86.AVPERMPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicOr32",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		asm:             loong64.AAMORDBW,
+		name:   "VPSRLQ256",
+		argLen: 2,
+		asm:    x86.AVPSRLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAnd32value",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		asm:             loong64.AAMANDDBW,
+		name:   "VPSRLQMasked256",
+		argLen: 3,
+		asm:    x86.AVPSRLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAnd64value",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		asm:             loong64.AAMANDDBV,
+		name:   "VPSRLVQ256",
+		argLen: 2,
+		asm:    x86.AVPSRLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicOr32value",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		asm:             loong64.AAMORDBW,
+		name:   "VPSRLVQMasked256",
+		argLen: 3,
+		asm:    x86.AVPSRLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicOr64value",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		asm:             loong64.AAMORDBV,
+		name:        "VPMAXUQ512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "LoweredNilCheck",
-		argLen:         2,
-		nilCheck:       true,
-		faultOnNilArg0: true,
+		name:        "VPMAXUQMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "FPFlagTrue",
-		argLen: 1,
+		name:        "VPMINUQ512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINUQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FPFlagFalse",
-		argLen: 1,
+		name:        "VPMINUQMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINUQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:      "LoweredGetClosurePtr",
-		argLen:    0,
-		zeroWidth: true,
+		name:        "VPMULUDQ512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMULUDQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 268435456}, // R29
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerSP",
-		argLen:            1,
-		rematerializeable: true,
+		name:        "VPMULUDQMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMULUDQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerPC",
-		argLen:            0,
-		rematerializeable: true,
+		name:   "VPERMPD512",
+		argLen: 2,
+		asm:    x86.AVPERMPD,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:         "LoweredWB",
-		auxType:      auxInt64,
-		argLen:       1,
-		clobberFlags: true,
+		name:   "VPERMQ512",
+		argLen: 2,
+		asm:    x86.AVPERMQ,
 		reg: regInfo{
-			clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 268435456}, // R29
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "LoweredPubBarrier",
-		argLen:         1,
-		hasSideEffects: true,
-		asm:            loong64.ADBAR,
-		reg:            regInfo{},
-	},
-	{
-		name:    "LoweredPanicBoundsA",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:         "VPERMI2Q512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2Q,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4194304}, // R23
-				{1, 8388608}, // R24
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsB",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:         "VPERMI2PD512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1048576}, // R21
-				{1, 4194304}, // R23
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsC",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:         "VPERMI2QMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2Q,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 524288},  // R20
-				{1, 1048576}, // R21
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "PRELD",
-		auxType:        auxInt64,
-		argLen:         2,
-		hasSideEffects: true,
-		asm:            loong64.APRELD,
+		name:         "VPERMI2PDMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2PD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "PRELDX",
-		auxType:        auxInt64,
-		argLen:         2,
-		hasSideEffects: true,
-		asm:            loong64.APRELDX,
+		name:   "VPERMQMasked512",
+		argLen: 3,
+		asm:    x86.AVPERMQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
-
 	{
-		name:        "ADD",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AADDU,
+		name:   "VPERMPDMasked512",
+		argLen: 3,
+		asm:    x86.AVPERMPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ADDconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     mips.AADDU,
+		name:   "VPSRLQ512",
+		argLen: 2,
+		asm:    x86.AVPSRLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31
+				{1, 2147418112},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SUB",
-		argLen: 2,
-		asm:    mips.ASUBU,
+		name:   "VPSRLQMasked512",
+		argLen: 3,
+		asm:    x86.AVPSRLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "SUBconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     mips.ASUBU,
+		name:   "VPSRLVQ512",
+		argLen: 2,
+		asm:    x86.AVPSRLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "MUL",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AMUL,
+		name:   "VPSRLVQMasked512",
+		argLen: 3,
+		asm:    x86.AVPSRLVQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 105553116266496, // HI LO
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MULT",
+		name:        "VPAVGB128",
 		argLen:      2,
 		commutative: true,
-		asm:         mips.AMUL,
+		asm:         x86.AVPAVGB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35184372088832}, // HI
-				{1, 70368744177664}, // LO
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MULTU",
-		argLen:      2,
+		name:        "VPAVGBMasked128",
+		argLen:      3,
 		commutative: true,
-		asm:         mips.AMULU,
+		asm:         x86.AVPAVGB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35184372088832}, // HI
-				{1, 70368744177664}, // LO
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "DIV",
+		name:   "VGF2P8MULB128",
 		argLen: 2,
-		asm:    mips.ADIV,
+		asm:    x86.AVGF2P8MULB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 35184372088832}, // HI
-				{1, 70368744177664}, // LO
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "DIVU",
-		argLen: 2,
-		asm:    mips.ADIVU,
+		name:   "VGF2P8MULBMasked128",
+		argLen: 3,
+		asm:    x86.AVGF2P8MULB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35184372088832}, // HI
-				{1, 70368744177664}, // LO
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "ADDF",
+		name:        "VPMAXUB128",
 		argLen:      2,
 		commutative: true,
-		asm:         mips.AADDF,
+		asm:         x86.AVPMAXUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "ADDD",
-		argLen:      2,
+		name:        "VPMAXUBMasked128",
+		argLen:      3,
 		commutative: true,
-		asm:         mips.AADDD,
+		asm:         x86.AVPMAXUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SUBF",
-		argLen: 2,
-		asm:    mips.ASUBF,
+		name:        "VPMINUB128",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SUBD",
-		argLen: 2,
-		asm:    mips.ASUBD,
+		name:        "VPMINUBMasked128",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MULF",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AMULF,
+		name:   "VPERMB128",
+		argLen: 2,
+		asm:    x86.AVPERMB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "MULD",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AMULD,
+		name:         "VPERMI2B128",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2B,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "DIVF",
-		argLen: 2,
-		asm:    mips.ADIVF,
+		name:         "VPERMI2BMasked128",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2B,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "DIVD",
-		argLen: 2,
-		asm:    mips.ADIVD,
+		name:   "VPERMBMasked128",
+		argLen: 3,
+		asm:    x86.AVPERMB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "AND",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AAND,
+		name:   "VPMADDUBSW128",
+		argLen: 2,
+		asm:    x86.AVPMADDUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ANDconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     mips.AAND,
+		name:   "VPMADDUBSWMasked128",
+		argLen: 3,
+		asm:    x86.AVPMADDUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "OR",
+		name:        "VPAVGB256",
 		argLen:      2,
 		commutative: true,
-		asm:         mips.AOR,
+		asm:         x86.AVPAVGB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "ORconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     mips.AOR,
+		name:        "VPAVGBMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPAVGB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "XOR",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AXOR,
+		name:   "VGF2P8MULB256",
+		argLen: 2,
+		asm:    x86.AVGF2P8MULB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "XORconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     mips.AXOR,
+		name:   "VGF2P8MULBMasked256",
+		argLen: 3,
+		asm:    x86.AVGF2P8MULB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "NOR",
+		name:        "VPMAXUB256",
 		argLen:      2,
 		commutative: true,
-		asm:         mips.ANOR,
+		asm:         x86.AVPMAXUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "NORconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     mips.ANOR,
+		name:        "VPMAXUBMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NEG",
-		argLen: 1,
+		name:        "VPMINUB256",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NEGF",
-		argLen: 1,
-		asm:    mips.ANEGF,
+		name:        "VPMINUBMasked256",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NEGD",
-		argLen: 1,
-		asm:    mips.ANEGD,
+		name:   "VPERMB256",
+		argLen: 2,
+		asm:    x86.AVPERMB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "ABSD",
-		argLen: 1,
-		asm:    mips.AABSD,
+		name:         "VPERMI2B256",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2B,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SQRTD",
-		argLen: 1,
-		asm:    mips.ASQRTD,
+		name:         "VPERMI2BMasked256",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2B,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SQRTF",
-		argLen: 1,
-		asm:    mips.ASQRTF,
+		name:   "VPERMBMasked256",
+		argLen: 3,
+		asm:    x86.AVPERMB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SLL",
+		name:   "VPMADDUBSW256",
 		argLen: 2,
-		asm:    mips.ASLL,
+		asm:    x86.AVPMADDUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SLLconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     mips.ASLL,
+		name:   "VPMADDUBSWMasked256",
+		argLen: 3,
+		asm:    x86.AVPMADDUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SRL",
-		argLen: 2,
-		asm:    mips.ASRL,
+		name:        "VPAVGB512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPAVGB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "SRLconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     mips.ASRL,
+		name:        "VPAVGBMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPAVGB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SRA",
+		name:   "VGF2P8MULB512",
 		argLen: 2,
-		asm:    mips.ASRA,
+		asm:    x86.AVGF2P8MULB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "SRAconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     mips.ASRA,
+		name:   "VGF2P8MULBMasked512",
+		argLen: 3,
+		asm:    x86.AVGF2P8MULB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CLZ",
-		argLen: 1,
-		asm:    mips.ACLZ,
+		name:        "VPMAXUB512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMAXUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SGT",
-		argLen: 2,
-		asm:    mips.ASGT,
+		name:        "VPMAXUBMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMAXUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SGTconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     mips.ASGT,
+		name:        "VPMINUB512",
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPMINUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SGTzero",
-		argLen: 1,
-		asm:    mips.ASGT,
+		name:        "VPMINUBMasked512",
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPMINUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SGTU",
+		name:   "VPERMB512",
 		argLen: 2,
-		asm:    mips.ASGTU,
+		asm:    x86.AVPERMB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "SGTUconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     mips.ASGTU,
+		name:         "VPERMI2B512",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2B,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SGTUzero",
-		argLen: 1,
-		asm:    mips.ASGTU,
+		name:         "VPERMI2BMasked512",
+		argLen:       4,
+		resultInArg0: true,
+		asm:          x86.AVPERMI2B,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{2, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPEQF",
-		argLen: 2,
-		asm:    mips.ACMPEQF,
+		name:   "VPERMBMasked512",
+		argLen: 3,
+		asm:    x86.AVPERMB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPEQD",
+		name:   "VPMADDUBSW512",
 		argLen: 2,
-		asm:    mips.ACMPEQD,
+		asm:    x86.AVPMADDUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "CMPGEF",
-		argLen: 2,
-		asm:    mips.ACMPGEF,
+		name:   "VPMADDUBSWMasked512",
+		argLen: 3,
+		asm:    x86.AVPMADDUBSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPGED",
-		argLen: 2,
-		asm:    mips.ACMPGED,
+		name:    "VRNDSCALEPS512",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVRNDSCALEPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "CMPGTF",
-		argLen: 2,
-		asm:    mips.ACMPGTF,
+		name:    "VRNDSCALEPSMasked512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVRNDSCALEPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPGTD",
-		argLen: 2,
-		asm:    mips.ACMPGTD,
+		name:    "VREDUCEPS512",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVREDUCEPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:              "MOVWconst",
-		auxType:           auxInt32,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               mips.AMOVW,
+		name:    "VREDUCEPSMasked512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVREDUCEPS,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:              "MOVFconst",
-		auxType:           auxFloat32,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               mips.AMOVF,
+		name:        "VCMPPS512",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVCMPPS,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:              "MOVDconst",
-		auxType:           auxFloat64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               mips.AMOVD,
+		name:        "VCMPPSMasked512",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVCMPPS,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:              "MOVWaddr",
-		auxType:           auxSymOff,
-		argLen:            1,
-		rematerializeable: true,
-		symEffect:         SymAddr,
-		asm:               mips.AMOVW,
+		name:    "VROUNDPS128",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVROUNDPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140737555464192}, // SP SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVBload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVB,
+		name:    "VRNDSCALEPS128",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVRNDSCALEPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVBUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVBU,
+		name:    "VRNDSCALEPSMasked128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVRNDSCALEPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVHload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVH,
+		name:    "VREDUCEPS128",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVREDUCEPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVHUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVHU,
+		name:    "VREDUCEPSMasked128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVREDUCEPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVWload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVW,
+		name:        "VDPPS128",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVDPPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVFload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVF,
+		name:        "VCMPPS128",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVCMPPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVDload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVD,
+		name:        "VCMPPSMasked128",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVCMPPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "MOVBstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVB,
+		name:    "VROUNDPS256",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVROUNDPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVHstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVH,
+		name:    "VRNDSCALEPS256",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVRNDSCALEPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVWstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVW,
+		name:    "VRNDSCALEPSMasked256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVRNDSCALEPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVFstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVF,
+		name:    "VREDUCEPS256",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVREDUCEPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVDstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVD,
+		name:    "VREDUCEPSMasked256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVREDUCEPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVBstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVB,
+		name:        "VDPPS256",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVDPPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVHstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVH,
+		name:        "VCMPPS256",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVCMPPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVWstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVW,
+		name:        "VCMPPSMasked256",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVCMPPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVWfpgp",
-		argLen: 1,
-		asm:    mips.AMOVW,
+		name:    "VEXTRACTF128128",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVEXTRACTF128,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWgpfp",
-		argLen: 1,
-		asm:    mips.AMOVW,
+		name:    "VINSERTF128256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVINSERTF128,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVBreg",
-		argLen: 1,
-		asm:    mips.AMOVB,
+		name:    "VROUNDPD128",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVROUNDPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVBUreg",
-		argLen: 1,
-		asm:    mips.AMOVBU,
+		name:    "VRNDSCALEPD128",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVRNDSCALEPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVHreg",
-		argLen: 1,
-		asm:    mips.AMOVH,
+		name:    "VRNDSCALEPDMasked128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVRNDSCALEPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVHUreg",
-		argLen: 1,
-		asm:    mips.AMOVHU,
+		name:    "VREDUCEPD128",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVREDUCEPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVWreg",
-		argLen: 1,
-		asm:    mips.AMOVW,
+		name:    "VREDUCEPDMasked128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVREDUCEPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "MOVWnop",
-		argLen:       1,
-		resultInArg0: true,
+		name:        "VDPPD128",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVDPPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "CMOVZ",
-		argLen:       3,
-		resultInArg0: true,
-		asm:          mips.ACMOVZ,
+		name:        "VCMPPD128",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVCMPPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
-				{1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
-				{2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "CMOVZzero",
-		argLen:       2,
-		resultInArg0: true,
-		asm:          mips.ACMOVZ,
+		name:        "VCMPPDMasked128",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVCMPPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
-				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVWF",
-		argLen: 1,
-		asm:    mips.AMOVWF,
+		name:    "VROUNDPD256",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVROUNDPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWD",
-		argLen: 1,
-		asm:    mips.AMOVWD,
+		name:    "VRNDSCALEPD256",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVRNDSCALEPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "TRUNCFW",
-		argLen: 1,
-		asm:    mips.ATRUNCFW,
+		name:    "VRNDSCALEPDMasked256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVRNDSCALEPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "TRUNCDW",
-		argLen: 1,
-		asm:    mips.ATRUNCDW,
+		name:    "VREDUCEPD256",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVREDUCEPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "MOVFD",
-		argLen: 1,
-		asm:    mips.AMOVFD,
+		name:    "VREDUCEPDMasked256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVREDUCEPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVDF",
-		argLen: 1,
-		asm:    mips.AMOVDF,
+		name:        "VCMPPD256",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVCMPPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:         "CALLstatic",
-		auxType:      auxCallOff,
-		argLen:       1,
-		clobberFlags: true,
-		call:         true,
+		name:        "VCMPPDMasked256",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVCMPPD,
 		reg: regInfo{
-			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+			},
 		},
 	},
 	{
-		name:         "CALLtail",
-		auxType:      auxCallOff,
-		argLen:       1,
-		clobberFlags: true,
-		call:         true,
-		tailCall:     true,
+		name:    "VRNDSCALEPD512",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVRNDSCALEPD,
 		reg: regInfo{
-			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 		},
 	},
 	{
-		name:         "CALLclosure",
-		auxType:      auxCallOff,
-		argLen:       3,
-		clobberFlags: true,
-		call:         true,
+		name:    "VRNDSCALEPDMasked512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVRNDSCALEPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 4194304},   // R22
-				{0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
 		},
 	},
 	{
-		name:         "CALLinter",
-		auxType:      auxCallOff,
-		argLen:       2,
-		clobberFlags: true,
-		call:         true,
+		name:    "VREDUCEPD512",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVREDUCEPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad8",
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:    "VREDUCEPDMasked512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVREDUCEPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad32",
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:        "VCMPPD512",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVCMPPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore8",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:        "VCMPPDMasked512",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVCMPPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore32",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:        "VPCMPWMasked256",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStorezero",
-		argLen:         2,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:    "VPCMPW256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "VPSHLDW256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHLDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAdd",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "VPSHLDWMasked256",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHLDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAddconst",
-		auxType:         auxInt32,
-		argLen:          2,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "VPSHRDW256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHRDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas",
-		argLen:          4,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "VPSHRDWMasked256",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHRDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{2, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicAnd",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		unsafePoint:    true,
-		asm:            mips.AAND,
+		name:        "VPCMPW512",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicOr",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		unsafePoint:    true,
-		asm:            mips.AOR,
+		name:        "VPCMPWMasked512",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "LoweredZero",
-		auxType:        auxInt32,
-		argLen:         3,
-		faultOnNilArg0: true,
+		name:    "VPSHLDW512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHLDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2},         // R1
-				{1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-			clobbers: 2, // R1
 		},
 	},
 	{
-		name:           "LoweredMove",
-		auxType:        auxInt32,
-		argLen:         4,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
+		name:    "VPSHLDWMasked512",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHLDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4},         // R2
-				{1, 2},         // R1
-				{2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 6, // R1 R2
 		},
 	},
 	{
-		name:           "LoweredNilCheck",
-		argLen:         2,
-		nilCheck:       true,
-		faultOnNilArg0: true,
+		name:    "VPSHRDW512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHRDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-		},
-	},
-	{
-		name:   "FPFlagTrue",
-		argLen: 1,
-		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "FPFlagFalse",
-		argLen: 1,
+		name:    "VPSHRDWMasked512",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHRDW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:      "LoweredGetClosurePtr",
-		argLen:    0,
-		zeroWidth: true,
+		name:        "VPCMPWMasked128",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 4194304}, // R22
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerSP",
-		argLen:            1,
-		rematerializeable: true,
+		name:    "VPEXTRW128",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVPEXTRW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerPC",
-		argLen:            0,
-		rematerializeable: true,
+		name:    "VPCMPW128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:         "LoweredWB",
-		auxType:      auxInt64,
-		argLen:       1,
-		clobberFlags: true,
+		name:    "VPINSRW128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPINSRW,
 		reg: regInfo{
-			clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+			inputs: []inputInfo{
+				{1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 16777216}, // R25
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LoweredPubBarrier",
-		argLen:         1,
-		hasSideEffects: true,
-		asm:            mips.ASYNC,
-		reg:            regInfo{},
-	},
-	{
-		name:    "LoweredPanicBoundsA",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:    "VPSHLDW128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHLDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 8},  // R3
-				{1, 16}, // R4
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsB",
-		auxType: auxInt64,
+		name:    "VPSHLDWMasked128",
+		auxType: auxInt8,
 		argLen:  3,
-		call:    true,
+		asm:     x86.AVPSHLDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4}, // R2
-				{1, 8}, // R3
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsC",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:    "VPSHRDW128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHRDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2}, // R1
-				{1, 4}, // R2
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicExtendA",
-		auxType: auxInt64,
-		argLen:  4,
-		call:    true,
+		name:    "VPSHRDWMasked128",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHRDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 32}, // R5
-				{1, 8},  // R3
-				{2, 16}, // R4
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicExtendB",
-		auxType: auxInt64,
-		argLen:  4,
-		call:    true,
+		name:        "VPCMPD512",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 32}, // R5
-				{1, 4},  // R2
-				{2, 8},  // R3
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicExtendC",
-		auxType: auxInt64,
-		argLen:  4,
-		call:    true,
+		name:        "VPCMPDMasked512",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 32}, // R5
-				{1, 2},  // R1
-				{2, 4},  // R2
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
-
 	{
-		name:        "ADDV",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AADDVU,
+		name:    "VPROLD512",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVPROLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "ADDVconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     mips.AADDVU,
+		name:    "VPROLDMasked512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPROLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SUBV",
-		argLen: 2,
-		asm:    mips.ASUBVU,
+		name:    "VPRORD512",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVPRORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "SUBVconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     mips.ASUBVU,
+		name:    "VPRORDMasked512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPRORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MULV",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AMULV,
+		name:    "VPSHLDD512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHLDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1152921504606846976}, // HI
-				{1, 2305843009213693952}, // LO
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "MULVU",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AMULVU,
+		name:    "VPSHLDDMasked512",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHLDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504606846976}, // HI
-				{1, 2305843009213693952}, // LO
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "DIVV",
-		argLen: 2,
-		asm:    mips.ADIVV,
+		name:    "VPSHRDD512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHRDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1152921504606846976}, // HI
-				{1, 2305843009213693952}, // LO
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "DIVVU",
-		argLen: 2,
-		asm:    mips.ADIVVU,
+		name:    "VPSHRDDMasked512",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHRDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504606846976}, // HI
-				{1, 2305843009213693952}, // LO
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "ADDF",
-		argLen:      2,
+		name:        "VPCMPDMasked128",
+		auxType:     auxInt8,
+		argLen:      3,
 		commutative: true,
-		asm:         mips.AADDF,
+		asm:         x86.AVPCMPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:        "ADDD",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AADDD,
+		name:    "VPEXTRD128",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVPEXTRD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
 			},
 		},
 	},
 	{
-		name:   "SUBF",
-		argLen: 2,
-		asm:    mips.ASUBF,
+		name:    "VPCMPD128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "SUBD",
-		argLen: 2,
-		asm:    mips.ASUBD,
+		name:    "VPROLD128",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVPROLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:        "MULF",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AMULF,
+		name:    "VPROLDMasked128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPROLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "MULD",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AMULD,
+		name:    "VPRORD128",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVPRORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "DIVF",
-		argLen: 2,
-		asm:    mips.ADIVF,
+		name:    "VPRORDMasked128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPRORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "DIVD",
-		argLen: 2,
-		asm:    mips.ADIVD,
+		name:    "VPINSRD128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPINSRD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "AND",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AAND,
+		name:    "VPSHLDD128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHLDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "ANDconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     mips.AAND,
+		name:    "VPSHLDDMasked128",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHLDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "OR",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.AOR,
+		name:    "VPSHRDD128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHRDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "ORconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     mips.AOR,
+		name:    "VPSHRDDMasked128",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHRDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:        "XOR",
-		argLen:      2,
+		name:        "VPCMPDMasked256",
+		auxType:     auxInt8,
+		argLen:      3,
 		commutative: true,
-		asm:         mips.AXOR,
+		asm:         x86.AVPCMPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:    "XORconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     mips.AXOR,
+		name:    "VPCMPD256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:        "NOR",
-		argLen:      2,
-		commutative: true,
-		asm:         mips.ANOR,
+		name:    "VPROLD256",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVPROLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "NORconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     mips.ANOR,
+		name:    "VPROLDMasked256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPROLD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NEGV",
-		argLen: 1,
+		name:    "VPRORD256",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVPRORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "NEGF",
-		argLen: 1,
-		asm:    mips.ANEGF,
+		name:    "VPRORDMasked256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPRORD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "NEGD",
-		argLen: 1,
-		asm:    mips.ANEGD,
+		name:    "VPSHLDD256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHLDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "ABSD",
-		argLen: 1,
-		asm:    mips.AABSD,
+		name:    "VPSHLDDMasked256",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHLDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SQRTD",
-		argLen: 1,
-		asm:    mips.ASQRTD,
+		name:    "VPSHRDD256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHRDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SQRTF",
-		argLen: 1,
-		asm:    mips.ASQRTF,
+		name:    "VPSHRDDMasked256",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHRDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SLLV",
-		argLen: 2,
-		asm:    mips.ASLLV,
+		name:        "VPCMPQMasked128",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:    "SLLVconst",
-		auxType: auxInt64,
+		name:    "VPEXTRQ128",
+		auxType: auxInt8,
 		argLen:  1,
-		asm:     mips.ASLLV,
+		asm:     x86.AVPEXTRQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
 			},
 		},
 	},
 	{
-		name:   "SRLV",
-		argLen: 2,
-		asm:    mips.ASRLV,
+		name:    "VPCMPQ128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:    "SRLVconst",
-		auxType: auxInt64,
+		name:    "VPROLQ128",
+		auxType: auxInt8,
 		argLen:  1,
-		asm:     mips.ASRLV,
+		asm:     x86.AVPROLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SRAV",
-		argLen: 2,
-		asm:    mips.ASRAV,
+		name:    "VPROLQMasked128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPROLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SRAVconst",
-		auxType: auxInt64,
+		name:    "VPRORQ128",
+		auxType: auxInt8,
 		argLen:  1,
-		asm:     mips.ASRAV,
+		asm:     x86.AVPRORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "SGT",
-		argLen: 2,
-		asm:    mips.ASGT,
+		name:    "VPRORQMasked128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPRORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:    "SGTconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     mips.ASGT,
+		name:    "VPINSRQ128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPINSRQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "SGTU",
-		argLen: 2,
-		asm:    mips.ASGTU,
+		name:    "VPSHLDQ128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHLDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:    "SGTUconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     mips.ASGTU,
+		name:    "VPSHLDQMasked128",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHLDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPEQF",
-		argLen: 2,
-		asm:    mips.ACMPEQF,
+		name:    "VPSHRDQ128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHRDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "CMPEQD",
-		argLen: 2,
-		asm:    mips.ACMPEQD,
+		name:    "VPSHRDQMasked128",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHRDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "CMPGEF",
-		argLen: 2,
-		asm:    mips.ACMPGEF,
+		name:        "VPCMPQMasked256",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "CMPGED",
-		argLen: 2,
-		asm:    mips.ACMPGED,
+		name:    "VPCMPQ256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "CMPGTF",
-		argLen: 2,
-		asm:    mips.ACMPGTF,
+		name:    "VPROLQ256",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVPROLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:   "CMPGTD",
-		argLen: 2,
-		asm:    mips.ACMPGTD,
+		name:    "VPROLQMasked256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPROLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-		},
-	},
-	{
-		name:              "MOVVconst",
-		auxType:           auxInt64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               mips.AMOVV,
-		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:              "MOVFconst",
-		auxType:           auxFloat64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               mips.AMOVF,
+		name:    "VPRORQ256",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVPRORQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:              "MOVDconst",
-		auxType:           auxFloat64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               mips.AMOVD,
+		name:    "VPRORQMasked256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPRORQ,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:              "MOVVaddr",
-		auxType:           auxSymOff,
-		argLen:            1,
-		rematerializeable: true,
-		symEffect:         SymAddr,
-		asm:               mips.AMOVV,
+		name:    "VPSHLDQ256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHLDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018460942336}, // SP SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVBload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVB,
+		name:    "VPSHLDQMasked256",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHLDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVBUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVBU,
+		name:    "VPSHRDQ256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHRDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVHload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVH,
+		name:    "VPSHRDQMasked256",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHRDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVHUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVHU,
+		name:        "VPCMPQ512",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "MOVWload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVW,
+		name:        "VPCMPQMasked512",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "MOVWUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVWU,
+		name:    "VPROLQ512",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVPROLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVVload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVV,
+		name:    "VPROLQMasked512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPROLQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVFload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVF,
+		name:    "VPRORQ512",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVPRORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVDload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            mips.AMOVD,
+		name:    "VPRORQMasked512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPRORQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVBstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVB,
+		name:    "VPSHLDQ512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHLDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVHstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVH,
+		name:    "VPSHLDQMasked512",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHLDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVWstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVW,
+		name:    "VPSHRDQ512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPSHRDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "MOVVstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVV,
+		name:    "VPSHRDQMasked512",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVPSHRDQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVFstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVF,
+		name:        "VPCMPBMasked128",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "MOVDstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVD,
+		name:    "VPEXTRB128",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVPEXTRB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
 			},
 		},
 	},
 	{
-		name:           "MOVBstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVB,
+		name:    "VPCMPB128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "MOVHstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVH,
+		name:    "VPINSRB128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPINSRB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "MOVWstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVW,
+		name:        "VPCMPBMasked256",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "MOVVstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            mips.AMOVV,
+		name:    "VEXTRACTI128128",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     x86.AVEXTRACTI128,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVWfpgp",
-		argLen: 1,
-		asm:    mips.AMOVW,
+		name:    "VPCMPB256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVWgpfp",
-		argLen: 1,
-		asm:    mips.AMOVW,
+		name:    "VINSERTI128256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVINSERTI128,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:   "MOVVfpgp",
-		argLen: 1,
-		asm:    mips.AMOVV,
+		name:        "VPCMPB512",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVVgpfp",
-		argLen: 1,
-		asm:    mips.AMOVV,
+		name:        "VPCMPBMasked512",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVBreg",
-		argLen: 1,
-		asm:    mips.AMOVB,
+		name:        "VPCMPUWMasked256",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVBUreg",
-		argLen: 1,
-		asm:    mips.AMOVBU,
+		name:    "VPCMPUW256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVHreg",
-		argLen: 1,
-		asm:    mips.AMOVH,
+		name:        "VPCMPUW512",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVHUreg",
-		argLen: 1,
-		asm:    mips.AMOVHU,
+		name:        "VPCMPUWMasked512",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVWreg",
-		argLen: 1,
-		asm:    mips.AMOVW,
+		name:        "VPCMPUWMasked128",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVWUreg",
-		argLen: 1,
-		asm:    mips.AMOVWU,
+		name:    "VPCMPUW128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPUW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVVreg",
-		argLen: 1,
-		asm:    mips.AMOVV,
+		name:        "VPCMPUD512",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:         "MOVVnop",
-		argLen:       1,
-		resultInArg0: true,
+		name:        "VPCMPUDMasked512",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVWF",
-		argLen: 1,
-		asm:    mips.AMOVWF,
+		name:        "VPCMPUDMasked128",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVWD",
-		argLen: 1,
-		asm:    mips.AMOVWD,
+		name:    "VPCMPUD128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVVF",
-		argLen: 1,
-		asm:    mips.AMOVVF,
+		name:        "VPCMPUDMasked256",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVVD",
-		argLen: 1,
-		asm:    mips.AMOVVD,
+		name:    "VPCMPUD256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "TRUNCFW",
-		argLen: 1,
-		asm:    mips.ATRUNCFW,
+		name:        "VPCMPUQMasked128",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "TRUNCDW",
-		argLen: 1,
-		asm:    mips.ATRUNCDW,
+		name:    "VPCMPUQ128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "TRUNCFV",
-		argLen: 1,
-		asm:    mips.ATRUNCFV,
+		name:        "VPCMPUQMasked256",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "TRUNCDV",
-		argLen: 1,
-		asm:    mips.ATRUNCDV,
+		name:    "VPCMPUQ256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVFD",
-		argLen: 1,
-		asm:    mips.AMOVFD,
+		name:        "VPCMPUQ512",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:   "MOVDF",
-		argLen: 1,
-		asm:    mips.AMOVDF,
+		name:        "VPCMPUQMasked512",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPUQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:         "CALLstatic",
-		auxType:      auxCallOff,
-		argLen:       1,
-		clobberFlags: true,
-		call:         true,
-		reg: regInfo{
-			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
-		},
-	},
-	{
-		name:         "CALLtail",
-		auxType:      auxCallOff,
-		argLen:       1,
-		clobberFlags: true,
-		call:         true,
-		tailCall:     true,
-		reg: regInfo{
-			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
-		},
-	},
-	{
-		name:         "CALLclosure",
-		auxType:      auxCallOff,
-		argLen:       3,
-		clobberFlags: true,
-		call:         true,
+		name:        "VPCMPUBMasked128",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 4194304},   // R22
-				{0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
-		},
-	},
-	{
-		name:         "CALLinter",
-		auxType:      auxCallOff,
-		argLen:       2,
-		clobberFlags: true,
-		call:         true,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
-			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
 		},
 	},
 	{
-		name:           "DUFFZERO",
-		auxType:        auxInt64,
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:    "VGF2P8AFFINEQB128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVGF2P8AFFINEQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-			clobbers: 134217730, // R1 R31
-		},
-	},
-	{
-		name:           "DUFFCOPY",
-		auxType:        auxInt64,
-		argLen:         3,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 4}, // R2
-				{1, 2}, // R1
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-			clobbers: 134217734, // R1 R2 R31
 		},
 	},
 	{
-		name:           "LoweredZero",
-		auxType:        auxInt64,
-		argLen:         3,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
+		name:    "VGF2P8AFFINEINVQB128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVGF2P8AFFINEINVQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2},         // R1
-				{1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+			},
+			outputs: []outputInfo{
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
-			clobbers: 2, // R1
 		},
 	},
 	{
-		name:           "LoweredMove",
-		auxType:        auxInt64,
-		argLen:         4,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
+		name:    "VGF2P8AFFINEINVQBMasked128",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVGF2P8AFFINEINVQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4},         // R2
-				{1, 2},         // R1
-				{2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
-			clobbers: 6, // R1 R2
 		},
 	},
 	{
-		name:           "LoweredAtomicAnd32",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		unsafePoint:    true,
-		asm:            mips.AAND,
+		name:    "VGF2P8AFFINEQBMasked128",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVGF2P8AFFINEQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicOr32",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		unsafePoint:    true,
-		asm:            mips.AOR,
+		name:    "VPCMPUB128",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad8",
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:        "VPCMPUBMasked256",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad32",
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:    "VGF2P8AFFINEQB256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVGF2P8AFFINEQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad64",
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:    "VGF2P8AFFINEINVQB256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVGF2P8AFFINEINVQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore8",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:    "VGF2P8AFFINEINVQBMasked256",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVGF2P8AFFINEINVQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore32",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:    "VGF2P8AFFINEQBMasked256",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVGF2P8AFFINEQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore64",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:    "VPCMPUB256",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVPCMPUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStorezero32",
-		argLen:         2,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:        "VPCMPUB512",
+		auxType:     auxInt8,
+		argLen:      2,
+		commutative: true,
+		asm:         x86.AVPCMPUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStorezero64",
-		argLen:         2,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:        "VPCMPUBMasked512",
+		auxType:     auxInt8,
+		argLen:      3,
+		commutative: true,
+		asm:         x86.AVPCMPUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+			},
+			outputs: []outputInfo{
+				{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange32",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "VGF2P8AFFINEQB512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVGF2P8AFFINEQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange64",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "VGF2P8AFFINEINVQB512",
+		auxType: auxInt8,
+		argLen:  2,
+		asm:     x86.AVGF2P8AFFINEINVQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+				{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAdd32",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "VGF2P8AFFINEINVQBMasked512",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVGF2P8AFFINEINVQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAdd64",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "VGF2P8AFFINEQBMasked512",
+		auxType: auxInt8,
+		argLen:  3,
+		asm:     x86.AVGF2P8AFFINEQB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+				{0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+				{1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
 			},
 		},
 	},
+
 	{
-		name:            "LoweredAtomicAddconst32",
-		auxType:         auxInt32,
-		argLen:          2,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:        "ADD",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAddconst64",
-		auxType:         auxInt64,
-		argLen:          2,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "ADDconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas32",
-		argLen:          4,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:   "SUB",
+		argLen: 2,
+		asm:    arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas64",
-		argLen:          4,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "SUBconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "LoweredNilCheck",
-		argLen:         2,
-		nilCheck:       true,
-		faultOnNilArg0: true,
+		name:   "RSB",
+		argLen: 2,
+		asm:    arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
-		},
-	},
-	{
-		name:   "FPFlagTrue",
-		argLen: 1,
-		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FPFlagFalse",
-		argLen: 1,
+		name:    "RSBconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.ARSB,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:      "LoweredGetClosurePtr",
-		argLen:    0,
-		zeroWidth: true,
+		name:        "MUL",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.AMUL,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+			},
 			outputs: []outputInfo{
-				{0, 4194304}, // R22
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerSP",
-		argLen:            1,
-		rematerializeable: true,
+		name:        "HMUL",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.AMULL,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerPC",
-		argLen:            0,
-		rematerializeable: true,
+		name:        "HMULU",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.AMULLU,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+			},
 			outputs: []outputInfo{
-				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:         "LoweredWB",
-		auxType:      auxInt64,
-		argLen:       1,
+		name:         "CALLudiv",
+		argLen:       2,
 		clobberFlags: true,
 		reg: regInfo{
-			clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
+			inputs: []inputInfo{
+				{0, 2}, // R1
+				{1, 1}, // R0
+			},
+			clobbers: 20492, // R2 R3 R12 R14
 			outputs: []outputInfo{
-				{0, 16777216}, // R25
+				{0, 1}, // R0
+				{1, 2}, // R1
 			},
 		},
 	},
 	{
-		name:           "LoweredPubBarrier",
-		argLen:         1,
-		hasSideEffects: true,
-		asm:            mips.ASYNC,
-		reg:            regInfo{},
-	},
-	{
-		name:    "LoweredPanicBoundsA",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:        "ADDS",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 8},  // R3
-				{1, 16}, // R4
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+			},
+			outputs: []outputInfo{
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsB",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:    "ADDSconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4}, // R2
-				{1, 8}, // R3
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+			},
+			outputs: []outputInfo{
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsC",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:        "ADC",
+		argLen:      3,
+		commutative: true,
+		asm:         arm.AADC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2}, // R1
-				{1, 4}, // R2
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
-
 	{
-		name:        "ADD",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AADD,
+		name:    "ADCconst",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AADC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:        "ADDCC",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AADDCC,
+		name:   "SUBS",
+		argLen: 2,
+		asm:    arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "ADDconst",
-		auxType: auxInt64,
+		name:    "SUBSconst",
+		auxType: auxInt32,
 		argLen:  1,
-		asm:     ppc64.AADD,
+		asm:     arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "ADDCCconst",
-		auxType: auxInt64,
+		name:    "RSBSconst",
+		auxType: auxInt32,
 		argLen:  1,
-		asm:     ppc64.AADDCCC,
+		asm:     arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
-			clobbers: 9223372036854775808, // XER
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
 		},
 	},
 	{
-		name:        "FADD",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AFADD,
+		name:   "SBC",
+		argLen: 3,
+		asm:    arm.ASBC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:        "FADDS",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AFADDS,
+		name:    "SBCconst",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ASBC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "SUB",
-		argLen: 2,
-		asm:    ppc64.ASUB,
+		name:    "RSCconst",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ARSC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "SUBCC",
-		argLen: 2,
-		asm:    ppc64.ASUBCC,
+		name:        "MULLU",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.AMULLU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "SUBFCconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.ASUBC,
+		name:   "MULA",
+		argLen: 3,
+		asm:    arm.AMULA,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
-			clobbers: 9223372036854775808, // XER
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FSUB",
-		argLen: 2,
-		asm:    ppc64.AFSUB,
+		name:   "MULS",
+		argLen: 3,
+		asm:    arm.AMULS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FSUBS",
-		argLen: 2,
-		asm:    ppc64.AFSUBS,
+		name:        "ADDF",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.AADDF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:   "XSMINJDP",
+		name:        "ADDD",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.AADDD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "SUBF",
 		argLen: 2,
-		asm:    ppc64.AXSMINJDP,
+		asm:    arm.ASUBF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:   "XSMAXJDP",
+		name:   "SUBD",
 		argLen: 2,
-		asm:    ppc64.AXSMAXJDP,
+		asm:    arm.ASUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:        "MULLD",
+		name:        "MULF",
 		argLen:      2,
 		commutative: true,
-		asm:         ppc64.AMULLD,
+		asm:         arm.AMULF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:        "MULLW",
+		name:        "MULD",
 		argLen:      2,
 		commutative: true,
-		asm:         ppc64.AMULLW,
+		asm:         arm.AMULD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:    "MULLDconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     ppc64.AMULLD,
+		name:        "NMULF",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.ANMULF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:    "MULLWconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     ppc64.AMULLW,
+		name:        "NMULD",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.ANMULD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:   "MADDLD",
-		argLen: 3,
-		asm:    ppc64.AMADDLD,
+		name:   "DIVF",
+		argLen: 2,
+		asm:    arm.ADIVF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:        "MULHD",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AMULHD,
+		name:   "DIVD",
+		argLen: 2,
+		asm:    arm.ADIVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:        "MULHW",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AMULHW,
+		name:         "MULAF",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          arm.AMULAF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:        "MULHDU",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AMULHDU,
+		name:         "MULAD",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          arm.AMULAD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:        "MULHDUCC",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AMULHDUCC,
+		name:         "MULSF",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          arm.AMULSF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:        "MULHWU",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AMULHWU,
+		name:         "MULSD",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          arm.AMULSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:        "FMUL",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AFMUL,
+		name:         "FMULAD",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          arm.AFMULAD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:        "FMULS",
+		name:        "AND",
 		argLen:      2,
 		commutative: true,
-		asm:         ppc64.AFMULS,
+		asm:         arm.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FMADD",
-		argLen: 3,
-		asm:    ppc64.AFMADD,
+		name:    "ANDconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FMADDS",
-		argLen: 3,
-		asm:    ppc64.AFMADDS,
+		name:        "OR",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FMSUB",
-		argLen: 3,
-		asm:    ppc64.AFMSUB,
+		name:    "ORconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FMSUBS",
-		argLen: 3,
-		asm:    ppc64.AFMSUBS,
+		name:        "XOR",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "SRAD",
-		argLen: 2,
-		asm:    ppc64.ASRAD,
+		name:    "XORconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
-			clobbers: 9223372036854775808, // XER
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "SRAW",
+		name:   "BIC",
 		argLen: 2,
-		asm:    ppc64.ASRAW,
+		asm:    arm.ABIC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
-			clobbers: 9223372036854775808, // XER
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "SRD",
-		argLen: 2,
-		asm:    ppc64.ASRD,
+		name:    "BICconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.ABIC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "SRW",
-		argLen: 2,
-		asm:    ppc64.ASRW,
+		name:    "BFX",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.ABFX,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "SLD",
-		argLen: 2,
-		asm:    ppc64.ASLD,
+		name:    "BFXU",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.ABFXU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "SLW",
-		argLen: 2,
-		asm:    ppc64.ASLW,
+		name:   "MVN",
+		argLen: 1,
+		asm:    arm.AMVN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "ROTL",
-		argLen: 2,
-		asm:    ppc64.AROTL,
+		name:   "NEGF",
+		argLen: 1,
+		asm:    arm.ANEGF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:   "ROTLW",
-		argLen: 2,
-		asm:    ppc64.AROTLW,
+		name:   "NEGD",
+		argLen: 1,
+		asm:    arm.ANEGD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:    "CLRLSLWI",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     ppc64.ACLRLSLWI,
+		name:   "SQRTD",
+		argLen: 1,
+		asm:    arm.ASQRTD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:    "CLRLSLDI",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     ppc64.ACLRLSLDI,
+		name:   "SQRTF",
+		argLen: 1,
+		asm:    arm.ASQRTF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:        "ADDC",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AADDC,
+		name:   "ABSD",
+		argLen: 1,
+		asm:    arm.AABSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
-			clobbers: 9223372036854775808, // XER
 			outputs: []outputInfo{
-				{1, 9223372036854775808}, // XER
-				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:   "SUBC",
-		argLen: 2,
-		asm:    ppc64.ASUBC,
+		name:   "CLZ",
+		argLen: 1,
+		asm:    arm.ACLZ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
-			clobbers: 9223372036854775808, // XER
 			outputs: []outputInfo{
-				{1, 9223372036854775808}, // XER
-				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "ADDCconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.AADDC,
+		name:   "REV",
+		argLen: 1,
+		asm:    arm.AREV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{1, 9223372036854775808}, // XER
-				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "SUBCconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.ASUBC,
+		name:   "REV16",
+		argLen: 1,
+		asm:    arm.AREV16,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{1, 9223372036854775808}, // XER
-				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:        "ADDE",
-		argLen:      3,
-		commutative: true,
-		asm:         ppc64.AADDE,
-		reg: regInfo{
+		name:   "RBIT",
+		argLen: 1,
+		asm:    arm.ARBIT,
+		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 9223372036854775808}, // XER
-				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
-			clobbers: 9223372036854775808, // XER
 			outputs: []outputInfo{
-				{1, 9223372036854775808}, // XER
-				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "ADDZE",
+		name:   "SLL",
 		argLen: 2,
-		asm:    ppc64.AADDZE,
+		asm:    arm.ASLL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 9223372036854775808}, // XER
-				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
-			clobbers: 9223372036854775808, // XER
 			outputs: []outputInfo{
-				{1, 9223372036854775808}, // XER
-				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "SUBE",
-		argLen: 3,
-		asm:    ppc64.ASUBE,
+		name:    "SLLconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.ASLL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{2, 9223372036854775808}, // XER
-				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
-			clobbers: 9223372036854775808, // XER
 			outputs: []outputInfo{
-				{1, 9223372036854775808}, // XER
-				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "ADDZEzero",
-		argLen: 1,
-		asm:    ppc64.AADDZE,
+		name:   "SRL",
+		argLen: 2,
+		asm:    arm.ASRL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372036854775808}, // XER
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
-			clobbers: 9223372036854775808, // XER
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "SUBZEzero",
-		argLen: 1,
-		asm:    ppc64.ASUBZE,
+		name:    "SRLconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.ASRL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372036854775808}, // XER
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
-			clobbers: 9223372036854775808, // XER
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "SRADconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.ASRAD,
+		name:   "SRA",
+		argLen: 2,
+		asm:    arm.ASRA,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
-			clobbers: 9223372036854775808, // XER
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "SRAWconst",
-		auxType: auxInt64,
+		name:    "SRAconst",
+		auxType: auxInt32,
 		argLen:  1,
-		asm:     ppc64.ASRAW,
+		asm:     arm.ASRA,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
-			clobbers: 9223372036854775808, // XER
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "SRDconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.ASRD,
+		name:   "SRR",
+		argLen: 2,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "SRWconst",
-		auxType: auxInt64,
+		name:    "SRRconst",
+		auxType: auxInt32,
 		argLen:  1,
-		asm:     ppc64.ASRW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "SLDconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.ASLD,
+		name:    "ADDshiftLL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "SLWconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.ASLW,
+		name:    "ADDshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "ROTLconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.AROTL,
+		name:    "ADDshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "ROTLWconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.AROTLW,
+		name:    "SUBshiftLL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "EXTSWSLconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.AEXTSWSLI,
+		name:    "SUBshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "RLWINM",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.ARLWNM,
+		name:    "SUBshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "RLWNM",
-		auxType: auxInt64,
+		name:    "RSBshiftLL",
+		auxType: auxInt32,
 		argLen:  2,
-		asm:     ppc64.ARLWNM,
+		asm:     arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:         "RLWMI",
-		auxType:      auxInt64,
-		argLen:       2,
-		resultInArg0: true,
-		asm:          ppc64.ARLWMI,
+		name:    "RSBshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "RLDICL",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.ARLDICL,
+		name:    "RSBshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "RLDICLCC",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.ARLDICLCC,
+		name:    "ANDshiftLL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "RLDICR",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.ARLDICR,
+		name:    "ANDshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "CNTLZD",
-		argLen: 1,
-		asm:    ppc64.ACNTLZD,
+		name:    "ANDshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "CNTLZDCC",
-		argLen: 1,
-		asm:    ppc64.ACNTLZDCC,
+		name:    "ORshiftLL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "CNTLZW",
-		argLen: 1,
-		asm:    ppc64.ACNTLZW,
+		name:    "ORshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "CNTTZD",
-		argLen: 1,
-		asm:    ppc64.ACNTTZD,
+		name:    "ORshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "CNTTZW",
-		argLen: 1,
-		asm:    ppc64.ACNTTZW,
+		name:    "XORshiftLL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "POPCNTD",
-		argLen: 1,
-		asm:    ppc64.APOPCNTD,
+		name:    "XORshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "POPCNTW",
-		argLen: 1,
-		asm:    ppc64.APOPCNTW,
+		name:    "XORshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "POPCNTB",
-		argLen: 1,
-		asm:    ppc64.APOPCNTB,
+		name:    "XORshiftRR",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FDIV",
-		argLen: 2,
-		asm:    ppc64.AFDIV,
+		name:    "BICshiftLL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ABIC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FDIVS",
-		argLen: 2,
-		asm:    ppc64.AFDIVS,
+		name:    "BICshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ABIC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "DIVD",
-		argLen: 2,
-		asm:    ppc64.ADIVD,
+		name:    "BICshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ABIC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "DIVW",
-		argLen: 2,
-		asm:    ppc64.ADIVW,
+		name:    "MVNshiftLL",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.AMVN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "DIVDU",
-		argLen: 2,
-		asm:    ppc64.ADIVDU,
+		name:    "MVNshiftRL",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.AMVN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "DIVWU",
-		argLen: 2,
-		asm:    ppc64.ADIVWU,
+		name:    "MVNshiftRA",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.AMVN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MODUD",
-		argLen: 2,
-		asm:    ppc64.AMODUD,
+		name:    "ADCshiftLL",
+		auxType: auxInt32,
+		argLen:  3,
+		asm:     arm.AADC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MODSD",
-		argLen: 2,
-		asm:    ppc64.AMODSD,
+		name:    "ADCshiftRL",
+		auxType: auxInt32,
+		argLen:  3,
+		asm:     arm.AADC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MODUW",
-		argLen: 2,
-		asm:    ppc64.AMODUW,
+		name:    "ADCshiftRA",
+		auxType: auxInt32,
+		argLen:  3,
+		asm:     arm.AADC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MODSW",
-		argLen: 2,
-		asm:    ppc64.AMODSW,
+		name:    "SBCshiftLL",
+		auxType: auxInt32,
+		argLen:  3,
+		asm:     arm.ASBC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FCTIDZ",
-		argLen: 1,
-		asm:    ppc64.AFCTIDZ,
+		name:    "SBCshiftRL",
+		auxType: auxInt32,
+		argLen:  3,
+		asm:     arm.ASBC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FCTIWZ",
-		argLen: 1,
-		asm:    ppc64.AFCTIWZ,
+		name:    "SBCshiftRA",
+		auxType: auxInt32,
+		argLen:  3,
+		asm:     arm.ASBC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FCFID",
-		argLen: 1,
-		asm:    ppc64.AFCFID,
+		name:    "RSCshiftLL",
+		auxType: auxInt32,
+		argLen:  3,
+		asm:     arm.ARSC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FCFIDS",
-		argLen: 1,
-		asm:    ppc64.AFCFIDS,
+		name:    "RSCshiftRL",
+		auxType: auxInt32,
+		argLen:  3,
+		asm:     arm.ARSC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FRSP",
-		argLen: 1,
-		asm:    ppc64.AFRSP,
+		name:    "RSCshiftRA",
+		auxType: auxInt32,
+		argLen:  3,
+		asm:     arm.ARSC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MFVSRD",
-		argLen: 1,
-		asm:    ppc64.AMFVSRD,
+		name:    "ADDSshiftLL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MTVSRD",
-		argLen: 1,
-		asm:    ppc64.AMTVSRD,
+		name:    "ADDSshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:        "AND",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AAND,
+		name:    "ADDSshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "ANDN",
-		argLen: 2,
-		asm:    ppc64.AANDN,
+		name:    "SUBSshiftLL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "ANDNCC",
-		argLen: 2,
-		asm:    ppc64.AANDNCC,
+		name:    "SUBSshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:        "ANDCC",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AANDCC,
+		name:    "SUBSshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:        "OR",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AOR,
+		name:    "RSBSshiftLL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "ORN",
-		argLen: 2,
-		asm:    ppc64.AORN,
+		name:    "RSBSshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:        "ORCC",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AORCC,
+		name:    "RSBSshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:        "NOR",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.ANOR,
+		name:   "ADDshiftLLreg",
+		argLen: 3,
+		asm:    arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:        "NORCC",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.ANORCC,
+		name:   "ADDshiftRLreg",
+		argLen: 3,
+		asm:    arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:        "XOR",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AXOR,
+		name:   "ADDshiftRAreg",
+		argLen: 3,
+		asm:    arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:        "XORCC",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AXORCC,
+		name:   "SUBshiftLLreg",
+		argLen: 3,
+		asm:    arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:        "EQV",
-		argLen:      2,
-		commutative: true,
-		asm:         ppc64.AEQV,
+		name:   "SUBshiftRLreg",
+		argLen: 3,
+		asm:    arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "NEG",
-		argLen: 1,
-		asm:    ppc64.ANEG,
+		name:   "SUBshiftRAreg",
+		argLen: 3,
+		asm:    arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "NEGCC",
-		argLen: 1,
-		asm:    ppc64.ANEGCC,
+		name:   "RSBshiftLLreg",
+		argLen: 3,
+		asm:    arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "BRD",
-		argLen: 1,
-		asm:    ppc64.ABRD,
+		name:   "RSBshiftRLreg",
+		argLen: 3,
+		asm:    arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "BRW",
-		argLen: 1,
-		asm:    ppc64.ABRW,
+		name:   "RSBshiftRAreg",
+		argLen: 3,
+		asm:    arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "BRH",
-		argLen: 1,
-		asm:    ppc64.ABRH,
+		name:   "ANDshiftLLreg",
+		argLen: 3,
+		asm:    arm.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FNEG",
-		argLen: 1,
-		asm:    ppc64.AFNEG,
+		name:   "ANDshiftRLreg",
+		argLen: 3,
+		asm:    arm.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FSQRT",
-		argLen: 1,
-		asm:    ppc64.AFSQRT,
+		name:   "ANDshiftRAreg",
+		argLen: 3,
+		asm:    arm.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FSQRTS",
-		argLen: 1,
-		asm:    ppc64.AFSQRTS,
+		name:   "ORshiftLLreg",
+		argLen: 3,
+		asm:    arm.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FFLOOR",
-		argLen: 1,
-		asm:    ppc64.AFRIM,
+		name:   "ORshiftRLreg",
+		argLen: 3,
+		asm:    arm.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FCEIL",
-		argLen: 1,
-		asm:    ppc64.AFRIP,
+		name:   "ORshiftRAreg",
+		argLen: 3,
+		asm:    arm.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FTRUNC",
-		argLen: 1,
-		asm:    ppc64.AFRIZ,
+		name:   "XORshiftLLreg",
+		argLen: 3,
+		asm:    arm.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FROUND",
-		argLen: 1,
-		asm:    ppc64.AFRIN,
+		name:   "XORshiftRLreg",
+		argLen: 3,
+		asm:    arm.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FABS",
-		argLen: 1,
-		asm:    ppc64.AFABS,
+		name:   "XORshiftRAreg",
+		argLen: 3,
+		asm:    arm.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FNABS",
-		argLen: 1,
-		asm:    ppc64.AFNABS,
+		name:   "BICshiftLLreg",
+		argLen: 3,
+		asm:    arm.ABIC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FCPSGN",
-		argLen: 2,
-		asm:    ppc64.AFCPSGN,
+		name:   "BICshiftRLreg",
+		argLen: 3,
+		asm:    arm.ABIC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "ORconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.AOR,
+		name:   "BICshiftRAreg",
+		argLen: 3,
+		asm:    arm.ABIC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "XORconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.AXOR,
+		name:   "MVNshiftLLreg",
+		argLen: 2,
+		asm:    arm.AMVN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "ANDCCconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.AANDCC,
+		name:   "MVNshiftRLreg",
+		argLen: 2,
+		asm:    arm.AMVN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:         "ANDconst",
-		auxType:      auxInt64,
-		argLen:       1,
-		clobberFlags: true,
-		asm:          ppc64.AANDCC,
+		name:   "MVNshiftRAreg",
+		argLen: 2,
+		asm:    arm.AMVN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVBreg",
-		argLen: 1,
-		asm:    ppc64.AMOVB,
+		name:   "ADCshiftLLreg",
+		argLen: 4,
+		asm:    arm.AADC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVBZreg",
-		argLen: 1,
-		asm:    ppc64.AMOVBZ,
+		name:   "ADCshiftRLreg",
+		argLen: 4,
+		asm:    arm.AADC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVHreg",
-		argLen: 1,
-		asm:    ppc64.AMOVH,
+		name:   "ADCshiftRAreg",
+		argLen: 4,
+		asm:    arm.AADC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVHZreg",
-		argLen: 1,
-		asm:    ppc64.AMOVHZ,
+		name:   "SBCshiftLLreg",
+		argLen: 4,
+		asm:    arm.ASBC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVWreg",
-		argLen: 1,
-		asm:    ppc64.AMOVW,
+		name:   "SBCshiftRLreg",
+		argLen: 4,
+		asm:    arm.ASBC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVWZreg",
-		argLen: 1,
-		asm:    ppc64.AMOVWZ,
+		name:   "SBCshiftRAreg",
+		argLen: 4,
+		asm:    arm.ASBC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVBZload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            ppc64.AMOVBZ,
+		name:   "RSCshiftLLreg",
+		argLen: 4,
+		asm:    arm.ARSC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVHload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            ppc64.AMOVH,
+		name:   "RSCshiftRLreg",
+		argLen: 4,
+		asm:    arm.ARSC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVHZload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            ppc64.AMOVHZ,
+		name:   "RSCshiftRAreg",
+		argLen: 4,
+		asm:    arm.ARSC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVWload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            ppc64.AMOVW,
+		name:   "ADDSshiftLLreg",
+		argLen: 3,
+		asm:    arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVWZload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            ppc64.AMOVWZ,
+		name:   "ADDSshiftRLreg",
+		argLen: 3,
+		asm:    arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVDload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            ppc64.AMOVD,
+		name:   "ADDSshiftRAreg",
+		argLen: 3,
+		asm:    arm.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVDBRload",
-		argLen:         2,
-		faultOnNilArg0: true,
-		asm:            ppc64.AMOVDBR,
+		name:   "SUBSshiftLLreg",
+		argLen: 3,
+		asm:    arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVWBRload",
-		argLen:         2,
-		faultOnNilArg0: true,
-		asm:            ppc64.AMOVWBR,
+		name:   "SUBSshiftRLreg",
+		argLen: 3,
+		asm:    arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVHBRload",
-		argLen:         2,
-		faultOnNilArg0: true,
-		asm:            ppc64.AMOVHBR,
+		name:   "SUBSshiftRAreg",
+		argLen: 3,
+		asm:    arm.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVBZloadidx",
+		name:   "RSBSshiftLLreg",
 		argLen: 3,
-		asm:    ppc64.AMOVBZ,
+		asm:    arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVHloadidx",
+		name:   "RSBSshiftRLreg",
 		argLen: 3,
-		asm:    ppc64.AMOVH,
+		asm:    arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVHZloadidx",
+		name:   "RSBSshiftRAreg",
 		argLen: 3,
-		asm:    ppc64.AMOVHZ,
+		asm:    arm.ARSB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 0},
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVWloadidx",
-		argLen: 3,
-		asm:    ppc64.AMOVW,
+		name:   "CMP",
+		argLen: 2,
+		asm:    arm.ACMP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVWZloadidx",
-		argLen: 3,
-		asm:    ppc64.AMOVWZ,
+		name:    "CMPconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.ACMP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVDloadidx",
-		argLen: 3,
-		asm:    ppc64.AMOVD,
+		name:        "CMN",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.ACMN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVHBRloadidx",
-		argLen: 3,
-		asm:    ppc64.AMOVHBR,
+		name:    "CMNconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.ACMN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVWBRloadidx",
-		argLen: 3,
-		asm:    ppc64.AMOVWBR,
+		name:        "TST",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVDBRloadidx",
-		argLen: 3,
-		asm:    ppc64.AMOVDBR,
+		name:    "TSTconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:   "FMOVDloadidx",
-		argLen: 3,
-		asm:    ppc64.AFMOVD,
+		name:        "TEQ",
+		argLen:      2,
+		commutative: true,
+		asm:         arm.ATEQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
-			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:   "FMOVSloadidx",
-		argLen: 3,
-		asm:    ppc64.AFMOVS,
+		name:    "TEQconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm.ATEQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
-			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:           "DCBT",
-		auxType:        auxInt64,
-		argLen:         2,
-		hasSideEffects: true,
-		asm:            ppc64.ADCBT,
+		name:   "CMPF",
+		argLen: 2,
+		asm:    arm.ACMPF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:           "MOVDBRstore",
-		argLen:         3,
-		faultOnNilArg0: true,
-		asm:            ppc64.AMOVDBR,
+		name:   "CMPD",
+		argLen: 2,
+		asm:    arm.ACMPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:           "MOVWBRstore",
-		argLen:         3,
-		faultOnNilArg0: true,
-		asm:            ppc64.AMOVWBR,
+		name:    "CMPshiftLL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ACMP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVHBRstore",
-		argLen:         3,
-		faultOnNilArg0: true,
-		asm:            ppc64.AMOVHBR,
+		name:    "CMPshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ACMP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:           "FMOVDload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            ppc64.AFMOVD,
+		name:    "CMPshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ACMP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
-			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:           "FMOVSload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            ppc64.AFMOVS,
+		name:    "CMNshiftLL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ACMN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
-			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVBstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            ppc64.AMOVB,
+		name:    "CMNshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ACMN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVHstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            ppc64.AMOVH,
+		name:    "CMNshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ACMN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVWstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            ppc64.AMOVW,
+		name:    "TSTshiftLL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVDstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            ppc64.AMOVD,
+		name:    "TSTshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:           "FMOVDstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            ppc64.AFMOVD,
+		name:    "TSTshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:           "FMOVSstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            ppc64.AFMOVS,
+		name:    "TEQshiftLL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ATEQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVBstoreidx",
-		argLen: 4,
-		asm:    ppc64.AMOVB,
+		name:    "TEQshiftRL",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ATEQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVHstoreidx",
-		argLen: 4,
-		asm:    ppc64.AMOVH,
+		name:    "TEQshiftRA",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     arm.ATEQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVWstoreidx",
-		argLen: 4,
-		asm:    ppc64.AMOVW,
+		name:   "CMPshiftLLreg",
+		argLen: 3,
+		asm:    arm.ACMP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVDstoreidx",
-		argLen: 4,
-		asm:    ppc64.AMOVD,
+		name:   "CMPshiftRLreg",
+		argLen: 3,
+		asm:    arm.ACMP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FMOVDstoreidx",
-		argLen: 4,
-		asm:    ppc64.AFMOVD,
+		name:   "CMPshiftRAreg",
+		argLen: 3,
+		asm:    arm.ACMP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FMOVSstoreidx",
-		argLen: 4,
-		asm:    ppc64.AFMOVS,
+		name:   "CMNshiftLLreg",
+		argLen: 3,
+		asm:    arm.ACMN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVHBRstoreidx",
-		argLen: 4,
-		asm:    ppc64.AMOVHBR,
+		name:   "CMNshiftRLreg",
+		argLen: 3,
+		asm:    arm.ACMN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVWBRstoreidx",
-		argLen: 4,
-		asm:    ppc64.AMOVWBR,
+		name:   "CMNshiftRAreg",
+		argLen: 3,
+		asm:    arm.ACMN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "MOVDBRstoreidx",
-		argLen: 4,
-		asm:    ppc64.AMOVDBR,
+		name:   "TSTshiftLLreg",
+		argLen: 3,
+		asm:    arm.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVBstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            ppc64.AMOVB,
+		name:   "TSTshiftRLreg",
+		argLen: 3,
+		asm:    arm.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVHstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            ppc64.AMOVH,
+		name:   "TSTshiftRAreg",
+		argLen: 3,
+		asm:    arm.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVWstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            ppc64.AMOVW,
+		name:   "TEQshiftLLreg",
+		argLen: 3,
+		asm:    arm.ATEQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "MOVDstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            ppc64.AMOVD,
+		name:   "TEQshiftRLreg",
+		argLen: 3,
+		asm:    arm.ATEQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:              "MOVDaddr",
-		auxType:           auxSymOff,
-		argLen:            1,
-		rematerializeable: true,
-		symEffect:         SymAddr,
-		asm:               ppc64.AMOVD,
+		name:   "TEQshiftRAreg",
+		argLen: 3,
+		asm:    arm.ATEQ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+		},
+	},
+	{
+		name:   "CMPF0",
+		argLen: 1,
+		asm:    arm.ACMPF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:              "MOVDconst",
-		auxType:           auxInt64,
+		name:   "CMPD0",
+		argLen: 1,
+		asm:    arm.ACMPD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:              "MOVWconst",
+		auxType:           auxInt32,
 		argLen:            0,
 		rematerializeable: true,
-		asm:               ppc64.AMOVD,
+		asm:               arm.AMOVW,
 		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:              "FMOVDconst",
+		name:              "MOVFconst",
 		auxType:           auxFloat64,
 		argLen:            0,
 		rematerializeable: true,
-		asm:               ppc64.AFMOVD,
+		asm:               arm.AMOVF,
 		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:              "FMOVSconst",
-		auxType:           auxFloat32,
+		name:              "MOVDconst",
+		auxType:           auxFloat64,
 		argLen:            0,
 		rematerializeable: true,
-		asm:               ppc64.AFMOVS,
+		asm:               arm.AMOVD,
 		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:   "FCMPU",
-		argLen: 2,
-		asm:    ppc64.AFCMPU,
+		name:              "MOVWaddr",
+		auxType:           auxSymOff,
+		argLen:            1,
+		rematerializeable: true,
+		symEffect:         SymAddr,
+		asm:               arm.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 4294975488}, // SP SB
+			},
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "CMP",
-		argLen: 2,
-		asm:    ppc64.ACMP,
+		name:           "MOVBload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "CMPU",
-		argLen: 2,
-		asm:    ppc64.ACMPU,
+		name:           "MOVBUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm.AMOVBU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "CMPW",
-		argLen: 2,
-		asm:    ppc64.ACMPW,
+		name:           "MOVHload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "CMPWU",
-		argLen: 2,
-		asm:    ppc64.ACMPWU,
+		name:           "MOVHUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm.AMOVHU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "CMPconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.ACMP,
+		name:           "MOVWload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:    "CMPUconst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     ppc64.ACMPU,
+		name:           "MOVFload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm.AMOVF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:    "CMPWconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     ppc64.ACMPW,
+		name:           "MOVDload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm.AMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:    "CMPWUconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     ppc64.ACMPWU,
+		name:           "MOVBstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            arm.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 			},
 		},
 	},
 	{
-		name:    "ISEL",
-		auxType: auxInt32,
-		argLen:  3,
-		asm:     ppc64.AISEL,
+		name:           "MOVHstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            arm.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 			},
 		},
 	},
 	{
-		name:    "ISELZ",
-		auxType: auxInt32,
-		argLen:  2,
-		asm:     ppc64.AISEL,
+		name:           "MOVWstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            arm.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 			},
 		},
 	},
 	{
-		name:    "SETBC",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     ppc64.ASETBC,
+		name:           "MOVFstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            arm.AMOVF,
 		reg: regInfo{
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			inputs: []inputInfo{
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:    "SETBCR",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     ppc64.ASETBCR,
+		name:           "MOVDstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            arm.AMOVD,
 		reg: regInfo{
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			inputs: []inputInfo{
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:   "Equal",
-		argLen: 1,
+		name:   "MOVWloadidx",
+		argLen: 3,
+		asm:    arm.AMOVW,
 		reg: regInfo{
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			inputs: []inputInfo{
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 			},
-		},
-	},
-	{
-		name:   "NotEqual",
-		argLen: 1,
-		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "LessThan",
-		argLen: 1,
+		name:    "MOVWloadshiftLL",
+		auxType: auxInt32,
+		argLen:  3,
+		asm:     arm.AMOVW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FLessThan",
-		argLen: 1,
+		name:    "MOVWloadshiftRL",
+		auxType: auxInt32,
+		argLen:  3,
+		asm:     arm.AMOVW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "LessEqual",
-		argLen: 1,
+		name:    "MOVWloadshiftRA",
+		auxType: auxInt32,
+		argLen:  3,
+		asm:     arm.AMOVW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FLessEqual",
-		argLen: 1,
+		name:   "MOVBUloadidx",
+		argLen: 3,
+		asm:    arm.AMOVBU,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "GreaterThan",
-		argLen: 1,
+		name:   "MOVBloadidx",
+		argLen: 3,
+		asm:    arm.AMOVB,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FGreaterThan",
-		argLen: 1,
+		name:   "MOVHUloadidx",
+		argLen: 3,
+		asm:    arm.AMOVHU,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "GreaterEqual",
-		argLen: 1,
+		name:   "MOVHloadidx",
+		argLen: 3,
+		asm:    arm.AMOVH,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:   "FGreaterEqual",
-		argLen: 1,
+		name:   "MOVWstoreidx",
+		argLen: 4,
+		asm:    arm.AMOVW,
 		reg: regInfo{
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			inputs: []inputInfo{
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 			},
 		},
 	},
 	{
-		name:      "LoweredGetClosurePtr",
-		argLen:    0,
-		zeroWidth: true,
+		name:    "MOVWstoreshiftLL",
+		auxType: auxInt32,
+		argLen:  4,
+		asm:     arm.AMOVW,
 		reg: regInfo{
-			outputs: []outputInfo{
-				{0, 2048}, // R11
+			inputs: []inputInfo{
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerSP",
-		argLen:            1,
-		rematerializeable: true,
+		name:    "MOVWstoreshiftRL",
+		auxType: auxInt32,
+		argLen:  4,
+		asm:     arm.AMOVW,
 		reg: regInfo{
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			inputs: []inputInfo{
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerPC",
-		argLen:            0,
-		rematerializeable: true,
+		name:    "MOVWstoreshiftRA",
+		auxType: auxInt32,
+		argLen:  4,
+		asm:     arm.AMOVW,
 		reg: regInfo{
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			inputs: []inputInfo{
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 			},
 		},
 	},
 	{
-		name:           "LoweredNilCheck",
-		argLen:         2,
-		clobberFlags:   true,
-		nilCheck:       true,
-		faultOnNilArg0: true,
+		name:   "MOVBstoreidx",
+		argLen: 4,
+		asm:    arm.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 			},
-			clobbers: 2147483648, // R31
 		},
 	},
 	{
-		name:         "LoweredRound32F",
-		argLen:       1,
-		resultInArg0: true,
-		zeroWidth:    true,
+		name:   "MOVHstoreidx",
+		argLen: 4,
+		asm:    arm.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+			},
+		},
+	},
+	{
+		name:   "MOVBreg",
+		argLen: 1,
+		asm:    arm.AMOVBS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:         "LoweredRound64F",
-		argLen:       1,
-		resultInArg0: true,
-		zeroWidth:    true,
+		name:   "MOVBUreg",
+		argLen: 1,
+		asm:    arm.AMOVBU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:         "CALLstatic",
-		auxType:      auxCallOff,
-		argLen:       -1,
-		clobberFlags: true,
-		call:         true,
+		name:   "MOVHreg",
+		argLen: 1,
+		asm:    arm.AMOVHS,
 		reg: regInfo{
-			clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
+			inputs: []inputInfo{
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
 		},
 	},
 	{
-		name:         "CALLtail",
-		auxType:      auxCallOff,
-		argLen:       -1,
-		clobberFlags: true,
-		call:         true,
-		tailCall:     true,
+		name:   "MOVHUreg",
+		argLen: 1,
+		asm:    arm.AMOVHU,
 		reg: regInfo{
-			clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
+			inputs: []inputInfo{
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
 		},
 	},
 	{
-		name:         "CALLclosure",
-		auxType:      auxCallOff,
-		argLen:       -1,
-		clobberFlags: true,
-		call:         true,
+		name:   "MOVWreg",
+		argLen: 1,
+		asm:    arm.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4096}, // R12
-				{1, 2048}, // R11
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
-			clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
 		},
 	},
 	{
-		name:         "CALLinter",
-		auxType:      auxCallOff,
-		argLen:       -1,
-		clobberFlags: true,
-		call:         true,
+		name:         "MOVWnop",
+		argLen:       1,
+		resultInArg0: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4096}, // R12
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
-			clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
 		},
 	},
 	{
-		name:           "LoweredZero",
-		auxType:        auxInt64,
-		argLen:         2,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		unsafePoint:    true,
+		name:   "MOVWF",
+		argLen: 1,
+		asm:    arm.AMOVWF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1048576}, // R20
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2147483648, // F15
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
-			clobbers: 1048576, // R20
 		},
 	},
 	{
-		name:           "LoweredZeroShort",
-		auxType:        auxInt64,
-		argLen:         2,
-		faultOnNilArg0: true,
-		unsafePoint:    true,
+		name:   "MOVWD",
+		argLen: 1,
+		asm:    arm.AMOVWD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2147483648, // F15
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:           "LoweredQuadZeroShort",
-		auxType:        auxInt64,
-		argLen:         2,
-		faultOnNilArg0: true,
-		unsafePoint:    true,
+		name:   "MOVWUF",
+		argLen: 1,
+		asm:    arm.AMOVWF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2147483648, // F15
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:           "LoweredQuadZero",
-		auxType:        auxInt64,
-		argLen:         2,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		unsafePoint:    true,
+		name:   "MOVWUD",
+		argLen: 1,
+		asm:    arm.AMOVWD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1048576}, // R20
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2147483648, // F15
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
-			clobbers: 1048576, // R20
 		},
 	},
 	{
-		name:           "LoweredMove",
-		auxType:        auxInt64,
-		argLen:         3,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
-		unsafePoint:    true,
+		name:   "MOVFW",
+		argLen: 1,
+		asm:    arm.AMOVFW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1048576}, // R20
-				{1, 2097152}, // R21
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			clobbers: 2147483648, // F15
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
-			clobbers: 3145728, // R20 R21
 		},
 	},
 	{
-		name:           "LoweredMoveShort",
-		auxType:        auxInt64,
-		argLen:         3,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
-		unsafePoint:    true,
+		name:   "MOVDW",
+		argLen: 1,
+		asm:    arm.AMOVDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			clobbers: 2147483648, // F15
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "LoweredQuadMove",
-		auxType:        auxInt64,
-		argLen:         3,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
-		unsafePoint:    true,
+		name:   "MOVFWU",
+		argLen: 1,
+		asm:    arm.AMOVFW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1048576}, // R20
-				{1, 2097152}, // R21
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			clobbers: 2147483648, // F15
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
-			clobbers: 3145728, // R20 R21
 		},
 	},
 	{
-		name:           "LoweredQuadMoveShort",
-		auxType:        auxInt64,
-		argLen:         3,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
-		unsafePoint:    true,
+		name:   "MOVDWU",
+		argLen: 1,
+		asm:    arm.AMOVDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			clobbers: 2147483648, // F15
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore8",
-		auxType:        auxInt64,
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:   "MOVFD",
+		argLen: 1,
+		asm:    arm.AMOVFD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore32",
-		auxType:        auxInt64,
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:   "MOVDF",
+		argLen: 1,
+		asm:    arm.AMOVDF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore64",
-		auxType:        auxInt64,
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:         "CMOVWHSconst",
+		auxType:      auxInt32,
+		argLen:       2,
+		resultInArg0: true,
+		asm:          arm.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad8",
-		auxType:        auxInt64,
-		argLen:         2,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
+		name:         "CMOVWLSconst",
+		auxType:      auxInt32,
+		argLen:       2,
+		resultInArg0: true,
+		asm:          arm.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad32",
-		auxType:        auxInt64,
-		argLen:         2,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
+		name:   "SRAcond",
+		argLen: 3,
+		asm:    arm.ASRA,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad64",
-		auxType:        auxInt64,
-		argLen:         2,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
+		name:         "CALLstatic",
+		auxType:      auxCallOff,
+		argLen:       1,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+		},
+	},
+	{
+		name:         "CALLtail",
+		auxType:      auxCallOff,
+		argLen:       1,
+		clobberFlags: true,
+		call:         true,
+		tailCall:     true,
+		reg: regInfo{
+			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+		},
+	},
+	{
+		name:         "CALLclosure",
+		auxType:      auxCallOff,
+		argLen:       3,
+		clobberFlags: true,
+		call:         true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 128},   // R7
+				{0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14
 			},
-			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+		},
+	},
+	{
+		name:         "CALLinter",
+		auxType:      auxCallOff,
+		argLen:       2,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
+			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 		},
 	},
 	{
-		name:           "LoweredAtomicLoadPtr",
-		auxType:        auxInt64,
+		name:           "LoweredNilCheck",
 		argLen:         2,
-		clobberFlags:   true,
+		nilCheck:       true,
 		faultOnNilArg0: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 			},
+		},
+	},
+	{
+		name:   "Equal",
+		argLen: 1,
+		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAdd32",
-		argLen:          3,
-		resultNotInArgs: true,
-		clobberFlags:    true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "NotEqual",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAdd64",
-		argLen:          3,
-		resultNotInArgs: true,
-		clobberFlags:    true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "LessThan",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange8",
-		argLen:          3,
-		resultNotInArgs: true,
-		clobberFlags:    true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "LessEqual",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange32",
-		argLen:          3,
-		resultNotInArgs: true,
-		clobberFlags:    true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "GreaterThan",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange64",
-		argLen:          3,
-		resultNotInArgs: true,
-		clobberFlags:    true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "GreaterEqual",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas64",
-		auxType:         auxInt64,
-		argLen:          4,
-		resultNotInArgs: true,
-		clobberFlags:    true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "LessThanU",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas32",
-		auxType:         auxInt64,
-		argLen:          4,
-		resultNotInArgs: true,
-		clobberFlags:    true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:   "LessEqualU",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-			},
 			outputs: []outputInfo{
-				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicAnd8",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		asm:            ppc64.AAND,
+		name:   "GreaterThanU",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicAnd32",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		asm:            ppc64.AAND,
+		name:   "GreaterEqualU",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicOr8",
+		name:           "DUFFZERO",
+		auxType:        auxInt64,
 		argLen:         3,
 		faultOnNilArg0: true,
-		hasSideEffects: true,
-		asm:            ppc64.AOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 2}, // R1
+				{1, 1}, // R0
 			},
+			clobbers: 20482, // R1 R12 R14
 		},
 	},
 	{
-		name:           "LoweredAtomicOr32",
+		name:           "DUFFCOPY",
+		auxType:        auxInt64,
 		argLen:         3,
 		faultOnNilArg0: true,
-		hasSideEffects: true,
-		asm:            ppc64.AOR,
+		faultOnNilArg1: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 4}, // R2
+				{1, 2}, // R1
 			},
+			clobbers: 20487, // R0 R1 R2 R12 R14
 		},
 	},
 	{
-		name:         "LoweredWB",
-		auxType:      auxInt64,
-		argLen:       1,
-		clobberFlags: true,
-		reg: regInfo{
-			clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
-			outputs: []outputInfo{
-				{0, 536870912}, // R29
+		name:           "LoweredZero",
+		auxType:        auxInt64,
+		argLen:         4,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2},     // R1
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 			},
+			clobbers: 2, // R1
 		},
 	},
 	{
-		name:           "LoweredPubBarrier",
-		argLen:         1,
-		hasSideEffects: true,
-		asm:            ppc64.ALWSYNC,
-		reg:            regInfo{},
+		name:           "LoweredMove",
+		auxType:        auxInt64,
+		argLen:         4,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4},     // R2
+				{1, 2},     // R1
+				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 6, // R1 R2
+		},
+	},
+	{
+		name:      "LoweredGetClosurePtr",
+		argLen:    0,
+		zeroWidth: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 128}, // R7
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerSP",
+		argLen:            1,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerPC",
+		argLen:            0,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+		},
 	},
 	{
 		name:    "LoweredPanicBoundsA",
@@ -33009,8 +37160,8 @@ var opcodeTable = [...]opInfo{
 		call:    true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 32}, // R5
-				{1, 64}, // R6
+				{0, 4}, // R2
+				{1, 8}, // R3
 			},
 		},
 	},
@@ -33021,8 +37172,8 @@ var opcodeTable = [...]opInfo{
 		call:    true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 16}, // R4
-				{1, 32}, // R5
+				{0, 2}, // R1
+				{1, 4}, // R2
 			},
 		},
 	},
@@ -33033,126 +37184,215 @@ var opcodeTable = [...]opInfo{
 		call:    true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 8},  // R3
-				{1, 16}, // R4
+				{0, 1}, // R0
+				{1, 2}, // R1
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicExtendA",
+		auxType: auxInt64,
+		argLen:  4,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 16}, // R4
+				{1, 4},  // R2
+				{2, 8},  // R3
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicExtendB",
+		auxType: auxInt64,
+		argLen:  4,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 16}, // R4
+				{1, 2},  // R1
+				{2, 4},  // R2
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicExtendC",
+		auxType: auxInt64,
+		argLen:  4,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 16}, // R4
+				{1, 1},  // R0
+				{2, 2},  // R1
 			},
 		},
 	},
+	{
+		name:    "FlagConstant",
+		auxType: auxFlagConstant,
+		argLen:  0,
+		reg:     regInfo{},
+	},
 	{
 		name:   "InvertFlags",
 		argLen: 1,
 		reg:    regInfo{},
 	},
 	{
-		name:   "FlagEQ",
-		argLen: 0,
-		reg:    regInfo{},
+		name:         "LoweredWB",
+		auxType:      auxInt64,
+		argLen:       1,
+		clobberFlags: true,
+		reg: regInfo{
+			clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			outputs: []outputInfo{
+				{0, 256}, // R8
+			},
+		},
 	},
+
 	{
-		name:   "FlagLT",
-		argLen: 0,
-		reg:    regInfo{},
+		name:        "ADCSflags",
+		argLen:      3,
+		commutative: true,
+		asm:         arm64.AADCS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+			},
+			outputs: []outputInfo{
+				{1, 0},
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+			},
+		},
 	},
 	{
-		name:   "FlagGT",
-		argLen: 0,
-		reg:    regInfo{},
+		name:   "ADCzerocarry",
+		argLen: 1,
+		asm:    arm64.AADC,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+			},
+		},
 	},
-
 	{
 		name:        "ADD",
 		argLen:      2,
 		commutative: true,
-		asm:         riscv.AADD,
+		asm:         arm64.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "ADDI",
+		name:    "ADDconst",
 		auxType: auxInt64,
 		argLen:  1,
-		asm:     riscv.AADDI,
+		asm:     arm64.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 1476395007}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "ADDIW",
+		name:    "ADDSconstflags",
 		auxType: auxInt64,
 		argLen:  1,
-		asm:     riscv.AADDIW,
+		asm:     arm64.AADDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 0},
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "NEG",
-		argLen: 1,
-		asm:    riscv.ANEG,
+		name:        "ADDSflags",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.AADDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 0},
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "NEGW",
-		argLen: 1,
-		asm:    riscv.ANEGW,
+		name:   "SUB",
+		argLen: 2,
+		asm:    arm64.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SUB",
-		argLen: 2,
-		asm:    riscv.ASUB,
+		name:    "SUBconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SUBW",
+		name:   "SBCSflags",
+		argLen: 3,
+		asm:    arm64.ASBCS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+			},
+			outputs: []outputInfo{
+				{1, 0},
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+			},
+		},
+	},
+	{
+		name:   "SUBSflags",
 		argLen: 2,
-		asm:    riscv.ASUBW,
+		asm:    arm64.ASUBS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 0},
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
@@ -33160,14 +37400,14 @@ var opcodeTable = [...]opInfo{
 		name:        "MUL",
 		argLen:      2,
 		commutative: true,
-		asm:         riscv.AMUL,
+		asm:         arm64.AMUL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
@@ -33175,9506 +37415,33041 @@ var opcodeTable = [...]opInfo{
 		name:        "MULW",
 		argLen:      2,
 		commutative: true,
-		asm:         riscv.AMULW,
+		asm:         arm64.AMULW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "MULH",
+		name:        "MNEG",
 		argLen:      2,
 		commutative: true,
-		asm:         riscv.AMULH,
+		asm:         arm64.AMNEG,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "MULHU",
+		name:        "MNEGW",
 		argLen:      2,
 		commutative: true,
-		asm:         riscv.AMULHU,
+		asm:         arm64.AMNEGW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:            "LoweredMuluhilo",
-		argLen:          2,
-		resultNotInArgs: true,
+		name:        "MULH",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.ASMULH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:            "LoweredMuluover",
-		argLen:          2,
-		resultNotInArgs: true,
+		name:        "UMULH",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.AUMULH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "DIV",
-		argLen: 2,
-		asm:    riscv.ADIV,
+		name:        "MULL",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.ASMULL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "DIVU",
-		argLen: 2,
-		asm:    riscv.ADIVU,
+		name:        "UMULL",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.AUMULL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "DIVW",
+		name:   "DIV",
 		argLen: 2,
-		asm:    riscv.ADIVW,
+		asm:    arm64.ASDIV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "DIVUW",
+		name:   "UDIV",
 		argLen: 2,
-		asm:    riscv.ADIVUW,
+		asm:    arm64.AUDIV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "REM",
+		name:   "DIVW",
 		argLen: 2,
-		asm:    riscv.AREM,
+		asm:    arm64.ASDIVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "REMU",
+		name:   "UDIVW",
 		argLen: 2,
-		asm:    riscv.AREMU,
+		asm:    arm64.AUDIVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "REMW",
+		name:   "MOD",
 		argLen: 2,
-		asm:    riscv.AREMW,
+		asm:    arm64.AREM,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "REMUW",
+		name:   "UMOD",
 		argLen: 2,
-		asm:    riscv.AREMUW,
+		asm:    arm64.AUREM,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:              "MOVaddr",
-		auxType:           auxSymOff,
-		argLen:            1,
-		rematerializeable: true,
-		symEffect:         SymAddr,
-		asm:               riscv.AMOV,
+		name:   "MODW",
+		argLen: 2,
+		asm:    arm64.AREMW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:              "MOVDconst",
-		auxType:           auxInt64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               riscv.AMOV,
+		name:   "UMODW",
+		argLen: 2,
+		asm:    arm64.AUREMW,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "MOVBload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            riscv.AMOVB,
+		name:        "FADDS",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.AFADDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVHload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            riscv.AMOVH,
+		name:        "FADDD",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.AFADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVWload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            riscv.AMOVW,
+		name:   "FSUBS",
+		argLen: 2,
+		asm:    arm64.AFSUBS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVDload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            riscv.AMOV,
+		name:   "FSUBD",
+		argLen: 2,
+		asm:    arm64.AFSUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVBUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            riscv.AMOVBU,
+		name:        "FMULS",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.AFMULS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVHUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            riscv.AMOVHU,
+		name:        "FMULD",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.AFMULD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVWUload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            riscv.AMOVWU,
+		name:        "FNMULS",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.AFNMULS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVBstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            riscv.AMOVB,
+		name:        "FNMULD",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.AFNMULD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVHstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            riscv.AMOVH,
+		name:   "FDIVS",
+		argLen: 2,
+		asm:    arm64.AFDIVS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVWstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            riscv.AMOVW,
+		name:   "FDIVD",
+		argLen: 2,
+		asm:    arm64.AFDIVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVDstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            riscv.AMOV,
+		name:        "AND",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "MOVBstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            riscv.AMOVB,
+		name:    "ANDconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "MOVHstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            riscv.AMOVH,
+		name:        "OR",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "MOVWstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            riscv.AMOVW,
+		name:    "ORconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "MOVDstorezero",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            riscv.AMOV,
+		name:        "XOR",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "MOVBreg",
-		argLen: 1,
-		asm:    riscv.AMOVB,
+		name:    "XORconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "MOVHreg",
-		argLen: 1,
-		asm:    riscv.AMOVH,
+		name:   "BIC",
+		argLen: 2,
+		asm:    arm64.ABIC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "MOVWreg",
-		argLen: 1,
-		asm:    riscv.AMOVW,
+		name:   "EON",
+		argLen: 2,
+		asm:    arm64.AEON,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "MOVDreg",
-		argLen: 1,
-		asm:    riscv.AMOV,
+		name:   "ORN",
+		argLen: 2,
+		asm:    arm64.AORN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "MOVBUreg",
+		name:   "MVN",
 		argLen: 1,
-		asm:    riscv.AMOVBU,
+		asm:    arm64.AMVN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "MOVHUreg",
+		name:   "NEG",
 		argLen: 1,
-		asm:    riscv.AMOVHU,
+		asm:    arm64.ANEG,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "MOVWUreg",
+		name:   "NEGSflags",
 		argLen: 1,
-		asm:    riscv.AMOVWU,
+		asm:    arm64.ANEGS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 0},
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "MOVDnop",
-		argLen:       1,
-		resultInArg0: true,
+		name:   "NGCzerocarry",
+		argLen: 1,
+		asm:    arm64.ANGC,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SLL",
-		argLen: 2,
-		asm:    riscv.ASLL,
+		name:   "FABSD",
+		argLen: 1,
+		asm:    arm64.AFABSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "SLLW",
-		argLen: 2,
-		asm:    riscv.ASLLW,
+		name:   "FNEGS",
+		argLen: 1,
+		asm:    arm64.AFNEGS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "SRA",
-		argLen: 2,
-		asm:    riscv.ASRA,
+		name:   "FNEGD",
+		argLen: 1,
+		asm:    arm64.AFNEGD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "SRAW",
-		argLen: 2,
-		asm:    riscv.ASRAW,
+		name:   "FSQRTD",
+		argLen: 1,
+		asm:    arm64.AFSQRTD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "SRL",
-		argLen: 2,
-		asm:    riscv.ASRL,
+		name:   "FSQRTS",
+		argLen: 1,
+		asm:    arm64.AFSQRTS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "SRLW",
+		name:   "FMIND",
 		argLen: 2,
-		asm:    riscv.ASRLW,
+		asm:    arm64.AFMIND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "SLLI",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     riscv.ASLLI,
+		name:   "FMINS",
+		argLen: 2,
+		asm:    arm64.AFMINS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "SLLIW",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     riscv.ASLLIW,
+		name:   "FMAXD",
+		argLen: 2,
+		asm:    arm64.AFMAXD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "SRAI",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     riscv.ASRAI,
+		name:   "FMAXS",
+		argLen: 2,
+		asm:    arm64.AFMAXS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "SRAIW",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     riscv.ASRAIW,
+		name:   "REV",
+		argLen: 1,
+		asm:    arm64.AREV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "SRLI",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     riscv.ASRLI,
+		name:   "REVW",
+		argLen: 1,
+		asm:    arm64.AREVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "SRLIW",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     riscv.ASRLIW,
+		name:   "REV16",
+		argLen: 1,
+		asm:    arm64.AREV16,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SH1ADD",
-		argLen: 2,
-		asm:    riscv.ASH1ADD,
+		name:   "REV16W",
+		argLen: 1,
+		asm:    arm64.AREV16W,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SH2ADD",
-		argLen: 2,
-		asm:    riscv.ASH2ADD,
+		name:   "RBIT",
+		argLen: 1,
+		asm:    arm64.ARBIT,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SH3ADD",
-		argLen: 2,
-		asm:    riscv.ASH3ADD,
+		name:   "RBITW",
+		argLen: 1,
+		asm:    arm64.ARBITW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "AND",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AAND,
+		name:   "CLZ",
+		argLen: 1,
+		asm:    arm64.ACLZ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "ANDN",
-		argLen: 2,
-		asm:    riscv.AANDN,
+		name:   "CLZW",
+		argLen: 1,
+		asm:    arm64.ACLZW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "ANDI",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     riscv.AANDI,
+		name:   "VCNT",
+		argLen: 1,
+		asm:    arm64.AVCNT,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "CLZ",
+		name:   "VUADDLV",
 		argLen: 1,
-		asm:    riscv.ACLZ,
+		asm:    arm64.AVUADDLV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "CLZW",
-		argLen: 1,
-		asm:    riscv.ACLZW,
+		name:         "LoweredRound32F",
+		argLen:       1,
+		resultInArg0: true,
+		zeroWidth:    true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "CPOP",
-		argLen: 1,
-		asm:    riscv.ACPOP,
+		name:         "LoweredRound64F",
+		argLen:       1,
+		resultInArg0: true,
+		zeroWidth:    true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "CPOPW",
-		argLen: 1,
-		asm:    riscv.ACPOPW,
+		name:   "FMADDS",
+		argLen: 3,
+		asm:    arm64.AFMADDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "CTZ",
-		argLen: 1,
-		asm:    riscv.ACTZ,
+		name:   "FMADDD",
+		argLen: 3,
+		asm:    arm64.AFMADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "CTZW",
-		argLen: 1,
-		asm:    riscv.ACTZW,
+		name:   "FNMADDS",
+		argLen: 3,
+		asm:    arm64.AFNMADDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "NOT",
-		argLen: 1,
-		asm:    riscv.ANOT,
+		name:   "FNMADDD",
+		argLen: 3,
+		asm:    arm64.AFNMADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:        "OR",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AOR,
+		name:   "FMSUBS",
+		argLen: 3,
+		asm:    arm64.AFMSUBS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "ORN",
-		argLen: 2,
-		asm:    riscv.AORN,
+		name:   "FMSUBD",
+		argLen: 3,
+		asm:    arm64.AFMSUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "ORI",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     riscv.AORI,
+		name:   "FNMSUBS",
+		argLen: 3,
+		asm:    arm64.AFNMSUBS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "REV8",
-		argLen: 1,
-		asm:    riscv.AREV8,
+		name:   "FNMSUBD",
+		argLen: 3,
+		asm:    arm64.AFNMSUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "ROL",
-		argLen: 2,
-		asm:    riscv.AROL,
+		name:   "MADD",
+		argLen: 3,
+		asm:    arm64.AMADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "ROLW",
-		argLen: 2,
-		asm:    riscv.AROLW,
+		name:   "MADDW",
+		argLen: 3,
+		asm:    arm64.AMADDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "ROR",
-		argLen: 2,
-		asm:    riscv.AROR,
+		name:   "MSUB",
+		argLen: 3,
+		asm:    arm64.AMSUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "RORI",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     riscv.ARORI,
+		name:   "MSUBW",
+		argLen: 3,
+		asm:    arm64.AMSUBW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "RORIW",
+		name:   "SLL",
+		argLen: 2,
+		asm:    arm64.ALSL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+			},
+		},
+	},
+	{
+		name:    "SLLconst",
 		auxType: auxInt64,
 		argLen:  1,
-		asm:     riscv.ARORIW,
+		asm:     arm64.ALSL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "RORW",
+		name:   "SRL",
 		argLen: 2,
-		asm:    riscv.ARORW,
+		asm:    arm64.ALSR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "XNOR",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AXNOR,
+		name:    "SRLconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.ALSR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "XOR",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AXOR,
+		name:   "SRA",
+		argLen: 2,
+		asm:    arm64.AASR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "XORI",
+		name:    "SRAconst",
 		auxType: auxInt64,
 		argLen:  1,
-		asm:     riscv.AXORI,
+		asm:     arm64.AASR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "MIN",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AMIN,
+		name:   "ROR",
+		argLen: 2,
+		asm:    arm64.AROR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "MAX",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AMAX,
+		name:   "RORW",
+		argLen: 2,
+		asm:    arm64.ARORW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "MINU",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AMINU,
+		name:    "RORconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.AROR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "MAXU",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AMAXU,
+		name:    "RORWconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.ARORW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SEQZ",
-		argLen: 1,
-		asm:    riscv.ASEQZ,
+		name:    "EXTRconst",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AEXTR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SNEZ",
-		argLen: 1,
-		asm:    riscv.ASNEZ,
+		name:    "EXTRWconst",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AEXTRW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SLT",
+		name:   "CMP",
 		argLen: 2,
-		asm:    riscv.ASLT,
+		asm:    arm64.ACMP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-			},
-			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:    "SLTI",
+		name:    "CMPconst",
 		auxType: auxInt64,
 		argLen:  1,
-		asm:     riscv.ASLTI,
+		asm:     arm64.ACMP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-			},
-			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:   "SLTU",
+		name:   "CMPW",
 		argLen: 2,
-		asm:    riscv.ASLTU,
+		asm:    arm64.ACMPW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-			},
-			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:    "SLTIU",
-		auxType: auxInt64,
+		name:    "CMPWconst",
+		auxType: auxInt32,
 		argLen:  1,
-		asm:     riscv.ASLTIU,
+		asm:     arm64.ACMPW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-			},
-			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:         "LoweredRound32F",
-		argLen:       1,
-		resultInArg0: true,
+		name:        "CMN",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.ACMN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:         "LoweredRound64F",
-		argLen:       1,
-		resultInArg0: true,
+		name:    "CMNconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.ACMN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:    "CALLstatic",
-		auxType: auxCallOff,
-		argLen:  -1,
-		call:    true,
+		name:        "CMNW",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.ACMNW,
 		reg: regInfo{
-			clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			inputs: []inputInfo{
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
 		},
 	},
 	{
-		name:     "CALLtail",
-		auxType:  auxCallOff,
-		argLen:   -1,
-		call:     true,
-		tailCall: true,
+		name:    "CMNWconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm64.ACMNW,
 		reg: regInfo{
-			clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			inputs: []inputInfo{
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
 		},
 	},
 	{
-		name:    "CALLclosure",
-		auxType: auxCallOff,
-		argLen:  -1,
-		call:    true,
+		name:        "TST",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 33554432},   // X26
-				{0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
-			clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:    "CALLinter",
-		auxType: auxCallOff,
-		argLen:  -1,
-		call:    true,
+		name:    "TSTconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
-			clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:           "DUFFZERO",
-		auxType:        auxInt64,
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:        "TSTW",
+		argLen:      2,
+		commutative: true,
+		asm:         arm64.ATSTW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 16777216}, // X25
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
-			clobbers: 16777216, // X25
 		},
 	},
 	{
-		name:           "DUFFCOPY",
-		auxType:        auxInt64,
-		argLen:         3,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
+		name:    "TSTWconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     arm64.ATSTW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 16777216}, // X25
-				{1, 8388608},  // X24
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
-			clobbers: 25165824, // X24 X25
 		},
 	},
 	{
-		name:           "LoweredZero",
-		auxType:        auxInt64,
-		argLen:         3,
-		faultOnNilArg0: true,
+		name:   "FCMPS",
+		argLen: 2,
+		asm:    arm64.AFCMPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 16},         // X5
-				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
-			clobbers: 16, // X5
 		},
 	},
 	{
-		name:           "LoweredMove",
-		auxType:        auxInt64,
-		argLen:         4,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
+		name:   "FCMPD",
+		argLen: 2,
+		asm:    arm64.AFCMPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 16},         // X5
-				{1, 32},         // X6
-				{2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
-			clobbers: 112, // X5 X6 X7
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad8",
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:   "FCMPS0",
+		argLen: 1,
+		asm:    arm64.AFCMPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
-			},
-			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad32",
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:   "FCMPD0",
+		argLen: 1,
+		asm:    arm64.AFCMPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
-			},
-			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicLoad64",
-		argLen:         2,
-		faultOnNilArg0: true,
+		name:    "MVNshiftLL",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.AMVN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore8",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:    "MVNshiftRL",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.AMVN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore32",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:    "MVNshiftRA",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.AMVN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicStore64",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
+		name:    "MVNshiftRO",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.AMVN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange32",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:    "NEGshiftLL",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.ANEG,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicExchange64",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
+		name:    "NEGshiftRL",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.ANEG,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAdd32",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "NEGshiftRA",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     arm64.ANEG,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicAdd64",
-		argLen:          3,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "ADDshiftLL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas32",
-		argLen:          4,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "ADDshiftRL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-				{2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:            "LoweredAtomicCas64",
-		argLen:          4,
-		resultNotInArgs: true,
-		faultOnNilArg0:  true,
-		hasSideEffects:  true,
-		unsafePoint:     true,
+		name:    "ADDshiftRA",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AADD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-				{2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicAnd32",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		asm:            riscv.AAMOANDW,
+		name:    "SUBshiftLL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
-		},
-	},
-	{
-		name:           "LoweredAtomicOr32",
-		argLen:         3,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		asm:            riscv.AAMOORW,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "LoweredNilCheck",
-		argLen:         2,
-		nilCheck:       true,
-		faultOnNilArg0: true,
+		name:    "SUBshiftRL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ASUB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
-		},
-	},
-	{
-		name:   "LoweredGetClosurePtr",
-		argLen: 0,
-		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 33554432}, // X26
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerSP",
-		argLen:            1,
-		rematerializeable: true,
+		name:    "SUBshiftRA",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ASUB,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerPC",
-		argLen:            0,
-		rematerializeable: true,
+		name:    "ANDshiftLL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AAND,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "LoweredWB",
-		auxType:      auxInt64,
-		argLen:       1,
-		clobberFlags: true,
+		name:    "ANDshiftRL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AAND,
 		reg: regInfo{
-			clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			inputs: []inputInfo{
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
 			outputs: []outputInfo{
-				{0, 8388608}, // X24
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "LoweredPubBarrier",
-		argLen:         1,
-		hasSideEffects: true,
-		asm:            riscv.AFENCE,
-		reg:            regInfo{},
-	},
-	{
-		name:    "LoweredPanicBoundsA",
+		name:    "ANDshiftRA",
 		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		argLen:  2,
+		asm:     arm64.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 64},        // X7
-				{1, 134217728}, // X28
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsB",
+		name:    "ANDshiftRO",
 		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		argLen:  2,
+		asm:     arm64.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 32}, // X6
-				{1, 64}, // X7
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsC",
+		name:    "ORshiftLL",
 		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		argLen:  2,
+		asm:     arm64.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 16}, // X5
-				{1, 32}, // X6
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "FADDS",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AFADDS,
+		name:    "ORshiftRL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FSUBS",
-		argLen: 2,
-		asm:    riscv.AFSUBS,
+		name:    "ORshiftRA",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "FMULS",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AFMULS,
+		name:    "ORshiftRO",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FDIVS",
-		argLen: 2,
-		asm:    riscv.AFDIVS,
+		name:    "XORshiftLL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "FMADDS",
-		argLen:      3,
-		commutative: true,
-		asm:         riscv.AFMADDS,
+		name:    "XORshiftRL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "FMSUBS",
-		argLen:      3,
-		commutative: true,
-		asm:         riscv.AFMSUBS,
+		name:    "XORshiftRA",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "FNMADDS",
-		argLen:      3,
-		commutative: true,
-		asm:         riscv.AFNMADDS,
+		name:    "XORshiftRO",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AEOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "FNMSUBS",
-		argLen:      3,
-		commutative: true,
-		asm:         riscv.AFNMSUBS,
+		name:    "BICshiftLL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ABIC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FSQRTS",
-		argLen: 1,
-		asm:    riscv.AFSQRTS,
+		name:    "BICshiftRL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ABIC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FNEGS",
-		argLen: 1,
-		asm:    riscv.AFNEGS,
+		name:    "BICshiftRA",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ABIC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FMVSX",
-		argLen: 1,
-		asm:    riscv.AFMVSX,
+		name:    "BICshiftRO",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ABIC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FCVTSW",
-		argLen: 1,
-		asm:    riscv.AFCVTSW,
+		name:    "EONshiftLL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AEON,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FCVTSL",
-		argLen: 1,
-		asm:    riscv.AFCVTSL,
+		name:    "EONshiftRL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AEON,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FCVTWS",
-		argLen: 1,
-		asm:    riscv.AFCVTWS,
+		name:    "EONshiftRA",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AEON,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FCVTLS",
-		argLen: 1,
-		asm:    riscv.AFCVTLS,
+		name:    "EONshiftRO",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AEON,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "FMOVWload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            riscv.AMOVF,
+		name:    "ORNshiftLL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AORN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "FMOVWstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            riscv.AMOVF,
+		name:    "ORNshiftRL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AORN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "FEQS",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AFEQS,
+		name:    "ORNshiftRA",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AORN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "FNES",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AFNES,
+		name:    "ORNshiftRO",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.AORN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FLTS",
-		argLen: 2,
-		asm:    riscv.AFLTS,
+		name:    "CMPshiftLL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ACMP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:   "FLES",
-		argLen: 2,
-		asm:    riscv.AFLES,
+		name:    "CMPshiftRL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ACMP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:            "LoweredFMAXS",
-		argLen:          2,
-		commutative:     true,
-		resultNotInArgs: true,
-		asm:             riscv.AFMAXS,
+		name:    "CMPshiftRA",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ACMP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:            "LoweredFMINS",
-		argLen:          2,
-		commutative:     true,
-		resultNotInArgs: true,
-		asm:             riscv.AFMINS,
+		name:    "CMNshiftLL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ACMN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:        "FADDD",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AFADDD,
+		name:    "CMNshiftRL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ACMN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:   "FSUBD",
-		argLen: 2,
-		asm:    riscv.AFSUBD,
+		name:    "CMNshiftRA",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ACMN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:        "FMULD",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AFMULD,
+		name:    "TSTshiftLL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:   "FDIVD",
-		argLen: 2,
-		asm:    riscv.AFDIVD,
+		name:    "TSTshiftRL",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:        "FMADDD",
-		argLen:      3,
-		commutative: true,
-		asm:         riscv.AFMADDD,
+		name:    "TSTshiftRA",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:        "FMSUBD",
-		argLen:      3,
-		commutative: true,
-		asm:         riscv.AFMSUBD,
+		name:    "TSTshiftRO",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     arm64.ATST,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:        "FNMADDD",
-		argLen:      3,
-		commutative: true,
-		asm:         riscv.AFNMADDD,
+		name:         "BFI",
+		auxType:      auxARM64BitField,
+		argLen:       2,
+		resultInArg0: true,
+		asm:          arm64.ABFI,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "FNMSUBD",
-		argLen:      3,
-		commutative: true,
-		asm:         riscv.AFNMSUBD,
+		name:         "BFXIL",
+		auxType:      auxARM64BitField,
+		argLen:       2,
+		resultInArg0: true,
+		asm:          arm64.ABFXIL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FSQRTD",
-		argLen: 1,
-		asm:    riscv.AFSQRTD,
+		name:    "SBFIZ",
+		auxType: auxARM64BitField,
+		argLen:  1,
+		asm:     arm64.ASBFIZ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FNEGD",
-		argLen: 1,
-		asm:    riscv.AFNEGD,
+		name:    "SBFX",
+		auxType: auxARM64BitField,
+		argLen:  1,
+		asm:     arm64.ASBFX,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FABSD",
-		argLen: 1,
-		asm:    riscv.AFABSD,
+		name:    "UBFIZ",
+		auxType: auxARM64BitField,
+		argLen:  1,
+		asm:     arm64.AUBFIZ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FSGNJD",
-		argLen: 2,
-		asm:    riscv.AFSGNJD,
+		name:    "UBFX",
+		auxType: auxARM64BitField,
+		argLen:  1,
+		asm:     arm64.AUBFX,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FMVDX",
-		argLen: 1,
-		asm:    riscv.AFMVDX,
+		name:              "MOVDconst",
+		auxType:           auxInt64,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               arm64.AMOVD,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FCVTDW",
-		argLen: 1,
-		asm:    riscv.AFCVTDW,
+		name:              "FMOVSconst",
+		auxType:           auxFloat64,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               arm64.AFMOVS,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-			},
 			outputs: []outputInfo{
 				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "FCVTDL",
-		argLen: 1,
-		asm:    riscv.AFCVTDL,
+		name:              "FMOVDconst",
+		auxType:           auxFloat64,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               arm64.AFMOVD,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-			},
 			outputs: []outputInfo{
 				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "FCVTWD",
-		argLen: 1,
-		asm:    riscv.AFCVTWD,
+		name:              "MOVDaddr",
+		auxType:           auxSymOff,
+		argLen:            1,
+		rematerializeable: true,
+		symEffect:         SymAddr,
+		asm:               arm64.AMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 9223372037928517632}, // SP SB
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FCVTLD",
-		argLen: 1,
-		asm:    riscv.AFCVTLD,
+		name:           "MOVBload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm64.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FCVTDS",
-		argLen: 1,
-		asm:    riscv.AFCVTDS,
+		name:           "MOVBUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm64.AMOVBU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FCVTSD",
-		argLen: 1,
-		asm:    riscv.AFCVTSD,
+		name:           "MOVHload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm64.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "FMOVDload",
+		name:           "MOVHUload",
 		auxType:        auxSymOff,
 		argLen:         2,
 		faultOnNilArg0: true,
 		symEffect:      SymRead,
-		asm:            riscv.AMOVD,
+		asm:            arm64.AMOVHU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "FMOVDstore",
+		name:           "MOVWload",
 		auxType:        auxSymOff,
-		argLen:         3,
+		argLen:         2,
 		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            riscv.AMOVD,
+		symEffect:      SymRead,
+		asm:            arm64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "FEQD",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AFEQD,
+		name:           "MOVWUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm64.AMOVWU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:        "FNED",
-		argLen:      2,
-		commutative: true,
-		asm:         riscv.AFNED,
+		name:           "MOVDload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm64.AMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FLTD",
-		argLen: 2,
-		asm:    riscv.AFLTD,
+		name:           "FMOVSload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm64.AFMOVS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "FLED",
-		argLen: 2,
-		asm:    riscv.AFLED,
+		name:           "FMOVDload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm64.AFMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:            "LoweredFMIND",
-		argLen:          2,
-		commutative:     true,
-		resultNotInArgs: true,
-		asm:             riscv.AFMIND,
+		name:           "LDP",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm64.ALDP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:            "LoweredFMAXD",
-		argLen:          2,
-		commutative:     true,
-		resultNotInArgs: true,
-		asm:             riscv.AFMAXD,
+		name:           "LDPW",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm64.ALDPW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
-
 	{
-		name:         "FADDS",
-		argLen:       2,
-		commutative:  true,
-		resultInArg0: true,
-		asm:          s390x.AFADDS,
+		name:           "LDPSW",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm64.ALDPSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:         "FADD",
-		argLen:       2,
-		commutative:  true,
-		resultInArg0: true,
-		asm:          s390x.AFADD,
+		name:           "FLDPD",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm64.AFLDPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "FSUBS",
-		argLen:       2,
-		resultInArg0: true,
-		asm:          s390x.AFSUBS,
+		name:           "FLDPS",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            arm64.AFLDPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "FSUB",
-		argLen:       2,
-		resultInArg0: true,
-		asm:          s390x.AFSUB,
+		name:   "MOVDloadidx",
+		argLen: 3,
+		asm:    arm64.AMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "FMULS",
-		argLen:       2,
-		commutative:  true,
-		resultInArg0: true,
-		asm:          s390x.AFMULS,
+		name:   "MOVWloadidx",
+		argLen: 3,
+		asm:    arm64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "FMUL",
-		argLen:       2,
-		commutative:  true,
-		resultInArg0: true,
-		asm:          s390x.AFMUL,
+		name:   "MOVWUloadidx",
+		argLen: 3,
+		asm:    arm64.AMOVWU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "FDIVS",
-		argLen:       2,
-		resultInArg0: true,
-		asm:          s390x.AFDIVS,
+		name:   "MOVHloadidx",
+		argLen: 3,
+		asm:    arm64.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "FDIV",
-		argLen:       2,
-		resultInArg0: true,
-		asm:          s390x.AFDIV,
+		name:   "MOVHUloadidx",
+		argLen: 3,
+		asm:    arm64.AMOVHU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "FNEGS",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.AFNEGS,
+		name:   "MOVBloadidx",
+		argLen: 3,
+		asm:    arm64.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "FNEG",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.AFNEG,
+		name:   "MOVBUloadidx",
+		argLen: 3,
+		asm:    arm64.AMOVBU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "FMADDS",
-		argLen:       3,
-		resultInArg0: true,
-		asm:          s390x.AFMADDS,
+		name:   "FMOVSloadidx",
+		argLen: 3,
+		asm:    arm64.AFMOVS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "FMADD",
-		argLen:       3,
-		resultInArg0: true,
-		asm:          s390x.AFMADD,
+		name:   "FMOVDloadidx",
+		argLen: 3,
+		asm:    arm64.AFMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "FMSUBS",
-		argLen:       3,
-		resultInArg0: true,
-		asm:          s390x.AFMSUBS,
+		name:   "MOVHloadidx2",
+		argLen: 3,
+		asm:    arm64.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "FMSUB",
-		argLen:       3,
-		resultInArg0: true,
-		asm:          s390x.AFMSUB,
+		name:   "MOVHUloadidx2",
+		argLen: 3,
+		asm:    arm64.AMOVHU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "LPDFR",
-		argLen: 1,
-		asm:    s390x.ALPDFR,
+		name:   "MOVWloadidx4",
+		argLen: 3,
+		asm:    arm64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "LNDFR",
-		argLen: 1,
-		asm:    s390x.ALNDFR,
+		name:   "MOVWUloadidx4",
+		argLen: 3,
+		asm:    arm64.AMOVWU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "CPSDR",
-		argLen: 2,
-		asm:    s390x.ACPSDR,
+		name:   "MOVDloadidx8",
+		argLen: 3,
+		asm:    arm64.AMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "FIDBR",
-		auxType: auxInt8,
-		argLen:  1,
-		asm:     s390x.AFIDBR,
+		name:   "FMOVSloadidx4",
+		argLen: 3,
+		asm:    arm64.AFMOVS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "FMOVSload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AFMOVS,
+		name:   "FMOVDloadidx8",
+		argLen: 3,
+		asm:    arm64.AFMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "FMOVDload",
+		name:           "MOVBstore",
 		auxType:        auxSymOff,
-		argLen:         2,
+		argLen:         3,
 		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AFMOVD,
+		symEffect:      SymWrite,
+		asm:            arm64.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-			},
-			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:              "FMOVSconst",
-		auxType:           auxFloat32,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               s390x.AFMOVS,
+		name:           "MOVHstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            arm64.AMOVH,
 		reg: regInfo{
-			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			inputs: []inputInfo{
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:              "FMOVDconst",
-		auxType:           auxFloat64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               s390x.AFMOVD,
+		name:           "MOVWstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            arm64.AMOVW,
 		reg: regInfo{
-			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			inputs: []inputInfo{
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:      "FMOVSloadidx",
-		auxType:   auxSymOff,
-		argLen:    3,
-		symEffect: SymRead,
-		asm:       s390x.AFMOVS,
+		name:           "MOVDstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            arm64.AMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
-			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:      "FMOVDloadidx",
-		auxType:   auxSymOff,
-		argLen:    3,
-		symEffect: SymRead,
-		asm:       s390x.AFMOVD,
+		name:           "FMOVSstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            arm64.AFMOVS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
-			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "FMOVSstore",
+		name:           "FMOVDstore",
 		auxType:        auxSymOff,
 		argLen:         3,
 		faultOnNilArg0: true,
 		symEffect:      SymWrite,
-		asm:            s390x.AFMOVS,
+		asm:            arm64.AFMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "FMOVDstore",
+		name:           "STP",
 		auxType:        auxSymOff,
-		argLen:         3,
+		argLen:         4,
 		faultOnNilArg0: true,
 		symEffect:      SymWrite,
-		asm:            s390x.AFMOVD,
+		asm:            arm64.ASTP,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:      "FMOVSstoreidx",
-		auxType:   auxSymOff,
-		argLen:    4,
-		symEffect: SymWrite,
-		asm:       s390x.AFMOVS,
+		name:           "STPW",
+		auxType:        auxSymOff,
+		argLen:         4,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            arm64.ASTPW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:      "FMOVDstoreidx",
-		auxType:   auxSymOff,
-		argLen:    4,
-		symEffect: SymWrite,
-		asm:       s390x.AFMOVD,
+		name:           "FSTPD",
+		auxType:        auxSymOff,
+		argLen:         4,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            arm64.AFSTPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "ADD",
-		argLen:       2,
-		commutative:  true,
-		clobberFlags: true,
-		asm:          s390x.AADD,
+		name:           "FSTPS",
+		auxType:        auxSymOff,
+		argLen:         4,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            arm64.AFSTPS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "ADDW",
-		argLen:       2,
-		commutative:  true,
-		clobberFlags: true,
-		asm:          s390x.AADDW,
+		name:   "MOVBstoreidx",
+		argLen: 4,
+		asm:    arm64.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:         "ADDconst",
-		auxType:      auxInt32,
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.AADD,
+		name:   "MOVHstoreidx",
+		argLen: 4,
+		asm:    arm64.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:         "ADDWconst",
-		auxType:      auxInt32,
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.AADDW,
+		name:   "MOVWstoreidx",
+		argLen: 4,
+		asm:    arm64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:           "ADDload",
-		auxType:        auxSymOff,
-		argLen:         3,
-		resultInArg0:   true,
-		clobberFlags:   true,
-		faultOnNilArg1: true,
-		symEffect:      SymRead,
-		asm:            s390x.AADD,
+		name:   "MOVDstoreidx",
+		argLen: 4,
+		asm:    arm64.AMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:           "ADDWload",
-		auxType:        auxSymOff,
-		argLen:         3,
-		resultInArg0:   true,
-		clobberFlags:   true,
-		faultOnNilArg1: true,
-		symEffect:      SymRead,
-		asm:            s390x.AADDW,
+		name:   "FMOVSstoreidx",
+		argLen: 4,
+		asm:    arm64.AFMOVS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "SUB",
-		argLen:       2,
-		clobberFlags: true,
-		asm:          s390x.ASUB,
+		name:   "FMOVDstoreidx",
+		argLen: 4,
+		asm:    arm64.AFMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "SUBW",
-		argLen:       2,
-		clobberFlags: true,
-		asm:          s390x.ASUBW,
+		name:   "MOVHstoreidx2",
+		argLen: 4,
+		asm:    arm64.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:         "SUBconst",
-		auxType:      auxInt32,
-		argLen:       1,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.ASUB,
+		name:   "MOVWstoreidx4",
+		argLen: 4,
+		asm:    arm64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:         "SUBWconst",
-		auxType:      auxInt32,
-		argLen:       1,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.ASUBW,
+		name:   "MOVDstoreidx8",
+		argLen: 4,
+		asm:    arm64.AMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:           "SUBload",
-		auxType:        auxSymOff,
-		argLen:         3,
-		resultInArg0:   true,
-		clobberFlags:   true,
-		faultOnNilArg1: true,
-		symEffect:      SymRead,
-		asm:            s390x.ASUB,
+		name:   "FMOVSstoreidx4",
+		argLen: 4,
+		asm:    arm64.AFMOVS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "SUBWload",
-		auxType:        auxSymOff,
-		argLen:         3,
-		resultInArg0:   true,
-		clobberFlags:   true,
-		faultOnNilArg1: true,
-		symEffect:      SymRead,
-		asm:            s390x.ASUBW,
+		name:   "FMOVDstoreidx8",
+		argLen: 4,
+		asm:    arm64.AFMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "MULLD",
-		argLen:       2,
-		commutative:  true,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AMULLD,
+		name:   "FMOVDgpfp",
+		argLen: 1,
+		asm:    arm64.AFMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "MULLW",
-		argLen:       2,
-		commutative:  true,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AMULLW,
+		name:   "FMOVDfpgp",
+		argLen: 1,
+		asm:    arm64.AFMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "MULLDconst",
-		auxType:      auxInt32,
-		argLen:       1,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AMULLD,
+		name:   "FMOVSgpfp",
+		argLen: 1,
+		asm:    arm64.AFMOVS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "MULLWconst",
-		auxType:      auxInt32,
-		argLen:       1,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AMULLW,
+		name:   "FMOVSfpgp",
+		argLen: 1,
+		asm:    arm64.AFMOVS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "MULLDload",
-		auxType:        auxSymOff,
-		argLen:         3,
-		resultInArg0:   true,
-		clobberFlags:   true,
-		faultOnNilArg1: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMULLD,
+		name:   "MOVBreg",
+		argLen: 1,
+		asm:    arm64.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "MULLWload",
-		auxType:        auxSymOff,
-		argLen:         3,
-		resultInArg0:   true,
-		clobberFlags:   true,
-		faultOnNilArg1: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMULLW,
+		name:   "MOVBUreg",
+		argLen: 1,
+		asm:    arm64.AMOVBU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "MULHD",
-		argLen:       2,
-		commutative:  true,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AMULHD,
+		name:   "MOVHreg",
+		argLen: 1,
+		asm:    arm64.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
-			clobbers: 2048, // R11
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "MULHDU",
-		argLen:       2,
-		commutative:  true,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AMULHDU,
+		name:   "MOVHUreg",
+		argLen: 1,
+		asm:    arm64.AMOVHU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
-			clobbers: 2048, // R11
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "DIVD",
-		argLen:       2,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.ADIVD,
+		name:   "MOVWreg",
+		argLen: 1,
+		asm:    arm64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
-			clobbers: 2048, // R11
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "DIVW",
-		argLen:       2,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.ADIVW,
+		name:   "MOVWUreg",
+		argLen: 1,
+		asm:    arm64.AMOVWU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
-			clobbers: 2048, // R11
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "DIVDU",
-		argLen:       2,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.ADIVDU,
+		name:   "MOVDreg",
+		argLen: 1,
+		asm:    arm64.AMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
-			clobbers: 2048, // R11
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "DIVWU",
-		argLen:       2,
+		name:         "MOVDnop",
+		argLen:       1,
 		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.ADIVWU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
-			clobbers: 2048, // R11
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "MODD",
-		argLen:       2,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AMODD,
+		name:   "SCVTFWS",
+		argLen: 1,
+		asm:    arm64.ASCVTFWS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
-			clobbers: 2048, // R11
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "MODW",
-		argLen:       2,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AMODW,
+		name:   "SCVTFWD",
+		argLen: 1,
+		asm:    arm64.ASCVTFWD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
-			clobbers: 2048, // R11
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "MODDU",
-		argLen:       2,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AMODDU,
+		name:   "UCVTFWS",
+		argLen: 1,
+		asm:    arm64.AUCVTFWS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
-			clobbers: 2048, // R11
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "MODWU",
-		argLen:       2,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AMODWU,
+		name:   "UCVTFWD",
+		argLen: 1,
+		asm:    arm64.AUCVTFWD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
-			clobbers: 2048, // R11
 			outputs: []outputInfo{
-				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "AND",
-		argLen:       2,
-		commutative:  true,
-		clobberFlags: true,
-		asm:          s390x.AAND,
+		name:   "SCVTFS",
+		argLen: 1,
+		asm:    arm64.ASCVTFS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "ANDW",
-		argLen:       2,
-		commutative:  true,
-		clobberFlags: true,
-		asm:          s390x.AANDW,
+		name:   "SCVTFD",
+		argLen: 1,
+		asm:    arm64.ASCVTFD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "ANDconst",
-		auxType:      auxInt64,
-		argLen:       1,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AAND,
+		name:   "UCVTFS",
+		argLen: 1,
+		asm:    arm64.AUCVTFS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "ANDWconst",
-		auxType:      auxInt32,
-		argLen:       1,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AANDW,
+		name:   "UCVTFD",
+		argLen: 1,
+		asm:    arm64.AUCVTFD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "ANDload",
-		auxType:        auxSymOff,
-		argLen:         3,
-		resultInArg0:   true,
-		clobberFlags:   true,
-		faultOnNilArg1: true,
-		symEffect:      SymRead,
-		asm:            s390x.AAND,
+		name:   "FCVTZSSW",
+		argLen: 1,
+		asm:    arm64.AFCVTZSSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "ANDWload",
-		auxType:        auxSymOff,
-		argLen:         3,
-		resultInArg0:   true,
-		clobberFlags:   true,
-		faultOnNilArg1: true,
-		symEffect:      SymRead,
-		asm:            s390x.AANDW,
+		name:   "FCVTZSDW",
+		argLen: 1,
+		asm:    arm64.AFCVTZSDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "OR",
-		argLen:       2,
-		commutative:  true,
-		clobberFlags: true,
-		asm:          s390x.AOR,
+		name:   "FCVTZUSW",
+		argLen: 1,
+		asm:    arm64.AFCVTZUSW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "ORW",
-		argLen:       2,
-		commutative:  true,
-		clobberFlags: true,
-		asm:          s390x.AORW,
+		name:   "FCVTZUDW",
+		argLen: 1,
+		asm:    arm64.AFCVTZUDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "ORconst",
-		auxType:      auxInt64,
-		argLen:       1,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AOR,
+		name:   "FCVTZSS",
+		argLen: 1,
+		asm:    arm64.AFCVTZSS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "ORWconst",
-		auxType:      auxInt32,
-		argLen:       1,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AORW,
+		name:   "FCVTZSD",
+		argLen: 1,
+		asm:    arm64.AFCVTZSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "ORload",
-		auxType:        auxSymOff,
-		argLen:         3,
-		resultInArg0:   true,
-		clobberFlags:   true,
-		faultOnNilArg1: true,
-		symEffect:      SymRead,
-		asm:            s390x.AOR,
+		name:   "FCVTZUS",
+		argLen: 1,
+		asm:    arm64.AFCVTZUS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:           "ORWload",
-		auxType:        auxSymOff,
-		argLen:         3,
-		resultInArg0:   true,
-		clobberFlags:   true,
-		faultOnNilArg1: true,
-		symEffect:      SymRead,
-		asm:            s390x.AORW,
+		name:   "FCVTZUD",
+		argLen: 1,
+		asm:    arm64.AFCVTZUD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "XOR",
-		argLen:       2,
-		commutative:  true,
-		clobberFlags: true,
-		asm:          s390x.AXOR,
+		name:   "FCVTSD",
+		argLen: 1,
+		asm:    arm64.AFCVTSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "XORW",
-		argLen:       2,
-		commutative:  true,
-		clobberFlags: true,
-		asm:          s390x.AXORW,
+		name:   "FCVTDS",
+		argLen: 1,
+		asm:    arm64.AFCVTDS,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "XORconst",
-		auxType:      auxInt64,
-		argLen:       1,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AXOR,
+		name:   "FRINTAD",
+		argLen: 1,
+		asm:    arm64.AFRINTAD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "XORWconst",
-		auxType:      auxInt32,
-		argLen:       1,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.AXORW,
+		name:   "FRINTMD",
+		argLen: 1,
+		asm:    arm64.AFRINTMD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "XORload",
-		auxType:        auxSymOff,
-		argLen:         3,
-		resultInArg0:   true,
-		clobberFlags:   true,
-		faultOnNilArg1: true,
-		symEffect:      SymRead,
-		asm:            s390x.AXOR,
+		name:   "FRINTND",
+		argLen: 1,
+		asm:    arm64.AFRINTND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "XORWload",
-		auxType:        auxSymOff,
-		argLen:         3,
-		resultInArg0:   true,
-		clobberFlags:   true,
-		faultOnNilArg1: true,
-		symEffect:      SymRead,
-		asm:            s390x.AXORW,
+		name:   "FRINTPD",
+		argLen: 1,
+		asm:    arm64.AFRINTPD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:        "ADDC",
-		argLen:      2,
-		commutative: true,
-		asm:         s390x.AADDC,
+		name:   "FRINTZD",
+		argLen: 1,
+		asm:    arm64.AFRINTZD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "ADDCconst",
-		auxType: auxInt16,
-		argLen:  1,
-		asm:     s390x.AADDC,
+		name:    "CSEL",
+		auxType: auxCCop,
+		argLen:  3,
+		asm:     arm64.ACSEL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "ADDE",
-		argLen:       3,
-		commutative:  true,
-		resultInArg0: true,
-		asm:          s390x.AADDE,
+		name:    "CSEL0",
+		auxType: auxCCop,
+		argLen:  2,
+		asm:     arm64.ACSEL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SUBC",
-		argLen: 2,
-		asm:    s390x.ASUBC,
+		name:    "CSINC",
+		auxType: auxCCop,
+		argLen:  3,
+		asm:     arm64.ACSINC,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "SUBE",
-		argLen:       3,
-		resultInArg0: true,
-		asm:          s390x.ASUBE,
+		name:    "CSINV",
+		auxType: auxCCop,
+		argLen:  3,
+		asm:     arm64.ACSINV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "CMP",
-		argLen: 2,
-		asm:    s390x.ACMP,
+		name:    "CSNEG",
+		auxType: auxCCop,
+		argLen:  3,
+		asm:     arm64.ACSNEG,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+			},
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "CMPW",
-		argLen: 2,
-		asm:    s390x.ACMPW,
+		name:    "CSETM",
+		auxType: auxCCop,
+		argLen:  1,
+		asm:     arm64.ACSETM,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "CMPU",
-		argLen: 2,
-		asm:    s390x.ACMPU,
+		name:         "CALLstatic",
+		auxType:      auxCallOff,
+		argLen:       -1,
+		clobberFlags: true,
+		call:         true,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
+			clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:   "CMPWU",
-		argLen: 2,
-		asm:    s390x.ACMPWU,
+		name:         "CALLtail",
+		auxType:      auxCallOff,
+		argLen:       -1,
+		clobberFlags: true,
+		call:         true,
+		tailCall:     true,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
+			clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:    "CMPconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     s390x.ACMP,
+		name:         "CALLclosure",
+		auxType:      auxCallOff,
+		argLen:       -1,
+		clobberFlags: true,
+		call:         true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 33554432},   // R26
+				{0, 1409286143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP
 			},
+			clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:    "CMPWconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     s390x.ACMPW,
+		name:         "CALLinter",
+		auxType:      auxCallOff,
+		argLen:       -1,
+		clobberFlags: true,
+		call:         true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
+			clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:    "CMPUconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     s390x.ACMPU,
+		name:           "LoweredNilCheck",
+		argLen:         2,
+		nilCheck:       true,
+		faultOnNilArg0: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 			},
 		},
 	},
 	{
-		name:    "CMPWUconst",
-		auxType: auxInt32,
-		argLen:  1,
-		asm:     s390x.ACMPWU,
+		name:   "Equal",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FCMPS",
-		argLen: 2,
-		asm:    s390x.ACEBR,
+		name:   "NotEqual",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FCMP",
-		argLen: 2,
-		asm:    s390x.AFCMPU,
+		name:   "LessThan",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "LTDBR",
+		name:   "LessEqual",
 		argLen: 1,
-		asm:    s390x.ALTDBR,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "LTEBR",
+		name:   "GreaterThan",
 		argLen: 1,
-		asm:    s390x.ALTEBR,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			outputs: []outputInfo{
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SLD",
-		argLen: 2,
-		asm:    s390x.ASLD,
+		name:   "GreaterEqual",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SLW",
-		argLen: 2,
-		asm:    s390x.ASLW,
+		name:   "LessThanU",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "SLDconst",
-		auxType: auxUInt8,
-		argLen:  1,
-		asm:     s390x.ASLD,
+		name:   "LessEqualU",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "SLWconst",
-		auxType: auxUInt8,
-		argLen:  1,
-		asm:     s390x.ASLW,
+		name:   "GreaterThanU",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SRD",
-		argLen: 2,
-		asm:    s390x.ASRD,
+		name:   "GreaterEqualU",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "SRW",
-		argLen: 2,
-		asm:    s390x.ASRW,
+		name:   "LessThanF",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "SRDconst",
-		auxType: auxUInt8,
-		argLen:  1,
-		asm:     s390x.ASRD,
+		name:   "LessEqualF",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "SRWconst",
-		auxType: auxUInt8,
-		argLen:  1,
-		asm:     s390x.ASRW,
+		name:   "GreaterThanF",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "SRAD",
-		argLen:       2,
-		clobberFlags: true,
-		asm:          s390x.ASRAD,
+		name:   "GreaterEqualF",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "SRAW",
-		argLen:       2,
-		clobberFlags: true,
-		asm:          s390x.ASRAW,
+		name:   "NotLessThanF",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "SRADconst",
-		auxType:      auxUInt8,
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ASRAD,
+		name:   "NotLessEqualF",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "SRAWconst",
-		auxType:      auxUInt8,
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ASRAW,
+		name:   "NotGreaterThanF",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "RLLG",
-		argLen: 2,
-		asm:    s390x.ARLLG,
+		name:   "NotGreaterEqualF",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "RLL",
-		argLen: 2,
-		asm:    s390x.ARLL,
+		name:   "LessThanNoov",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:    "RLLconst",
-		auxType: auxUInt8,
-		argLen:  1,
-		asm:     s390x.ARLL,
+		name:   "GreaterEqualNoov",
+		argLen: 1,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "RXSBG",
-		auxType:      auxS390XRotateParams,
-		argLen:       2,
-		resultInArg0: true,
-		clobberFlags: true,
-		asm:          s390x.ARXSBG,
+		name:        "DUFFZERO",
+		auxType:     auxInt64,
+		argLen:      2,
+		unsafePoint: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 524288}, // R20
 			},
+			clobbers: 269156352, // R16 R17 R20 R30
 		},
 	},
 	{
-		name:         "RISBGZ",
-		auxType:      auxS390XRotateParams,
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ARISBGZ,
+		name:           "LoweredZero",
+		argLen:         3,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 65536},     // R16
+				{1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
+			clobbers: 65536, // R16
 		},
 	},
 	{
-		name:         "NEG",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ANEG,
+		name:        "DUFFCOPY",
+		auxType:     auxInt64,
+		argLen:      3,
+		unsafePoint: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1048576}, // R21
+				{1, 524288},  // R20
 			},
+			clobbers: 303759360, // R16 R17 R20 R21 R26 R30
 		},
 	},
 	{
-		name:         "NEGW",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ANEGW,
+		name:           "LoweredMove",
+		argLen:         4,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 131072},    // R17
+				{1, 65536},     // R16
+				{2, 318767103}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30
 			},
+			clobbers: 16973824, // R16 R17 R25
+		},
+	},
+	{
+		name:      "LoweredGetClosurePtr",
+		argLen:    0,
+		zeroWidth: true,
+		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 33554432}, // R26
 			},
 		},
 	},
 	{
-		name:         "NOT",
-		argLen:       1,
-		resultInArg0: true,
-		clobberFlags: true,
+		name:              "LoweredGetCallerSP",
+		argLen:            1,
+		rematerializeable: true,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "NOTW",
-		argLen:       1,
-		resultInArg0: true,
-		clobberFlags: true,
+		name:              "LoweredGetCallerPC",
+		argLen:            0,
+		rematerializeable: true,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FSQRT",
+		name:    "FlagConstant",
+		auxType: auxFlagConstant,
+		argLen:  0,
+		reg:     regInfo{},
+	},
+	{
+		name:   "InvertFlags",
 		argLen: 1,
-		asm:    s390x.AFSQRT,
+		reg:    regInfo{},
+	},
+	{
+		name:           "LDAR",
+		argLen:         2,
+		faultOnNilArg0: true,
+		asm:            arm64.ALDAR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "FSQRTS",
-		argLen: 1,
-		asm:    s390x.AFSQRTS,
+		name:           "LDARB",
+		argLen:         2,
+		faultOnNilArg0: true,
+		asm:            arm64.ALDARB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "LOCGR",
-		auxType:      auxS390XCCMask,
-		argLen:       3,
-		resultInArg0: true,
-		asm:          s390x.ALOCGR,
+		name:           "LDARW",
+		argLen:         2,
+		faultOnNilArg0: true,
+		asm:            arm64.ALDARW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "MOVBreg",
-		argLen: 1,
-		asm:    s390x.AMOVB,
+		name:           "STLRB",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		asm:            arm64.ASTLRB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:   "MOVBZreg",
-		argLen: 1,
-		asm:    s390x.AMOVBZ,
+		name:           "STLR",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		asm:            arm64.ASTLR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+		},
+	},
+	{
+		name:           "STLRW",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		asm:            arm64.ASTLRW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:   "MOVHreg",
-		argLen: 1,
-		asm:    s390x.AMOVH,
+		name:            "LoweredAtomicExchange64",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "MOVHZreg",
-		argLen: 1,
-		asm:    s390x.AMOVHZ,
+		name:            "LoweredAtomicExchange32",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "MOVWreg",
-		argLen: 1,
-		asm:    s390x.AMOVW,
+		name:            "LoweredAtomicExchange8",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "MOVWZreg",
-		argLen: 1,
-		asm:    s390x.AMOVWZ,
+		name:            "LoweredAtomicExchange64Variant",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:              "MOVDconst",
-		auxType:           auxInt64,
-		argLen:            0,
-		rematerializeable: true,
-		asm:               s390x.AMOVD,
+		name:            "LoweredAtomicExchange32Variant",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "LDGR",
-		argLen: 1,
-		asm:    s390x.ALDGR,
+		name:            "LoweredAtomicExchange8Variant",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "LGDR",
-		argLen: 1,
-		asm:    s390x.ALGDR,
+		name:            "LoweredAtomicAdd64",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CFDBRA",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACFDBRA,
+		name:            "LoweredAtomicAdd32",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CGDBRA",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACGDBRA,
+		name:            "LoweredAtomicAdd64Variant",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CFEBRA",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACFEBRA,
+		name:            "LoweredAtomicAdd32Variant",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CGEBRA",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACGEBRA,
+		name:            "LoweredAtomicCas64",
+		argLen:          4,
+		resultNotInArgs: true,
+		clobberFlags:    true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CEFBRA",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACEFBRA,
+		name:            "LoweredAtomicCas32",
+		argLen:          4,
+		resultNotInArgs: true,
+		clobberFlags:    true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CDFBRA",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACDFBRA,
+		name:            "LoweredAtomicCas64Variant",
+		argLen:          4,
+		resultNotInArgs: true,
+		clobberFlags:    true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CEGBRA",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACEGBRA,
+		name:            "LoweredAtomicCas32Variant",
+		argLen:          4,
+		resultNotInArgs: true,
+		clobberFlags:    true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CDGBRA",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACDGBRA,
+		name:            "LoweredAtomicAnd8",
+		argLen:          3,
+		resultNotInArgs: true,
+		needIntTemp:     true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		asm:             arm64.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CLFEBR",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACLFEBR,
+		name:            "LoweredAtomicOr8",
+		argLen:          3,
+		resultNotInArgs: true,
+		needIntTemp:     true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		asm:             arm64.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CLFDBR",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACLFDBR,
+		name:            "LoweredAtomicAnd64",
+		argLen:          3,
+		resultNotInArgs: true,
+		needIntTemp:     true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		asm:             arm64.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CLGEBR",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACLGEBR,
+		name:            "LoweredAtomicOr64",
+		argLen:          3,
+		resultNotInArgs: true,
+		needIntTemp:     true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		asm:             arm64.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CLGDBR",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACLGDBR,
+		name:            "LoweredAtomicAnd32",
+		argLen:          3,
+		resultNotInArgs: true,
+		needIntTemp:     true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		asm:             arm64.AAND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CELFBR",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACELFBR,
+		name:            "LoweredAtomicOr32",
+		argLen:          3,
+		resultNotInArgs: true,
+		needIntTemp:     true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		asm:             arm64.AORR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CDLFBR",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACDLFBR,
+		name:            "LoweredAtomicAnd8Variant",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CELGBR",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACELGBR,
+		name:            "LoweredAtomicOr8Variant",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:         "CDLGBR",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.ACDLGBR,
+		name:            "LoweredAtomicAnd64Variant",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "LEDBR",
-		argLen: 1,
-		asm:    s390x.ALEDBR,
+		name:            "LoweredAtomicOr64Variant",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:   "LDEBR",
-		argLen: 1,
-		asm:    s390x.ALDEBR,
+		name:            "LoweredAtomicAnd32Variant",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:              "MOVDaddr",
-		auxType:           auxSymOff,
-		argLen:            1,
-		rematerializeable: true,
-		symEffect:         SymAddr,
+		name:            "LoweredAtomicOr32Variant",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295000064}, // SP SB
+				{1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 			},
 		},
 	},
 	{
-		name:      "MOVDaddridx",
-		auxType:   auxSymOff,
-		argLen:    2,
-		symEffect: SymAddr,
+		name:         "LoweredWB",
+		auxType:      auxInt64,
+		argLen:       1,
+		clobberFlags: true,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 4295000064}, // SP SB
-				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-			},
+			clobbers: 9223372034975924224, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 16777216}, // R25
 			},
 		},
 	},
 	{
-		name:           "MOVBZload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMOVBZ,
+		name:    "LoweredPanicBoundsA",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4}, // R2
+				{1, 8}, // R3
 			},
 		},
 	},
 	{
-		name:           "MOVBload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMOVB,
+		name:    "LoweredPanicBoundsB",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 2}, // R1
+				{1, 4}, // R2
 			},
 		},
 	},
 	{
-		name:           "MOVHZload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMOVHZ,
+		name:    "LoweredPanicBoundsC",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1}, // R0
+				{1, 2}, // R1
 			},
 		},
 	},
 	{
-		name:           "MOVHload",
-		auxType:        auxSymOff,
+		name:           "PRFM",
+		auxType:        auxInt64,
 		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMOVH,
+		hasSideEffects: true,
+		asm:            arm64.APRFM,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-			},
-			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 			},
 		},
 	},
 	{
-		name:           "MOVWZload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMOVWZ,
+		name:           "DMB",
+		auxType:        auxInt64,
+		argLen:         1,
+		hasSideEffects: true,
+		asm:            arm64.ADMB,
+		reg:            regInfo{},
+	},
+	{
+		name:      "ZERO",
+		argLen:    0,
+		zeroWidth: true,
+		fixedReg:  true,
+		reg:       regInfo{},
+	},
+
+	{
+		name:   "NEGV",
+		argLen: 1,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "MOVWload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMOVW,
+		name:   "NEGF",
+		argLen: 1,
+		asm:    loong64.ANEGF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVDload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMOVD,
+		name:   "NEGD",
+		argLen: 1,
+		asm:    loong64.ANEGD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "MOVWBR",
+		name:   "SQRTD",
 		argLen: 1,
-		asm:    s390x.AMOVWBR,
+		asm:    loong64.ASQRTD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "MOVDBR",
+		name:   "SQRTF",
 		argLen: 1,
-		asm:    s390x.AMOVDBR,
+		asm:    loong64.ASQRTF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVHBRload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMOVHBR,
+		name:   "ABSD",
+		argLen: 1,
+		asm:    loong64.AABSD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVWBRload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMOVWBR,
+		name:   "CLZW",
+		argLen: 1,
+		asm:    loong64.ACLZW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "MOVDBRload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMOVDBR,
+		name:   "CLZV",
+		argLen: 1,
+		asm:    loong64.ACLZV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "MOVBstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVB,
+		name:   "CTZW",
+		argLen: 1,
+		asm:    loong64.ACTZW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "MOVHstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVH,
+		name:   "CTZV",
+		argLen: 1,
+		asm:    loong64.ACTZV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "MOVWstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVW,
+		name:   "REVB2H",
+		argLen: 1,
+		asm:    loong64.AREVB2H,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "MOVDstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVD,
+		name:   "REVB2W",
+		argLen: 1,
+		asm:    loong64.AREVB2W,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "MOVHBRstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVHBR,
+		name:   "REVBV",
+		argLen: 1,
+		asm:    loong64.AREVBV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "MOVWBRstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVWBR,
+		name:   "BITREV4B",
+		argLen: 1,
+		asm:    loong64.ABITREV4B,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "MOVDBRstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVDBR,
+		name:   "BITREVW",
+		argLen: 1,
+		asm:    loong64.ABITREVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "MVC",
-		auxType:        auxSymValAndOff,
-		argLen:         3,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
-		symEffect:      SymNone,
-		asm:            s390x.AMVC,
+		name:   "BITREVV",
+		argLen: 1,
+		asm:    loong64.ABITREVV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:        "MOVBZloadidx",
-		auxType:     auxSymOff,
-		argLen:      3,
-		commutative: true,
-		symEffect:   SymRead,
-		asm:         s390x.AMOVBZ,
+		name:   "VPCNT64",
+		argLen: 1,
+		asm:    loong64.AVPCNTV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:        "MOVBloadidx",
-		auxType:     auxSymOff,
-		argLen:      3,
-		commutative: true,
-		symEffect:   SymRead,
-		asm:         s390x.AMOVB,
+		name:   "VPCNT32",
+		argLen: 1,
+		asm:    loong64.AVPCNTW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:        "MOVHZloadidx",
-		auxType:     auxSymOff,
-		argLen:      3,
-		commutative: true,
-		symEffect:   SymRead,
-		asm:         s390x.AMOVHZ,
+		name:   "VPCNT16",
+		argLen: 1,
+		asm:    loong64.AVPCNTH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:        "MOVHloadidx",
-		auxType:     auxSymOff,
-		argLen:      3,
+		name:        "ADDV",
+		argLen:      2,
 		commutative: true,
-		symEffect:   SymRead,
-		asm:         s390x.AMOVH,
+		asm:         loong64.AADDVU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:        "MOVWZloadidx",
-		auxType:     auxSymOff,
-		argLen:      3,
-		commutative: true,
-		symEffect:   SymRead,
-		asm:         s390x.AMOVWZ,
+		name:    "ADDVconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.AADDVU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:        "MOVWloadidx",
-		auxType:     auxSymOff,
-		argLen:      3,
-		commutative: true,
-		symEffect:   SymRead,
-		asm:         s390x.AMOVW,
+		name:   "SUBV",
+		argLen: 2,
+		asm:    loong64.ASUBVU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:        "MOVDloadidx",
-		auxType:     auxSymOff,
-		argLen:      3,
-		commutative: true,
-		symEffect:   SymRead,
-		asm:         s390x.AMOVD,
+		name:    "SUBVconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.ASUBVU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:        "MOVHBRloadidx",
-		auxType:     auxSymOff,
-		argLen:      3,
+		name:        "MULV",
+		argLen:      2,
 		commutative: true,
-		symEffect:   SymRead,
-		asm:         s390x.AMOVHBR,
+		asm:         loong64.AMULV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:        "MOVWBRloadidx",
-		auxType:     auxSymOff,
-		argLen:      3,
+		name:        "MULHV",
+		argLen:      2,
 		commutative: true,
-		symEffect:   SymRead,
-		asm:         s390x.AMOVWBR,
+		asm:         loong64.AMULHV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:        "MOVDBRloadidx",
-		auxType:     auxSymOff,
-		argLen:      3,
+		name:        "MULHVU",
+		argLen:      2,
 		commutative: true,
-		symEffect:   SymRead,
-		asm:         s390x.AMOVDBR,
+		asm:         loong64.AMULHVU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:        "MOVBstoreidx",
-		auxType:     auxSymOff,
-		argLen:      4,
-		commutative: true,
-		symEffect:   SymWrite,
-		asm:         s390x.AMOVB,
+		name:   "DIVV",
+		argLen: 2,
+		asm:    loong64.ADIVV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:        "MOVHstoreidx",
-		auxType:     auxSymOff,
-		argLen:      4,
-		commutative: true,
-		symEffect:   SymWrite,
-		asm:         s390x.AMOVH,
+		name:   "DIVVU",
+		argLen: 2,
+		asm:    loong64.ADIVVU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:        "MOVWstoreidx",
-		auxType:     auxSymOff,
-		argLen:      4,
-		commutative: true,
-		symEffect:   SymWrite,
-		asm:         s390x.AMOVW,
+		name:   "REMV",
+		argLen: 2,
+		asm:    loong64.AREMV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:        "MOVDstoreidx",
-		auxType:     auxSymOff,
-		argLen:      4,
-		commutative: true,
-		symEffect:   SymWrite,
-		asm:         s390x.AMOVD,
+		name:   "REMVU",
+		argLen: 2,
+		asm:    loong64.AREMVU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:        "MOVHBRstoreidx",
-		auxType:     auxSymOff,
-		argLen:      4,
+		name:        "ADDF",
+		argLen:      2,
 		commutative: true,
-		symEffect:   SymWrite,
-		asm:         s390x.AMOVHBR,
+		asm:         loong64.AADDF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:        "MOVWBRstoreidx",
-		auxType:     auxSymOff,
-		argLen:      4,
+		name:        "ADDD",
+		argLen:      2,
 		commutative: true,
-		symEffect:   SymWrite,
-		asm:         s390x.AMOVWBR,
+		asm:         loong64.AADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:        "MOVDBRstoreidx",
-		auxType:     auxSymOff,
-		argLen:      4,
-		commutative: true,
-		symEffect:   SymWrite,
-		asm:         s390x.AMOVDBR,
+		name:   "SUBF",
+		argLen: 2,
+		asm:    loong64.ASUBF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVBstoreconst",
-		auxType:        auxSymValAndOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVB,
+		name:   "SUBD",
+		argLen: 2,
+		asm:    loong64.ASUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVHstoreconst",
-		auxType:        auxSymValAndOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVH,
+		name:        "MULF",
+		argLen:      2,
+		commutative: true,
+		asm:         loong64.AMULF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVWstoreconst",
-		auxType:        auxSymValAndOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVW,
+		name:        "MULD",
+		argLen:      2,
+		commutative: true,
+		asm:         loong64.AMULD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVDstoreconst",
-		auxType:        auxSymValAndOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVD,
+		name:   "DIVF",
+		argLen: 2,
+		asm:    loong64.ADIVF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "CLEAR",
-		auxType:        auxSymValAndOff,
-		argLen:         2,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.ACLEAR,
+		name:   "DIVD",
+		argLen: 2,
+		asm:    loong64.ADIVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:         "CALLstatic",
-		auxType:      auxCallOff,
-		argLen:       1,
-		clobberFlags: true,
-		call:         true,
+		name:        "AND",
+		argLen:      2,
+		commutative: true,
+		asm:         loong64.AAND,
 		reg: regInfo{
-			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			inputs: []inputInfo{
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
 		},
 	},
 	{
-		name:         "CALLtail",
-		auxType:      auxCallOff,
-		argLen:       1,
-		clobberFlags: true,
-		call:         true,
-		tailCall:     true,
+		name:    "ANDconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.AAND,
 		reg: regInfo{
-			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			inputs: []inputInfo{
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
 		},
 	},
 	{
-		name:         "CALLclosure",
-		auxType:      auxCallOff,
-		argLen:       3,
-		clobberFlags: true,
-		call:         true,
-		reg: regInfo{
+		name:        "OR",
+		argLen:      2,
+		commutative: true,
+		asm:         loong64.AOR,
+		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 4096},  // R12
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
-			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 		},
 	},
 	{
-		name:         "CALLinter",
-		auxType:      auxCallOff,
-		argLen:       2,
-		clobberFlags: true,
-		call:         true,
+		name:    "ORconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.AOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
-			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-		},
-	},
-	{
-		name:   "InvertFlags",
-		argLen: 1,
-		reg:    regInfo{},
-	},
-	{
-		name:   "LoweredGetG",
-		argLen: 1,
-		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:      "LoweredGetClosurePtr",
-		argLen:    0,
-		zeroWidth: true,
+		name:        "XOR",
+		argLen:      2,
+		commutative: true,
+		asm:         loong64.AXOR,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
 			outputs: []outputInfo{
-				{0, 4096}, // R12
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerSP",
-		argLen:            1,
-		rematerializeable: true,
+		name:    "XORconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.AXOR,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerPC",
-		argLen:            0,
-		rematerializeable: true,
+		name:        "NOR",
+		argLen:      2,
+		commutative: true,
+		asm:         loong64.ANOR,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "LoweredNilCheck",
-		argLen:         2,
-		clobberFlags:   true,
-		nilCheck:       true,
-		faultOnNilArg0: true,
+		name:    "NORconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.ANOR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:         "LoweredRound32F",
-		argLen:       1,
-		resultInArg0: true,
-		zeroWidth:    true,
+		name:   "ANDN",
+		argLen: 2,
+		asm:    loong64.AANDN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:         "LoweredRound64F",
-		argLen:       1,
-		resultInArg0: true,
-		zeroWidth:    true,
+		name:   "ORN",
+		argLen: 2,
+		asm:    loong64.AORN,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:         "LoweredWB",
-		auxType:      auxInt64,
-		argLen:       1,
-		clobberFlags: true,
+		name:        "FMADDF",
+		argLen:      3,
+		commutative: true,
+		asm:         loong64.AFMADDF,
 		reg: regInfo{
-			clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			inputs: []inputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
 			outputs: []outputInfo{
-				{0, 512}, // R9
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsA",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:        "FMADDD",
+		argLen:      3,
+		commutative: true,
+		asm:         loong64.AFMADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4}, // R2
-				{1, 8}, // R3
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsB",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:        "FMSUBF",
+		argLen:      3,
+		commutative: true,
+		asm:         loong64.AFMSUBF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2}, // R1
-				{1, 4}, // R2
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "LoweredPanicBoundsC",
-		auxType: auxInt64,
-		argLen:  3,
-		call:    true,
+		name:        "FMSUBD",
+		argLen:      3,
+		commutative: true,
+		asm:         loong64.AFMSUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1}, // R0
-				{1, 2}, // R1
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "FlagEQ",
-		argLen: 0,
-		reg:    regInfo{},
-	},
-	{
-		name:   "FlagLT",
-		argLen: 0,
-		reg:    regInfo{},
-	},
-	{
-		name:   "FlagGT",
-		argLen: 0,
-		reg:    regInfo{},
-	},
-	{
-		name:   "FlagOV",
-		argLen: 0,
-		reg:    regInfo{},
-	},
-	{
-		name:   "SYNC",
-		argLen: 1,
-		asm:    s390x.ASYNC,
-		reg:    regInfo{},
-	},
-	{
-		name:           "MOVBZatomicload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMOVBZ,
+		name:        "FNMADDF",
+		argLen:      3,
+		commutative: true,
+		asm:         loong64.AFNMADDF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVWZatomicload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMOVWZ,
+		name:        "FNMADDD",
+		argLen:      3,
+		commutative: true,
+		asm:         loong64.AFNMADDD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVDatomicload",
-		auxType:        auxSymOff,
-		argLen:         2,
-		faultOnNilArg0: true,
-		symEffect:      SymRead,
-		asm:            s390x.AMOVD,
+		name:        "FNMSUBF",
+		argLen:      3,
+		commutative: true,
+		asm:         loong64.AFNMSUBF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVBatomicstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVB,
+		name:        "FNMSUBD",
+		argLen:      3,
+		commutative: true,
+		asm:         loong64.AFNMSUBD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVWatomicstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVW,
+		name:            "FMINF",
+		argLen:          2,
+		commutative:     true,
+		resultNotInArgs: true,
+		asm:             loong64.AFMINF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "MOVDatomicstore",
-		auxType:        auxSymOff,
-		argLen:         3,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		symEffect:      SymWrite,
-		asm:            s390x.AMOVD,
+		name:            "FMIND",
+		argLen:          2,
+		commutative:     true,
+		resultNotInArgs: true,
+		asm:             loong64.AFMIND,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "LAA",
-		auxType:        auxSymOff,
-		argLen:         3,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		symEffect:      SymRdWr,
-		asm:            s390x.ALAA,
+		name:            "FMAXF",
+		argLen:          2,
+		commutative:     true,
+		resultNotInArgs: true,
+		asm:             loong64.AFMAXF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "LAAG",
-		auxType:        auxSymOff,
-		argLen:         3,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		symEffect:      SymRdWr,
-		asm:            s390x.ALAAG,
+		name:            "FMAXD",
+		argLen:          2,
+		commutative:     true,
+		resultNotInArgs: true,
+		asm:             loong64.AFMAXD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "AddTupleFirst32",
-		argLen: 2,
-		reg:    regInfo{},
-	},
-	{
-		name:   "AddTupleFirst64",
+		name:   "MASKEQZ",
 		argLen: 2,
-		reg:    regInfo{},
-	},
-	{
-		name:           "LAN",
-		argLen:         3,
-		clobberFlags:   true,
-		hasSideEffects: true,
-		asm:            s390x.ALAN,
+		asm:    loong64.AMASKEQZ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "LANfloor",
-		argLen:         3,
-		clobberFlags:   true,
-		hasSideEffects: true,
-		asm:            s390x.ALAN,
+		name:   "MASKNEZ",
+		argLen: 2,
+		asm:    loong64.AMASKNEZ,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2},     // R1
-				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
-			clobbers: 2, // R1
 		},
 	},
 	{
-		name:           "LAO",
-		argLen:         3,
-		clobberFlags:   true,
-		hasSideEffects: true,
-		asm:            s390x.ALAO,
+		name:   "FCOPYSGD",
+		argLen: 2,
+		asm:    loong64.AFCOPYSGD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "LAOfloor",
-		argLen:         3,
-		clobberFlags:   true,
-		hasSideEffects: true,
-		asm:            s390x.ALAO,
+		name:   "SLL",
+		argLen: 2,
+		asm:    loong64.ASLL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2},     // R1
-				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
-			clobbers: 2, // R1
 		},
 	},
 	{
-		name:           "LoweredAtomicCas32",
-		auxType:        auxSymOff,
-		argLen:         4,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		symEffect:      SymRdWr,
-		asm:            s390x.ACS,
+		name:   "SLLV",
+		argLen: 2,
+		asm:    loong64.ASLLV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1},     // R0
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
-			clobbers: 1, // R0
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicCas64",
-		auxType:        auxSymOff,
-		argLen:         4,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		symEffect:      SymRdWr,
-		asm:            s390x.ACSG,
+		name:    "SLLconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.ASLL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 1},     // R0
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
-			clobbers: 1, // R0
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicExchange32",
-		auxType:        auxSymOff,
-		argLen:         3,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		symEffect:      SymRdWr,
-		asm:            s390x.ACS,
+		name:    "SLLVconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.ASLLV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 1}, // R0
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "LoweredAtomicExchange64",
-		auxType:        auxSymOff,
-		argLen:         3,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		hasSideEffects: true,
-		symEffect:      SymRdWr,
-		asm:            s390x.ACSG,
+		name:   "SRL",
+		argLen: 2,
+		asm:    loong64.ASRL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{1, 0},
-				{0, 1}, // R0
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:         "FLOGR",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.AFLOGR,
+		name:   "SRLV",
+		argLen: 2,
+		asm:    loong64.ASRLV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
-			clobbers: 2, // R1
 			outputs: []outputInfo{
-				{0, 1}, // R0
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:         "POPCNT",
-		argLen:       1,
-		clobberFlags: true,
-		asm:          s390x.APOPCNT,
+		name:    "SRLconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.ASRL,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "MLGR",
-		argLen: 2,
-		asm:    s390x.AMLGR,
+		name:    "SRLVconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.ASRLV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 8},     // R3
-				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 4}, // R2
-				{1, 8}, // R3
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "SumBytes2",
-		argLen: 1,
-		reg:    regInfo{},
+		name:   "SRA",
+		argLen: 2,
+		asm:    loong64.ASRA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
 	},
 	{
-		name:   "SumBytes4",
-		argLen: 1,
-		reg:    regInfo{},
+		name:   "SRAV",
+		argLen: 2,
+		asm:    loong64.ASRAV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
 	},
 	{
-		name:   "SumBytes8",
-		argLen: 1,
-		reg:    regInfo{},
+		name:    "SRAconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.ASRA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
 	},
 	{
-		name:           "STMG2",
-		auxType:        auxSymOff,
-		argLen:         4,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.ASTMG,
+		name:    "SRAVconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.ASRAV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 2},     // R1
-				{2, 4},     // R2
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "STMG3",
-		auxType:        auxSymOff,
-		argLen:         5,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.ASTMG,
+		name:   "ROTR",
+		argLen: 2,
+		asm:    loong64.AROTR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 2},     // R1
-				{2, 4},     // R2
-				{3, 8},     // R3
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "STMG4",
-		auxType:        auxSymOff,
-		argLen:         6,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.ASTMG,
+		name:   "ROTRV",
+		argLen: 2,
+		asm:    loong64.AROTRV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 2},     // R1
-				{2, 4},     // R2
-				{3, 8},     // R3
-				{4, 16},    // R4
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "STM2",
-		auxType:        auxSymOff,
-		argLen:         4,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.ASTMY,
+		name:    "ROTRconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.AROTR,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 2},     // R1
-				{2, 4},     // R2
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "STM3",
-		auxType:        auxSymOff,
-		argLen:         5,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.ASTMY,
+		name:    "ROTRVconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.AROTRV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 2},     // R1
-				{2, 4},     // R2
-				{3, 8},     // R3
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "STM4",
-		auxType:        auxSymOff,
-		argLen:         6,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		symEffect:      SymWrite,
-		asm:            s390x.ASTMY,
+		name:   "SGT",
+		argLen: 2,
+		asm:    loong64.ASGT,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 2},     // R1
-				{2, 4},     // R2
-				{3, 8},     // R3
-				{4, 16},    // R4
-				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:           "LoweredMove",
-		auxType:        auxInt64,
-		argLen:         4,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
-		faultOnNilArg1: true,
+		name:    "SGTconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.ASGT,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2},     // R1
-				{1, 4},     // R2
-				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
-			clobbers: 6, // R1 R2
 		},
 	},
 	{
-		name:           "LoweredZero",
-		auxType:        auxInt64,
-		argLen:         3,
-		clobberFlags:   true,
-		faultOnNilArg0: true,
+		name:   "SGTU",
+		argLen: 2,
+		asm:    loong64.ASGTU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 2},     // R1
-				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
-			clobbers: 2, // R1
 		},
 	},
-
 	{
-		name:    "LoweredStaticCall",
-		auxType: auxCallOff,
+		name:    "SGTUconst",
+		auxType: auxInt64,
 		argLen:  1,
-		call:    true,
+		asm:     loong64.ASGTU,
 		reg: regInfo{
-			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+			inputs: []inputInfo{
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
 		},
 	},
 	{
-		name:     "LoweredTailCall",
-		auxType:  auxCallOff,
-		argLen:   1,
-		call:     true,
-		tailCall: true,
+		name:   "CMPEQF",
+		argLen: 2,
+		asm:    loong64.ACMPEQF,
 		reg: regInfo{
-			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+			inputs: []inputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
 		},
 	},
 	{
-		name:    "LoweredClosureCall",
-		auxType: auxCallOff,
-		argLen:  3,
-		call:    true,
+		name:   "CMPEQD",
+		argLen: 2,
+		asm:    loong64.ACMPEQD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
-				{1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
-			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
 		},
 	},
 	{
-		name:    "LoweredInterCall",
-		auxType: auxCallOff,
-		argLen:  2,
-		call:    true,
+		name:   "CMPGEF",
+		argLen: 2,
+		asm:    loong64.ACMPGEF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
-			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
 		},
 	},
 	{
-		name:              "LoweredAddr",
-		auxType:           auxSymOff,
-		argLen:            1,
-		rematerializeable: true,
-		symEffect:         SymAddr,
+		name:   "CMPGED",
+		argLen: 2,
+		asm:    loong64.ACMPGED,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+		},
+	},
+	{
+		name:   "CMPGTF",
+		argLen: 2,
+		asm:    loong64.ACMPGTF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "LoweredMove",
-		auxType: auxInt64,
-		argLen:  3,
+		name:   "CMPGTD",
+		argLen: 2,
+		asm:    loong64.ACMPGTD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
-				{1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "LoweredZero",
+		name:    "BSTRPICKW",
 		auxType: auxInt64,
-		argLen:  2,
+		argLen:  1,
+		asm:     loong64.ABSTRPICKW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "LoweredGetClosurePtr",
-		argLen: 0,
+		name:    "BSTRPICKV",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     loong64.ABSTRPICKV,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerPC",
+		name:              "MOVVconst",
+		auxType:           auxInt64,
 		argLen:            0,
 		rematerializeable: true,
+		asm:               loong64.AMOVV,
 		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:              "LoweredGetCallerSP",
-		argLen:            1,
+		name:              "MOVFconst",
+		auxType:           auxFloat64,
+		argLen:            0,
 		rematerializeable: true,
+		asm:               loong64.AMOVF,
 		reg: regInfo{
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:           "LoweredNilCheck",
-		argLen:         2,
-		nilCheck:       true,
-		faultOnNilArg0: true,
+		name:              "MOVDconst",
+		auxType:           auxFloat64,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               loong64.AMOVD,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "LoweredWB",
-		auxType: auxInt64,
-		argLen:  1,
+		name:              "MOVVaddr",
+		auxType:           auxSymOff,
+		argLen:            1,
+		rematerializeable: true,
+		symEffect:         SymAddr,
+		asm:               loong64.AMOVV,
 		reg: regInfo{
-			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+			inputs: []inputInfo{
+				{0, 4611686018427387908}, // SP SB
+			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "LoweredConvert",
-		argLen: 2,
+		name:           "MOVBload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            loong64.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "Select",
-		argLen: 3,
-		asm:    wasm.ASelect,
+		name:           "MOVBUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            loong64.AMOVBU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:    "I64Load8U",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     wasm.AI64Load8U,
+		name:           "MOVHload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            loong64.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:    "I64Load8S",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     wasm.AI64Load8S,
+		name:           "MOVHUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            loong64.AMOVHU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:    "I64Load16U",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     wasm.AI64Load16U,
+		name:           "MOVWload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            loong64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:    "I64Load16S",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     wasm.AI64Load16S,
+		name:           "MOVWUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            loong64.AMOVWU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:    "I64Load32U",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     wasm.AI64Load32U,
+		name:           "MOVVload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            loong64.AMOVV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:    "I64Load32S",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     wasm.AI64Load32S,
+		name:           "MOVFload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            loong64.AMOVF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "I64Load",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     wasm.AI64Load,
+		name:           "MOVDload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            loong64.AMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:    "I64Store8",
-		auxType: auxInt64,
-		argLen:  3,
-		asm:     wasm.AI64Store8,
+		name:   "MOVVloadidx",
+		argLen: 3,
+		asm:    loong64.AMOVV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:    "I64Store16",
-		auxType: auxInt64,
-		argLen:  3,
-		asm:     wasm.AI64Store16,
+		name:   "MOVWloadidx",
+		argLen: 3,
+		asm:    loong64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
-		},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
 	},
 	{
-		name:    "I64Store32",
-		auxType: auxInt64,
-		argLen:  3,
-		asm:     wasm.AI64Store32,
+		name:   "MOVWUloadidx",
+		argLen: 3,
+		asm:    loong64.AMOVWU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:    "I64Store",
-		auxType: auxInt64,
-		argLen:  3,
-		asm:     wasm.AI64Store,
+		name:   "MOVHloadidx",
+		argLen: 3,
+		asm:    loong64.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:    "F32Load",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     wasm.AF32Load,
+		name:   "MOVHUloadidx",
+		argLen: 3,
+		asm:    loong64.AMOVHU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:    "F64Load",
-		auxType: auxInt64,
-		argLen:  2,
-		asm:     wasm.AF64Load,
+		name:   "MOVBloadidx",
+		argLen: 3,
+		asm:    loong64.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:    "F32Store",
-		auxType: auxInt64,
-		argLen:  3,
-		asm:     wasm.AF32Store,
+		name:   "MOVBUloadidx",
+		argLen: 3,
+		asm:    loong64.AMOVBU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 4294901760},       // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:    "F64Store",
-		auxType: auxInt64,
-		argLen:  3,
-		asm:     wasm.AF64Store,
+		name:   "MOVFloadidx",
+		argLen: 3,
+		asm:    loong64.AMOVF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{1, 281470681743360},  // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:              "I64Const",
-		auxType:           auxInt64,
-		argLen:            0,
-		rematerializeable: true,
+		name:   "MOVDloadidx",
+		argLen: 3,
+		asm:    loong64.AMOVD,
 		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:              "F32Const",
-		auxType:           auxFloat32,
-		argLen:            0,
-		rematerializeable: true,
+		name:           "MOVBstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            loong64.AMOVB,
 		reg: regInfo{
-			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			inputs: []inputInfo{
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:              "F64Const",
-		auxType:           auxFloat64,
-		argLen:            0,
-		rematerializeable: true,
+		name:           "MOVHstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            loong64.AMOVH,
 		reg: regInfo{
-			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			inputs: []inputInfo{
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "I64Eqz",
-		argLen: 1,
-		asm:    wasm.AI64Eqz,
+		name:           "MOVWstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            loong64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "I64Eq",
-		argLen: 2,
-		asm:    wasm.AI64Eq,
+		name:           "MOVVstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            loong64.AMOVV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "I64Ne",
-		argLen: 2,
-		asm:    wasm.AI64Ne,
+		name:           "MOVFstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            loong64.AMOVF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "I64LtS",
-		argLen: 2,
-		asm:    wasm.AI64LtS,
+		name:           "MOVDstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            loong64.AMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "I64LtU",
-		argLen: 2,
-		asm:    wasm.AI64LtU,
+		name:   "MOVBstoreidx",
+		argLen: 4,
+		asm:    loong64.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "I64GtS",
-		argLen: 2,
-		asm:    wasm.AI64GtS,
+		name:   "MOVHstoreidx",
+		argLen: 4,
+		asm:    loong64.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "I64GtU",
-		argLen: 2,
-		asm:    wasm.AI64GtU,
+		name:   "MOVWstoreidx",
+		argLen: 4,
+		asm:    loong64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "I64LeS",
-		argLen: 2,
-		asm:    wasm.AI64LeS,
+		name:   "MOVVstoreidx",
+		argLen: 4,
+		asm:    loong64.AMOVV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "I64LeU",
-		argLen: 2,
-		asm:    wasm.AI64LeU,
+		name:   "MOVFstoreidx",
+		argLen: 4,
+		asm:    loong64.AMOVF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "I64GeS",
-		argLen: 2,
-		asm:    wasm.AI64GeS,
+		name:   "MOVDstoreidx",
+		argLen: 4,
+		asm:    loong64.AMOVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+				{2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "I64GeU",
-		argLen: 2,
-		asm:    wasm.AI64GeU,
+		name:           "MOVBstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            loong64.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "F32Eq",
-		argLen: 2,
-		asm:    wasm.AF32Eq,
+		name:           "MOVHstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            loong64.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "F32Ne",
-		argLen: 2,
-		asm:    wasm.AF32Ne,
+		name:           "MOVWstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            loong64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "F32Lt",
-		argLen: 2,
-		asm:    wasm.AF32Lt,
+		name:           "MOVVstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            loong64.AMOVV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "F32Gt",
-		argLen: 2,
-		asm:    wasm.AF32Gt,
+		name:   "MOVBstorezeroidx",
+		argLen: 3,
+		asm:    loong64.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "F32Le",
-		argLen: 2,
-		asm:    wasm.AF32Le,
+		name:   "MOVHstorezeroidx",
+		argLen: 3,
+		asm:    loong64.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "F32Ge",
-		argLen: 2,
-		asm:    wasm.AF32Ge,
+		name:   "MOVWstorezeroidx",
+		argLen: 3,
+		asm:    loong64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "F64Eq",
-		argLen: 2,
-		asm:    wasm.AF64Eq,
+		name:   "MOVVstorezeroidx",
+		argLen: 3,
+		asm:    loong64.AMOVV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "F64Ne",
-		argLen: 2,
-		asm:    wasm.AF64Ne,
+		name:   "MOVWfpgp",
+		argLen: 1,
+		asm:    loong64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F64Lt",
-		argLen: 2,
-		asm:    wasm.AF64Lt,
+		name:   "MOVWgpfp",
+		argLen: 1,
+		asm:    loong64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "F64Gt",
-		argLen: 2,
-		asm:    wasm.AF64Gt,
+		name:   "MOVVfpgp",
+		argLen: 1,
+		asm:    loong64.AMOVV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F64Le",
-		argLen: 2,
-		asm:    wasm.AF64Le,
+		name:   "MOVVgpfp",
+		argLen: 1,
+		asm:    loong64.AMOVV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "F64Ge",
-		argLen: 2,
-		asm:    wasm.AF64Ge,
+		name:   "MOVBreg",
+		argLen: 1,
+		asm:    loong64.AMOVB,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "I64Add",
-		argLen: 2,
-		asm:    wasm.AI64Add,
+		name:   "MOVBUreg",
+		argLen: 1,
+		asm:    loong64.AMOVBU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:    "I64AddConst",
-		auxType: auxInt64,
-		argLen:  1,
-		asm:     wasm.AI64Add,
+		name:   "MOVHreg",
+		argLen: 1,
+		asm:    loong64.AMOVH,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "I64Sub",
-		argLen: 2,
-		asm:    wasm.AI64Sub,
+		name:   "MOVHUreg",
+		argLen: 1,
+		asm:    loong64.AMOVHU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "I64Mul",
-		argLen: 2,
-		asm:    wasm.AI64Mul,
+		name:   "MOVWreg",
+		argLen: 1,
+		asm:    loong64.AMOVW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "I64DivS",
-		argLen: 2,
-		asm:    wasm.AI64DivS,
+		name:   "MOVWUreg",
+		argLen: 1,
+		asm:    loong64.AMOVWU,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "I64DivU",
-		argLen: 2,
-		asm:    wasm.AI64DivU,
+		name:   "MOVVreg",
+		argLen: 1,
+		asm:    loong64.AMOVV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "I64RemS",
-		argLen: 2,
-		asm:    wasm.AI64RemS,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+		name:         "MOVVnop",
+		argLen:       1,
+		resultInArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "I64RemU",
-		argLen: 2,
-		asm:    wasm.AI64RemU,
+		name:   "MOVWF",
+		argLen: 1,
+		asm:    loong64.AMOVWF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "I64And",
-		argLen: 2,
-		asm:    wasm.AI64And,
+		name:   "MOVWD",
+		argLen: 1,
+		asm:    loong64.AMOVWD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "I64Or",
-		argLen: 2,
-		asm:    wasm.AI64Or,
+		name:   "MOVVF",
+		argLen: 1,
+		asm:    loong64.AMOVVF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "I64Xor",
-		argLen: 2,
-		asm:    wasm.AI64Xor,
+		name:   "MOVVD",
+		argLen: 1,
+		asm:    loong64.AMOVVD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "I64Shl",
-		argLen: 2,
-		asm:    wasm.AI64Shl,
+		name:   "TRUNCFW",
+		argLen: 1,
+		asm:    loong64.ATRUNCFW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "I64ShrS",
-		argLen: 2,
-		asm:    wasm.AI64ShrS,
+		name:   "TRUNCDW",
+		argLen: 1,
+		asm:    loong64.ATRUNCDW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "I64ShrU",
-		argLen: 2,
-		asm:    wasm.AI64ShrU,
+		name:   "TRUNCFV",
+		argLen: 1,
+		asm:    loong64.ATRUNCFV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "F32Neg",
+		name:   "TRUNCDV",
 		argLen: 1,
-		asm:    wasm.AF32Neg,
+		asm:    loong64.ATRUNCDV,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "F32Add",
-		argLen: 2,
-		asm:    wasm.AF32Add,
+		name:   "MOVFD",
+		argLen: 1,
+		asm:    loong64.AMOVFD,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "F32Sub",
-		argLen: 2,
-		asm:    wasm.AF32Sub,
+		name:   "MOVDF",
+		argLen: 1,
+		asm:    loong64.AMOVDF,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "F32Mul",
-		argLen: 2,
-		asm:    wasm.AF32Mul,
+		name:         "LoweredRound32F",
+		argLen:       1,
+		resultInArg0: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "F32Div",
-		argLen: 2,
-		asm:    wasm.AF32Div,
+		name:         "LoweredRound64F",
+		argLen:       1,
+		resultInArg0: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 			},
 		},
 	},
 	{
-		name:   "F64Neg",
-		argLen: 1,
-		asm:    wasm.AF64Neg,
+		name:         "CALLstatic",
+		auxType:      auxCallOff,
+		argLen:       -1,
+		clobberFlags: true,
+		call:         true,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
+			clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:   "F64Add",
-		argLen: 2,
-		asm:    wasm.AF64Add,
+		name:         "CALLtail",
+		auxType:      auxCallOff,
+		argLen:       -1,
+		clobberFlags: true,
+		call:         true,
+		tailCall:     true,
 		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
+			clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:   "F64Sub",
-		argLen: 2,
-		asm:    wasm.AF64Sub,
+		name:         "CALLclosure",
+		auxType:      auxCallOff,
+		argLen:       -1,
+		clobberFlags: true,
+		call:         true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 268435456},  // R29
+				{0, 1071644668}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
+			clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:   "F64Mul",
-		argLen: 2,
-		asm:    wasm.AF64Mul,
+		name:         "CALLinter",
+		auxType:      auxCallOff,
+		argLen:       -1,
+		clobberFlags: true,
+		call:         true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
+			clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 		},
 	},
 	{
-		name:   "F64Div",
-		argLen: 2,
-		asm:    wasm.AF64Div,
+		name:           "DUFFZERO",
+		auxType:        auxInt64,
+		argLen:         2,
+		faultOnNilArg0: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 524288}, // R20
 			},
+			clobbers: 524290, // R1 R20
 		},
 	},
 	{
-		name:   "I64TruncSatF64S",
-		argLen: 1,
-		asm:    wasm.AI64TruncSatF64S,
+		name:           "DUFFCOPY",
+		auxType:        auxInt64,
+		argLen:         3,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1048576}, // R21
+				{1, 524288},  // R20
 			},
+			clobbers: 1572866, // R1 R20 R21
 		},
 	},
 	{
-		name:   "I64TruncSatF64U",
-		argLen: 1,
-		asm:    wasm.AI64TruncSatF64U,
+		name:           "LoweredZero",
+		auxType:        auxInt64,
+		argLen:         3,
+		faultOnNilArg0: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 524288},     // R20
+				{1, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
+			clobbers: 524288, // R20
 		},
 	},
 	{
-		name:   "I64TruncSatF32S",
-		argLen: 1,
-		asm:    wasm.AI64TruncSatF32S,
+		name:           "LoweredMove",
+		auxType:        auxInt64,
+		argLen:         4,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1048576},    // R21
+				{1, 524288},     // R20
+				{2, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
+			clobbers: 1572864, // R20 R21
 		},
 	},
 	{
-		name:   "I64TruncSatF32U",
-		argLen: 1,
-		asm:    wasm.AI64TruncSatF32U,
+		name:           "LoweredAtomicLoad8",
+		argLen:         2,
+		faultOnNilArg0: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F32ConvertI64S",
-		argLen: 1,
-		asm:    wasm.AF32ConvertI64S,
+		name:           "LoweredAtomicLoad32",
+		argLen:         2,
+		faultOnNilArg0: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F32ConvertI64U",
-		argLen: 1,
-		asm:    wasm.AF32ConvertI64U,
+		name:           "LoweredAtomicLoad64",
+		argLen:         2,
+		faultOnNilArg0: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F64ConvertI64S",
-		argLen: 1,
-		asm:    wasm.AF64ConvertI64S,
+		name:           "LoweredAtomicStore8",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
-			},
-			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "F64ConvertI64U",
-		argLen: 1,
-		asm:    wasm.AF64ConvertI64U,
+		name:           "LoweredAtomicStore32",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
-			},
-			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "F32DemoteF64",
-		argLen: 1,
-		asm:    wasm.AF32DemoteF64,
+		name:           "LoweredAtomicStore64",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "F64PromoteF32",
-		argLen: 1,
-		asm:    wasm.AF64PromoteF32,
+		name:           "LoweredAtomicStore8Variant",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-			},
-			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "I64Extend8S",
-		argLen: 1,
-		asm:    wasm.AI64Extend8S,
+		name:           "LoweredAtomicStore32Variant",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "I64Extend16S",
-		argLen: 1,
-		asm:    wasm.AI64Extend16S,
+		name:           "LoweredAtomicStore64Variant",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 		},
 	},
 	{
-		name:   "I64Extend32S",
-		argLen: 1,
-		asm:    wasm.AI64Extend32S,
+		name:            "LoweredAtomicExchange32",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F32Sqrt",
-		argLen: 1,
-		asm:    wasm.AF32Sqrt,
+		name:            "LoweredAtomicExchange64",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F32Trunc",
-		argLen: 1,
-		asm:    wasm.AF32Trunc,
+		name:            "LoweredAtomicExchange8Variant",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F32Ceil",
-		argLen: 1,
-		asm:    wasm.AF32Ceil,
+		name:            "LoweredAtomicAdd32",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F32Floor",
-		argLen: 1,
-		asm:    wasm.AF32Floor,
+		name:            "LoweredAtomicAdd64",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F32Nearest",
-		argLen: 1,
-		asm:    wasm.AF32Nearest,
+		name:            "LoweredAtomicCas32",
+		argLen:          4,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F32Abs",
-		argLen: 1,
-		asm:    wasm.AF32Abs,
+		name:            "LoweredAtomicCas64",
+		argLen:          4,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F32Copysign",
-		argLen: 2,
-		asm:    wasm.AF32Copysign,
+		name:            "LoweredAtomicCas64Variant",
+		argLen:          4,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F64Sqrt",
-		argLen: 1,
-		asm:    wasm.AF64Sqrt,
+		name:            "LoweredAtomicCas32Variant",
+		argLen:          4,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F64Trunc",
-		argLen: 1,
-		asm:    wasm.AF64Trunc,
+		name:            "LoweredAtomicAnd32",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		asm:             loong64.AAMANDDBW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 			},
 		},
 	},
 	{
-		name:   "F64Ceil",
-		argLen: 1,
-		asm:    wasm.AF64Ceil,
+		name:            "LoweredAtomicOr32",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		asm:             loong64.AAMORDBW,
 		reg: regInfo{
 			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 			},
 			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicAnd32value",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		asm:             loong64.AAMANDDBW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicAnd64value",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		asm:             loong64.AAMANDDBV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicOr32value",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		asm:             loong64.AAMORDBW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicOr64value",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		asm:             loong64.AAMORDBV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+				{0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
+	},
+	{
+		name:           "LoweredNilCheck",
+		argLen:         2,
+		nilCheck:       true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
+	},
+	{
+		name:   "FPFlagTrue",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
+	},
+	{
+		name:   "FPFlagFalse",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
+	},
+	{
+		name:      "LoweredGetClosurePtr",
+		argLen:    0,
+		zeroWidth: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 268435456}, // R29
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerSP",
+		argLen:            1,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerPC",
+		argLen:            0,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
+	},
+	{
+		name:         "LoweredWB",
+		auxType:      auxInt64,
+		argLen:       1,
+		clobberFlags: true,
+		reg: regInfo{
+			clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			outputs: []outputInfo{
+				{0, 268435456}, // R29
+			},
+		},
+	},
+	{
+		name:           "LoweredPubBarrier",
+		argLen:         1,
+		hasSideEffects: true,
+		asm:            loong64.ADBAR,
+		reg:            regInfo{},
+	},
+	{
+		name:    "LoweredPanicBoundsA",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4194304}, // R23
+				{1, 8388608}, // R24
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicBoundsB",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1048576}, // R21
+				{1, 4194304}, // R23
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicBoundsC",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 524288},  // R20
+				{1, 1048576}, // R21
+			},
+		},
+	},
+	{
+		name:           "PRELD",
+		auxType:        auxInt64,
+		argLen:         2,
+		hasSideEffects: true,
+		asm:            loong64.APRELD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
+	},
+	{
+		name:           "PRELDX",
+		auxType:        auxInt64,
+		argLen:         2,
+		hasSideEffects: true,
+		asm:            loong64.APRELDX,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+			},
+		},
+	},
+
+	{
+		name:        "ADD",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AADDU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:    "ADDconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     mips.AADDU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "SUB",
+		argLen: 2,
+		asm:    mips.ASUBU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:    "SUBconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     mips.ASUBU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:        "MUL",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AMUL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			clobbers: 105553116266496, // HI LO
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:        "MULT",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AMUL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 35184372088832}, // HI
+				{1, 70368744177664}, // LO
+			},
+		},
+	},
+	{
+		name:        "MULTU",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AMULU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 35184372088832}, // HI
+				{1, 70368744177664}, // LO
+			},
+		},
+	},
+	{
+		name:   "DIV",
+		argLen: 2,
+		asm:    mips.ADIV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 35184372088832}, // HI
+				{1, 70368744177664}, // LO
+			},
+		},
+	},
+	{
+		name:   "DIVU",
+		argLen: 2,
+		asm:    mips.ADIVU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 35184372088832}, // HI
+				{1, 70368744177664}, // LO
+			},
+		},
+	},
+	{
+		name:        "ADDF",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AADDF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:        "ADDD",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AADDD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "SUBF",
+		argLen: 2,
+		asm:    mips.ASUBF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "SUBD",
+		argLen: 2,
+		asm:    mips.ASUBD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:        "MULF",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AMULF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:        "MULD",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AMULD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "DIVF",
+		argLen: 2,
+		asm:    mips.ADIVF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "DIVD",
+		argLen: 2,
+		asm:    mips.ADIVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:        "AND",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AAND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:    "ANDconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     mips.AAND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 			},
 		},
 	},
 	{
-		name:   "F64Floor",
-		argLen: 1,
-		asm:    wasm.AF64Floor,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-		},
+		name:        "OR",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:    "ORconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     mips.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:        "XOR",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AXOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:    "XORconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     mips.AXOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:        "NOR",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.ANOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:    "NORconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     mips.ANOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "NEG",
+		argLen: 1,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "NEGF",
+		argLen: 1,
+		asm:    mips.ANEGF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "NEGD",
+		argLen: 1,
+		asm:    mips.ANEGD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "ABSD",
+		argLen: 1,
+		asm:    mips.AABSD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "SQRTD",
+		argLen: 1,
+		asm:    mips.ASQRTD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "SQRTF",
+		argLen: 1,
+		asm:    mips.ASQRTF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "SLL",
+		argLen: 2,
+		asm:    mips.ASLL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:    "SLLconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     mips.ASLL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "SRL",
+		argLen: 2,
+		asm:    mips.ASRL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:    "SRLconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     mips.ASRL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "SRA",
+		argLen: 2,
+		asm:    mips.ASRA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:    "SRAconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     mips.ASRA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "CLZ",
+		argLen: 1,
+		asm:    mips.ACLZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "SGT",
+		argLen: 2,
+		asm:    mips.ASGT,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:    "SGTconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     mips.ASGT,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "SGTzero",
+		argLen: 1,
+		asm:    mips.ASGT,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "SGTU",
+		argLen: 2,
+		asm:    mips.ASGTU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:    "SGTUconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     mips.ASGTU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "SGTUzero",
+		argLen: 1,
+		asm:    mips.ASGTU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "CMPEQF",
+		argLen: 2,
+		asm:    mips.ACMPEQF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "CMPEQD",
+		argLen: 2,
+		asm:    mips.ACMPEQD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "CMPGEF",
+		argLen: 2,
+		asm:    mips.ACMPGEF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "CMPGED",
+		argLen: 2,
+		asm:    mips.ACMPGED,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "CMPGTF",
+		argLen: 2,
+		asm:    mips.ACMPGTF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "CMPGTD",
+		argLen: 2,
+		asm:    mips.ACMPGTD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:              "MOVWconst",
+		auxType:           auxInt32,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               mips.AMOVW,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:              "MOVFconst",
+		auxType:           auxFloat32,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               mips.AMOVF,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:              "MOVDconst",
+		auxType:           auxFloat64,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               mips.AMOVD,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:              "MOVWaddr",
+		auxType:           auxSymOff,
+		argLen:            1,
+		rematerializeable: true,
+		symEffect:         SymAddr,
+		asm:               mips.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140737555464192}, // SP SB
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:           "MOVBload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:           "MOVBUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVBU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:           "MOVHload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:           "MOVHUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVHU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:           "MOVWload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:           "MOVFload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:           "MOVDload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:           "MOVBstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVHstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVWstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVFstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVDstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVBstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVHstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVWstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:   "MOVWfpgp",
+		argLen: 1,
+		asm:    mips.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "MOVWgpfp",
+		argLen: 1,
+		asm:    mips.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "MOVBreg",
+		argLen: 1,
+		asm:    mips.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "MOVBUreg",
+		argLen: 1,
+		asm:    mips.AMOVBU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "MOVHreg",
+		argLen: 1,
+		asm:    mips.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "MOVHUreg",
+		argLen: 1,
+		asm:    mips.AMOVHU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "MOVWreg",
+		argLen: 1,
+		asm:    mips.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:         "MOVWnop",
+		argLen:       1,
+		resultInArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:         "CMOVZ",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          mips.ACMOVZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:         "CMOVZzero",
+		argLen:       2,
+		resultInArg0: true,
+		asm:          mips.ACMOVZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "MOVWF",
+		argLen: 1,
+		asm:    mips.AMOVWF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "MOVWD",
+		argLen: 1,
+		asm:    mips.AMOVWD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "TRUNCFW",
+		argLen: 1,
+		asm:    mips.ATRUNCFW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "TRUNCDW",
+		argLen: 1,
+		asm:    mips.ATRUNCDW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "MOVFD",
+		argLen: 1,
+		asm:    mips.AMOVFD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:   "MOVDF",
+		argLen: 1,
+		asm:    mips.AMOVDF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+			outputs: []outputInfo{
+				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+			},
+		},
+	},
+	{
+		name:         "CALLstatic",
+		auxType:      auxCallOff,
+		argLen:       1,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+		},
+	},
+	{
+		name:         "CALLtail",
+		auxType:      auxCallOff,
+		argLen:       1,
+		clobberFlags: true,
+		call:         true,
+		tailCall:     true,
+		reg: regInfo{
+			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+		},
+	},
+	{
+		name:         "CALLclosure",
+		auxType:      auxCallOff,
+		argLen:       3,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 4194304},   // R22
+				{0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31
+			},
+			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+		},
+	},
+	{
+		name:         "CALLinter",
+		auxType:      auxCallOff,
+		argLen:       2,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+		},
+	},
+	{
+		name:           "LoweredAtomicLoad8",
+		argLen:         2,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicLoad32",
+		argLen:         2,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStore8",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStore32",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStorezero",
+		argLen:         2,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicExchange",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicAdd",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicAddconst",
+		auxType:         auxInt32,
+		argLen:          2,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicCas",
+		argLen:          4,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{2, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicAnd",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		unsafePoint:    true,
+		asm:            mips.AAND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicOr",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		unsafePoint:    true,
+		asm:            mips.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredZero",
+		auxType:        auxInt32,
+		argLen:         3,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2},         // R1
+				{1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+			clobbers: 2, // R1
+		},
+	},
+	{
+		name:           "LoweredMove",
+		auxType:        auxInt32,
+		argLen:         4,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4},         // R2
+				{1, 2},         // R1
+				{2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+			clobbers: 6, // R1 R2
+		},
+	},
+	{
+		name:           "LoweredNilCheck",
+		argLen:         2,
+		nilCheck:       true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+			},
+		},
+	},
+	{
+		name:   "FPFlagTrue",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:   "FPFlagFalse",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:      "LoweredGetClosurePtr",
+		argLen:    0,
+		zeroWidth: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 4194304}, // R22
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerSP",
+		argLen:            1,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerPC",
+		argLen:            0,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+			},
+		},
+	},
+	{
+		name:         "LoweredWB",
+		auxType:      auxInt64,
+		argLen:       1,
+		clobberFlags: true,
+		reg: regInfo{
+			clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+			outputs: []outputInfo{
+				{0, 16777216}, // R25
+			},
+		},
+	},
+	{
+		name:           "LoweredPubBarrier",
+		argLen:         1,
+		hasSideEffects: true,
+		asm:            mips.ASYNC,
+		reg:            regInfo{},
+	},
+	{
+		name:    "LoweredPanicBoundsA",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 8},  // R3
+				{1, 16}, // R4
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicBoundsB",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4}, // R2
+				{1, 8}, // R3
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicBoundsC",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2}, // R1
+				{1, 4}, // R2
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicExtendA",
+		auxType: auxInt64,
+		argLen:  4,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 32}, // R5
+				{1, 8},  // R3
+				{2, 16}, // R4
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicExtendB",
+		auxType: auxInt64,
+		argLen:  4,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 32}, // R5
+				{1, 4},  // R2
+				{2, 8},  // R3
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicExtendC",
+		auxType: auxInt64,
+		argLen:  4,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 32}, // R5
+				{1, 2},  // R1
+				{2, 4},  // R2
+			},
+		},
+	},
+
+	{
+		name:        "ADDV",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AADDVU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:    "ADDVconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     mips.AADDVU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "SUBV",
+		argLen: 2,
+		asm:    mips.ASUBVU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:    "SUBVconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     mips.ASUBVU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:        "MULV",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AMULV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504606846976}, // HI
+				{1, 2305843009213693952}, // LO
+			},
+		},
+	},
+	{
+		name:        "MULVU",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AMULVU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504606846976}, // HI
+				{1, 2305843009213693952}, // LO
+			},
+		},
+	},
+	{
+		name:   "DIVV",
+		argLen: 2,
+		asm:    mips.ADIVV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504606846976}, // HI
+				{1, 2305843009213693952}, // LO
+			},
+		},
+	},
+	{
+		name:   "DIVVU",
+		argLen: 2,
+		asm:    mips.ADIVVU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504606846976}, // HI
+				{1, 2305843009213693952}, // LO
+			},
+		},
+	},
+	{
+		name:        "ADDF",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AADDF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "ADDD",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AADDD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "SUBF",
+		argLen: 2,
+		asm:    mips.ASUBF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "SUBD",
+		argLen: 2,
+		asm:    mips.ASUBD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "MULF",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AMULF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "MULD",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AMULD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "DIVF",
+		argLen: 2,
+		asm:    mips.ADIVF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "DIVD",
+		argLen: 2,
+		asm:    mips.ADIVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "AND",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AAND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:    "ANDconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     mips.AAND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:        "OR",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:    "ORconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     mips.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:        "XOR",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.AXOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:    "XORconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     mips.AXOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:        "NOR",
+		argLen:      2,
+		commutative: true,
+		asm:         mips.ANOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:    "NORconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     mips.ANOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "NEGV",
+		argLen: 1,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "NEGF",
+		argLen: 1,
+		asm:    mips.ANEGF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "NEGD",
+		argLen: 1,
+		asm:    mips.ANEGD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "ABSD",
+		argLen: 1,
+		asm:    mips.AABSD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "SQRTD",
+		argLen: 1,
+		asm:    mips.ASQRTD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "SQRTF",
+		argLen: 1,
+		asm:    mips.ASQRTF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "SLLV",
+		argLen: 2,
+		asm:    mips.ASLLV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:    "SLLVconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     mips.ASLLV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "SRLV",
+		argLen: 2,
+		asm:    mips.ASRLV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:    "SRLVconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     mips.ASRLV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "SRAV",
+		argLen: 2,
+		asm:    mips.ASRAV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:    "SRAVconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     mips.ASRAV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "SGT",
+		argLen: 2,
+		asm:    mips.ASGT,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:    "SGTconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     mips.ASGT,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "SGTU",
+		argLen: 2,
+		asm:    mips.ASGTU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:    "SGTUconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     mips.ASGTU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "CMPEQF",
+		argLen: 2,
+		asm:    mips.ACMPEQF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "CMPEQD",
+		argLen: 2,
+		asm:    mips.ACMPEQD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "CMPGEF",
+		argLen: 2,
+		asm:    mips.ACMPGEF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "CMPGED",
+		argLen: 2,
+		asm:    mips.ACMPGED,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "CMPGTF",
+		argLen: 2,
+		asm:    mips.ACMPGTF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "CMPGTD",
+		argLen: 2,
+		asm:    mips.ACMPGTD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:              "MOVVconst",
+		auxType:           auxInt64,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               mips.AMOVV,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:              "MOVFconst",
+		auxType:           auxFloat64,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               mips.AMOVF,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:              "MOVDconst",
+		auxType:           auxFloat64,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               mips.AMOVD,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:              "MOVVaddr",
+		auxType:           auxSymOff,
+		argLen:            1,
+		rematerializeable: true,
+		symEffect:         SymAddr,
+		asm:               mips.AMOVV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018460942336}, // SP SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:           "MOVBload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:           "MOVBUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVBU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:           "MOVHload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:           "MOVHUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVHU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:           "MOVWload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:           "MOVWUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVWU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:           "MOVVload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:           "MOVFload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:           "MOVDload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            mips.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:           "MOVBstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVHstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVWstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVVstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVFstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:           "MOVDstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:           "MOVBstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVHstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVWstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "MOVVstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            mips.AMOVV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:   "MOVWfpgp",
+		argLen: 1,
+		asm:    mips.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "MOVWgpfp",
+		argLen: 1,
+		asm:    mips.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "MOVVfpgp",
+		argLen: 1,
+		asm:    mips.AMOVV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "MOVVgpfp",
+		argLen: 1,
+		asm:    mips.AMOVV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "MOVBreg",
+		argLen: 1,
+		asm:    mips.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "MOVBUreg",
+		argLen: 1,
+		asm:    mips.AMOVBU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "MOVHreg",
+		argLen: 1,
+		asm:    mips.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "MOVHUreg",
+		argLen: 1,
+		asm:    mips.AMOVHU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "MOVWreg",
+		argLen: 1,
+		asm:    mips.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "MOVWUreg",
+		argLen: 1,
+		asm:    mips.AMOVWU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "MOVVreg",
+		argLen: 1,
+		asm:    mips.AMOVV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:         "MOVVnop",
+		argLen:       1,
+		resultInArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "MOVWF",
+		argLen: 1,
+		asm:    mips.AMOVWF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "MOVWD",
+		argLen: 1,
+		asm:    mips.AMOVWD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "MOVVF",
+		argLen: 1,
+		asm:    mips.AMOVVF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "MOVVD",
+		argLen: 1,
+		asm:    mips.AMOVVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "TRUNCFW",
+		argLen: 1,
+		asm:    mips.ATRUNCFW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "TRUNCDW",
+		argLen: 1,
+		asm:    mips.ATRUNCDW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "TRUNCFV",
+		argLen: 1,
+		asm:    mips.ATRUNCFV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "TRUNCDV",
+		argLen: 1,
+		asm:    mips.ATRUNCDV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "MOVFD",
+		argLen: 1,
+		asm:    mips.AMOVFD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "MOVDF",
+		argLen: 1,
+		asm:    mips.AMOVDF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:         "CALLstatic",
+		auxType:      auxCallOff,
+		argLen:       1,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
+		},
+	},
+	{
+		name:         "CALLtail",
+		auxType:      auxCallOff,
+		argLen:       1,
+		clobberFlags: true,
+		call:         true,
+		tailCall:     true,
+		reg: regInfo{
+			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
+		},
+	},
+	{
+		name:         "CALLclosure",
+		auxType:      auxCallOff,
+		argLen:       3,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 4194304},   // R22
+				{0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31
+			},
+			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
+		},
+	},
+	{
+		name:         "CALLinter",
+		auxType:      auxCallOff,
+		argLen:       2,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
+		},
+	},
+	{
+		name:           "DUFFZERO",
+		auxType:        auxInt64,
+		argLen:         2,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+			clobbers: 134217730, // R1 R31
+		},
+	},
+	{
+		name:           "DUFFCOPY",
+		auxType:        auxInt64,
+		argLen:         3,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4}, // R2
+				{1, 2}, // R1
+			},
+			clobbers: 134217734, // R1 R2 R31
+		},
+	},
+	{
+		name:           "LoweredZero",
+		auxType:        auxInt64,
+		argLen:         3,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2},         // R1
+				{1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+			clobbers: 2, // R1
+		},
+	},
+	{
+		name:           "LoweredMove",
+		auxType:        auxInt64,
+		argLen:         4,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4},         // R2
+				{1, 2},         // R1
+				{2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+			clobbers: 6, // R1 R2
+		},
+	},
+	{
+		name:           "LoweredAtomicAnd32",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		unsafePoint:    true,
+		asm:            mips.AAND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicOr32",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		unsafePoint:    true,
+		asm:            mips.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicLoad8",
+		argLen:         2,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicLoad32",
+		argLen:         2,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicLoad64",
+		argLen:         2,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStore8",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStore32",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStore64",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStorezero32",
+		argLen:         2,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStorezero64",
+		argLen:         2,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicExchange32",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicExchange64",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicAdd32",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicAdd64",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicAddconst32",
+		auxType:         auxInt32,
+		argLen:          2,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicAddconst64",
+		auxType:         auxInt64,
+		argLen:          2,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicCas32",
+		argLen:          4,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicCas64",
+		argLen:          4,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+			},
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:           "LoweredNilCheck",
+		argLen:         2,
+		nilCheck:       true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+			},
+		},
+	},
+	{
+		name:   "FPFlagTrue",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:   "FPFlagFalse",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:      "LoweredGetClosurePtr",
+		argLen:    0,
+		zeroWidth: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 4194304}, // R22
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerSP",
+		argLen:            1,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerPC",
+		argLen:            0,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+			},
+		},
+	},
+	{
+		name:         "LoweredWB",
+		auxType:      auxInt64,
+		argLen:       1,
+		clobberFlags: true,
+		reg: regInfo{
+			clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
+			outputs: []outputInfo{
+				{0, 16777216}, // R25
+			},
+		},
+	},
+	{
+		name:           "LoweredPubBarrier",
+		argLen:         1,
+		hasSideEffects: true,
+		asm:            mips.ASYNC,
+		reg:            regInfo{},
+	},
+	{
+		name:    "LoweredPanicBoundsA",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 8},  // R3
+				{1, 16}, // R4
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicBoundsB",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4}, // R2
+				{1, 8}, // R3
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicBoundsC",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2}, // R1
+				{1, 4}, // R2
+			},
+		},
+	},
+
+	{
+		name:        "ADD",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AADD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "ADDCC",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AADDCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "ADDconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.AADD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "ADDCCconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.AADDCCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			clobbers: 9223372036854775808, // XER
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "FADD",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AFADD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:        "FADDS",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AFADDS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "SUB",
+		argLen: 2,
+		asm:    ppc64.ASUB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "SUBCC",
+		argLen: 2,
+		asm:    ppc64.ASUBCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "SUBFCconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ASUBC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			clobbers: 9223372036854775808, // XER
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "FSUB",
+		argLen: 2,
+		asm:    ppc64.AFSUB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FSUBS",
+		argLen: 2,
+		asm:    ppc64.AFSUBS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "XSMINJDP",
+		argLen: 2,
+		asm:    ppc64.AXSMINJDP,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "XSMAXJDP",
+		argLen: 2,
+		asm:    ppc64.AXSMAXJDP,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:        "MULLD",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AMULLD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "MULLW",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AMULLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "MULLDconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     ppc64.AMULLD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "MULLWconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     ppc64.AMULLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MADDLD",
+		argLen: 3,
+		asm:    ppc64.AMADDLD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "MULHD",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AMULHD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "MULHW",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AMULHW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "MULHDU",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AMULHDU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "MULHDUCC",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AMULHDUCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "MULHWU",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AMULHWU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "FMUL",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AFMUL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:        "FMULS",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AFMULS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FMADD",
+		argLen: 3,
+		asm:    ppc64.AFMADD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FMADDS",
+		argLen: 3,
+		asm:    ppc64.AFMADDS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FMSUB",
+		argLen: 3,
+		asm:    ppc64.AFMSUB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FMSUBS",
+		argLen: 3,
+		asm:    ppc64.AFMSUBS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "SRAD",
+		argLen: 2,
+		asm:    ppc64.ASRAD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			clobbers: 9223372036854775808, // XER
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "SRAW",
+		argLen: 2,
+		asm:    ppc64.ASRAW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			clobbers: 9223372036854775808, // XER
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "SRD",
+		argLen: 2,
+		asm:    ppc64.ASRD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "SRW",
+		argLen: 2,
+		asm:    ppc64.ASRW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "SLD",
+		argLen: 2,
+		asm:    ppc64.ASLD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "SLW",
+		argLen: 2,
+		asm:    ppc64.ASLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "ROTL",
+		argLen: 2,
+		asm:    ppc64.AROTL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "ROTLW",
+		argLen: 2,
+		asm:    ppc64.AROTLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "CLRLSLWI",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     ppc64.ACLRLSLWI,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "CLRLSLDI",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     ppc64.ACLRLSLDI,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "ADDC",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AADDC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			clobbers: 9223372036854775808, // XER
+			outputs: []outputInfo{
+				{1, 9223372036854775808}, // XER
+				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "SUBC",
+		argLen: 2,
+		asm:    ppc64.ASUBC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			clobbers: 9223372036854775808, // XER
+			outputs: []outputInfo{
+				{1, 9223372036854775808}, // XER
+				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "ADDCconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.AADDC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{1, 9223372036854775808}, // XER
+				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "SUBCconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ASUBC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{1, 9223372036854775808}, // XER
+				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "ADDE",
+		argLen:      3,
+		commutative: true,
+		asm:         ppc64.AADDE,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 9223372036854775808}, // XER
+				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			clobbers: 9223372036854775808, // XER
+			outputs: []outputInfo{
+				{1, 9223372036854775808}, // XER
+				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "ADDZE",
+		argLen: 2,
+		asm:    ppc64.AADDZE,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 9223372036854775808}, // XER
+				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			clobbers: 9223372036854775808, // XER
+			outputs: []outputInfo{
+				{1, 9223372036854775808}, // XER
+				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "SUBE",
+		argLen: 3,
+		asm:    ppc64.ASUBE,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{2, 9223372036854775808}, // XER
+				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			clobbers: 9223372036854775808, // XER
+			outputs: []outputInfo{
+				{1, 9223372036854775808}, // XER
+				{0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "ADDZEzero",
+		argLen: 1,
+		asm:    ppc64.AADDZE,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372036854775808}, // XER
+			},
+			clobbers: 9223372036854775808, // XER
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "SUBZEzero",
+		argLen: 1,
+		asm:    ppc64.ASUBZE,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372036854775808}, // XER
+			},
+			clobbers: 9223372036854775808, // XER
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "SRADconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ASRAD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			clobbers: 9223372036854775808, // XER
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "SRAWconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ASRAW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			clobbers: 9223372036854775808, // XER
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "SRDconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ASRD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "SRWconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ASRW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "SLDconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ASLD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "SLWconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ASLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "ROTLconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.AROTL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "ROTLWconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.AROTLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "EXTSWSLconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.AEXTSWSLI,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "RLWINM",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ARLWNM,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "RLWNM",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     ppc64.ARLWNM,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:         "RLWMI",
+		auxType:      auxInt64,
+		argLen:       2,
+		resultInArg0: true,
+		asm:          ppc64.ARLWMI,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "RLDICL",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ARLDICL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "RLDICLCC",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ARLDICLCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "RLDICR",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ARLDICR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "CNTLZD",
+		argLen: 1,
+		asm:    ppc64.ACNTLZD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "CNTLZDCC",
+		argLen: 1,
+		asm:    ppc64.ACNTLZDCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "CNTLZW",
+		argLen: 1,
+		asm:    ppc64.ACNTLZW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "CNTTZD",
+		argLen: 1,
+		asm:    ppc64.ACNTTZD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "CNTTZW",
+		argLen: 1,
+		asm:    ppc64.ACNTTZW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "POPCNTD",
+		argLen: 1,
+		asm:    ppc64.APOPCNTD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "POPCNTW",
+		argLen: 1,
+		asm:    ppc64.APOPCNTW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "POPCNTB",
+		argLen: 1,
+		asm:    ppc64.APOPCNTB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "FDIV",
+		argLen: 2,
+		asm:    ppc64.AFDIV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FDIVS",
+		argLen: 2,
+		asm:    ppc64.AFDIVS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "DIVD",
+		argLen: 2,
+		asm:    ppc64.ADIVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "DIVW",
+		argLen: 2,
+		asm:    ppc64.ADIVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "DIVDU",
+		argLen: 2,
+		asm:    ppc64.ADIVDU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "DIVWU",
+		argLen: 2,
+		asm:    ppc64.ADIVWU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MODUD",
+		argLen: 2,
+		asm:    ppc64.AMODUD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MODSD",
+		argLen: 2,
+		asm:    ppc64.AMODSD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MODUW",
+		argLen: 2,
+		asm:    ppc64.AMODUW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MODSW",
+		argLen: 2,
+		asm:    ppc64.AMODSW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "FCTIDZ",
+		argLen: 1,
+		asm:    ppc64.AFCTIDZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FCTIWZ",
+		argLen: 1,
+		asm:    ppc64.AFCTIWZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FCFID",
+		argLen: 1,
+		asm:    ppc64.AFCFID,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FCFIDS",
+		argLen: 1,
+		asm:    ppc64.AFCFIDS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FRSP",
+		argLen: 1,
+		asm:    ppc64.AFRSP,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "MFVSRD",
+		argLen: 1,
+		asm:    ppc64.AMFVSRD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MTVSRD",
+		argLen: 1,
+		asm:    ppc64.AMTVSRD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:        "AND",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AAND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "ANDN",
+		argLen: 2,
+		asm:    ppc64.AANDN,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "ANDNCC",
+		argLen: 2,
+		asm:    ppc64.AANDNCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "ANDCC",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AANDCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "OR",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "ORN",
+		argLen: 2,
+		asm:    ppc64.AORN,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "ORCC",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AORCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "NOR",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.ANOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "NORCC",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.ANORCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "XOR",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AXOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "XORCC",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AXORCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:        "EQV",
+		argLen:      2,
+		commutative: true,
+		asm:         ppc64.AEQV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "NEG",
+		argLen: 1,
+		asm:    ppc64.ANEG,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "NEGCC",
+		argLen: 1,
+		asm:    ppc64.ANEGCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "BRD",
+		argLen: 1,
+		asm:    ppc64.ABRD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "BRW",
+		argLen: 1,
+		asm:    ppc64.ABRW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "BRH",
+		argLen: 1,
+		asm:    ppc64.ABRH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "FNEG",
+		argLen: 1,
+		asm:    ppc64.AFNEG,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FSQRT",
+		argLen: 1,
+		asm:    ppc64.AFSQRT,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FSQRTS",
+		argLen: 1,
+		asm:    ppc64.AFSQRTS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FFLOOR",
+		argLen: 1,
+		asm:    ppc64.AFRIM,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FCEIL",
+		argLen: 1,
+		asm:    ppc64.AFRIP,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FTRUNC",
+		argLen: 1,
+		asm:    ppc64.AFRIZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FROUND",
+		argLen: 1,
+		asm:    ppc64.AFRIN,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FABS",
+		argLen: 1,
+		asm:    ppc64.AFABS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FNABS",
+		argLen: 1,
+		asm:    ppc64.AFNABS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FCPSGN",
+		argLen: 2,
+		asm:    ppc64.AFCPSGN,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:    "ORconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "XORconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.AXOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "ANDCCconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.AANDCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:         "ANDconst",
+		auxType:      auxInt64,
+		argLen:       1,
+		clobberFlags: true,
+		asm:          ppc64.AANDCC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVBreg",
+		argLen: 1,
+		asm:    ppc64.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVBZreg",
+		argLen: 1,
+		asm:    ppc64.AMOVBZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVHreg",
+		argLen: 1,
+		asm:    ppc64.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVHZreg",
+		argLen: 1,
+		asm:    ppc64.AMOVHZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVWreg",
+		argLen: 1,
+		asm:    ppc64.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVWZreg",
+		argLen: 1,
+		asm:    ppc64.AMOVWZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVBZload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            ppc64.AMOVBZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVHload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            ppc64.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVHZload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            ppc64.AMOVHZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVWload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            ppc64.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVWZload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            ppc64.AMOVWZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVDload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            ppc64.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVDBRload",
+		argLen:         2,
+		faultOnNilArg0: true,
+		asm:            ppc64.AMOVDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVWBRload",
+		argLen:         2,
+		faultOnNilArg0: true,
+		asm:            ppc64.AMOVWBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVHBRload",
+		argLen:         2,
+		faultOnNilArg0: true,
+		asm:            ppc64.AMOVHBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVBZloadidx",
+		argLen: 3,
+		asm:    ppc64.AMOVBZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVHloadidx",
+		argLen: 3,
+		asm:    ppc64.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVHZloadidx",
+		argLen: 3,
+		asm:    ppc64.AMOVHZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVWloadidx",
+		argLen: 3,
+		asm:    ppc64.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVWZloadidx",
+		argLen: 3,
+		asm:    ppc64.AMOVWZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVDloadidx",
+		argLen: 3,
+		asm:    ppc64.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVHBRloadidx",
+		argLen: 3,
+		asm:    ppc64.AMOVHBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVWBRloadidx",
+		argLen: 3,
+		asm:    ppc64.AMOVWBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVDBRloadidx",
+		argLen: 3,
+		asm:    ppc64.AMOVDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "FMOVDloadidx",
+		argLen: 3,
+		asm:    ppc64.AFMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FMOVSloadidx",
+		argLen: 3,
+		asm:    ppc64.AFMOVS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:           "DCBT",
+		auxType:        auxInt64,
+		argLen:         2,
+		hasSideEffects: true,
+		asm:            ppc64.ADCBT,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVDBRstore",
+		argLen:         3,
+		faultOnNilArg0: true,
+		asm:            ppc64.AMOVDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVWBRstore",
+		argLen:         3,
+		faultOnNilArg0: true,
+		asm:            ppc64.AMOVWBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVHBRstore",
+		argLen:         3,
+		faultOnNilArg0: true,
+		asm:            ppc64.AMOVHBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "FMOVDload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            ppc64.AFMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:           "FMOVSload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            ppc64.AFMOVS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:           "MOVBstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            ppc64.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVHstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            ppc64.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVWstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            ppc64.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVDstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            ppc64.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "FMOVDstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            ppc64.AFMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:           "FMOVSstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            ppc64.AFMOVS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "MOVBstoreidx",
+		argLen: 4,
+		asm:    ppc64.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVHstoreidx",
+		argLen: 4,
+		asm:    ppc64.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVWstoreidx",
+		argLen: 4,
+		asm:    ppc64.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVDstoreidx",
+		argLen: 4,
+		asm:    ppc64.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "FMOVDstoreidx",
+		argLen: 4,
+		asm:    ppc64.AFMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FMOVSstoreidx",
+		argLen: 4,
+		asm:    ppc64.AFMOVS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "MOVHBRstoreidx",
+		argLen: 4,
+		asm:    ppc64.AMOVHBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVWBRstoreidx",
+		argLen: 4,
+		asm:    ppc64.AMOVWBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "MOVDBRstoreidx",
+		argLen: 4,
+		asm:    ppc64.AMOVDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVBstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            ppc64.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVHstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            ppc64.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVWstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            ppc64.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "MOVDstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            ppc64.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:              "MOVDaddr",
+		auxType:           auxSymOff,
+		argLen:            1,
+		rematerializeable: true,
+		symEffect:         SymAddr,
+		asm:               ppc64.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:              "MOVDconst",
+		auxType:           auxInt64,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               ppc64.AMOVD,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:              "FMOVDconst",
+		auxType:           auxFloat64,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               ppc64.AFMOVD,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:              "FMOVSconst",
+		auxType:           auxFloat32,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               ppc64.AFMOVS,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "FCMPU",
+		argLen: 2,
+		asm:    ppc64.AFCMPU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+				{1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:   "CMP",
+		argLen: 2,
+		asm:    ppc64.ACMP,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "CMPU",
+		argLen: 2,
+		asm:    ppc64.ACMPU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "CMPW",
+		argLen: 2,
+		asm:    ppc64.ACMPW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "CMPWU",
+		argLen: 2,
+		asm:    ppc64.ACMPWU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "CMPconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ACMP,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "CMPUconst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     ppc64.ACMPU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "CMPWconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     ppc64.ACMPW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "CMPWUconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     ppc64.ACMPWU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "ISEL",
+		auxType: auxInt32,
+		argLen:  3,
+		asm:     ppc64.AISEL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "ISELZ",
+		auxType: auxInt32,
+		argLen:  2,
+		asm:     ppc64.AISEL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "SETBC",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     ppc64.ASETBC,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:    "SETBCR",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     ppc64.ASETBCR,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "Equal",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "NotEqual",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "LessThan",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "FLessThan",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "LessEqual",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "FLessEqual",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "GreaterThan",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "FGreaterThan",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "GreaterEqual",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:   "FGreaterEqual",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:      "LoweredGetClosurePtr",
+		argLen:    0,
+		zeroWidth: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 2048}, // R11
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerSP",
+		argLen:            1,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerPC",
+		argLen:            0,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredNilCheck",
+		argLen:         2,
+		clobberFlags:   true,
+		nilCheck:       true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			clobbers: 2147483648, // R31
+		},
+	},
+	{
+		name:         "LoweredRound32F",
+		argLen:       1,
+		resultInArg0: true,
+		zeroWidth:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:         "LoweredRound64F",
+		argLen:       1,
+		resultInArg0: true,
+		zeroWidth:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+			outputs: []outputInfo{
+				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+			},
+		},
+	},
+	{
+		name:         "CALLstatic",
+		auxType:      auxCallOff,
+		argLen:       -1,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
+		},
+	},
+	{
+		name:         "CALLtail",
+		auxType:      auxCallOff,
+		argLen:       -1,
+		clobberFlags: true,
+		call:         true,
+		tailCall:     true,
+		reg: regInfo{
+			clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
+		},
+	},
+	{
+		name:         "CALLclosure",
+		auxType:      auxCallOff,
+		argLen:       -1,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4096}, // R12
+				{1, 2048}, // R11
+			},
+			clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
+		},
+	},
+	{
+		name:         "CALLinter",
+		auxType:      auxCallOff,
+		argLen:       -1,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4096}, // R12
+			},
+			clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
+		},
+	},
+	{
+		name:           "LoweredZero",
+		auxType:        auxInt64,
+		argLen:         2,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		unsafePoint:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1048576}, // R20
+			},
+			clobbers: 1048576, // R20
+		},
+	},
+	{
+		name:           "LoweredZeroShort",
+		auxType:        auxInt64,
+		argLen:         2,
+		faultOnNilArg0: true,
+		unsafePoint:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredQuadZeroShort",
+		auxType:        auxInt64,
+		argLen:         2,
+		faultOnNilArg0: true,
+		unsafePoint:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredQuadZero",
+		auxType:        auxInt64,
+		argLen:         2,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		unsafePoint:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1048576}, // R20
+			},
+			clobbers: 1048576, // R20
+		},
+	},
+	{
+		name:           "LoweredMove",
+		auxType:        auxInt64,
+		argLen:         3,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
+		unsafePoint:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1048576}, // R20
+				{1, 2097152}, // R21
+			},
+			clobbers: 3145728, // R20 R21
+		},
+	},
+	{
+		name:           "LoweredMoveShort",
+		auxType:        auxInt64,
+		argLen:         3,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
+		unsafePoint:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredQuadMove",
+		auxType:        auxInt64,
+		argLen:         3,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
+		unsafePoint:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1048576}, // R20
+				{1, 2097152}, // R21
+			},
+			clobbers: 3145728, // R20 R21
+		},
+	},
+	{
+		name:           "LoweredQuadMoveShort",
+		auxType:        auxInt64,
+		argLen:         3,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
+		unsafePoint:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStore8",
+		auxType:        auxInt64,
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStore32",
+		auxType:        auxInt64,
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStore64",
+		auxType:        auxInt64,
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicLoad8",
+		auxType:        auxInt64,
+		argLen:         2,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicLoad32",
+		auxType:        auxInt64,
+		argLen:         2,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicLoad64",
+		auxType:        auxInt64,
+		argLen:         2,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicLoadPtr",
+		auxType:        auxInt64,
+		argLen:         2,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicAdd32",
+		argLen:          3,
+		resultNotInArgs: true,
+		clobberFlags:    true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicAdd64",
+		argLen:          3,
+		resultNotInArgs: true,
+		clobberFlags:    true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicExchange8",
+		argLen:          3,
+		resultNotInArgs: true,
+		clobberFlags:    true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicExchange32",
+		argLen:          3,
+		resultNotInArgs: true,
+		clobberFlags:    true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicExchange64",
+		argLen:          3,
+		resultNotInArgs: true,
+		clobberFlags:    true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicCas64",
+		auxType:         auxInt64,
+		argLen:          4,
+		resultNotInArgs: true,
+		clobberFlags:    true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicCas32",
+		auxType:         auxInt64,
+		argLen:          4,
+		resultNotInArgs: true,
+		clobberFlags:    true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+			outputs: []outputInfo{
+				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicAnd8",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		asm:            ppc64.AAND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicAnd32",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		asm:            ppc64.AAND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicOr8",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		asm:            ppc64.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicOr32",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		asm:            ppc64.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+			},
+		},
+	},
+	{
+		name:         "LoweredWB",
+		auxType:      auxInt64,
+		argLen:       1,
+		clobberFlags: true,
+		reg: regInfo{
+			clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
+			outputs: []outputInfo{
+				{0, 536870912}, // R29
+			},
+		},
+	},
+	{
+		name:           "LoweredPubBarrier",
+		argLen:         1,
+		hasSideEffects: true,
+		asm:            ppc64.ALWSYNC,
+		reg:            regInfo{},
+	},
+	{
+		name:    "LoweredPanicBoundsA",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 32}, // R5
+				{1, 64}, // R6
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicBoundsB",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 16}, // R4
+				{1, 32}, // R5
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicBoundsC",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 8},  // R3
+				{1, 16}, // R4
+			},
+		},
+	},
+	{
+		name:   "InvertFlags",
+		argLen: 1,
+		reg:    regInfo{},
+	},
+	{
+		name:   "FlagEQ",
+		argLen: 0,
+		reg:    regInfo{},
+	},
+	{
+		name:   "FlagLT",
+		argLen: 0,
+		reg:    regInfo{},
+	},
+	{
+		name:   "FlagGT",
+		argLen: 0,
+		reg:    regInfo{},
+	},
+
+	{
+		name:        "ADD",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AADD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "ADDI",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.AADDI,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "ADDIW",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.AADDIW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "NEG",
+		argLen: 1,
+		asm:    riscv.ANEG,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "NEGW",
+		argLen: 1,
+		asm:    riscv.ANEGW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SUB",
+		argLen: 2,
+		asm:    riscv.ASUB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SUBW",
+		argLen: 2,
+		asm:    riscv.ASUBW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "MUL",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AMUL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "MULW",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AMULW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "MULH",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AMULH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "MULHU",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AMULHU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:            "LoweredMuluhilo",
+		argLen:          2,
+		resultNotInArgs: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:            "LoweredMuluover",
+		argLen:          2,
+		resultNotInArgs: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "DIV",
+		argLen: 2,
+		asm:    riscv.ADIV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "DIVU",
+		argLen: 2,
+		asm:    riscv.ADIVU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "DIVW",
+		argLen: 2,
+		asm:    riscv.ADIVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "DIVUW",
+		argLen: 2,
+		asm:    riscv.ADIVUW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "REM",
+		argLen: 2,
+		asm:    riscv.AREM,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "REMU",
+		argLen: 2,
+		asm:    riscv.AREMU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "REMW",
+		argLen: 2,
+		asm:    riscv.AREMW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "REMUW",
+		argLen: 2,
+		asm:    riscv.AREMUW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:              "MOVaddr",
+		auxType:           auxSymOff,
+		argLen:            1,
+		rematerializeable: true,
+		symEffect:         SymAddr,
+		asm:               riscv.AMOV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:              "MOVDconst",
+		auxType:           auxInt64,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               riscv.AMOV,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:           "MOVBload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            riscv.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:           "MOVHload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            riscv.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:           "MOVWload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            riscv.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:           "MOVDload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            riscv.AMOV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:           "MOVBUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            riscv.AMOVBU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:           "MOVHUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            riscv.AMOVHU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:           "MOVWUload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            riscv.AMOVWU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:           "MOVBstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            riscv.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+		},
+	},
+	{
+		name:           "MOVHstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            riscv.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+		},
+	},
+	{
+		name:           "MOVWstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            riscv.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+		},
+	},
+	{
+		name:           "MOVDstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            riscv.AMOV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+		},
+	},
+	{
+		name:           "MOVBstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            riscv.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+		},
+	},
+	{
+		name:           "MOVHstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            riscv.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+		},
+	},
+	{
+		name:           "MOVWstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            riscv.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+		},
+	},
+	{
+		name:           "MOVDstorezero",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            riscv.AMOV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+		},
+	},
+	{
+		name:   "MOVBreg",
+		argLen: 1,
+		asm:    riscv.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "MOVHreg",
+		argLen: 1,
+		asm:    riscv.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "MOVWreg",
+		argLen: 1,
+		asm:    riscv.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "MOVDreg",
+		argLen: 1,
+		asm:    riscv.AMOV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "MOVBUreg",
+		argLen: 1,
+		asm:    riscv.AMOVBU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "MOVHUreg",
+		argLen: 1,
+		asm:    riscv.AMOVHU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "MOVWUreg",
+		argLen: 1,
+		asm:    riscv.AMOVWU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:         "MOVDnop",
+		argLen:       1,
+		resultInArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SLL",
+		argLen: 2,
+		asm:    riscv.ASLL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SLLW",
+		argLen: 2,
+		asm:    riscv.ASLLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SRA",
+		argLen: 2,
+		asm:    riscv.ASRA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SRAW",
+		argLen: 2,
+		asm:    riscv.ASRAW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SRL",
+		argLen: 2,
+		asm:    riscv.ASRL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SRLW",
+		argLen: 2,
+		asm:    riscv.ASRLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "SLLI",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.ASLLI,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "SLLIW",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.ASLLIW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "SRAI",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.ASRAI,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "SRAIW",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.ASRAIW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "SRLI",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.ASRLI,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "SRLIW",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.ASRLIW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SH1ADD",
+		argLen: 2,
+		asm:    riscv.ASH1ADD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SH2ADD",
+		argLen: 2,
+		asm:    riscv.ASH2ADD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SH3ADD",
+		argLen: 2,
+		asm:    riscv.ASH3ADD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "AND",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AAND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "ANDN",
+		argLen: 2,
+		asm:    riscv.AANDN,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "ANDI",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.AANDI,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "CLZ",
+		argLen: 1,
+		asm:    riscv.ACLZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "CLZW",
+		argLen: 1,
+		asm:    riscv.ACLZW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "CPOP",
+		argLen: 1,
+		asm:    riscv.ACPOP,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "CPOPW",
+		argLen: 1,
+		asm:    riscv.ACPOPW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "CTZ",
+		argLen: 1,
+		asm:    riscv.ACTZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "CTZW",
+		argLen: 1,
+		asm:    riscv.ACTZW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "NOT",
+		argLen: 1,
+		asm:    riscv.ANOT,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "OR",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "ORN",
+		argLen: 2,
+		asm:    riscv.AORN,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "ORI",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.AORI,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "REV8",
+		argLen: 1,
+		asm:    riscv.AREV8,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "ROL",
+		argLen: 2,
+		asm:    riscv.AROL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "ROLW",
+		argLen: 2,
+		asm:    riscv.AROLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "ROR",
+		argLen: 2,
+		asm:    riscv.AROR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "RORI",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.ARORI,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "RORIW",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.ARORIW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "RORW",
+		argLen: 2,
+		asm:    riscv.ARORW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "XNOR",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AXNOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "XOR",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AXOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "XORI",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.AXORI,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "MIN",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AMIN,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "MAX",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AMAX,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "MINU",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AMINU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "MAXU",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AMAXU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SEQZ",
+		argLen: 1,
+		asm:    riscv.ASEQZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SNEZ",
+		argLen: 1,
+		asm:    riscv.ASNEZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SLT",
+		argLen: 2,
+		asm:    riscv.ASLT,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "SLTI",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.ASLTI,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "SLTU",
+		argLen: 2,
+		asm:    riscv.ASLTU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:    "SLTIU",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     riscv.ASLTIU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:         "LoweredRound32F",
+		argLen:       1,
+		resultInArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:         "LoweredRound64F",
+		argLen:       1,
+		resultInArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:    "CALLstatic",
+		auxType: auxCallOff,
+		argLen:  -1,
+		call:    true,
+		reg: regInfo{
+			clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+		},
+	},
+	{
+		name:     "CALLtail",
+		auxType:  auxCallOff,
+		argLen:   -1,
+		call:     true,
+		tailCall: true,
+		reg: regInfo{
+			clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+		},
+	},
+	{
+		name:    "CALLclosure",
+		auxType: auxCallOff,
+		argLen:  -1,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 33554432},   // X26
+				{0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+		},
+	},
+	{
+		name:    "CALLinter",
+		auxType: auxCallOff,
+		argLen:  -1,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+		},
+	},
+	{
+		name:           "DUFFZERO",
+		auxType:        auxInt64,
+		argLen:         2,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 16777216}, // X25
+			},
+			clobbers: 16777216, // X25
+		},
+	},
+	{
+		name:           "DUFFCOPY",
+		auxType:        auxInt64,
+		argLen:         3,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 16777216}, // X25
+				{1, 8388608},  // X24
+			},
+			clobbers: 25165824, // X24 X25
+		},
+	},
+	{
+		name:           "LoweredZero",
+		auxType:        auxInt64,
+		argLen:         3,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 16},         // X5
+				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			clobbers: 16, // X5
+		},
+	},
+	{
+		name:           "LoweredMove",
+		auxType:        auxInt64,
+		argLen:         4,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 16},         // X5
+				{1, 32},         // X6
+				{2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			clobbers: 112, // X5 X6 X7
+		},
+	},
+	{
+		name:           "LoweredAtomicLoad8",
+		argLen:         2,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicLoad32",
+		argLen:         2,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicLoad64",
+		argLen:         2,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStore8",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStore32",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicStore64",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicExchange32",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicExchange64",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicAdd32",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicAdd64",
+		argLen:          3,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicCas32",
+		argLen:          4,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+				{2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:            "LoweredAtomicCas64",
+		argLen:          4,
+		resultNotInArgs: true,
+		faultOnNilArg0:  true,
+		hasSideEffects:  true,
+		unsafePoint:     true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+				{2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicAnd32",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		asm:            riscv.AAMOANDW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicOr32",
+		argLen:         3,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		asm:            riscv.AAMOORW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+			},
+		},
+	},
+	{
+		name:           "LoweredNilCheck",
+		argLen:         2,
+		nilCheck:       true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "LoweredGetClosurePtr",
+		argLen: 0,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 33554432}, // X26
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerSP",
+		argLen:            1,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerPC",
+		argLen:            0,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:         "LoweredWB",
+		auxType:      auxInt64,
+		argLen:       1,
+		clobberFlags: true,
+		reg: regInfo{
+			clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			outputs: []outputInfo{
+				{0, 8388608}, // X24
+			},
+		},
+	},
+	{
+		name:           "LoweredPubBarrier",
+		argLen:         1,
+		hasSideEffects: true,
+		asm:            riscv.AFENCE,
+		reg:            regInfo{},
+	},
+	{
+		name:    "LoweredPanicBoundsA",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 64},        // X7
+				{1, 134217728}, // X28
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicBoundsB",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 32}, // X6
+				{1, 64}, // X7
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicBoundsC",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 16}, // X5
+				{1, 32}, // X6
+			},
+		},
+	},
+	{
+		name:        "FADDS",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AFADDS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FSUBS",
+		argLen: 2,
+		asm:    riscv.AFSUBS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "FMULS",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AFMULS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FDIVS",
+		argLen: 2,
+		asm:    riscv.AFDIVS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "FMADDS",
+		argLen:      3,
+		commutative: true,
+		asm:         riscv.AFMADDS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "FMSUBS",
+		argLen:      3,
+		commutative: true,
+		asm:         riscv.AFMSUBS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "FNMADDS",
+		argLen:      3,
+		commutative: true,
+		asm:         riscv.AFNMADDS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "FNMSUBS",
+		argLen:      3,
+		commutative: true,
+		asm:         riscv.AFNMSUBS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FSQRTS",
+		argLen: 1,
+		asm:    riscv.AFSQRTS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FNEGS",
+		argLen: 1,
+		asm:    riscv.AFNEGS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FMVSX",
+		argLen: 1,
+		asm:    riscv.AFMVSX,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FCVTSW",
+		argLen: 1,
+		asm:    riscv.AFCVTSW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FCVTSL",
+		argLen: 1,
+		asm:    riscv.AFCVTSL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FCVTWS",
+		argLen: 1,
+		asm:    riscv.AFCVTWS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "FCVTLS",
+		argLen: 1,
+		asm:    riscv.AFCVTLS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:           "FMOVWload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            riscv.AMOVF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:           "FMOVWstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            riscv.AMOVF,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "FEQS",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AFEQS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "FNES",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AFNES,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "FLTS",
+		argLen: 2,
+		asm:    riscv.AFLTS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "FLES",
+		argLen: 2,
+		asm:    riscv.AFLES,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:            "LoweredFMAXS",
+		argLen:          2,
+		commutative:     true,
+		resultNotInArgs: true,
+		asm:             riscv.AFMAXS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:            "LoweredFMINS",
+		argLen:          2,
+		commutative:     true,
+		resultNotInArgs: true,
+		asm:             riscv.AFMINS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "FADDD",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AFADDD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FSUBD",
+		argLen: 2,
+		asm:    riscv.AFSUBD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "FMULD",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AFMULD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FDIVD",
+		argLen: 2,
+		asm:    riscv.AFDIVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "FMADDD",
+		argLen:      3,
+		commutative: true,
+		asm:         riscv.AFMADDD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "FMSUBD",
+		argLen:      3,
+		commutative: true,
+		asm:         riscv.AFMSUBD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "FNMADDD",
+		argLen:      3,
+		commutative: true,
+		asm:         riscv.AFNMADDD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "FNMSUBD",
+		argLen:      3,
+		commutative: true,
+		asm:         riscv.AFNMSUBD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FSQRTD",
+		argLen: 1,
+		asm:    riscv.AFSQRTD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FNEGD",
+		argLen: 1,
+		asm:    riscv.AFNEGD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FABSD",
+		argLen: 1,
+		asm:    riscv.AFABSD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FSGNJD",
+		argLen: 2,
+		asm:    riscv.AFSGNJD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FMVDX",
+		argLen: 1,
+		asm:    riscv.AFMVDX,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FCVTDW",
+		argLen: 1,
+		asm:    riscv.AFCVTDW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FCVTDL",
+		argLen: 1,
+		asm:    riscv.AFCVTDL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FCVTWD",
+		argLen: 1,
+		asm:    riscv.AFCVTWD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "FCVTLD",
+		argLen: 1,
+		asm:    riscv.AFCVTLD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "FCVTDS",
+		argLen: 1,
+		asm:    riscv.AFCVTDS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "FCVTSD",
+		argLen: 1,
+		asm:    riscv.AFCVTSD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:           "FMOVDload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            riscv.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:           "FMOVDstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            riscv.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:        "FEQD",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AFEQD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:        "FNED",
+		argLen:      2,
+		commutative: true,
+		asm:         riscv.AFNED,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "FLTD",
+		argLen: 2,
+		asm:    riscv.AFLTD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:   "FLED",
+		argLen: 2,
+		asm:    riscv.AFLED,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+			},
+		},
+	},
+	{
+		name:            "LoweredFMIND",
+		argLen:          2,
+		commutative:     true,
+		resultNotInArgs: true,
+		asm:             riscv.AFMIND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:            "LoweredFMAXD",
+		argLen:          2,
+		commutative:     true,
+		resultNotInArgs: true,
+		asm:             riscv.AFMAXD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+
+	{
+		name:         "FADDS",
+		argLen:       2,
+		commutative:  true,
+		resultInArg0: true,
+		asm:          s390x.AFADDS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "FADD",
+		argLen:       2,
+		commutative:  true,
+		resultInArg0: true,
+		asm:          s390x.AFADD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "FSUBS",
+		argLen:       2,
+		resultInArg0: true,
+		asm:          s390x.AFSUBS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "FSUB",
+		argLen:       2,
+		resultInArg0: true,
+		asm:          s390x.AFSUB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "FMULS",
+		argLen:       2,
+		commutative:  true,
+		resultInArg0: true,
+		asm:          s390x.AFMULS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "FMUL",
+		argLen:       2,
+		commutative:  true,
+		resultInArg0: true,
+		asm:          s390x.AFMUL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "FDIVS",
+		argLen:       2,
+		resultInArg0: true,
+		asm:          s390x.AFDIVS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "FDIV",
+		argLen:       2,
+		resultInArg0: true,
+		asm:          s390x.AFDIV,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "FNEGS",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.AFNEGS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "FNEG",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.AFNEG,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "FMADDS",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          s390x.AFMADDS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "FMADD",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          s390x.AFMADD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "FMSUBS",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          s390x.AFMSUBS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "FMSUB",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          s390x.AFMSUB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "LPDFR",
+		argLen: 1,
+		asm:    s390x.ALPDFR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "LNDFR",
+		argLen: 1,
+		asm:    s390x.ALNDFR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "CPSDR",
+		argLen: 2,
+		asm:    s390x.ACPSDR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:    "FIDBR",
+		auxType: auxInt8,
+		argLen:  1,
+		asm:     s390x.AFIDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:           "FMOVSload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AFMOVS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:           "FMOVDload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AFMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:              "FMOVSconst",
+		auxType:           auxFloat32,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               s390x.AFMOVS,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:              "FMOVDconst",
+		auxType:           auxFloat64,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               s390x.AFMOVD,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:      "FMOVSloadidx",
+		auxType:   auxSymOff,
+		argLen:    3,
+		symEffect: SymRead,
+		asm:       s390x.AFMOVS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:      "FMOVDloadidx",
+		auxType:   auxSymOff,
+		argLen:    3,
+		symEffect: SymRead,
+		asm:       s390x.AFMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:           "FMOVSstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AFMOVS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:           "FMOVDstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AFMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:      "FMOVSstoreidx",
+		auxType:   auxSymOff,
+		argLen:    4,
+		symEffect: SymWrite,
+		asm:       s390x.AFMOVS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:      "FMOVDstoreidx",
+		auxType:   auxSymOff,
+		argLen:    4,
+		symEffect: SymWrite,
+		asm:       s390x.AFMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "ADD",
+		argLen:       2,
+		commutative:  true,
+		clobberFlags: true,
+		asm:          s390x.AADD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "ADDW",
+		argLen:       2,
+		commutative:  true,
+		clobberFlags: true,
+		asm:          s390x.AADDW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "ADDconst",
+		auxType:      auxInt32,
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.AADD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "ADDWconst",
+		auxType:      auxInt32,
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.AADDW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "ADDload",
+		auxType:        auxSymOff,
+		argLen:         3,
+		resultInArg0:   true,
+		clobberFlags:   true,
+		faultOnNilArg1: true,
+		symEffect:      SymRead,
+		asm:            s390x.AADD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "ADDWload",
+		auxType:        auxSymOff,
+		argLen:         3,
+		resultInArg0:   true,
+		clobberFlags:   true,
+		faultOnNilArg1: true,
+		symEffect:      SymRead,
+		asm:            s390x.AADDW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "SUB",
+		argLen:       2,
+		clobberFlags: true,
+		asm:          s390x.ASUB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "SUBW",
+		argLen:       2,
+		clobberFlags: true,
+		asm:          s390x.ASUBW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "SUBconst",
+		auxType:      auxInt32,
+		argLen:       1,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.ASUB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "SUBWconst",
+		auxType:      auxInt32,
+		argLen:       1,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.ASUBW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "SUBload",
+		auxType:        auxSymOff,
+		argLen:         3,
+		resultInArg0:   true,
+		clobberFlags:   true,
+		faultOnNilArg1: true,
+		symEffect:      SymRead,
+		asm:            s390x.ASUB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "SUBWload",
+		auxType:        auxSymOff,
+		argLen:         3,
+		resultInArg0:   true,
+		clobberFlags:   true,
+		faultOnNilArg1: true,
+		symEffect:      SymRead,
+		asm:            s390x.ASUBW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "MULLD",
+		argLen:       2,
+		commutative:  true,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AMULLD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "MULLW",
+		argLen:       2,
+		commutative:  true,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AMULLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "MULLDconst",
+		auxType:      auxInt32,
+		argLen:       1,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AMULLD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "MULLWconst",
+		auxType:      auxInt32,
+		argLen:       1,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AMULLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MULLDload",
+		auxType:        auxSymOff,
+		argLen:         3,
+		resultInArg0:   true,
+		clobberFlags:   true,
+		faultOnNilArg1: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMULLD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MULLWload",
+		auxType:        auxSymOff,
+		argLen:         3,
+		resultInArg0:   true,
+		clobberFlags:   true,
+		faultOnNilArg1: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMULLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "MULHD",
+		argLen:       2,
+		commutative:  true,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AMULHD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2048, // R11
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+		},
+	},
+	{
+		name:         "MULHDU",
+		argLen:       2,
+		commutative:  true,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AMULHDU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2048, // R11
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+		},
+	},
+	{
+		name:         "DIVD",
+		argLen:       2,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.ADIVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2048, // R11
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+		},
+	},
+	{
+		name:         "DIVW",
+		argLen:       2,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.ADIVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2048, // R11
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+		},
+	},
+	{
+		name:         "DIVDU",
+		argLen:       2,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.ADIVDU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2048, // R11
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+		},
+	},
+	{
+		name:         "DIVWU",
+		argLen:       2,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.ADIVWU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2048, // R11
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+		},
+	},
+	{
+		name:         "MODD",
+		argLen:       2,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AMODD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2048, // R11
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+		},
+	},
+	{
+		name:         "MODW",
+		argLen:       2,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AMODW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2048, // R11
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+		},
+	},
+	{
+		name:         "MODDU",
+		argLen:       2,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AMODDU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2048, // R11
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+		},
+	},
+	{
+		name:         "MODWU",
+		argLen:       2,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AMODWU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+			clobbers: 2048, // R11
+			outputs: []outputInfo{
+				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+			},
+		},
+	},
+	{
+		name:         "AND",
+		argLen:       2,
+		commutative:  true,
+		clobberFlags: true,
+		asm:          s390x.AAND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "ANDW",
+		argLen:       2,
+		commutative:  true,
+		clobberFlags: true,
+		asm:          s390x.AANDW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "ANDconst",
+		auxType:      auxInt64,
+		argLen:       1,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AAND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "ANDWconst",
+		auxType:      auxInt32,
+		argLen:       1,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AANDW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "ANDload",
+		auxType:        auxSymOff,
+		argLen:         3,
+		resultInArg0:   true,
+		clobberFlags:   true,
+		faultOnNilArg1: true,
+		symEffect:      SymRead,
+		asm:            s390x.AAND,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "ANDWload",
+		auxType:        auxSymOff,
+		argLen:         3,
+		resultInArg0:   true,
+		clobberFlags:   true,
+		faultOnNilArg1: true,
+		symEffect:      SymRead,
+		asm:            s390x.AANDW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "OR",
+		argLen:       2,
+		commutative:  true,
+		clobberFlags: true,
+		asm:          s390x.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "ORW",
+		argLen:       2,
+		commutative:  true,
+		clobberFlags: true,
+		asm:          s390x.AORW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "ORconst",
+		auxType:      auxInt64,
+		argLen:       1,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "ORWconst",
+		auxType:      auxInt32,
+		argLen:       1,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AORW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "ORload",
+		auxType:        auxSymOff,
+		argLen:         3,
+		resultInArg0:   true,
+		clobberFlags:   true,
+		faultOnNilArg1: true,
+		symEffect:      SymRead,
+		asm:            s390x.AOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "ORWload",
+		auxType:        auxSymOff,
+		argLen:         3,
+		resultInArg0:   true,
+		clobberFlags:   true,
+		faultOnNilArg1: true,
+		symEffect:      SymRead,
+		asm:            s390x.AORW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "XOR",
+		argLen:       2,
+		commutative:  true,
+		clobberFlags: true,
+		asm:          s390x.AXOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "XORW",
+		argLen:       2,
+		commutative:  true,
+		clobberFlags: true,
+		asm:          s390x.AXORW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "XORconst",
+		auxType:      auxInt64,
+		argLen:       1,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AXOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "XORWconst",
+		auxType:      auxInt32,
+		argLen:       1,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.AXORW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "XORload",
+		auxType:        auxSymOff,
+		argLen:         3,
+		resultInArg0:   true,
+		clobberFlags:   true,
+		faultOnNilArg1: true,
+		symEffect:      SymRead,
+		asm:            s390x.AXOR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "XORWload",
+		auxType:        auxSymOff,
+		argLen:         3,
+		resultInArg0:   true,
+		clobberFlags:   true,
+		faultOnNilArg1: true,
+		symEffect:      SymRead,
+		asm:            s390x.AXORW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:        "ADDC",
+		argLen:      2,
+		commutative: true,
+		asm:         s390x.AADDC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:    "ADDCconst",
+		auxType: auxInt16,
+		argLen:  1,
+		asm:     s390x.AADDC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "ADDE",
+		argLen:       3,
+		commutative:  true,
+		resultInArg0: true,
+		asm:          s390x.AADDE,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "SUBC",
+		argLen: 2,
+		asm:    s390x.ASUBC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "SUBE",
+		argLen:       3,
+		resultInArg0: true,
+		asm:          s390x.ASUBE,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "CMP",
+		argLen: 2,
+		asm:    s390x.ACMP,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:   "CMPW",
+		argLen: 2,
+		asm:    s390x.ACMPW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:   "CMPU",
+		argLen: 2,
+		asm:    s390x.ACMPU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:   "CMPWU",
+		argLen: 2,
+		asm:    s390x.ACMPWU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:    "CMPconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     s390x.ACMP,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:    "CMPWconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     s390x.ACMPW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:    "CMPUconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     s390x.ACMPU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:    "CMPWUconst",
+		auxType: auxInt32,
+		argLen:  1,
+		asm:     s390x.ACMPWU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:   "FCMPS",
+		argLen: 2,
+		asm:    s390x.ACEBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "FCMP",
+		argLen: 2,
+		asm:    s390x.AFCMPU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "LTDBR",
+		argLen: 1,
+		asm:    s390x.ALTDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "LTEBR",
+		argLen: 1,
+		asm:    s390x.ALTEBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "SLD",
+		argLen: 2,
+		asm:    s390x.ASLD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "SLW",
+		argLen: 2,
+		asm:    s390x.ASLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:    "SLDconst",
+		auxType: auxUInt8,
+		argLen:  1,
+		asm:     s390x.ASLD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:    "SLWconst",
+		auxType: auxUInt8,
+		argLen:  1,
+		asm:     s390x.ASLW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "SRD",
+		argLen: 2,
+		asm:    s390x.ASRD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "SRW",
+		argLen: 2,
+		asm:    s390x.ASRW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:    "SRDconst",
+		auxType: auxUInt8,
+		argLen:  1,
+		asm:     s390x.ASRD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:    "SRWconst",
+		auxType: auxUInt8,
+		argLen:  1,
+		asm:     s390x.ASRW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "SRAD",
+		argLen:       2,
+		clobberFlags: true,
+		asm:          s390x.ASRAD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "SRAW",
+		argLen:       2,
+		clobberFlags: true,
+		asm:          s390x.ASRAW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "SRADconst",
+		auxType:      auxUInt8,
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ASRAD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "SRAWconst",
+		auxType:      auxUInt8,
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ASRAW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "RLLG",
+		argLen: 2,
+		asm:    s390x.ARLLG,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "RLL",
+		argLen: 2,
+		asm:    s390x.ARLL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:    "RLLconst",
+		auxType: auxUInt8,
+		argLen:  1,
+		asm:     s390x.ARLL,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "RXSBG",
+		auxType:      auxS390XRotateParams,
+		argLen:       2,
+		resultInArg0: true,
+		clobberFlags: true,
+		asm:          s390x.ARXSBG,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "RISBGZ",
+		auxType:      auxS390XRotateParams,
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ARISBGZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "NEG",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ANEG,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "NEGW",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ANEGW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "NOT",
+		argLen:       1,
+		resultInArg0: true,
+		clobberFlags: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "NOTW",
+		argLen:       1,
+		resultInArg0: true,
+		clobberFlags: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "FSQRT",
+		argLen: 1,
+		asm:    s390x.AFSQRT,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "FSQRTS",
+		argLen: 1,
+		asm:    s390x.AFSQRTS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "LOCGR",
+		auxType:      auxS390XCCMask,
+		argLen:       3,
+		resultInArg0: true,
+		asm:          s390x.ALOCGR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "MOVBreg",
+		argLen: 1,
+		asm:    s390x.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "MOVBZreg",
+		argLen: 1,
+		asm:    s390x.AMOVBZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "MOVHreg",
+		argLen: 1,
+		asm:    s390x.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "MOVHZreg",
+		argLen: 1,
+		asm:    s390x.AMOVHZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "MOVWreg",
+		argLen: 1,
+		asm:    s390x.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "MOVWZreg",
+		argLen: 1,
+		asm:    s390x.AMOVWZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:              "MOVDconst",
+		auxType:           auxInt64,
+		argLen:            0,
+		rematerializeable: true,
+		asm:               s390x.AMOVD,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "LDGR",
+		argLen: 1,
+		asm:    s390x.ALDGR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "LGDR",
+		argLen: 1,
+		asm:    s390x.ALGDR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "CFDBRA",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACFDBRA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "CGDBRA",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACGDBRA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "CFEBRA",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACFEBRA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "CGEBRA",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACGEBRA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "CEFBRA",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACEFBRA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "CDFBRA",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACDFBRA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "CEGBRA",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACEGBRA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "CDGBRA",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACDGBRA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "CLFEBR",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACLFEBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "CLFDBR",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACLFDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "CLGEBR",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACLGEBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "CLGDBR",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACLGDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "CELFBR",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACELFBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "CDLFBR",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACDLFBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "CELGBR",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACELGBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "CDLGBR",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.ACDLGBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "LEDBR",
+		argLen: 1,
+		asm:    s390x.ALEDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "LDEBR",
+		argLen: 1,
+		asm:    s390x.ALDEBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:              "MOVDaddr",
+		auxType:           auxSymOff,
+		argLen:            1,
+		rematerializeable: true,
+		symEffect:         SymAddr,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295000064}, // SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:      "MOVDaddridx",
+		auxType:   auxSymOff,
+		argLen:    2,
+		symEffect: SymAddr,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295000064}, // SP SB
+				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVBZload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMOVBZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVBload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVHZload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMOVHZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVHload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVWZload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMOVWZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVWload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVDload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "MOVWBR",
+		argLen: 1,
+		asm:    s390x.AMOVWBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "MOVDBR",
+		argLen: 1,
+		asm:    s390x.AMOVDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVHBRload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMOVHBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVWBRload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMOVWBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVDBRload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMOVDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVBstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "MOVHstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "MOVWstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "MOVDstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "MOVHBRstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVHBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "MOVWBRstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVWBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "MOVDBRstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "MVC",
+		auxType:        auxSymValAndOff,
+		argLen:         3,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
+		symEffect:      SymNone,
+		asm:            s390x.AMVC,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:        "MOVBZloadidx",
+		auxType:     auxSymOff,
+		argLen:      3,
+		commutative: true,
+		symEffect:   SymRead,
+		asm:         s390x.AMOVBZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:        "MOVBloadidx",
+		auxType:     auxSymOff,
+		argLen:      3,
+		commutative: true,
+		symEffect:   SymRead,
+		asm:         s390x.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:        "MOVHZloadidx",
+		auxType:     auxSymOff,
+		argLen:      3,
+		commutative: true,
+		symEffect:   SymRead,
+		asm:         s390x.AMOVHZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:        "MOVHloadidx",
+		auxType:     auxSymOff,
+		argLen:      3,
+		commutative: true,
+		symEffect:   SymRead,
+		asm:         s390x.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:        "MOVWZloadidx",
+		auxType:     auxSymOff,
+		argLen:      3,
+		commutative: true,
+		symEffect:   SymRead,
+		asm:         s390x.AMOVWZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:        "MOVWloadidx",
+		auxType:     auxSymOff,
+		argLen:      3,
+		commutative: true,
+		symEffect:   SymRead,
+		asm:         s390x.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:        "MOVDloadidx",
+		auxType:     auxSymOff,
+		argLen:      3,
+		commutative: true,
+		symEffect:   SymRead,
+		asm:         s390x.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:        "MOVHBRloadidx",
+		auxType:     auxSymOff,
+		argLen:      3,
+		commutative: true,
+		symEffect:   SymRead,
+		asm:         s390x.AMOVHBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:        "MOVWBRloadidx",
+		auxType:     auxSymOff,
+		argLen:      3,
+		commutative: true,
+		symEffect:   SymRead,
+		asm:         s390x.AMOVWBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:        "MOVDBRloadidx",
+		auxType:     auxSymOff,
+		argLen:      3,
+		commutative: true,
+		symEffect:   SymRead,
+		asm:         s390x.AMOVDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:        "MOVBstoreidx",
+		auxType:     auxSymOff,
+		argLen:      4,
+		commutative: true,
+		symEffect:   SymWrite,
+		asm:         s390x.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:        "MOVHstoreidx",
+		auxType:     auxSymOff,
+		argLen:      4,
+		commutative: true,
+		symEffect:   SymWrite,
+		asm:         s390x.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:        "MOVWstoreidx",
+		auxType:     auxSymOff,
+		argLen:      4,
+		commutative: true,
+		symEffect:   SymWrite,
+		asm:         s390x.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:        "MOVDstoreidx",
+		auxType:     auxSymOff,
+		argLen:      4,
+		commutative: true,
+		symEffect:   SymWrite,
+		asm:         s390x.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:        "MOVHBRstoreidx",
+		auxType:     auxSymOff,
+		argLen:      4,
+		commutative: true,
+		symEffect:   SymWrite,
+		asm:         s390x.AMOVHBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:        "MOVWBRstoreidx",
+		auxType:     auxSymOff,
+		argLen:      4,
+		commutative: true,
+		symEffect:   SymWrite,
+		asm:         s390x.AMOVWBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:        "MOVDBRstoreidx",
+		auxType:     auxSymOff,
+		argLen:      4,
+		commutative: true,
+		symEffect:   SymWrite,
+		asm:         s390x.AMOVDBR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "MOVBstoreconst",
+		auxType:        auxSymValAndOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+		},
+	},
+	{
+		name:           "MOVHstoreconst",
+		auxType:        auxSymValAndOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVH,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+		},
+	},
+	{
+		name:           "MOVWstoreconst",
+		auxType:        auxSymValAndOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+		},
+	},
+	{
+		name:           "MOVDstoreconst",
+		auxType:        auxSymValAndOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+		},
+	},
+	{
+		name:           "CLEAR",
+		auxType:        auxSymValAndOff,
+		argLen:         2,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.ACLEAR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:         "CALLstatic",
+		auxType:      auxCallOff,
+		argLen:       1,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+		},
+	},
+	{
+		name:         "CALLtail",
+		auxType:      auxCallOff,
+		argLen:       1,
+		clobberFlags: true,
+		call:         true,
+		tailCall:     true,
+		reg: regInfo{
+			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+		},
+	},
+	{
+		name:         "CALLclosure",
+		auxType:      auxCallOff,
+		argLen:       3,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 4096},  // R12
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+		},
+	},
+	{
+		name:         "CALLinter",
+		auxType:      auxCallOff,
+		argLen:       2,
+		clobberFlags: true,
+		call:         true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+		},
+	},
+	{
+		name:   "InvertFlags",
+		argLen: 1,
+		reg:    regInfo{},
+	},
+	{
+		name:   "LoweredGetG",
+		argLen: 1,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:      "LoweredGetClosurePtr",
+		argLen:    0,
+		zeroWidth: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 4096}, // R12
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerSP",
+		argLen:            1,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerPC",
+		argLen:            0,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "LoweredNilCheck",
+		argLen:         2,
+		clobberFlags:   true,
+		nilCheck:       true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:         "LoweredRound32F",
+		argLen:       1,
+		resultInArg0: true,
+		zeroWidth:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "LoweredRound64F",
+		argLen:       1,
+		resultInArg0: true,
+		zeroWidth:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:         "LoweredWB",
+		auxType:      auxInt64,
+		argLen:       1,
+		clobberFlags: true,
+		reg: regInfo{
+			clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			outputs: []outputInfo{
+				{0, 512}, // R9
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicBoundsA",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4}, // R2
+				{1, 8}, // R3
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicBoundsB",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2}, // R1
+				{1, 4}, // R2
+			},
+		},
+	},
+	{
+		name:    "LoweredPanicBoundsC",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1}, // R0
+				{1, 2}, // R1
+			},
+		},
+	},
+	{
+		name:   "FlagEQ",
+		argLen: 0,
+		reg:    regInfo{},
+	},
+	{
+		name:   "FlagLT",
+		argLen: 0,
+		reg:    regInfo{},
+	},
+	{
+		name:   "FlagGT",
+		argLen: 0,
+		reg:    regInfo{},
+	},
+	{
+		name:   "FlagOV",
+		argLen: 0,
+		reg:    regInfo{},
+	},
+	{
+		name:   "SYNC",
+		argLen: 1,
+		asm:    s390x.ASYNC,
+		reg:    regInfo{},
+	},
+	{
+		name:           "MOVBZatomicload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMOVBZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVWZatomicload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMOVWZ,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVDatomicload",
+		auxType:        auxSymOff,
+		argLen:         2,
+		faultOnNilArg0: true,
+		symEffect:      SymRead,
+		asm:            s390x.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "MOVBatomicstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVB,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "MOVWatomicstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVW,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "MOVDatomicstore",
+		auxType:        auxSymOff,
+		argLen:         3,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		symEffect:      SymWrite,
+		asm:            s390x.AMOVD,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "LAA",
+		auxType:        auxSymOff,
+		argLen:         3,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		symEffect:      SymRdWr,
+		asm:            s390x.ALAA,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "LAAG",
+		auxType:        auxSymOff,
+		argLen:         3,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		symEffect:      SymRdWr,
+		asm:            s390x.ALAAG,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "AddTupleFirst32",
+		argLen: 2,
+		reg:    regInfo{},
+	},
+	{
+		name:   "AddTupleFirst64",
+		argLen: 2,
+		reg:    regInfo{},
+	},
+	{
+		name:           "LAN",
+		argLen:         3,
+		clobberFlags:   true,
+		hasSideEffects: true,
+		asm:            s390x.ALAN,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "LANfloor",
+		argLen:         3,
+		clobberFlags:   true,
+		hasSideEffects: true,
+		asm:            s390x.ALAN,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2},     // R1
+				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			clobbers: 2, // R1
+		},
+	},
+	{
+		name:           "LAO",
+		argLen:         3,
+		clobberFlags:   true,
+		hasSideEffects: true,
+		asm:            s390x.ALAO,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "LAOfloor",
+		argLen:         3,
+		clobberFlags:   true,
+		hasSideEffects: true,
+		asm:            s390x.ALAO,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2},     // R1
+				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			clobbers: 2, // R1
+		},
+	},
+	{
+		name:           "LoweredAtomicCas32",
+		auxType:        auxSymOff,
+		argLen:         4,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		symEffect:      SymRdWr,
+		asm:            s390x.ACS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1},     // R0
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			clobbers: 1, // R0
+			outputs: []outputInfo{
+				{1, 0},
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicCas64",
+		auxType:        auxSymOff,
+		argLen:         4,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		symEffect:      SymRdWr,
+		asm:            s390x.ACSG,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 1},     // R0
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			clobbers: 1, // R0
+			outputs: []outputInfo{
+				{1, 0},
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicExchange32",
+		auxType:        auxSymOff,
+		argLen:         3,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		symEffect:      SymRdWr,
+		asm:            s390x.ACS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{1, 0},
+				{0, 1}, // R0
+			},
+		},
+	},
+	{
+		name:           "LoweredAtomicExchange64",
+		auxType:        auxSymOff,
+		argLen:         3,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		hasSideEffects: true,
+		symEffect:      SymRdWr,
+		asm:            s390x.ACSG,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			outputs: []outputInfo{
+				{1, 0},
+				{0, 1}, // R0
+			},
+		},
+	},
+	{
+		name:         "FLOGR",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.AFLOGR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			clobbers: 2, // R1
+			outputs: []outputInfo{
+				{0, 1}, // R0
+			},
+		},
+	},
+	{
+		name:         "POPCNT",
+		argLen:       1,
+		clobberFlags: true,
+		asm:          s390x.APOPCNT,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+		},
+	},
+	{
+		name:   "MLGR",
+		argLen: 2,
+		asm:    s390x.AMLGR,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 8},     // R3
+				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+			},
+			outputs: []outputInfo{
+				{0, 4}, // R2
+				{1, 8}, // R3
+			},
+		},
+	},
+	{
+		name:   "SumBytes2",
+		argLen: 1,
+		reg:    regInfo{},
+	},
+	{
+		name:   "SumBytes4",
+		argLen: 1,
+		reg:    regInfo{},
+	},
+	{
+		name:   "SumBytes8",
+		argLen: 1,
+		reg:    regInfo{},
+	},
+	{
+		name:           "STMG2",
+		auxType:        auxSymOff,
+		argLen:         4,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.ASTMG,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 2},     // R1
+				{2, 4},     // R2
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "STMG3",
+		auxType:        auxSymOff,
+		argLen:         5,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.ASTMG,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 2},     // R1
+				{2, 4},     // R2
+				{3, 8},     // R3
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "STMG4",
+		auxType:        auxSymOff,
+		argLen:         6,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.ASTMG,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 2},     // R1
+				{2, 4},     // R2
+				{3, 8},     // R3
+				{4, 16},    // R4
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "STM2",
+		auxType:        auxSymOff,
+		argLen:         4,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.ASTMY,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 2},     // R1
+				{2, 4},     // R2
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "STM3",
+		auxType:        auxSymOff,
+		argLen:         5,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.ASTMY,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 2},     // R1
+				{2, 4},     // R2
+				{3, 8},     // R3
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "STM4",
+		auxType:        auxSymOff,
+		argLen:         6,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		symEffect:      SymWrite,
+		asm:            s390x.ASTMY,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 2},     // R1
+				{2, 4},     // R2
+				{3, 8},     // R3
+				{4, 16},    // R4
+				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+		},
+	},
+	{
+		name:           "LoweredMove",
+		auxType:        auxInt64,
+		argLen:         4,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		faultOnNilArg1: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2},     // R1
+				{1, 4},     // R2
+				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			clobbers: 6, // R1 R2
+		},
+	},
+	{
+		name:           "LoweredZero",
+		auxType:        auxInt64,
+		argLen:         3,
+		clobberFlags:   true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 2},     // R1
+				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+			},
+			clobbers: 2, // R1
+		},
+	},
+
+	{
+		name:    "LoweredStaticCall",
+		auxType: auxCallOff,
+		argLen:  1,
+		call:    true,
+		reg: regInfo{
+			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+		},
+	},
+	{
+		name:     "LoweredTailCall",
+		auxType:  auxCallOff,
+		argLen:   1,
+		call:     true,
+		tailCall: true,
+		reg: regInfo{
+			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+		},
+	},
+	{
+		name:    "LoweredClosureCall",
+		auxType: auxCallOff,
+		argLen:  3,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+		},
+	},
+	{
+		name:    "LoweredInterCall",
+		auxType: auxCallOff,
+		argLen:  2,
+		call:    true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+		},
+	},
+	{
+		name:              "LoweredAddr",
+		auxType:           auxSymOff,
+		argLen:            1,
+		rematerializeable: true,
+		symEffect:         SymAddr,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:    "LoweredMove",
+		auxType: auxInt64,
+		argLen:  3,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+				{1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:    "LoweredZero",
+		auxType: auxInt64,
+		argLen:  2,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "LoweredGetClosurePtr",
+		argLen: 0,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerPC",
+		argLen:            0,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:              "LoweredGetCallerSP",
+		argLen:            1,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:           "LoweredNilCheck",
+		argLen:         2,
+		nilCheck:       true,
+		faultOnNilArg0: true,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:    "LoweredWB",
+		auxType: auxInt64,
+		argLen:  1,
+		reg: regInfo{
+			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "LoweredConvert",
+		argLen: 2,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "Select",
+		argLen: 3,
+		asm:    wasm.ASelect,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:    "I64Load8U",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     wasm.AI64Load8U,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:    "I64Load8S",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     wasm.AI64Load8S,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:    "I64Load16U",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     wasm.AI64Load16U,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:    "I64Load16S",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     wasm.AI64Load16S,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:    "I64Load32U",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     wasm.AI64Load32U,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:    "I64Load32S",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     wasm.AI64Load32S,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:    "I64Load",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     wasm.AI64Load,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:    "I64Store8",
+		auxType: auxInt64,
+		argLen:  3,
+		asm:     wasm.AI64Store8,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+		},
+	},
+	{
+		name:    "I64Store16",
+		auxType: auxInt64,
+		argLen:  3,
+		asm:     wasm.AI64Store16,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+		},
+	},
+	{
+		name:    "I64Store32",
+		auxType: auxInt64,
+		argLen:  3,
+		asm:     wasm.AI64Store32,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+		},
+	},
+	{
+		name:    "I64Store",
+		auxType: auxInt64,
+		argLen:  3,
+		asm:     wasm.AI64Store,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+		},
+	},
+	{
+		name:    "F32Load",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     wasm.AF32Load,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:    "F64Load",
+		auxType: auxInt64,
+		argLen:  2,
+		asm:     wasm.AF64Load,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:    "F32Store",
+		auxType: auxInt64,
+		argLen:  3,
+		asm:     wasm.AF32Store,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 4294901760},       // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+		},
+	},
+	{
+		name:    "F64Store",
+		auxType: auxInt64,
+		argLen:  3,
+		asm:     wasm.AF64Store,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{1, 281470681743360},  // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+			},
+		},
+	},
+	{
+		name:              "I64Const",
+		auxType:           auxInt64,
+		argLen:            0,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:              "F32Const",
+		auxType:           auxFloat32,
+		argLen:            0,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:              "F64Const",
+		auxType:           auxFloat64,
+		argLen:            0,
+		rematerializeable: true,
+		reg: regInfo{
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "I64Eqz",
+		argLen: 1,
+		asm:    wasm.AI64Eqz,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64Eq",
+		argLen: 2,
+		asm:    wasm.AI64Eq,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64Ne",
+		argLen: 2,
+		asm:    wasm.AI64Ne,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64LtS",
+		argLen: 2,
+		asm:    wasm.AI64LtS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64LtU",
+		argLen: 2,
+		asm:    wasm.AI64LtU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64GtS",
+		argLen: 2,
+		asm:    wasm.AI64GtS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64GtU",
+		argLen: 2,
+		asm:    wasm.AI64GtU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64LeS",
+		argLen: 2,
+		asm:    wasm.AI64LeS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64LeU",
+		argLen: 2,
+		asm:    wasm.AI64LeU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64GeS",
+		argLen: 2,
+		asm:    wasm.AI64GeS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64GeU",
+		argLen: 2,
+		asm:    wasm.AI64GeU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F32Eq",
+		argLen: 2,
+		asm:    wasm.AF32Eq,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F32Ne",
+		argLen: 2,
+		asm:    wasm.AF32Ne,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F32Lt",
+		argLen: 2,
+		asm:    wasm.AF32Lt,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F32Gt",
+		argLen: 2,
+		asm:    wasm.AF32Gt,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F32Le",
+		argLen: 2,
+		asm:    wasm.AF32Le,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F32Ge",
+		argLen: 2,
+		asm:    wasm.AF32Ge,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F64Eq",
+		argLen: 2,
+		asm:    wasm.AF64Eq,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F64Ne",
+		argLen: 2,
+		asm:    wasm.AF64Ne,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F64Lt",
+		argLen: 2,
+		asm:    wasm.AF64Lt,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F64Gt",
+		argLen: 2,
+		asm:    wasm.AF64Gt,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F64Le",
+		argLen: 2,
+		asm:    wasm.AF64Le,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F64Ge",
+		argLen: 2,
+		asm:    wasm.AF64Ge,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64Add",
+		argLen: 2,
+		asm:    wasm.AI64Add,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:    "I64AddConst",
+		auxType: auxInt64,
+		argLen:  1,
+		asm:     wasm.AI64Add,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64Sub",
+		argLen: 2,
+		asm:    wasm.AI64Sub,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64Mul",
+		argLen: 2,
+		asm:    wasm.AI64Mul,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64DivS",
+		argLen: 2,
+		asm:    wasm.AI64DivS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64DivU",
+		argLen: 2,
+		asm:    wasm.AI64DivU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64RemS",
+		argLen: 2,
+		asm:    wasm.AI64RemS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64RemU",
+		argLen: 2,
+		asm:    wasm.AI64RemU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64And",
+		argLen: 2,
+		asm:    wasm.AI64And,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64Or",
+		argLen: 2,
+		asm:    wasm.AI64Or,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64Xor",
+		argLen: 2,
+		asm:    wasm.AI64Xor,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64Shl",
+		argLen: 2,
+		asm:    wasm.AI64Shl,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64ShrS",
+		argLen: 2,
+		asm:    wasm.AI64ShrS,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64ShrU",
+		argLen: 2,
+		asm:    wasm.AI64ShrU,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F32Neg",
+		argLen: 1,
+		asm:    wasm.AF32Neg,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F32Add",
+		argLen: 2,
+		asm:    wasm.AF32Add,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F32Sub",
+		argLen: 2,
+		asm:    wasm.AF32Sub,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F32Mul",
+		argLen: 2,
+		asm:    wasm.AF32Mul,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F32Div",
+		argLen: 2,
+		asm:    wasm.AF32Div,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F64Neg",
+		argLen: 1,
+		asm:    wasm.AF64Neg,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "F64Add",
+		argLen: 2,
+		asm:    wasm.AF64Add,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "F64Sub",
+		argLen: 2,
+		asm:    wasm.AF64Sub,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "F64Mul",
+		argLen: 2,
+		asm:    wasm.AF64Mul,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "F64Div",
+		argLen: 2,
+		asm:    wasm.AF64Div,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "I64TruncSatF64S",
+		argLen: 1,
+		asm:    wasm.AI64TruncSatF64S,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64TruncSatF64U",
+		argLen: 1,
+		asm:    wasm.AI64TruncSatF64U,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64TruncSatF32S",
+		argLen: 1,
+		asm:    wasm.AI64TruncSatF32S,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64TruncSatF32U",
+		argLen: 1,
+		asm:    wasm.AI64TruncSatF32U,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F32ConvertI64S",
+		argLen: 1,
+		asm:    wasm.AF32ConvertI64S,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F32ConvertI64U",
+		argLen: 1,
+		asm:    wasm.AF32ConvertI64U,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F64ConvertI64S",
+		argLen: 1,
+		asm:    wasm.AF64ConvertI64S,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "F64ConvertI64U",
+		argLen: 1,
+		asm:    wasm.AF64ConvertI64U,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "F32DemoteF64",
+		argLen: 1,
+		asm:    wasm.AF32DemoteF64,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F64PromoteF32",
+		argLen: 1,
+		asm:    wasm.AF64PromoteF32,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "I64Extend8S",
+		argLen: 1,
+		asm:    wasm.AI64Extend8S,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64Extend16S",
+		argLen: 1,
+		asm:    wasm.AI64Extend16S,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64Extend32S",
+		argLen: 1,
+		asm:    wasm.AI64Extend32S,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "F32Sqrt",
+		argLen: 1,
+		asm:    wasm.AF32Sqrt,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F32Trunc",
+		argLen: 1,
+		asm:    wasm.AF32Trunc,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F32Ceil",
+		argLen: 1,
+		asm:    wasm.AF32Ceil,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F32Floor",
+		argLen: 1,
+		asm:    wasm.AF32Floor,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F32Nearest",
+		argLen: 1,
+		asm:    wasm.AF32Nearest,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F32Abs",
+		argLen: 1,
+		asm:    wasm.AF32Abs,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F32Copysign",
+		argLen: 2,
+		asm:    wasm.AF32Copysign,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+			outputs: []outputInfo{
+				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+			},
+		},
+	},
+	{
+		name:   "F64Sqrt",
+		argLen: 1,
+		asm:    wasm.AF64Sqrt,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "F64Trunc",
+		argLen: 1,
+		asm:    wasm.AF64Trunc,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "F64Ceil",
+		argLen: 1,
+		asm:    wasm.AF64Ceil,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "F64Floor",
+		argLen: 1,
+		asm:    wasm.AF64Floor,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "F64Nearest",
+		argLen: 1,
+		asm:    wasm.AF64Nearest,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "F64Abs",
+		argLen: 1,
+		asm:    wasm.AF64Abs,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "F64Copysign",
+		argLen: 2,
+		asm:    wasm.AF64Copysign,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+			outputs: []outputInfo{
+				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+			},
+		},
+	},
+	{
+		name:   "I64Ctz",
+		argLen: 1,
+		asm:    wasm.AI64Ctz,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64Clz",
+		argLen: 1,
+		asm:    wasm.AI64Clz,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I32Rotl",
+		argLen: 2,
+		asm:    wasm.AI32Rotl,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64Rotl",
+		argLen: 2,
+		asm:    wasm.AI64Rotl,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+	{
+		name:   "I64Popcnt",
+		argLen: 1,
+		asm:    wasm.AI64Popcnt,
+		reg: regInfo{
+			inputs: []inputInfo{
+				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+			},
+			outputs: []outputInfo{
+				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+			},
+		},
+	},
+
+	{
+		name:        "Add8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Add16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Add32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Add64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AddPtr",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "Add32F",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Add64F",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "Sub8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Sub16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Sub32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Sub64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubPtr",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Sub32F",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Sub64F",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "Mul8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Mul16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Mul32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Mul64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Mul32F",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Mul64F",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "Div32F",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Div64F",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "Hmul32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Hmul32u",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Hmul64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Hmul64u",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Mul32uhilo",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Mul64uhilo",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Mul32uover",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Mul64uover",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "Avg32u",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Avg64u",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Div8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Div8u",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Div16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Div16u",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Div32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Div32u",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Div64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Div64u",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Div128u",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Mod8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Mod8u",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Mod16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Mod16u",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Mod32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Mod32u",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Mod64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Mod64u",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "And8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "And16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "And32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "And64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Or8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Or16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Or32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Or64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Xor8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Xor16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Xor32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Xor64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "Lsh8x8",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh8x16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh8x32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh8x64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh16x8",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh16x16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh16x32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh16x64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh32x8",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh32x16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh32x32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh32x64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh64x8",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh64x16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh64x32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Lsh64x64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh8x8",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh8x16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh8x32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh8x64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh16x8",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh16x16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh16x32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh16x64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh32x8",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh32x16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh32x32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh32x64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh64x8",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh64x16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh64x32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh64x64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh8Ux8",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh8Ux16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh8Ux32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh8Ux64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh16Ux8",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh16Ux16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh16Ux32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh16Ux64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh32Ux8",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh32Ux16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh32Ux32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh32Ux64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh64Ux8",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh64Ux16",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh64Ux32",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Rsh64Ux64",
+		auxType: auxBool,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "Eq8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Eq16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Eq32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Eq64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqPtr",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "EqInter",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "EqSlice",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "Eq32F",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Eq64F",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Neq8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Neq16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Neq32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Neq64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NeqPtr",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "NeqInter",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "NeqSlice",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "Neq32F",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Neq64F",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "Less8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Less8U",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Less16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Less16U",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Less32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Less32U",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Less64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Less64U",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Less32F",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Less64F",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Leq8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Leq8U",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Leq16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Leq16U",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Leq32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Leq32U",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Leq64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Leq64U",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Leq32F",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Leq64F",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "CondSelect",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "AndB",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrB",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqB",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NeqB",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "Not",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Neg8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Neg16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Neg32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Neg64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Neg32F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Neg64F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Com8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Com16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Com32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Com64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Ctz8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Ctz16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Ctz32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Ctz64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Ctz64On32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Ctz8NonZero",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Ctz16NonZero",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Ctz32NonZero",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Ctz64NonZero",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "BitLen8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "BitLen16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "BitLen32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "BitLen64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Bswap16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Bswap32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Bswap64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "BitRev8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "BitRev16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "BitRev32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "BitRev64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCount8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCount16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCount32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCount64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "RotateLeft64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeft32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeft16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeft8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Sqrt",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Sqrt32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Floor",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Ceil",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Trunc",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Round",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "RoundToEven",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Abs",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Copysign",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Min64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Max64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Min64u",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Max64u",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Min64F",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Min32F",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Max64F",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Max32F",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "FMA",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:      "Phi",
+		argLen:    -1,
+		zeroWidth: true,
+		generic:   true,
+	},
+	{
+		name:    "Copy",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:         "Convert",
+		argLen:       2,
+		resultInArg0: true,
+		zeroWidth:    true,
+		generic:      true,
+	},
+	{
+		name:    "ConstBool",
+		auxType: auxBool,
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:    "ConstString",
+		auxType: auxString,
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:    "ConstNil",
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:    "Const8",
+		auxType: auxInt8,
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:    "Const16",
+		auxType: auxInt16,
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:    "Const32",
+		auxType: auxInt32,
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:    "Const64",
+		auxType: auxInt64,
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:    "Const32F",
+		auxType: auxFloat32,
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:    "Const64F",
+		auxType: auxFloat64,
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:    "ConstInterface",
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:    "ConstSlice",
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:      "InitMem",
+		argLen:    0,
+		zeroWidth: true,
+		generic:   true,
+	},
+	{
+		name:      "Arg",
+		auxType:   auxSymOff,
+		argLen:    0,
+		zeroWidth: true,
+		symEffect: SymRead,
+		generic:   true,
+	},
+	{
+		name:      "ArgIntReg",
+		auxType:   auxNameOffsetInt8,
+		argLen:    0,
+		zeroWidth: true,
+		generic:   true,
+	},
+	{
+		name:      "ArgFloatReg",
+		auxType:   auxNameOffsetInt8,
+		argLen:    0,
+		zeroWidth: true,
+		generic:   true,
+	},
+	{
+		name:      "Addr",
+		auxType:   auxSym,
+		argLen:    1,
+		symEffect: SymAddr,
+		generic:   true,
+	},
+	{
+		name:      "LocalAddr",
+		auxType:   auxSym,
+		argLen:    2,
+		symEffect: SymAddr,
+		generic:   true,
+	},
+	{
+		name:      "SP",
+		argLen:    0,
+		zeroWidth: true,
+		fixedReg:  true,
+		generic:   true,
+	},
+	{
+		name:      "SB",
+		argLen:    0,
+		zeroWidth: true,
+		fixedReg:  true,
+		generic:   true,
+	},
+	{
+		name:      "SPanchored",
+		argLen:    2,
+		zeroWidth: true,
+		generic:   true,
+	},
+	{
+		name:    "Load",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Dereference",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Store",
+		auxType: auxTyp,
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Move",
+		auxType: auxTypSize,
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Zero",
+		auxType: auxTypSize,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "StoreWB",
+		auxType: auxTyp,
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "MoveWB",
+		auxType: auxTypSize,
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ZeroWB",
+		auxType: auxTypSize,
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "WBend",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "WB",
+		auxType: auxInt64,
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:      "HasCPUFeature",
+		auxType:   auxSym,
+		argLen:    0,
+		symEffect: SymNone,
+		generic:   true,
+	},
+	{
+		name:    "PanicBounds",
+		auxType: auxInt64,
+		argLen:  3,
+		call:    true,
+		generic: true,
+	},
+	{
+		name:    "PanicExtend",
+		auxType: auxInt64,
+		argLen:  4,
+		call:    true,
+		generic: true,
+	},
+	{
+		name:    "ClosureCall",
+		auxType: auxCallOff,
+		argLen:  -1,
+		call:    true,
+		generic: true,
+	},
+	{
+		name:    "StaticCall",
+		auxType: auxCallOff,
+		argLen:  -1,
+		call:    true,
+		generic: true,
+	},
+	{
+		name:    "InterCall",
+		auxType: auxCallOff,
+		argLen:  -1,
+		call:    true,
+		generic: true,
+	},
+	{
+		name:    "TailCall",
+		auxType: auxCallOff,
+		argLen:  -1,
+		call:    true,
+		generic: true,
+	},
+	{
+		name:    "ClosureLECall",
+		auxType: auxCallOff,
+		argLen:  -1,
+		call:    true,
+		generic: true,
+	},
+	{
+		name:    "StaticLECall",
+		auxType: auxCallOff,
+		argLen:  -1,
+		call:    true,
+		generic: true,
+	},
+	{
+		name:    "InterLECall",
+		auxType: auxCallOff,
+		argLen:  -1,
+		call:    true,
+		generic: true,
+	},
+	{
+		name:    "TailLECall",
+		auxType: auxCallOff,
+		argLen:  -1,
+		call:    true,
+		generic: true,
+	},
+	{
+		name:    "SignExt8to16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SignExt8to32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SignExt8to64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SignExt16to32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SignExt16to64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SignExt32to64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ZeroExt8to16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ZeroExt8to32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ZeroExt8to64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ZeroExt16to32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ZeroExt16to64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ZeroExt32to64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Trunc16to8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Trunc32to8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Trunc32to16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Trunc64to8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Trunc64to16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Trunc64to32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt32to32F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt32to64F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt64to32F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt64to64F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt32Fto32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt32Fto64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt64Fto32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt64Fto64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt32Fto64F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt64Fto32F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "CvtBoolToUint8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Round32F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Round64F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "IsNonNil",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "IsInBounds",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "IsSliceInBounds",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:     "NilCheck",
+		argLen:   2,
+		nilCheck: true,
+		generic:  true,
+	},
+	{
+		name:      "GetG",
+		argLen:    1,
+		zeroWidth: true,
+		generic:   true,
+	},
+	{
+		name:    "GetClosurePtr",
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:    "GetCallerPC",
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:    "GetCallerSP",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PtrIndex",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "OffPtr",
+		auxType: auxInt64,
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SliceMake",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SlicePtr",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SliceLen",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SliceCap",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SlicePtrUnchecked",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ComplexMake",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ComplexReal",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ComplexImag",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "StringMake",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "StringPtr",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "StringLen",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "IMake",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ITab",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "IData",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "StructMake",
+		argLen:  -1,
+		generic: true,
+	},
+	{
+		name:    "StructSelect",
+		auxType: auxInt64,
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ArrayMake0",
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:    "ArrayMake1",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ArraySelect",
+		auxType: auxInt64,
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "StoreReg",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "LoadReg",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:      "FwdRef",
+		auxType:   auxSym,
+		argLen:    0,
+		symEffect: SymNone,
+		generic:   true,
+	},
+	{
+		name:    "Unknown",
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:      "VarDef",
+		auxType:   auxSym,
+		argLen:    1,
+		zeroWidth: true,
+		symEffect: SymNone,
+		generic:   true,
+	},
+	{
+		name:      "VarLive",
+		auxType:   auxSym,
+		argLen:    1,
+		zeroWidth: true,
+		symEffect: SymRead,
+		generic:   true,
+	},
+	{
+		name:      "KeepAlive",
+		argLen:    2,
+		zeroWidth: true,
+		generic:   true,
+	},
+	{
+		name:    "InlMark",
+		auxType: auxInt32,
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Int64Make",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Int64Hi",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Int64Lo",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:        "Add32carry",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "Add32withcarry",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "Sub32carry",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Sub32withcarry",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "Add64carry",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "Sub64borrow",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Signmask",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Zeromask",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Slicemask",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SpectreIndex",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SpectreSliceIndex",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Cvt32Uto32F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt32Uto64F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt32Fto32U",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt64Fto32U",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt64Uto32F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt64Uto64F",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt32Fto64U",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "Cvt64Fto64U",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:      "Select0",
+		argLen:    1,
+		zeroWidth: true,
+		generic:   true,
+	},
+	{
+		name:      "Select1",
+		argLen:    1,
+		zeroWidth: true,
+		generic:   true,
+	},
+	{
+		name:    "MakeTuple",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SelectN",
+		auxType: auxInt64,
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SelectNAddr",
+		auxType: auxInt64,
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "MakeResult",
+		argLen:  -1,
+		generic: true,
+	},
+	{
+		name:    "AtomicLoad8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AtomicLoad32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AtomicLoad64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AtomicLoadPtr",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AtomicLoadAcq32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AtomicLoadAcq64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:           "AtomicStore8",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicStore32",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicStore64",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicStorePtrNoWB",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicStoreRel32",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicStoreRel64",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicExchange8",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicExchange32",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicExchange64",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicAdd32",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicAdd64",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicCompareAndSwap32",
+		argLen:         4,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicCompareAndSwap64",
+		argLen:         4,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicCompareAndSwapRel32",
+		argLen:         4,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicAnd8",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicOr8",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicAnd32",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicOr32",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicAnd64value",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicAnd32value",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicAnd8value",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicOr64value",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicOr32value",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicOr8value",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicStore8Variant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicStore32Variant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicStore64Variant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicAdd32Variant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicAdd64Variant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicExchange8Variant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicExchange32Variant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicExchange64Variant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicCompareAndSwap32Variant",
+		argLen:         4,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicCompareAndSwap64Variant",
+		argLen:         4,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicAnd64valueVariant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicOr64valueVariant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicAnd32valueVariant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicOr32valueVariant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicAnd8valueVariant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "AtomicOr8valueVariant",
+		argLen:         3,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "PubBarrier",
+		argLen:         1,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:      "Clobber",
+		auxType:   auxSymOff,
+		argLen:    0,
+		symEffect: SymNone,
+		generic:   true,
+	},
+	{
+		name:    "ClobberReg",
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:           "PrefetchCache",
+		argLen:         2,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:           "PrefetchCacheStreamed",
+		argLen:         2,
+		hasSideEffects: true,
+		generic:        true,
+	},
+	{
+		name:    "Add32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ZeroSIMD",
+		argLen:  0,
+		generic: true,
+	},
+	{
+		name:        "AddFloat32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedFloat32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "ApproximateReciprocalFloat32x16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalMaskedFloat32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalOfSqrtFloat32x16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalOfSqrtMaskedFloat32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "CompressFloat32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "DivFloat32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "DivMaskedFloat32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "EqualFloat32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedFloat32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "FusedMultiplyAddFloat32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddMaskedFloat32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddSubFloat32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddSubMaskedFloat32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplySubAddFloat32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplySubAddMaskedFloat32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "GreaterFloat32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualFloat32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedFloat32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedFloat32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "IsNanFloat32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "IsNanMaskedFloat32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "LessFloat32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualFloat32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedFloat32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedFloat32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxFloat32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedFloat32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinFloat32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedFloat32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulFloat32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "MulByPowOf2Float32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "MulByPowOf2MaskedFloat32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MulMaskedFloat32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualFloat32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedFloat32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "SqrtFloat32x16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SqrtMaskedFloat32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubFloat32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedFloat32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "AddFloat32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedFloat32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AddSubFloat32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalFloat32x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalMaskedFloat32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalOfSqrtFloat32x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalOfSqrtMaskedFloat32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "CeilFloat32x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "CompressFloat32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "DivFloat32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "DivMaskedFloat32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "DotProdBroadcastFloat32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualFloat32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedFloat32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "FloorFloat32x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddFloat32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddMaskedFloat32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddSubFloat32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddSubMaskedFloat32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplySubAddFloat32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplySubAddMaskedFloat32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "GreaterFloat32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualFloat32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedFloat32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedFloat32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "IsNanFloat32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "IsNanMaskedFloat32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "LessFloat32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualFloat32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedFloat32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedFloat32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxFloat32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedFloat32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinFloat32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedFloat32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulFloat32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "MulByPowOf2Float32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "MulByPowOf2MaskedFloat32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MulMaskedFloat32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualFloat32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedFloat32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairwiseAddFloat32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairwiseSubFloat32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RoundFloat32x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SqrtFloat32x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SqrtMaskedFloat32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubFloat32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedFloat32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "TruncFloat32x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:        "AddFloat32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedFloat32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AddSubFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalFloat32x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalMaskedFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalOfSqrtFloat32x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalOfSqrtMaskedFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "CeilFloat32x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "CompressFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "DivFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "DivMaskedFloat32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "DotProdBroadcastFloat32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualFloat32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedFloat32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "FloorFloat32x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddFloat32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddMaskedFloat32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddSubFloat32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddSubMaskedFloat32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplySubAddFloat32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplySubAddMaskedFloat32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "GreaterFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedFloat32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedFloat32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "IsNanFloat32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "IsNanMaskedFloat32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "LessFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedFloat32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedFloat32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxFloat32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedFloat32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinFloat32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedFloat32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulFloat32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "MulByPowOf2Float32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "MulByPowOf2MaskedFloat32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MulMaskedFloat32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualFloat32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedFloat32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairwiseAddFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairwiseSubFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RoundFloat32x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SqrtFloat32x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SqrtMaskedFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedFloat32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "TruncFloat32x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:        "AddFloat64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedFloat64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AddSubFloat64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalFloat64x2",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalMaskedFloat64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalOfSqrtFloat64x2",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalOfSqrtMaskedFloat64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "CeilFloat64x2",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "CompressFloat64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "DivFloat64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "DivMaskedFloat64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "DotProdBroadcastFloat64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualFloat64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedFloat64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "FloorFloat64x2",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddFloat64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddMaskedFloat64x2",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddSubFloat64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddSubMaskedFloat64x2",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplySubAddFloat64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplySubAddMaskedFloat64x2",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "GreaterFloat64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualFloat64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedFloat64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedFloat64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "IsNanFloat64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "IsNanMaskedFloat64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "LessFloat64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualFloat64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedFloat64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedFloat64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxFloat64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedFloat64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinFloat64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedFloat64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulFloat64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "MulByPowOf2Float64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "MulByPowOf2MaskedFloat64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MulMaskedFloat64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualFloat64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedFloat64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairwiseAddFloat64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairwiseSubFloat64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RoundFloat64x2",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SqrtFloat64x2",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SqrtMaskedFloat64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubFloat64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedFloat64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "TruncFloat64x2",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:        "AddFloat64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedFloat64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AddSubFloat64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalFloat64x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalMaskedFloat64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalOfSqrtFloat64x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalOfSqrtMaskedFloat64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "CeilFloat64x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "CompressFloat64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "DivFloat64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "DivMaskedFloat64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "EqualFloat64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedFloat64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "FloorFloat64x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddFloat64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddMaskedFloat64x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddSubFloat64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddSubMaskedFloat64x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplySubAddFloat64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplySubAddMaskedFloat64x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "GreaterFloat64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualFloat64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedFloat64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedFloat64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "IsNanFloat64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "IsNanMaskedFloat64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "LessFloat64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualFloat64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedFloat64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedFloat64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxFloat64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedFloat64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinFloat64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedFloat64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulFloat64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "MulByPowOf2Float64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "MulByPowOf2MaskedFloat64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MulMaskedFloat64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualFloat64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedFloat64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairwiseAddFloat64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairwiseSubFloat64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RoundFloat64x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SqrtFloat64x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SqrtMaskedFloat64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubFloat64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedFloat64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "TruncFloat64x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:        "AddFloat64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedFloat64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "ApproximateReciprocalFloat64x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalMaskedFloat64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalOfSqrtFloat64x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "ApproximateReciprocalOfSqrtMaskedFloat64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "CompressFloat64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "DivFloat64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "DivMaskedFloat64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "EqualFloat64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedFloat64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "FusedMultiplyAddFloat64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddMaskedFloat64x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddSubFloat64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplyAddSubMaskedFloat64x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplySubAddFloat64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "FusedMultiplySubAddMaskedFloat64x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "GreaterFloat64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualFloat64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedFloat64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedFloat64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "IsNanFloat64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "IsNanMaskedFloat64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "LessFloat64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualFloat64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedFloat64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedFloat64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxFloat64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedFloat64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinFloat64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedFloat64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulFloat64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "MulByPowOf2Float64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "MulByPowOf2MaskedFloat64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MulMaskedFloat64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualFloat64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedFloat64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "SqrtFloat64x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "SqrtMaskedFloat64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubFloat64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedFloat64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteInt16x16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteMaskedInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AddInt16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedInt16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndInt16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "CompressInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualInt16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedInt16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxInt16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedInt16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinInt16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedInt16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulHighInt16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulHighMaskedInt16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowInt16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowMaskedInt16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualInt16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedInt16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrInt16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairDotProdInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairDotProdMaskedInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PairwiseAddInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairwiseSubInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PopCountInt16x16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "SaturatedAddInt16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "SaturatedAddMaskedInt16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "SaturatedPairwiseAddInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SaturatedPairwiseSubInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SaturatedSubInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SaturatedSubMaskedInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedInt16x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedInt16x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SignInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorInt16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AbsoluteInt16x32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteMaskedInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AddInt16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedInt16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "CompressInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualInt16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedInt16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxInt16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedInt16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinInt16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedInt16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulHighInt16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulHighMaskedInt16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowInt16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowMaskedInt16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualInt16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedInt16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairDotProdInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairDotProdMaskedInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PopCountInt16x32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "SaturatedAddInt16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "SaturatedAddMaskedInt16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "SaturatedSubInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SaturatedSubMaskedInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedInt16x32",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedInt16x32",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteInt16x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteMaskedInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AddInt16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedInt16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndInt16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "CompressInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualInt16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedInt16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxInt16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedInt16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinInt16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedInt16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulHighInt16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulHighMaskedInt16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowInt16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowMaskedInt16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualInt16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedInt16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrInt16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairDotProdInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairDotProdMaskedInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PairwiseAddInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairwiseSubInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PopCountInt16x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "SaturatedAddInt16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "SaturatedAddMaskedInt16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "SaturatedPairwiseAddInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SaturatedPairwiseSubInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SaturatedSubInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SaturatedSubMaskedInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedInt16x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedInt16x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SignInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorInt16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AbsoluteInt32x16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteMaskedInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AddInt32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedInt32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndInt32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndMaskedInt32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AndNotMaskedInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "CompressInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualInt32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedInt32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxInt32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedInt32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinInt32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedInt32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowInt32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowMaskedInt32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualInt32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedInt32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrInt32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrMaskedInt32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairDotProdAccumulateInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PairDotProdAccumulateMaskedInt32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "PopCountInt32x16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftMaskedInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "RotateRightInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateRightMaskedInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SaturatedPairDotProdAccumulateInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SaturatedPairDotProdAccumulateMaskedInt32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedInt32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedInt32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "UnsignedSignedQuadDotProdAccumulateInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "UnsignedSignedQuadDotProdAccumulateMaskedInt32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:        "XorInt32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "XorMaskedInt32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AbsoluteInt32x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteMaskedInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AddInt32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedInt32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndInt32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndMaskedInt32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AndNotMaskedInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "CompressInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualInt32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedInt32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxInt32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedInt32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinInt32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedInt32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenInt32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowInt32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowMaskedInt32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualInt32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedInt32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrInt32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrMaskedInt32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairDotProdAccumulateInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PairDotProdAccumulateMaskedInt32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "PairwiseAddInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairwiseSubInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PopCountInt32x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftMaskedInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "RotateRightInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateRightMaskedInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SaturatedPairDotProdAccumulateInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SaturatedPairDotProdAccumulateMaskedInt32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedInt32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedInt32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SignInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubInt32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "UnsignedSignedQuadDotProdAccumulateInt32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "UnsignedSignedQuadDotProdAccumulateMaskedInt32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:        "XorInt32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "XorMaskedInt32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AbsoluteInt32x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteMaskedInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AddInt32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedInt32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndInt32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndMaskedInt32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AndNotMaskedInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "CompressInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualInt32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedInt32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxInt32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedInt32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinInt32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedInt32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenInt32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowInt32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowMaskedInt32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualInt32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedInt32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrInt32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrMaskedInt32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairDotProdAccumulateInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PairDotProdAccumulateMaskedInt32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "PairwiseAddInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairwiseSubInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PopCountInt32x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftMaskedInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "RotateRightInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateRightMaskedInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SaturatedPairDotProdAccumulateInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SaturatedPairDotProdAccumulateMaskedInt32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedInt32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedInt32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SignInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "UnsignedSignedQuadDotProdAccumulateInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "UnsignedSignedQuadDotProdAccumulateMaskedInt32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:        "XorInt32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "XorMaskedInt32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AbsoluteInt64x2",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteMaskedInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AddInt64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedInt64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndInt64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndMaskedInt64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AndNotMaskedInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "CompressInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualInt64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedInt64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxInt64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedInt64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinInt64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedInt64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenInt64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenMaskedInt64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowInt64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowMaskedInt64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualInt64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedInt64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrInt64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrMaskedInt64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PopCountInt64x2",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftMaskedInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "RotateRightInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateRightMaskedInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedInt64x2",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedInt64x2",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubInt64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedInt64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorInt64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "XorMaskedInt64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AbsoluteInt64x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteMaskedInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AddInt64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedInt64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndInt64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndMaskedInt64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AndNotMaskedInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "CompressInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualInt64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedInt64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxInt64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedInt64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinInt64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedInt64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenInt64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenMaskedInt64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowInt64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowMaskedInt64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualInt64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedInt64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrInt64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrMaskedInt64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PopCountInt64x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftMaskedInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "RotateRightInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateRightMaskedInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedInt64x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedInt64x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubInt64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorInt64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "XorMaskedInt64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AbsoluteInt64x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteMaskedInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AddInt64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedInt64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndInt64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndMaskedInt64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AndNotMaskedInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "CompressInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualInt64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedInt64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxInt64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedInt64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinInt64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedInt64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenInt64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenMaskedInt64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowInt64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulLowMaskedInt64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualInt64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedInt64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrInt64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrMaskedInt64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PopCountInt64x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftMaskedInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "RotateRightInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateRightMaskedInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedInt64x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedInt64x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubInt64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorInt64x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "XorMaskedInt64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AbsoluteInt8x16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteMaskedInt8x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AddInt8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedInt8x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndInt8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotInt8x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "CompressInt8x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualInt8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedInt8x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterInt8x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualInt8x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedInt8x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedInt8x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessInt8x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualInt8x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedInt8x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedInt8x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxInt8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedInt8x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinInt8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedInt8x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualInt8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedInt8x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrInt8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PopCountInt8x16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedInt8x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "SaturatedAddInt8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "SaturatedAddMaskedInt8x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "SaturatedSubInt8x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SaturatedSubMaskedInt8x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SignInt8x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubInt8x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedInt8x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorInt8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AbsoluteInt8x32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteMaskedInt8x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AddInt8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedInt8x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndInt8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotInt8x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "CompressInt8x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualInt8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedInt8x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterInt8x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualInt8x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedInt8x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedInt8x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessInt8x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualInt8x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedInt8x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedInt8x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxInt8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedInt8x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinInt8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedInt8x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualInt8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedInt8x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrInt8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PopCountInt8x32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedInt8x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "SaturatedAddInt8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "SaturatedAddMaskedInt8x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "SaturatedSubInt8x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SaturatedSubMaskedInt8x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SignInt8x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubInt8x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedInt8x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorInt8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AbsoluteInt8x64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "AbsoluteMaskedInt8x64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AddInt8x64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedInt8x64",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "CompressInt8x64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualInt8x64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedInt8x64",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterInt8x64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualInt8x64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedInt8x64",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedInt8x64",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessInt8x64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualInt8x64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedInt8x64",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedInt8x64",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxInt8x64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedInt8x64",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinInt8x64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedInt8x64",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualInt8x64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedInt8x64",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PopCountInt8x64",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedInt8x64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "SaturatedAddInt8x64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "SaturatedAddMaskedInt8x64",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "SaturatedSubInt8x64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SaturatedSubMaskedInt8x64",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubInt8x64",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedInt8x64",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "AddUint16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedUint16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndUint16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AverageUint16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AverageMaskedUint16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "CompressUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualUint16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedUint16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedUint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedUint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedUint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedUint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxUint16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedUint16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinUint16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedUint16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulHighUint16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulHighMaskedUint16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualUint16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedUint16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrUint16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairwiseAddUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairwiseSubUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PermuteInt16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PermuteUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Permute2Uint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Int16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedInt16x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedUint16x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedUint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedInt16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PopCountUint16x16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "SaturatedAddUint16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "SaturatedAddMaskedUint16x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "SaturatedSubUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SaturatedSubMaskedUint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedUint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedUint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromUint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedUint16x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedUint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromUint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedUint16x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedUint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubUint16x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedUint16x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorUint16x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddUint16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedUint16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AverageUint16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AverageMaskedUint16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "CompressUint16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualUint16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedUint16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterUint16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualUint16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedUint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedUint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessUint16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualUint16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedUint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedUint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxUint16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedUint16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinUint16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedUint16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulHighUint16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulHighMaskedUint16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualUint16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedUint16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PermuteUint16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PermuteInt16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Permute2Uint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Int16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedUint16x32",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedInt16x32",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedUint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedInt16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PopCountUint16x32",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedUint16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "SaturatedAddUint16x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "SaturatedAddMaskedUint16x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "SaturatedSubUint16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SaturatedSubMaskedUint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftUint16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedUint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightUint16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedUint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftUint16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromUint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedUint16x32",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedUint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightUint16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromUint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedUint16x32",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedUint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubUint16x32",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedUint16x32",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "AddUint16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedUint16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndUint16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AverageUint16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AverageMaskedUint16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "CompressUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualUint16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedUint16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedUint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedUint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedUint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedUint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxUint16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedUint16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinUint16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedUint16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulHighUint16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulHighMaskedUint16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualUint16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedUint16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrUint16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairwiseAddUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairwiseSubUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PermuteInt16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PermuteUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Permute2Int16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Uint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedInt16x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedUint16x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedUint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedInt16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PopCountUint16x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "SaturatedAddUint16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "SaturatedAddMaskedUint16x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "SaturatedSubUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SaturatedSubMaskedUint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedUint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedUint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromUint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedUint16x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedUint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromUint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedUint16x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedUint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubUint16x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedUint16x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorUint16x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddUint32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedUint32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndUint32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndMaskedUint32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AndNotMaskedUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "CompressUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualUint32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedUint32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxUint32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedUint32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinUint32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedUint32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualUint32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedUint32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrUint32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrMaskedUint32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PermuteFloat32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PermuteInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PermuteUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Permute2Uint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Float32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Int32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedInt32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedFloat32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedUint32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedInt32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedFloat32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PopCountUint32x16",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftMaskedUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "RotateRightUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateRightMaskedUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedUint32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedUint32x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubUint32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedUint32x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorUint32x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "XorMaskedUint32x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddUint32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedUint32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndUint32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndMaskedUint32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AndNotMaskedUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "CompressUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualUint32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedUint32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxUint32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedUint32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinUint32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedUint32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenUint32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualUint32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedUint32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrUint32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrMaskedUint32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairwiseAddUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairwiseSubUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Permute2Float32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Uint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Int32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedInt32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedUint32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedFloat32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "PopCountUint32x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftMaskedUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "RotateRightUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateRightMaskedUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedUint32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedUint32x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubUint32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedUint32x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorUint32x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "XorMaskedUint32x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddUint32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedUint32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndUint32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndMaskedUint32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AndNotMaskedUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "CompressUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualUint32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedUint32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxUint32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedUint32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinUint32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedUint32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenUint32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualUint32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedUint32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrUint32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrMaskedUint32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PairwiseAddUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PairwiseSubUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PermuteUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PermuteFloat32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PermuteInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Permute2Int32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Float32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Uint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedFloat32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedUint32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedInt32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedInt32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedFloat32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PopCountUint32x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftMaskedUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "RotateRightUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateRightMaskedUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedUint32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedUint32x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubUint32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedUint32x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorUint32x8",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "XorMaskedUint32x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddUint64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedUint64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndUint64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndMaskedUint64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AndNotMaskedUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "CompressUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualUint64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedUint64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxUint64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedUint64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinUint64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedUint64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenUint64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenMaskedUint64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualUint64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedUint64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrUint64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrMaskedUint64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "Permute2Float64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Uint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Int64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedInt64x2",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedFloat64x2",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedUint64x2",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "PopCountUint64x2",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftMaskedUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "RotateRightUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateRightMaskedUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedUint64x2",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedUint64x2",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubUint64x2",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedUint64x2",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorUint64x2",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "XorMaskedUint64x2",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddUint64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AddMaskedUint64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndUint64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndMaskedUint64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "AndNotMaskedUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "CompressUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualUint64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedUint64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GreaterUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "GreaterEqualMaskedUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "GreaterMaskedUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "LessEqualMaskedUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxUint64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedUint64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinUint64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedUint64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenUint64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenMaskedUint64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualUint64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedUint64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrUint64x4",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrMaskedUint64x4",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PermuteUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "PermuteInt64x4",
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:   "F64Nearest",
-		argLen: 1,
-		asm:    wasm.AF64Nearest,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-		},
+		name:    "PermuteFloat64x4",
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:   "F64Abs",
-		argLen: 1,
-		asm:    wasm.AF64Abs,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-		},
+		name:    "Permute2Float64x4",
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:   "F64Copysign",
-		argLen: 2,
-		asm:    wasm.AF64Copysign,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-			outputs: []outputInfo{
-				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-			},
-		},
+		name:    "Permute2Int64x4",
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:   "I64Ctz",
-		argLen: 1,
-		asm:    wasm.AI64Ctz,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
-			},
-		},
+		name:    "Permute2Uint64x4",
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:   "I64Clz",
-		argLen: 1,
-		asm:    wasm.AI64Clz,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
-			},
-		},
+		name:    "Permute2MaskedFloat64x4",
+		argLen:  4,
+		generic: true,
 	},
 	{
-		name:   "I32Rotl",
-		argLen: 2,
-		asm:    wasm.AI32Rotl,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
-			},
-		},
+		name:    "Permute2MaskedUint64x4",
+		argLen:  4,
+		generic: true,
 	},
 	{
-		name:   "I64Rotl",
-		argLen: 2,
-		asm:    wasm.AI64Rotl,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
-			},
-		},
+		name:    "Permute2MaskedInt64x4",
+		argLen:  4,
+		generic: true,
 	},
 	{
-		name:   "I64Popcnt",
-		argLen: 1,
-		asm:    wasm.AI64Popcnt,
-		reg: regInfo{
-			inputs: []inputInfo{
-				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-			},
-			outputs: []outputInfo{
-				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
-			},
-		},
+		name:    "PermuteMaskedFloat64x4",
+		argLen:  3,
+		generic: true,
 	},
-
 	{
-		name:        "Add8",
+		name:    "PermuteMaskedInt64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PopCountUint64x4",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftMaskedUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "RotateRightUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateRightMaskedUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedUint64x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedUint64x4",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubUint64x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedUint64x4",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorUint64x4",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Add16",
-		argLen:      2,
+		name:        "XorMaskedUint64x4",
+		argLen:      3,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Add32",
+		name:        "AddUint64x8",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Add64",
+		name:        "AddMaskedUint64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AndUint64x8",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:    "AddPtr",
+		name:        "AndMaskedUint64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "AndNotUint64x8",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:        "Add32F",
+		name:    "AndNotMaskedUint64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "CompressUint64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualUint64x8",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Add64F",
-		argLen:      2,
+		name:        "EqualMaskedUint64x8",
+		argLen:      3,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:    "Sub8",
+		name:    "GreaterUint64x8",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Sub16",
+		name:    "GreaterEqualUint64x8",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Sub32",
-		argLen:  2,
+		name:    "GreaterEqualMaskedUint64x8",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Sub64",
-		argLen:  2,
+		name:    "GreaterMaskedUint64x8",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "SubPtr",
+		name:    "LessUint64x8",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Sub32F",
+		name:    "LessEqualUint64x8",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Sub64F",
-		argLen:  2,
+		name:    "LessEqualMaskedUint64x8",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:        "Mul8",
+		name:    "LessMaskedUint64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxUint64x8",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Mul16",
-		argLen:      2,
+		name:        "MaxMaskedUint64x8",
+		argLen:      3,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Mul32",
+		name:        "MinUint64x8",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Mul64",
+		name:        "MinMaskedUint64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MulEvenWidenUint64x8",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Mul32F",
+		name:        "MulEvenWidenMaskedUint64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualUint64x8",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Mul64F",
+		name:        "NotEqualMaskedUint64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrUint64x8",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:    "Div32F",
+		name:        "OrMaskedUint64x8",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PermuteFloat64x8",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Div64F",
+		name:    "PermuteInt64x8",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:        "Hmul32",
+		name:    "PermuteUint64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "Permute2Int64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Float64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Uint64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedUint64x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedInt64x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedFloat64x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedUint64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedFloat64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedInt64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "PopCountUint64x8",
+		argLen:  1,
+		generic: true,
+	},
+	{
+		name:    "PopCountMaskedUint64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftUint64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateLeftMaskedUint64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "RotateRightUint64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "RotateRightMaskedUint64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftUint64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllLeftMaskedUint64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightUint64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightMaskedUint64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftUint64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromUint64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftAndFillUpperFromMaskedUint64x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftLeftMaskedUint64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightUint64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromUint64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightAndFillUpperFromMaskedUint64x8",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "ShiftRightMaskedUint64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "SubUint64x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "SubMaskedUint64x8",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "XorUint64x8",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Hmul32u",
-		argLen:      2,
+		name:        "XorMaskedUint64x8",
+		argLen:      3,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Hmul64",
+		name:        "AddUint8x16",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Hmul64u",
-		argLen:      2,
+		name:        "AddMaskedUint8x16",
+		argLen:      3,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Mul32uhilo",
+		name:        "AndUint8x16",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Mul64uhilo",
+		name:    "AndNotUint8x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "AverageUint8x16",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Mul32uover",
-		argLen:      2,
+		name:        "AverageMaskedUint8x16",
+		argLen:      3,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Mul64uover",
+		name:    "CompressUint8x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:        "EqualUint8x16",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:    "Avg32u",
+		name:        "EqualMaskedUint8x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GaloisFieldMulUint8x16",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Avg64u",
-		argLen:  2,
+		name:    "GaloisFieldMulMaskedUint8x16",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Div8",
+		name:    "GreaterUint8x16",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Div8u",
+		name:    "GreaterEqualUint8x16",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Div16",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "GreaterEqualMaskedUint8x16",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Div16u",
-		argLen:  2,
+		name:    "GreaterMaskedUint8x16",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Div32",
-		auxType: auxBool,
+		name:    "LessUint8x16",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Div32u",
+		name:    "LessEqualUint8x16",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Div64",
-		auxType: auxBool,
+		name:    "LessEqualMaskedUint8x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "LessMaskedUint8x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:        "MaxUint8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MaxMaskedUint8x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinUint8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "MinMaskedUint8x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualUint8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "NotEqualMaskedUint8x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "OrUint8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "PermuteUint8x16",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Div64u",
+		name:    "PermuteInt8x16",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Div128u",
+		name:    "Permute2Uint8x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2Int8x16",
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedInt8x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "Permute2MaskedUint8x16",
+		argLen:  4,
+		generic: true,
+	},
+	{
+		name:    "PermuteMaskedUint8x16",
 		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Mod8",
-		argLen:  2,
+		name:    "PermuteMaskedInt8x16",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Mod8u",
-		argLen:  2,
+		name:    "PopCountUint8x16",
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Mod16",
-		auxType: auxBool,
+		name:    "PopCountMaskedUint8x16",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Mod16u",
-		argLen:  2,
-		generic: true,
+		name:        "SaturatedAddUint8x16",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
 	},
 	{
-		name:    "Mod32",
-		auxType: auxBool,
+		name:        "SaturatedAddMaskedUint8x16",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "SaturatedSubUint8x16",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Mod32u",
-		argLen:  2,
+		name:    "SaturatedSubMaskedUint8x16",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Mod64",
-		auxType: auxBool,
+		name:    "SaturatedUnsignedSignedPairDotProdUint8x16",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Mod64u",
-		argLen:  2,
+		name:    "SaturatedUnsignedSignedPairDotProdMaskedUint8x16",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:        "And8",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "SubUint8x16",
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:        "And16",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "SubMaskedUint8x16",
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:        "And32",
+		name:        "XorUint8x16",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "And64",
+		name:        "AddUint8x32",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Or8",
-		argLen:      2,
+		name:        "AddMaskedUint8x32",
+		argLen:      3,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Or16",
+		name:        "AndUint8x32",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Or32",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "AndNotUint8x32",
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:        "Or64",
+		name:        "AverageUint8x32",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Xor8",
-		argLen:      2,
+		name:        "AverageMaskedUint8x32",
+		argLen:      3,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Xor16",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "CompressUint8x32",
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:        "Xor32",
+		name:        "EqualUint8x32",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Xor64",
-		argLen:      2,
+		name:        "EqualMaskedUint8x32",
+		argLen:      3,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:    "Lsh8x8",
-		auxType: auxBool,
+		name:    "GaloisFieldMulUint8x32",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Lsh8x16",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "GaloisFieldMulMaskedUint8x32",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Lsh8x32",
-		auxType: auxBool,
+		name:    "GreaterUint8x32",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Lsh8x64",
-		auxType: auxBool,
+		name:    "GreaterEqualUint8x32",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Lsh16x8",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "GreaterEqualMaskedUint8x32",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Lsh16x16",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "GreaterMaskedUint8x32",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Lsh16x32",
-		auxType: auxBool,
+		name:    "LessUint8x32",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Lsh16x64",
-		auxType: auxBool,
+		name:    "LessEqualUint8x32",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Lsh32x8",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "LessEqualMaskedUint8x32",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Lsh32x16",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "LessMaskedUint8x32",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Lsh32x32",
-		auxType: auxBool,
-		argLen:  2,
-		generic: true,
+		name:        "MaxUint8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
 	},
 	{
-		name:    "Lsh32x64",
-		auxType: auxBool,
-		argLen:  2,
-		generic: true,
+		name:        "MaxMaskedUint8x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
 	},
 	{
-		name:    "Lsh64x8",
-		auxType: auxBool,
-		argLen:  2,
-		generic: true,
+		name:        "MinUint8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
 	},
 	{
-		name:    "Lsh64x16",
-		auxType: auxBool,
-		argLen:  2,
-		generic: true,
+		name:        "MinMaskedUint8x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
 	},
 	{
-		name:    "Lsh64x32",
-		auxType: auxBool,
-		argLen:  2,
-		generic: true,
+		name:        "NotEqualUint8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
 	},
 	{
-		name:    "Lsh64x64",
-		auxType: auxBool,
-		argLen:  2,
-		generic: true,
+		name:        "NotEqualMaskedUint8x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
 	},
 	{
-		name:    "Rsh8x8",
-		auxType: auxBool,
-		argLen:  2,
-		generic: true,
+		name:        "OrUint8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
 	},
 	{
-		name:    "Rsh8x16",
-		auxType: auxBool,
+		name:    "PermuteUint8x32",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Rsh8x32",
-		auxType: auxBool,
+		name:    "PermuteInt8x32",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Rsh8x64",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "Permute2Int8x32",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Rsh16x8",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "Permute2Uint8x32",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Rsh16x16",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "Permute2MaskedUint8x32",
+		argLen:  4,
 		generic: true,
 	},
 	{
-		name:    "Rsh16x32",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "Permute2MaskedInt8x32",
+		argLen:  4,
 		generic: true,
 	},
 	{
-		name:    "Rsh16x64",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "PermuteMaskedUint8x32",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Rsh32x8",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "PermuteMaskedInt8x32",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Rsh32x16",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "PopCountUint8x32",
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Rsh32x32",
-		auxType: auxBool,
+		name:    "PopCountMaskedUint8x32",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Rsh32x64",
-		auxType: auxBool,
-		argLen:  2,
-		generic: true,
+		name:        "SaturatedAddUint8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
 	},
 	{
-		name:    "Rsh64x8",
-		auxType: auxBool,
-		argLen:  2,
-		generic: true,
+		name:        "SaturatedAddMaskedUint8x32",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
 	},
 	{
-		name:    "Rsh64x16",
-		auxType: auxBool,
+		name:    "SaturatedSubUint8x32",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Rsh64x32",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "SaturatedSubMaskedUint8x32",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Rsh64x64",
-		auxType: auxBool,
+		name:    "SaturatedUnsignedSignedPairDotProdUint8x32",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Rsh8Ux8",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "SaturatedUnsignedSignedPairDotProdMaskedUint8x32",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Rsh8Ux16",
-		auxType: auxBool,
+		name:    "SubUint8x32",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Rsh8Ux32",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "SubMaskedUint8x32",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Rsh8Ux64",
-		auxType: auxBool,
-		argLen:  2,
-		generic: true,
+		name:        "XorUint8x32",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
 	},
 	{
-		name:    "Rsh16Ux8",
-		auxType: auxBool,
-		argLen:  2,
-		generic: true,
+		name:        "AddUint8x64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
 	},
 	{
-		name:    "Rsh16Ux16",
-		auxType: auxBool,
+		name:        "AddMaskedUint8x64",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AverageUint8x64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "AverageMaskedUint8x64",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "CompressUint8x64",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Rsh16Ux32",
-		auxType: auxBool,
+		name:        "EqualUint8x64",
+		argLen:      2,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:        "EqualMaskedUint8x64",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
+	},
+	{
+		name:    "GaloisFieldMulUint8x64",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Rsh16Ux64",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "GaloisFieldMulMaskedUint8x64",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Rsh32Ux8",
-		auxType: auxBool,
+		name:    "GreaterUint8x64",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Rsh32Ux16",
-		auxType: auxBool,
+		name:    "GreaterEqualUint8x64",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Rsh32Ux32",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "GreaterEqualMaskedUint8x64",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Rsh32Ux64",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "GreaterMaskedUint8x64",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Rsh64Ux8",
-		auxType: auxBool,
+		name:    "LessUint8x64",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Rsh64Ux16",
-		auxType: auxBool,
+		name:    "LessEqualUint8x64",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Rsh64Ux32",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "LessEqualMaskedUint8x64",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Rsh64Ux64",
-		auxType: auxBool,
-		argLen:  2,
+		name:    "LessMaskedUint8x64",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:        "Eq8",
+		name:        "MaxUint8x64",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Eq16",
-		argLen:      2,
+		name:        "MaxMaskedUint8x64",
+		argLen:      3,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Eq32",
+		name:        "MinUint8x64",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Eq64",
-		argLen:      2,
+		name:        "MinMaskedUint8x64",
+		argLen:      3,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "EqPtr",
+		name:        "NotEqualUint8x64",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:    "EqInter",
-		argLen:  2,
-		generic: true,
+		name:        "NotEqualMaskedUint8x64",
+		argLen:      3,
+		commutative: true,
+		generic:     true,
 	},
 	{
-		name:    "EqSlice",
+		name:    "PermuteInt8x64",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:        "Eq32F",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "PermuteUint8x64",
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:        "Eq64F",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "Permute2Uint8x64",
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:        "Neq8",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "Permute2Int8x64",
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:        "Neq16",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "Permute2MaskedUint8x64",
+		argLen:  4,
+		generic: true,
 	},
 	{
-		name:        "Neq32",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "Permute2MaskedInt8x64",
+		argLen:  4,
+		generic: true,
 	},
 	{
-		name:        "Neq64",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "PermuteMaskedUint8x64",
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:        "NeqPtr",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "PermuteMaskedInt8x64",
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:    "NeqInter",
-		argLen:  2,
+		name:    "PopCountUint8x64",
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "NeqSlice",
+		name:    "PopCountMaskedUint8x64",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:        "Neq32F",
+		name:        "SaturatedAddUint8x64",
 		argLen:      2,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:        "Neq64F",
-		argLen:      2,
+		name:        "SaturatedAddMaskedUint8x64",
+		argLen:      3,
 		commutative: true,
 		generic:     true,
 	},
 	{
-		name:    "Less8",
+		name:    "SaturatedSubUint8x64",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Less8U",
-		argLen:  2,
+		name:    "SaturatedSubMaskedUint8x64",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Less16",
+		name:    "SaturatedUnsignedSignedPairDotProdUint8x64",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Less16U",
-		argLen:  2,
+		name:    "SaturatedUnsignedSignedPairDotProdMaskedUint8x64",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Less32",
+		name:    "SubUint8x64",
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Less32U",
-		argLen:  2,
+		name:    "SubMaskedUint8x64",
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Less64",
-		argLen:  2,
+		name:    "CeilWithPrecisionFloat32x16",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Less64U",
+		name:    "CeilWithPrecisionMaskedFloat32x16",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Less32F",
-		argLen:  2,
+		name:    "DiffWithCeilWithPrecisionFloat32x16",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Less64F",
+		name:    "DiffWithCeilWithPrecisionMaskedFloat32x16",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Leq8",
-		argLen:  2,
+		name:    "DiffWithFloorWithPrecisionFloat32x16",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Leq8U",
+		name:    "DiffWithFloorWithPrecisionMaskedFloat32x16",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Leq16",
-		argLen:  2,
+		name:    "DiffWithRoundWithPrecisionFloat32x16",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Leq16U",
+		name:    "DiffWithRoundWithPrecisionMaskedFloat32x16",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Leq32",
-		argLen:  2,
+		name:    "DiffWithTruncWithPrecisionFloat32x16",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Leq32U",
+		name:    "DiffWithTruncWithPrecisionMaskedFloat32x16",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Leq64",
-		argLen:  2,
+		name:    "FloorWithPrecisionFloat32x16",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Leq64U",
+		name:    "FloorWithPrecisionMaskedFloat32x16",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Leq32F",
-		argLen:  2,
+		name:    "RoundWithPrecisionFloat32x16",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Leq64F",
+		name:    "RoundWithPrecisionMaskedFloat32x16",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "CondSelect",
-		argLen:  3,
+		name:    "TruncWithPrecisionFloat32x16",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:        "AndB",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
-	},
-	{
-		name:        "OrB",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "TruncWithPrecisionMaskedFloat32x16",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:        "EqB",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "CeilWithPrecisionFloat32x4",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:        "NeqB",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
+		name:    "CeilWithPrecisionMaskedFloat32x4",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:    "Not",
+		name:    "DiffWithCeilWithPrecisionFloat32x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Neg8",
-		argLen:  1,
+		name:    "DiffWithCeilWithPrecisionMaskedFloat32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Neg16",
+		name:    "DiffWithFloorWithPrecisionFloat32x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Neg32",
-		argLen:  1,
+		name:    "DiffWithFloorWithPrecisionMaskedFloat32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Neg64",
+		name:    "DiffWithRoundWithPrecisionFloat32x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Neg32F",
-		argLen:  1,
+		name:    "DiffWithRoundWithPrecisionMaskedFloat32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Neg64F",
+		name:    "DiffWithTruncWithPrecisionFloat32x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Com8",
-		argLen:  1,
+		name:    "DiffWithTruncWithPrecisionMaskedFloat32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Com16",
+		name:    "FloorWithPrecisionFloat32x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Com32",
-		argLen:  1,
+		name:    "FloorWithPrecisionMaskedFloat32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Com64",
+		name:    "RoundWithPrecisionFloat32x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Ctz8",
-		argLen:  1,
+		name:    "RoundWithPrecisionMaskedFloat32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Ctz16",
+		name:    "TruncWithPrecisionFloat32x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Ctz32",
-		argLen:  1,
+		name:    "TruncWithPrecisionMaskedFloat32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Ctz64",
+		name:    "CeilWithPrecisionFloat32x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Ctz64On32",
+		name:    "CeilWithPrecisionMaskedFloat32x8",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Ctz8NonZero",
+		name:    "DiffWithCeilWithPrecisionFloat32x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Ctz16NonZero",
-		argLen:  1,
+		name:    "DiffWithCeilWithPrecisionMaskedFloat32x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Ctz32NonZero",
+		name:    "DiffWithFloorWithPrecisionFloat32x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Ctz64NonZero",
-		argLen:  1,
+		name:    "DiffWithFloorWithPrecisionMaskedFloat32x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "BitLen8",
+		name:    "DiffWithRoundWithPrecisionFloat32x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "BitLen16",
-		argLen:  1,
+		name:    "DiffWithRoundWithPrecisionMaskedFloat32x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "BitLen32",
+		name:    "DiffWithTruncWithPrecisionFloat32x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "BitLen64",
-		argLen:  1,
+		name:    "DiffWithTruncWithPrecisionMaskedFloat32x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Bswap16",
+		name:    "FloorWithPrecisionFloat32x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Bswap32",
-		argLen:  1,
+		name:    "FloorWithPrecisionMaskedFloat32x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Bswap64",
+		name:    "Get128Float32x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "BitRev8",
+		name:    "RoundWithPrecisionFloat32x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "BitRev16",
-		argLen:  1,
+		name:    "RoundWithPrecisionMaskedFloat32x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "BitRev32",
-		argLen:  1,
+		name:    "Set128Float32x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "BitRev64",
+		name:    "TruncWithPrecisionFloat32x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "PopCount8",
-		argLen:  1,
+		name:    "TruncWithPrecisionMaskedFloat32x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "PopCount16",
+		name:    "CeilWithPrecisionFloat64x2",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "PopCount32",
-		argLen:  1,
+		name:    "CeilWithPrecisionMaskedFloat64x2",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "PopCount64",
+		name:    "DiffWithCeilWithPrecisionFloat64x2",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "RotateLeft64",
+		name:    "DiffWithCeilWithPrecisionMaskedFloat64x2",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "RotateLeft32",
-		argLen:  2,
+		name:    "DiffWithFloorWithPrecisionFloat64x2",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "RotateLeft16",
+		name:    "DiffWithFloorWithPrecisionMaskedFloat64x2",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "RotateLeft8",
-		argLen:  2,
+		name:    "DiffWithRoundWithPrecisionFloat64x2",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Sqrt",
-		argLen:  1,
+		name:    "DiffWithRoundWithPrecisionMaskedFloat64x2",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Sqrt32",
+		name:    "DiffWithTruncWithPrecisionFloat64x2",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Floor",
-		argLen:  1,
+		name:    "DiffWithTruncWithPrecisionMaskedFloat64x2",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Ceil",
+		name:    "FloorWithPrecisionFloat64x2",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Trunc",
-		argLen:  1,
+		name:    "FloorWithPrecisionMaskedFloat64x2",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Round",
+		name:    "RoundWithPrecisionFloat64x2",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "RoundToEven",
-		argLen:  1,
+		name:    "RoundWithPrecisionMaskedFloat64x2",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Abs",
+		name:    "TruncWithPrecisionFloat64x2",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Copysign",
+		name:    "TruncWithPrecisionMaskedFloat64x2",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Min64",
-		argLen:  2,
+		name:    "CeilWithPrecisionFloat64x4",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Max64",
+		name:    "CeilWithPrecisionMaskedFloat64x4",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Min64u",
-		argLen:  2,
+		name:    "DiffWithCeilWithPrecisionFloat64x4",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Max64u",
+		name:    "DiffWithCeilWithPrecisionMaskedFloat64x4",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Min64F",
-		argLen:  2,
+		name:    "DiffWithFloorWithPrecisionFloat64x4",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Min32F",
+		name:    "DiffWithFloorWithPrecisionMaskedFloat64x4",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Max64F",
-		argLen:  2,
+		name:    "DiffWithRoundWithPrecisionFloat64x4",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Max32F",
+		name:    "DiffWithRoundWithPrecisionMaskedFloat64x4",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "FMA",
-		argLen:  3,
+		name:    "DiffWithTruncWithPrecisionFloat64x4",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:      "Phi",
-		argLen:    -1,
-		zeroWidth: true,
-		generic:   true,
+		name:    "DiffWithTruncWithPrecisionMaskedFloat64x4",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:    "Copy",
+		name:    "FloorWithPrecisionFloat64x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:         "Convert",
-		argLen:       2,
-		resultInArg0: true,
-		zeroWidth:    true,
-		generic:      true,
-	},
-	{
-		name:    "ConstBool",
-		auxType: auxBool,
-		argLen:  0,
+		name:    "FloorWithPrecisionMaskedFloat64x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "ConstString",
-		auxType: auxString,
-		argLen:  0,
+		name:    "Get128Float64x4",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "ConstNil",
-		argLen:  0,
+		name:    "RoundWithPrecisionFloat64x4",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Const8",
+		name:    "RoundWithPrecisionMaskedFloat64x4",
 		auxType: auxInt8,
-		argLen:  0,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Const16",
-		auxType: auxInt16,
-		argLen:  0,
+		name:    "Set128Float64x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Const32",
-		auxType: auxInt32,
-		argLen:  0,
+		name:    "TruncWithPrecisionFloat64x4",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Const64",
-		auxType: auxInt64,
-		argLen:  0,
+		name:    "TruncWithPrecisionMaskedFloat64x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Const32F",
-		auxType: auxFloat32,
-		argLen:  0,
+		name:    "CeilWithPrecisionFloat64x8",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Const64F",
-		auxType: auxFloat64,
-		argLen:  0,
+		name:    "CeilWithPrecisionMaskedFloat64x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "ConstInterface",
-		argLen:  0,
+		name:    "DiffWithCeilWithPrecisionFloat64x8",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "ConstSlice",
-		argLen:  0,
+		name:    "DiffWithCeilWithPrecisionMaskedFloat64x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:      "InitMem",
-		argLen:    0,
-		zeroWidth: true,
-		generic:   true,
+		name:    "DiffWithFloorWithPrecisionFloat64x8",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:      "Arg",
-		auxType:   auxSymOff,
-		argLen:    0,
-		zeroWidth: true,
-		symEffect: SymRead,
-		generic:   true,
+		name:    "DiffWithFloorWithPrecisionMaskedFloat64x8",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:      "ArgIntReg",
-		auxType:   auxNameOffsetInt8,
-		argLen:    0,
-		zeroWidth: true,
-		generic:   true,
+		name:    "DiffWithRoundWithPrecisionFloat64x8",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:      "ArgFloatReg",
-		auxType:   auxNameOffsetInt8,
-		argLen:    0,
-		zeroWidth: true,
-		generic:   true,
+		name:    "DiffWithRoundWithPrecisionMaskedFloat64x8",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:      "Addr",
-		auxType:   auxSym,
-		argLen:    1,
-		symEffect: SymAddr,
-		generic:   true,
+		name:    "DiffWithTruncWithPrecisionFloat64x8",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:      "LocalAddr",
-		auxType:   auxSym,
-		argLen:    2,
-		symEffect: SymAddr,
-		generic:   true,
+		name:    "DiffWithTruncWithPrecisionMaskedFloat64x8",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:      "SP",
-		argLen:    0,
-		zeroWidth: true,
-		fixedReg:  true,
-		generic:   true,
+		name:    "FloorWithPrecisionFloat64x8",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:      "SB",
-		argLen:    0,
-		zeroWidth: true,
-		fixedReg:  true,
-		generic:   true,
+		name:    "FloorWithPrecisionMaskedFloat64x8",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:      "SPanchored",
-		argLen:    2,
-		zeroWidth: true,
-		generic:   true,
+		name:    "RoundWithPrecisionFloat64x8",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:    "Load",
+		name:    "RoundWithPrecisionMaskedFloat64x8",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Dereference",
-		argLen:  2,
+		name:    "TruncWithPrecisionFloat64x8",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Store",
-		auxType: auxTyp,
-		argLen:  3,
+		name:    "TruncWithPrecisionMaskedFloat64x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Move",
-		auxType: auxTypSize,
-		argLen:  3,
+		name:    "Get128Int16x16",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Zero",
-		auxType: auxTypSize,
+		name:    "Set128Int16x16",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "StoreWB",
-		auxType: auxTyp,
-		argLen:  3,
+		name:    "ShiftAllLeftAndFillUpperFromInt16x16",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "MoveWB",
-		auxType: auxTypSize,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedInt16x16",
+		auxType: auxInt8,
 		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "ZeroWB",
-		auxType: auxTypSize,
+		name:    "ShiftAllRightAndFillUpperFromInt16x16",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "WBend",
-		argLen:  1,
+		name:    "ShiftAllRightAndFillUpperFromMaskedInt16x16",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "WB",
-		auxType: auxInt64,
-		argLen:  1,
+		name:    "ShiftAllLeftAndFillUpperFromInt16x32",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:      "HasCPUFeature",
-		auxType:   auxSym,
-		argLen:    0,
-		symEffect: SymNone,
-		generic:   true,
-	},
-	{
-		name:    "PanicBounds",
-		auxType: auxInt64,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedInt16x32",
+		auxType: auxInt8,
 		argLen:  3,
-		call:    true,
 		generic: true,
 	},
 	{
-		name:    "PanicExtend",
-		auxType: auxInt64,
-		argLen:  4,
-		call:    true,
+		name:    "ShiftAllRightAndFillUpperFromInt16x32",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "ClosureCall",
-		auxType: auxCallOff,
-		argLen:  -1,
-		call:    true,
+		name:    "ShiftAllRightAndFillUpperFromMaskedInt16x32",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "StaticCall",
-		auxType: auxCallOff,
-		argLen:  -1,
-		call:    true,
+		name:    "GetElemInt16x8",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "InterCall",
-		auxType: auxCallOff,
-		argLen:  -1,
-		call:    true,
+		name:    "SetElemInt16x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "TailCall",
-		auxType: auxCallOff,
-		argLen:  -1,
-		call:    true,
+		name:    "ShiftAllLeftAndFillUpperFromInt16x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "ClosureLECall",
-		auxType: auxCallOff,
-		argLen:  -1,
-		call:    true,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedInt16x8",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "StaticLECall",
-		auxType: auxCallOff,
-		argLen:  -1,
-		call:    true,
+		name:    "ShiftAllRightAndFillUpperFromInt16x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "InterLECall",
-		auxType: auxCallOff,
-		argLen:  -1,
-		call:    true,
+		name:    "ShiftAllRightAndFillUpperFromMaskedInt16x8",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "TailLECall",
-		auxType: auxCallOff,
-		argLen:  -1,
-		call:    true,
+		name:    "RotateAllLeftInt32x16",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "SignExt8to16",
-		argLen:  1,
+		name:    "RotateAllLeftMaskedInt32x16",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "SignExt8to32",
+		name:    "RotateAllRightInt32x16",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "SignExt8to64",
-		argLen:  1,
+		name:    "RotateAllRightMaskedInt32x16",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "SignExt16to32",
-		argLen:  1,
+		name:    "ShiftAllLeftAndFillUpperFromInt32x16",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "SignExt16to64",
-		argLen:  1,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedInt32x16",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "SignExt32to64",
-		argLen:  1,
+		name:    "ShiftAllRightAndFillUpperFromInt32x16",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "ZeroExt8to16",
-		argLen:  1,
+		name:    "ShiftAllRightAndFillUpperFromMaskedInt32x16",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "ZeroExt8to32",
+		name:    "GetElemInt32x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "ZeroExt8to64",
+		name:    "RotateAllLeftInt32x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "ZeroExt16to32",
-		argLen:  1,
+		name:    "RotateAllLeftMaskedInt32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "ZeroExt16to64",
+		name:    "RotateAllRightInt32x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "ZeroExt32to64",
-		argLen:  1,
+		name:    "RotateAllRightMaskedInt32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Trunc16to8",
-		argLen:  1,
+		name:    "SetElemInt32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Trunc32to8",
-		argLen:  1,
+		name:    "ShiftAllLeftAndFillUpperFromInt32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Trunc32to16",
-		argLen:  1,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedInt32x4",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Trunc64to8",
-		argLen:  1,
+		name:    "ShiftAllRightAndFillUpperFromInt32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Trunc64to16",
-		argLen:  1,
+		name:    "ShiftAllRightAndFillUpperFromMaskedInt32x4",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Trunc64to32",
+		name:    "Get128Int32x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Cvt32to32F",
+		name:    "RotateAllLeftInt32x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Cvt32to64F",
-		argLen:  1,
+		name:    "RotateAllLeftMaskedInt32x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Cvt64to32F",
+		name:    "RotateAllRightInt32x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Cvt64to64F",
-		argLen:  1,
+		name:    "RotateAllRightMaskedInt32x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Cvt32Fto32",
-		argLen:  1,
+		name:    "Set128Int32x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Cvt32Fto64",
-		argLen:  1,
+		name:    "ShiftAllLeftAndFillUpperFromInt32x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Cvt64Fto32",
-		argLen:  1,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedInt32x8",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Cvt64Fto64",
-		argLen:  1,
+		name:    "ShiftAllRightAndFillUpperFromInt32x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Cvt32Fto64F",
-		argLen:  1,
+		name:    "ShiftAllRightAndFillUpperFromMaskedInt32x8",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Cvt64Fto32F",
+		name:    "GetElemInt64x2",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "CvtBoolToUint8",
+		name:    "RotateAllLeftInt64x2",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Round32F",
-		argLen:  1,
+		name:    "RotateAllLeftMaskedInt64x2",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Round64F",
+		name:    "RotateAllRightInt64x2",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "IsNonNil",
-		argLen:  1,
+		name:    "RotateAllRightMaskedInt64x2",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "IsInBounds",
+		name:    "SetElemInt64x2",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "IsSliceInBounds",
+		name:    "ShiftAllLeftAndFillUpperFromInt64x2",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:     "NilCheck",
-		argLen:   2,
-		nilCheck: true,
-		generic:  true,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedInt64x2",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:      "GetG",
-		argLen:    1,
-		zeroWidth: true,
-		generic:   true,
+		name:    "ShiftAllRightAndFillUpperFromInt64x2",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:    "GetClosurePtr",
-		argLen:  0,
+		name:    "ShiftAllRightAndFillUpperFromMaskedInt64x2",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "GetCallerPC",
-		argLen:  0,
+		name:    "Get128Int64x4",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "GetCallerSP",
+		name:    "RotateAllLeftInt64x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "PtrIndex",
+		name:    "RotateAllLeftMaskedInt64x4",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "OffPtr",
-		auxType: auxInt64,
+		name:    "RotateAllRightInt64x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "SliceMake",
-		argLen:  3,
-		generic: true,
-	},
-	{
-		name:    "SlicePtr",
-		argLen:  1,
+		name:    "RotateAllRightMaskedInt64x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "SliceLen",
-		argLen:  1,
+		name:    "Set128Int64x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "SliceCap",
-		argLen:  1,
+		name:    "ShiftAllLeftAndFillUpperFromInt64x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "SlicePtrUnchecked",
-		argLen:  1,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedInt64x4",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "ComplexMake",
+		name:    "ShiftAllRightAndFillUpperFromInt64x4",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "ComplexReal",
-		argLen:  1,
+		name:    "ShiftAllRightAndFillUpperFromMaskedInt64x4",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "ComplexImag",
+		name:    "RotateAllLeftInt64x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "StringMake",
+		name:    "RotateAllLeftMaskedInt64x8",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "StringPtr",
+		name:    "RotateAllRightInt64x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "StringLen",
-		argLen:  1,
+		name:    "RotateAllRightMaskedInt64x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "IMake",
+		name:    "ShiftAllLeftAndFillUpperFromInt64x8",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "ITab",
-		argLen:  1,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedInt64x8",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "IData",
-		argLen:  1,
+		name:    "ShiftAllRightAndFillUpperFromInt64x8",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "StructMake",
-		argLen:  -1,
+		name:    "ShiftAllRightAndFillUpperFromMaskedInt64x8",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "StructSelect",
-		auxType: auxInt64,
+		name:    "GetElemInt8x16",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "ArrayMake0",
-		argLen:  0,
+		name:    "SetElemInt8x16",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "ArrayMake1",
+		name:    "Get128Int8x32",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "ArraySelect",
-		auxType: auxInt64,
-		argLen:  1,
+		name:    "Set128Int8x32",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "StoreReg",
+		name:    "Get128Uint16x16",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "LoadReg",
-		argLen:  1,
+		name:    "Set128Uint16x16",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:      "FwdRef",
-		auxType:   auxSym,
-		argLen:    0,
-		symEffect: SymNone,
-		generic:   true,
+		name:    "ShiftAllLeftAndFillUpperFromUint16x16",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:    "Unknown",
-		argLen:  0,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedUint16x16",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:      "VarDef",
-		auxType:   auxSym,
-		argLen:    1,
-		zeroWidth: true,
-		symEffect: SymNone,
-		generic:   true,
+		name:    "ShiftAllRightAndFillUpperFromUint16x16",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:      "VarLive",
-		auxType:   auxSym,
-		argLen:    1,
-		zeroWidth: true,
-		symEffect: SymRead,
-		generic:   true,
+		name:    "ShiftAllRightAndFillUpperFromMaskedUint16x16",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:      "KeepAlive",
-		argLen:    2,
-		zeroWidth: true,
-		generic:   true,
+		name:    "ShiftAllLeftAndFillUpperFromUint16x32",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:    "InlMark",
-		auxType: auxInt32,
-		argLen:  1,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedUint16x32",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Int64Make",
+		name:    "ShiftAllRightAndFillUpperFromUint16x32",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Int64Hi",
-		argLen:  1,
+		name:    "ShiftAllRightAndFillUpperFromMaskedUint16x32",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Int64Lo",
+		name:    "GetElemUint16x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:        "Add32carry",
-		argLen:      2,
-		commutative: true,
-		generic:     true,
-	},
-	{
-		name:        "Add32withcarry",
-		argLen:      3,
-		commutative: true,
-		generic:     true,
+		name:    "SetElemUint16x8",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:    "Sub32carry",
+		name:    "ShiftAllLeftAndFillUpperFromUint16x8",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Sub32withcarry",
+		name:    "ShiftAllLeftAndFillUpperFromMaskedUint16x8",
+		auxType: auxInt8,
 		argLen:  3,
 		generic: true,
 	},
 	{
-		name:        "Add64carry",
-		argLen:      3,
-		commutative: true,
-		generic:     true,
+		name:    "ShiftAllRightAndFillUpperFromUint16x8",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:    "Sub64borrow",
+		name:    "ShiftAllRightAndFillUpperFromMaskedUint16x8",
+		auxType: auxInt8,
 		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Signmask",
+		name:    "RotateAllLeftUint32x16",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Zeromask",
-		argLen:  1,
+		name:    "RotateAllLeftMaskedUint32x16",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Slicemask",
+		name:    "RotateAllRightUint32x16",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "SpectreIndex",
+		name:    "RotateAllRightMaskedUint32x16",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "SpectreSliceIndex",
+		name:    "ShiftAllLeftAndFillUpperFromUint32x16",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Cvt32Uto32F",
-		argLen:  1,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedUint32x16",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Cvt32Uto64F",
-		argLen:  1,
+		name:    "ShiftAllRightAndFillUpperFromUint32x16",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Cvt32Fto32U",
-		argLen:  1,
+		name:    "ShiftAllRightAndFillUpperFromMaskedUint32x16",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "Cvt64Fto32U",
+		name:    "GetElemUint32x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Cvt64Uto32F",
+		name:    "RotateAllLeftUint32x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Cvt64Uto64F",
-		argLen:  1,
+		name:    "RotateAllLeftMaskedUint32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "Cvt32Fto64U",
+		name:    "RotateAllRightUint32x4",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "Cvt64Fto64U",
-		argLen:  1,
+		name:    "RotateAllRightMaskedUint32x4",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:      "Select0",
-		argLen:    1,
-		zeroWidth: true,
-		generic:   true,
+		name:    "SetElemUint32x4",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:      "Select1",
-		argLen:    1,
-		zeroWidth: true,
-		generic:   true,
+		name:    "ShiftAllLeftAndFillUpperFromUint32x4",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:    "MakeTuple",
+		name:    "ShiftAllLeftAndFillUpperFromMaskedUint32x4",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightAndFillUpperFromUint32x4",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "SelectN",
-		auxType: auxInt64,
-		argLen:  1,
+		name:    "ShiftAllRightAndFillUpperFromMaskedUint32x4",
+		auxType: auxInt8,
+		argLen:  3,
 		generic: true,
 	},
 	{
-		name:    "SelectNAddr",
-		auxType: auxInt64,
+		name:    "Get128Uint32x8",
+		auxType: auxInt8,
 		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "MakeResult",
-		argLen:  -1,
+		name:    "RotateAllLeftUint32x8",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "AtomicLoad8",
+		name:    "RotateAllLeftMaskedUint32x8",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "AtomicLoad32",
-		argLen:  2,
+		name:    "RotateAllRightUint32x8",
+		auxType: auxInt8,
+		argLen:  1,
 		generic: true,
 	},
 	{
-		name:    "AtomicLoad64",
+		name:    "RotateAllRightMaskedUint32x8",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "AtomicLoadPtr",
+		name:    "Set128Uint32x8",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "AtomicLoadAcq32",
+		name:    "ShiftAllLeftAndFillUpperFromUint32x8",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:    "AtomicLoadAcq64",
+		name:    "ShiftAllLeftAndFillUpperFromMaskedUint32x8",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
+	},
+	{
+		name:    "ShiftAllRightAndFillUpperFromUint32x8",
+		auxType: auxInt8,
 		argLen:  2,
 		generic: true,
 	},
 	{
-		name:           "AtomicStore8",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "ShiftAllRightAndFillUpperFromMaskedUint32x8",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:           "AtomicStore32",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "GetElemUint64x2",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:           "AtomicStore64",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "RotateAllLeftUint64x2",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:           "AtomicStorePtrNoWB",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "RotateAllLeftMaskedUint64x2",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicStoreRel32",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "RotateAllRightUint64x2",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:           "AtomicStoreRel64",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "RotateAllRightMaskedUint64x2",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicExchange8",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "SetElemUint64x2",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicExchange32",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "ShiftAllLeftAndFillUpperFromUint64x2",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicExchange64",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedUint64x2",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:           "AtomicAdd32",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "ShiftAllRightAndFillUpperFromUint64x2",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicAdd64",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "ShiftAllRightAndFillUpperFromMaskedUint64x2",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:           "AtomicCompareAndSwap32",
-		argLen:         4,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "Get128Uint64x4",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:           "AtomicCompareAndSwap64",
-		argLen:         4,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "RotateAllLeftUint64x4",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:           "AtomicCompareAndSwapRel32",
-		argLen:         4,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "RotateAllLeftMaskedUint64x4",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicAnd8",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "RotateAllRightUint64x4",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:           "AtomicOr8",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "RotateAllRightMaskedUint64x4",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicAnd32",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "Set128Uint64x4",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicOr32",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "ShiftAllLeftAndFillUpperFromUint64x4",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicAnd64value",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedUint64x4",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:           "AtomicAnd32value",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "ShiftAllRightAndFillUpperFromUint64x4",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicAnd8value",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "ShiftAllRightAndFillUpperFromMaskedUint64x4",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:           "AtomicOr64value",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "RotateAllLeftUint64x8",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:           "AtomicOr32value",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "RotateAllLeftMaskedUint64x8",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicOr8value",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "RotateAllRightUint64x8",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:           "AtomicStore8Variant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "RotateAllRightMaskedUint64x8",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicStore32Variant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "ShiftAllLeftAndFillUpperFromUint64x8",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicStore64Variant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "ShiftAllLeftAndFillUpperFromMaskedUint64x8",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:           "AtomicAdd32Variant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "ShiftAllRightAndFillUpperFromUint64x8",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicAdd64Variant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "ShiftAllRightAndFillUpperFromMaskedUint64x8",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:           "AtomicExchange8Variant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "GaloisFieldAffineTransformUint8x16",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicExchange32Variant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "GaloisFieldAffineTransformInverseUint8x16",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicExchange64Variant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "GaloisFieldAffineTransformInverseMaskedUint8x16",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:           "AtomicCompareAndSwap32Variant",
-		argLen:         4,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "GaloisFieldAffineTransformMaskedUint8x16",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:           "AtomicCompareAndSwap64Variant",
-		argLen:         4,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "GetElemUint8x16",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:           "AtomicAnd64valueVariant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "SetElemUint8x16",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicOr64valueVariant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "GaloisFieldAffineTransformUint8x32",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicAnd32valueVariant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "GaloisFieldAffineTransformInverseUint8x32",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:           "AtomicOr32valueVariant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "GaloisFieldAffineTransformInverseMaskedUint8x32",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:           "AtomicAnd8valueVariant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "GaloisFieldAffineTransformMaskedUint8x32",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:           "AtomicOr8valueVariant",
-		argLen:         3,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "Get128Uint8x32",
+		auxType: auxInt8,
+		argLen:  1,
+		generic: true,
 	},
 	{
-		name:           "PubBarrier",
-		argLen:         1,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "Set128Uint8x32",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:      "Clobber",
-		auxType:   auxSymOff,
-		argLen:    0,
-		symEffect: SymNone,
-		generic:   true,
+		name:    "GaloisFieldAffineTransformUint8x64",
+		auxType: auxInt8,
+		argLen:  2,
+		generic: true,
 	},
 	{
-		name:    "ClobberReg",
-		argLen:  0,
+		name:    "GaloisFieldAffineTransformInverseUint8x64",
+		auxType: auxInt8,
+		argLen:  2,
 		generic: true,
 	},
 	{
-		name:           "PrefetchCache",
-		argLen:         2,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "GaloisFieldAffineTransformInverseMaskedUint8x64",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 	{
-		name:           "PrefetchCacheStreamed",
-		argLen:         2,
-		hasSideEffects: true,
-		generic:        true,
+		name:    "GaloisFieldAffineTransformMaskedUint8x64",
+		auxType: auxInt8,
+		argLen:  3,
+		generic: true,
 	},
 }
 
@@ -42747,13 +70522,37 @@ var registersAMD64 = [...]Register{
 	{29, x86.REG_X13, "X13"},
 	{30, x86.REG_X14, "X14"},
 	{31, x86.REG_X15, "X15"},
-	{32, 0, "SB"},
+	{32, x86.REG_X16, "X16"},
+	{33, x86.REG_X17, "X17"},
+	{34, x86.REG_X18, "X18"},
+	{35, x86.REG_X19, "X19"},
+	{36, x86.REG_X20, "X20"},
+	{37, x86.REG_X21, "X21"},
+	{38, x86.REG_X22, "X22"},
+	{39, x86.REG_X23, "X23"},
+	{40, x86.REG_X24, "X24"},
+	{41, x86.REG_X25, "X25"},
+	{42, x86.REG_X26, "X26"},
+	{43, x86.REG_X27, "X27"},
+	{44, x86.REG_X28, "X28"},
+	{45, x86.REG_X29, "X29"},
+	{46, x86.REG_X30, "X30"},
+	{47, x86.REG_X31, "X31"},
+	{48, x86.REG_K0, "K0"},
+	{49, x86.REG_K1, "K1"},
+	{50, x86.REG_K2, "K2"},
+	{51, x86.REG_K3, "K3"},
+	{52, x86.REG_K4, "K4"},
+	{53, x86.REG_K5, "K5"},
+	{54, x86.REG_K6, "K6"},
+	{55, x86.REG_K7, "K7"},
+	{56, 0, "SB"},
 }
 var paramIntRegAMD64 = []int8{0, 3, 1, 7, 6, 8, 9, 10, 11}
 var paramFloatRegAMD64 = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30}
 var gpRegMaskAMD64 = regMask(49135)
 var fpRegMaskAMD64 = regMask(2147418112)
-var specialRegMaskAMD64 = regMask(2147483648)
+var specialRegMaskAMD64 = regMask(71494646231990272)
 var framepointerRegAMD64 = int8(5)
 var linkRegAMD64 = int8(-1)
 var registersARM = [...]Register{
diff --git a/src/cmd/compile/internal/ssa/regalloc.go b/src/cmd/compile/internal/ssa/regalloc.go
index f1e210fe9b8b08..d4ce7a815b8b2c 100644
--- a/src/cmd/compile/internal/ssa/regalloc.go
+++ b/src/cmd/compile/internal/ssa/regalloc.go
@@ -898,6 +898,14 @@ func (s *regAllocState) compatRegs(t *types.Type) regMask {
 	if t.IsTuple() || t.IsFlags() {
 		return 0
 	}
+	if t.IsSIMD() {
+		if t.Size() > 8 {
+			return s.f.Config.fpRegMask & s.allocatable
+		} else {
+			// K mask
+			return s.f.Config.gpRegMask & s.allocatable
+		}
+	}
 	if t.IsFloat() || t == types.TypeInt128 {
 		if t.Kind() == types.TFLOAT32 && s.f.Config.fp32RegMask != 0 {
 			m = s.f.Config.fp32RegMask
diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go
index 3d7af5f365a116..5c7cafd6f23697 100644
--- a/src/cmd/compile/internal/ssa/rewriteAMD64.go
+++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go
@@ -501,6 +501,30 @@ func rewriteValueAMD64(v *Value) bool {
 		return rewriteValueAMD64_OpAMD64TESTW(v)
 	case OpAMD64TESTWconst:
 		return rewriteValueAMD64_OpAMD64TESTWconst(v)
+	case OpAMD64VPMOVVec16x16ToM:
+		return rewriteValueAMD64_OpAMD64VPMOVVec16x16ToM(v)
+	case OpAMD64VPMOVVec16x32ToM:
+		return rewriteValueAMD64_OpAMD64VPMOVVec16x32ToM(v)
+	case OpAMD64VPMOVVec16x8ToM:
+		return rewriteValueAMD64_OpAMD64VPMOVVec16x8ToM(v)
+	case OpAMD64VPMOVVec32x16ToM:
+		return rewriteValueAMD64_OpAMD64VPMOVVec32x16ToM(v)
+	case OpAMD64VPMOVVec32x4ToM:
+		return rewriteValueAMD64_OpAMD64VPMOVVec32x4ToM(v)
+	case OpAMD64VPMOVVec32x8ToM:
+		return rewriteValueAMD64_OpAMD64VPMOVVec32x8ToM(v)
+	case OpAMD64VPMOVVec64x2ToM:
+		return rewriteValueAMD64_OpAMD64VPMOVVec64x2ToM(v)
+	case OpAMD64VPMOVVec64x4ToM:
+		return rewriteValueAMD64_OpAMD64VPMOVVec64x4ToM(v)
+	case OpAMD64VPMOVVec64x8ToM:
+		return rewriteValueAMD64_OpAMD64VPMOVVec64x8ToM(v)
+	case OpAMD64VPMOVVec8x16ToM:
+		return rewriteValueAMD64_OpAMD64VPMOVVec8x16ToM(v)
+	case OpAMD64VPMOVVec8x32ToM:
+		return rewriteValueAMD64_OpAMD64VPMOVVec8x32ToM(v)
+	case OpAMD64VPMOVVec8x64ToM:
+		return rewriteValueAMD64_OpAMD64VPMOVVec8x64ToM(v)
 	case OpAMD64XADDLlock:
 		return rewriteValueAMD64_OpAMD64XADDLlock(v)
 	case OpAMD64XADDQlock:
@@ -529,6 +553,66 @@ func rewriteValueAMD64(v *Value) bool {
 		return rewriteValueAMD64_OpAMD64XORQload(v)
 	case OpAMD64XORQmodify:
 		return rewriteValueAMD64_OpAMD64XORQmodify(v)
+	case OpAbsoluteInt16x16:
+		v.Op = OpAMD64VPABSW256
+		return true
+	case OpAbsoluteInt16x32:
+		v.Op = OpAMD64VPABSW512
+		return true
+	case OpAbsoluteInt16x8:
+		v.Op = OpAMD64VPABSW128
+		return true
+	case OpAbsoluteInt32x16:
+		v.Op = OpAMD64VPABSD512
+		return true
+	case OpAbsoluteInt32x4:
+		v.Op = OpAMD64VPABSD128
+		return true
+	case OpAbsoluteInt32x8:
+		v.Op = OpAMD64VPABSD256
+		return true
+	case OpAbsoluteInt64x2:
+		v.Op = OpAMD64VPABSQ128
+		return true
+	case OpAbsoluteInt64x4:
+		v.Op = OpAMD64VPABSQ256
+		return true
+	case OpAbsoluteInt64x8:
+		v.Op = OpAMD64VPABSQ512
+		return true
+	case OpAbsoluteInt8x16:
+		v.Op = OpAMD64VPABSB128
+		return true
+	case OpAbsoluteInt8x32:
+		v.Op = OpAMD64VPABSB256
+		return true
+	case OpAbsoluteInt8x64:
+		v.Op = OpAMD64VPABSB512
+		return true
+	case OpAbsoluteMaskedInt16x16:
+		return rewriteValueAMD64_OpAbsoluteMaskedInt16x16(v)
+	case OpAbsoluteMaskedInt16x32:
+		return rewriteValueAMD64_OpAbsoluteMaskedInt16x32(v)
+	case OpAbsoluteMaskedInt16x8:
+		return rewriteValueAMD64_OpAbsoluteMaskedInt16x8(v)
+	case OpAbsoluteMaskedInt32x16:
+		return rewriteValueAMD64_OpAbsoluteMaskedInt32x16(v)
+	case OpAbsoluteMaskedInt32x4:
+		return rewriteValueAMD64_OpAbsoluteMaskedInt32x4(v)
+	case OpAbsoluteMaskedInt32x8:
+		return rewriteValueAMD64_OpAbsoluteMaskedInt32x8(v)
+	case OpAbsoluteMaskedInt64x2:
+		return rewriteValueAMD64_OpAbsoluteMaskedInt64x2(v)
+	case OpAbsoluteMaskedInt64x4:
+		return rewriteValueAMD64_OpAbsoluteMaskedInt64x4(v)
+	case OpAbsoluteMaskedInt64x8:
+		return rewriteValueAMD64_OpAbsoluteMaskedInt64x8(v)
+	case OpAbsoluteMaskedInt8x16:
+		return rewriteValueAMD64_OpAbsoluteMaskedInt8x16(v)
+	case OpAbsoluteMaskedInt8x32:
+		return rewriteValueAMD64_OpAbsoluteMaskedInt8x32(v)
+	case OpAbsoluteMaskedInt8x64:
+		return rewriteValueAMD64_OpAbsoluteMaskedInt8x64(v)
 	case OpAdd16:
 		v.Op = OpAMD64ADDL
 		return true
@@ -547,9 +631,171 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpAdd8:
 		v.Op = OpAMD64ADDL
 		return true
+	case OpAddFloat32x16:
+		v.Op = OpAMD64VADDPS512
+		return true
+	case OpAddFloat32x4:
+		v.Op = OpAMD64VADDPS128
+		return true
+	case OpAddFloat32x8:
+		v.Op = OpAMD64VADDPS256
+		return true
+	case OpAddFloat64x2:
+		v.Op = OpAMD64VADDPD128
+		return true
+	case OpAddFloat64x4:
+		v.Op = OpAMD64VADDPD256
+		return true
+	case OpAddFloat64x8:
+		v.Op = OpAMD64VADDPD512
+		return true
+	case OpAddInt16x16:
+		v.Op = OpAMD64VPADDW256
+		return true
+	case OpAddInt16x32:
+		v.Op = OpAMD64VPADDW512
+		return true
+	case OpAddInt16x8:
+		v.Op = OpAMD64VPADDW128
+		return true
+	case OpAddInt32x16:
+		v.Op = OpAMD64VPADDD512
+		return true
+	case OpAddInt32x4:
+		v.Op = OpAMD64VPADDD128
+		return true
+	case OpAddInt32x8:
+		v.Op = OpAMD64VPADDD256
+		return true
+	case OpAddInt64x2:
+		v.Op = OpAMD64VPADDQ128
+		return true
+	case OpAddInt64x4:
+		v.Op = OpAMD64VPADDQ256
+		return true
+	case OpAddInt64x8:
+		v.Op = OpAMD64VPADDQ512
+		return true
+	case OpAddInt8x16:
+		v.Op = OpAMD64VPADDB128
+		return true
+	case OpAddInt8x32:
+		v.Op = OpAMD64VPADDB256
+		return true
+	case OpAddInt8x64:
+		v.Op = OpAMD64VPADDB512
+		return true
+	case OpAddMaskedFloat32x16:
+		return rewriteValueAMD64_OpAddMaskedFloat32x16(v)
+	case OpAddMaskedFloat32x4:
+		return rewriteValueAMD64_OpAddMaskedFloat32x4(v)
+	case OpAddMaskedFloat32x8:
+		return rewriteValueAMD64_OpAddMaskedFloat32x8(v)
+	case OpAddMaskedFloat64x2:
+		return rewriteValueAMD64_OpAddMaskedFloat64x2(v)
+	case OpAddMaskedFloat64x4:
+		return rewriteValueAMD64_OpAddMaskedFloat64x4(v)
+	case OpAddMaskedFloat64x8:
+		return rewriteValueAMD64_OpAddMaskedFloat64x8(v)
+	case OpAddMaskedInt16x16:
+		return rewriteValueAMD64_OpAddMaskedInt16x16(v)
+	case OpAddMaskedInt16x32:
+		return rewriteValueAMD64_OpAddMaskedInt16x32(v)
+	case OpAddMaskedInt16x8:
+		return rewriteValueAMD64_OpAddMaskedInt16x8(v)
+	case OpAddMaskedInt32x16:
+		return rewriteValueAMD64_OpAddMaskedInt32x16(v)
+	case OpAddMaskedInt32x4:
+		return rewriteValueAMD64_OpAddMaskedInt32x4(v)
+	case OpAddMaskedInt32x8:
+		return rewriteValueAMD64_OpAddMaskedInt32x8(v)
+	case OpAddMaskedInt64x2:
+		return rewriteValueAMD64_OpAddMaskedInt64x2(v)
+	case OpAddMaskedInt64x4:
+		return rewriteValueAMD64_OpAddMaskedInt64x4(v)
+	case OpAddMaskedInt64x8:
+		return rewriteValueAMD64_OpAddMaskedInt64x8(v)
+	case OpAddMaskedInt8x16:
+		return rewriteValueAMD64_OpAddMaskedInt8x16(v)
+	case OpAddMaskedInt8x32:
+		return rewriteValueAMD64_OpAddMaskedInt8x32(v)
+	case OpAddMaskedInt8x64:
+		return rewriteValueAMD64_OpAddMaskedInt8x64(v)
+	case OpAddMaskedUint16x16:
+		return rewriteValueAMD64_OpAddMaskedUint16x16(v)
+	case OpAddMaskedUint16x32:
+		return rewriteValueAMD64_OpAddMaskedUint16x32(v)
+	case OpAddMaskedUint16x8:
+		return rewriteValueAMD64_OpAddMaskedUint16x8(v)
+	case OpAddMaskedUint32x16:
+		return rewriteValueAMD64_OpAddMaskedUint32x16(v)
+	case OpAddMaskedUint32x4:
+		return rewriteValueAMD64_OpAddMaskedUint32x4(v)
+	case OpAddMaskedUint32x8:
+		return rewriteValueAMD64_OpAddMaskedUint32x8(v)
+	case OpAddMaskedUint64x2:
+		return rewriteValueAMD64_OpAddMaskedUint64x2(v)
+	case OpAddMaskedUint64x4:
+		return rewriteValueAMD64_OpAddMaskedUint64x4(v)
+	case OpAddMaskedUint64x8:
+		return rewriteValueAMD64_OpAddMaskedUint64x8(v)
+	case OpAddMaskedUint8x16:
+		return rewriteValueAMD64_OpAddMaskedUint8x16(v)
+	case OpAddMaskedUint8x32:
+		return rewriteValueAMD64_OpAddMaskedUint8x32(v)
+	case OpAddMaskedUint8x64:
+		return rewriteValueAMD64_OpAddMaskedUint8x64(v)
 	case OpAddPtr:
 		v.Op = OpAMD64ADDQ
 		return true
+	case OpAddSubFloat32x4:
+		v.Op = OpAMD64VADDSUBPS128
+		return true
+	case OpAddSubFloat32x8:
+		v.Op = OpAMD64VADDSUBPS256
+		return true
+	case OpAddSubFloat64x2:
+		v.Op = OpAMD64VADDSUBPD128
+		return true
+	case OpAddSubFloat64x4:
+		v.Op = OpAMD64VADDSUBPD256
+		return true
+	case OpAddUint16x16:
+		v.Op = OpAMD64VPADDW256
+		return true
+	case OpAddUint16x32:
+		v.Op = OpAMD64VPADDW512
+		return true
+	case OpAddUint16x8:
+		v.Op = OpAMD64VPADDW128
+		return true
+	case OpAddUint32x16:
+		v.Op = OpAMD64VPADDD512
+		return true
+	case OpAddUint32x4:
+		v.Op = OpAMD64VPADDD128
+		return true
+	case OpAddUint32x8:
+		v.Op = OpAMD64VPADDD256
+		return true
+	case OpAddUint64x2:
+		v.Op = OpAMD64VPADDQ128
+		return true
+	case OpAddUint64x4:
+		v.Op = OpAMD64VPADDQ256
+		return true
+	case OpAddUint64x8:
+		v.Op = OpAMD64VPADDQ512
+		return true
+	case OpAddUint8x16:
+		v.Op = OpAMD64VPADDB128
+		return true
+	case OpAddUint8x32:
+		v.Op = OpAMD64VPADDB256
+		return true
+	case OpAddUint8x64:
+		v.Op = OpAMD64VPADDB512
+		return true
 	case OpAddr:
 		return rewriteValueAMD64_OpAddr(v)
 	case OpAnd16:
@@ -567,6 +813,234 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpAndB:
 		v.Op = OpAMD64ANDL
 		return true
+	case OpAndInt16x16:
+		v.Op = OpAMD64VPAND256
+		return true
+	case OpAndInt16x8:
+		v.Op = OpAMD64VPAND128
+		return true
+	case OpAndInt32x16:
+		v.Op = OpAMD64VPANDD512
+		return true
+	case OpAndInt32x4:
+		v.Op = OpAMD64VPAND128
+		return true
+	case OpAndInt32x8:
+		v.Op = OpAMD64VPAND256
+		return true
+	case OpAndInt64x2:
+		v.Op = OpAMD64VPAND128
+		return true
+	case OpAndInt64x4:
+		v.Op = OpAMD64VPAND256
+		return true
+	case OpAndInt64x8:
+		v.Op = OpAMD64VPANDQ512
+		return true
+	case OpAndInt8x16:
+		v.Op = OpAMD64VPAND128
+		return true
+	case OpAndInt8x32:
+		v.Op = OpAMD64VPAND256
+		return true
+	case OpAndMaskedInt32x16:
+		return rewriteValueAMD64_OpAndMaskedInt32x16(v)
+	case OpAndMaskedInt32x4:
+		return rewriteValueAMD64_OpAndMaskedInt32x4(v)
+	case OpAndMaskedInt32x8:
+		return rewriteValueAMD64_OpAndMaskedInt32x8(v)
+	case OpAndMaskedInt64x2:
+		return rewriteValueAMD64_OpAndMaskedInt64x2(v)
+	case OpAndMaskedInt64x4:
+		return rewriteValueAMD64_OpAndMaskedInt64x4(v)
+	case OpAndMaskedInt64x8:
+		return rewriteValueAMD64_OpAndMaskedInt64x8(v)
+	case OpAndMaskedUint32x16:
+		return rewriteValueAMD64_OpAndMaskedUint32x16(v)
+	case OpAndMaskedUint32x4:
+		return rewriteValueAMD64_OpAndMaskedUint32x4(v)
+	case OpAndMaskedUint32x8:
+		return rewriteValueAMD64_OpAndMaskedUint32x8(v)
+	case OpAndMaskedUint64x2:
+		return rewriteValueAMD64_OpAndMaskedUint64x2(v)
+	case OpAndMaskedUint64x4:
+		return rewriteValueAMD64_OpAndMaskedUint64x4(v)
+	case OpAndMaskedUint64x8:
+		return rewriteValueAMD64_OpAndMaskedUint64x8(v)
+	case OpAndNotInt16x16:
+		v.Op = OpAMD64VPANDN256
+		return true
+	case OpAndNotInt16x8:
+		v.Op = OpAMD64VPANDN128
+		return true
+	case OpAndNotInt32x16:
+		v.Op = OpAMD64VPANDND512
+		return true
+	case OpAndNotInt32x4:
+		v.Op = OpAMD64VPANDN128
+		return true
+	case OpAndNotInt32x8:
+		v.Op = OpAMD64VPANDN256
+		return true
+	case OpAndNotInt64x2:
+		v.Op = OpAMD64VPANDN128
+		return true
+	case OpAndNotInt64x4:
+		v.Op = OpAMD64VPANDN256
+		return true
+	case OpAndNotInt64x8:
+		v.Op = OpAMD64VPANDNQ512
+		return true
+	case OpAndNotInt8x16:
+		v.Op = OpAMD64VPANDN128
+		return true
+	case OpAndNotInt8x32:
+		v.Op = OpAMD64VPANDN256
+		return true
+	case OpAndNotMaskedInt32x16:
+		return rewriteValueAMD64_OpAndNotMaskedInt32x16(v)
+	case OpAndNotMaskedInt32x4:
+		return rewriteValueAMD64_OpAndNotMaskedInt32x4(v)
+	case OpAndNotMaskedInt32x8:
+		return rewriteValueAMD64_OpAndNotMaskedInt32x8(v)
+	case OpAndNotMaskedInt64x2:
+		return rewriteValueAMD64_OpAndNotMaskedInt64x2(v)
+	case OpAndNotMaskedInt64x4:
+		return rewriteValueAMD64_OpAndNotMaskedInt64x4(v)
+	case OpAndNotMaskedInt64x8:
+		return rewriteValueAMD64_OpAndNotMaskedInt64x8(v)
+	case OpAndNotMaskedUint32x16:
+		return rewriteValueAMD64_OpAndNotMaskedUint32x16(v)
+	case OpAndNotMaskedUint32x4:
+		return rewriteValueAMD64_OpAndNotMaskedUint32x4(v)
+	case OpAndNotMaskedUint32x8:
+		return rewriteValueAMD64_OpAndNotMaskedUint32x8(v)
+	case OpAndNotMaskedUint64x2:
+		return rewriteValueAMD64_OpAndNotMaskedUint64x2(v)
+	case OpAndNotMaskedUint64x4:
+		return rewriteValueAMD64_OpAndNotMaskedUint64x4(v)
+	case OpAndNotMaskedUint64x8:
+		return rewriteValueAMD64_OpAndNotMaskedUint64x8(v)
+	case OpAndNotUint16x16:
+		v.Op = OpAMD64VPANDN256
+		return true
+	case OpAndNotUint16x8:
+		v.Op = OpAMD64VPANDN128
+		return true
+	case OpAndNotUint32x16:
+		v.Op = OpAMD64VPANDND512
+		return true
+	case OpAndNotUint32x4:
+		v.Op = OpAMD64VPANDN128
+		return true
+	case OpAndNotUint32x8:
+		v.Op = OpAMD64VPANDN256
+		return true
+	case OpAndNotUint64x2:
+		v.Op = OpAMD64VPANDN128
+		return true
+	case OpAndNotUint64x4:
+		v.Op = OpAMD64VPANDN256
+		return true
+	case OpAndNotUint64x8:
+		v.Op = OpAMD64VPANDNQ512
+		return true
+	case OpAndNotUint8x16:
+		v.Op = OpAMD64VPANDN128
+		return true
+	case OpAndNotUint8x32:
+		v.Op = OpAMD64VPANDN256
+		return true
+	case OpAndUint16x16:
+		v.Op = OpAMD64VPAND256
+		return true
+	case OpAndUint16x8:
+		v.Op = OpAMD64VPAND128
+		return true
+	case OpAndUint32x16:
+		v.Op = OpAMD64VPANDD512
+		return true
+	case OpAndUint32x4:
+		v.Op = OpAMD64VPAND128
+		return true
+	case OpAndUint32x8:
+		v.Op = OpAMD64VPAND256
+		return true
+	case OpAndUint64x2:
+		v.Op = OpAMD64VPAND128
+		return true
+	case OpAndUint64x4:
+		v.Op = OpAMD64VPAND256
+		return true
+	case OpAndUint64x8:
+		v.Op = OpAMD64VPANDQ512
+		return true
+	case OpAndUint8x16:
+		v.Op = OpAMD64VPAND128
+		return true
+	case OpAndUint8x32:
+		v.Op = OpAMD64VPAND256
+		return true
+	case OpApproximateReciprocalFloat32x16:
+		v.Op = OpAMD64VRCP14PS512
+		return true
+	case OpApproximateReciprocalFloat32x4:
+		v.Op = OpAMD64VRCP14PS128
+		return true
+	case OpApproximateReciprocalFloat32x8:
+		v.Op = OpAMD64VRCP14PS256
+		return true
+	case OpApproximateReciprocalFloat64x2:
+		v.Op = OpAMD64VRCP14PD128
+		return true
+	case OpApproximateReciprocalFloat64x4:
+		v.Op = OpAMD64VRCP14PD256
+		return true
+	case OpApproximateReciprocalFloat64x8:
+		v.Op = OpAMD64VRCP14PD512
+		return true
+	case OpApproximateReciprocalMaskedFloat32x16:
+		return rewriteValueAMD64_OpApproximateReciprocalMaskedFloat32x16(v)
+	case OpApproximateReciprocalMaskedFloat32x4:
+		return rewriteValueAMD64_OpApproximateReciprocalMaskedFloat32x4(v)
+	case OpApproximateReciprocalMaskedFloat32x8:
+		return rewriteValueAMD64_OpApproximateReciprocalMaskedFloat32x8(v)
+	case OpApproximateReciprocalMaskedFloat64x2:
+		return rewriteValueAMD64_OpApproximateReciprocalMaskedFloat64x2(v)
+	case OpApproximateReciprocalMaskedFloat64x4:
+		return rewriteValueAMD64_OpApproximateReciprocalMaskedFloat64x4(v)
+	case OpApproximateReciprocalMaskedFloat64x8:
+		return rewriteValueAMD64_OpApproximateReciprocalMaskedFloat64x8(v)
+	case OpApproximateReciprocalOfSqrtFloat32x16:
+		v.Op = OpAMD64VRSQRT14PS512
+		return true
+	case OpApproximateReciprocalOfSqrtFloat32x4:
+		v.Op = OpAMD64VRSQRTPS128
+		return true
+	case OpApproximateReciprocalOfSqrtFloat32x8:
+		v.Op = OpAMD64VRSQRTPS256
+		return true
+	case OpApproximateReciprocalOfSqrtFloat64x2:
+		v.Op = OpAMD64VRSQRT14PD128
+		return true
+	case OpApproximateReciprocalOfSqrtFloat64x4:
+		v.Op = OpAMD64VRSQRT14PD256
+		return true
+	case OpApproximateReciprocalOfSqrtFloat64x8:
+		v.Op = OpAMD64VRSQRT14PD512
+		return true
+	case OpApproximateReciprocalOfSqrtMaskedFloat32x16:
+		return rewriteValueAMD64_OpApproximateReciprocalOfSqrtMaskedFloat32x16(v)
+	case OpApproximateReciprocalOfSqrtMaskedFloat32x4:
+		return rewriteValueAMD64_OpApproximateReciprocalOfSqrtMaskedFloat32x4(v)
+	case OpApproximateReciprocalOfSqrtMaskedFloat32x8:
+		return rewriteValueAMD64_OpApproximateReciprocalOfSqrtMaskedFloat32x8(v)
+	case OpApproximateReciprocalOfSqrtMaskedFloat64x2:
+		return rewriteValueAMD64_OpApproximateReciprocalOfSqrtMaskedFloat64x2(v)
+	case OpApproximateReciprocalOfSqrtMaskedFloat64x4:
+		return rewriteValueAMD64_OpApproximateReciprocalOfSqrtMaskedFloat64x4(v)
+	case OpApproximateReciprocalOfSqrtMaskedFloat64x8:
+		return rewriteValueAMD64_OpApproximateReciprocalOfSqrtMaskedFloat64x8(v)
 	case OpAtomicAdd32:
 		return rewriteValueAMD64_OpAtomicAdd32(v)
 	case OpAtomicAdd64:
@@ -613,6 +1087,36 @@ func rewriteValueAMD64(v *Value) bool {
 		return rewriteValueAMD64_OpAtomicStore8(v)
 	case OpAtomicStorePtrNoWB:
 		return rewriteValueAMD64_OpAtomicStorePtrNoWB(v)
+	case OpAverageMaskedUint16x16:
+		return rewriteValueAMD64_OpAverageMaskedUint16x16(v)
+	case OpAverageMaskedUint16x32:
+		return rewriteValueAMD64_OpAverageMaskedUint16x32(v)
+	case OpAverageMaskedUint16x8:
+		return rewriteValueAMD64_OpAverageMaskedUint16x8(v)
+	case OpAverageMaskedUint8x16:
+		return rewriteValueAMD64_OpAverageMaskedUint8x16(v)
+	case OpAverageMaskedUint8x32:
+		return rewriteValueAMD64_OpAverageMaskedUint8x32(v)
+	case OpAverageMaskedUint8x64:
+		return rewriteValueAMD64_OpAverageMaskedUint8x64(v)
+	case OpAverageUint16x16:
+		v.Op = OpAMD64VPAVGW256
+		return true
+	case OpAverageUint16x32:
+		v.Op = OpAMD64VPAVGW512
+		return true
+	case OpAverageUint16x8:
+		v.Op = OpAMD64VPAVGW128
+		return true
+	case OpAverageUint8x16:
+		v.Op = OpAMD64VPAVGB128
+		return true
+	case OpAverageUint8x32:
+		v.Op = OpAMD64VPAVGB256
+		return true
+	case OpAverageUint8x64:
+		v.Op = OpAMD64VPAVGB512
+		return true
 	case OpAvg64u:
 		v.Op = OpAMD64AVGQU
 		return true
@@ -634,6 +1138,38 @@ func rewriteValueAMD64(v *Value) bool {
 		return true
 	case OpCeil:
 		return rewriteValueAMD64_OpCeil(v)
+	case OpCeilFloat32x4:
+		return rewriteValueAMD64_OpCeilFloat32x4(v)
+	case OpCeilFloat32x8:
+		return rewriteValueAMD64_OpCeilFloat32x8(v)
+	case OpCeilFloat64x2:
+		return rewriteValueAMD64_OpCeilFloat64x2(v)
+	case OpCeilFloat64x4:
+		return rewriteValueAMD64_OpCeilFloat64x4(v)
+	case OpCeilWithPrecisionFloat32x16:
+		return rewriteValueAMD64_OpCeilWithPrecisionFloat32x16(v)
+	case OpCeilWithPrecisionFloat32x4:
+		return rewriteValueAMD64_OpCeilWithPrecisionFloat32x4(v)
+	case OpCeilWithPrecisionFloat32x8:
+		return rewriteValueAMD64_OpCeilWithPrecisionFloat32x8(v)
+	case OpCeilWithPrecisionFloat64x2:
+		return rewriteValueAMD64_OpCeilWithPrecisionFloat64x2(v)
+	case OpCeilWithPrecisionFloat64x4:
+		return rewriteValueAMD64_OpCeilWithPrecisionFloat64x4(v)
+	case OpCeilWithPrecisionFloat64x8:
+		return rewriteValueAMD64_OpCeilWithPrecisionFloat64x8(v)
+	case OpCeilWithPrecisionMaskedFloat32x16:
+		return rewriteValueAMD64_OpCeilWithPrecisionMaskedFloat32x16(v)
+	case OpCeilWithPrecisionMaskedFloat32x4:
+		return rewriteValueAMD64_OpCeilWithPrecisionMaskedFloat32x4(v)
+	case OpCeilWithPrecisionMaskedFloat32x8:
+		return rewriteValueAMD64_OpCeilWithPrecisionMaskedFloat32x8(v)
+	case OpCeilWithPrecisionMaskedFloat64x2:
+		return rewriteValueAMD64_OpCeilWithPrecisionMaskedFloat64x2(v)
+	case OpCeilWithPrecisionMaskedFloat64x4:
+		return rewriteValueAMD64_OpCeilWithPrecisionMaskedFloat64x4(v)
+	case OpCeilWithPrecisionMaskedFloat64x8:
+		return rewriteValueAMD64_OpCeilWithPrecisionMaskedFloat64x8(v)
 	case OpClosureCall:
 		v.Op = OpAMD64CALLclosure
 		return true
@@ -649,6 +1185,66 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpCom8:
 		v.Op = OpAMD64NOTL
 		return true
+	case OpCompressFloat32x16:
+		return rewriteValueAMD64_OpCompressFloat32x16(v)
+	case OpCompressFloat32x4:
+		return rewriteValueAMD64_OpCompressFloat32x4(v)
+	case OpCompressFloat32x8:
+		return rewriteValueAMD64_OpCompressFloat32x8(v)
+	case OpCompressFloat64x2:
+		return rewriteValueAMD64_OpCompressFloat64x2(v)
+	case OpCompressFloat64x4:
+		return rewriteValueAMD64_OpCompressFloat64x4(v)
+	case OpCompressFloat64x8:
+		return rewriteValueAMD64_OpCompressFloat64x8(v)
+	case OpCompressInt16x16:
+		return rewriteValueAMD64_OpCompressInt16x16(v)
+	case OpCompressInt16x32:
+		return rewriteValueAMD64_OpCompressInt16x32(v)
+	case OpCompressInt16x8:
+		return rewriteValueAMD64_OpCompressInt16x8(v)
+	case OpCompressInt32x16:
+		return rewriteValueAMD64_OpCompressInt32x16(v)
+	case OpCompressInt32x4:
+		return rewriteValueAMD64_OpCompressInt32x4(v)
+	case OpCompressInt32x8:
+		return rewriteValueAMD64_OpCompressInt32x8(v)
+	case OpCompressInt64x2:
+		return rewriteValueAMD64_OpCompressInt64x2(v)
+	case OpCompressInt64x4:
+		return rewriteValueAMD64_OpCompressInt64x4(v)
+	case OpCompressInt64x8:
+		return rewriteValueAMD64_OpCompressInt64x8(v)
+	case OpCompressInt8x16:
+		return rewriteValueAMD64_OpCompressInt8x16(v)
+	case OpCompressInt8x32:
+		return rewriteValueAMD64_OpCompressInt8x32(v)
+	case OpCompressInt8x64:
+		return rewriteValueAMD64_OpCompressInt8x64(v)
+	case OpCompressUint16x16:
+		return rewriteValueAMD64_OpCompressUint16x16(v)
+	case OpCompressUint16x32:
+		return rewriteValueAMD64_OpCompressUint16x32(v)
+	case OpCompressUint16x8:
+		return rewriteValueAMD64_OpCompressUint16x8(v)
+	case OpCompressUint32x16:
+		return rewriteValueAMD64_OpCompressUint32x16(v)
+	case OpCompressUint32x4:
+		return rewriteValueAMD64_OpCompressUint32x4(v)
+	case OpCompressUint32x8:
+		return rewriteValueAMD64_OpCompressUint32x8(v)
+	case OpCompressUint64x2:
+		return rewriteValueAMD64_OpCompressUint64x2(v)
+	case OpCompressUint64x4:
+		return rewriteValueAMD64_OpCompressUint64x4(v)
+	case OpCompressUint64x8:
+		return rewriteValueAMD64_OpCompressUint64x8(v)
+	case OpCompressUint8x16:
+		return rewriteValueAMD64_OpCompressUint8x16(v)
+	case OpCompressUint8x32:
+		return rewriteValueAMD64_OpCompressUint8x32(v)
+	case OpCompressUint8x64:
+		return rewriteValueAMD64_OpCompressUint8x64(v)
 	case OpCondSelect:
 		return rewriteValueAMD64_OpCondSelect(v)
 	case OpConst16:
@@ -720,6 +1316,102 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpCvtBoolToUint8:
 		v.Op = OpCopy
 		return true
+	case OpDiffWithCeilWithPrecisionFloat32x16:
+		return rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat32x16(v)
+	case OpDiffWithCeilWithPrecisionFloat32x4:
+		return rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat32x4(v)
+	case OpDiffWithCeilWithPrecisionFloat32x8:
+		return rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat32x8(v)
+	case OpDiffWithCeilWithPrecisionFloat64x2:
+		return rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat64x2(v)
+	case OpDiffWithCeilWithPrecisionFloat64x4:
+		return rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat64x4(v)
+	case OpDiffWithCeilWithPrecisionFloat64x8:
+		return rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat64x8(v)
+	case OpDiffWithCeilWithPrecisionMaskedFloat32x16:
+		return rewriteValueAMD64_OpDiffWithCeilWithPrecisionMaskedFloat32x16(v)
+	case OpDiffWithCeilWithPrecisionMaskedFloat32x4:
+		return rewriteValueAMD64_OpDiffWithCeilWithPrecisionMaskedFloat32x4(v)
+	case OpDiffWithCeilWithPrecisionMaskedFloat32x8:
+		return rewriteValueAMD64_OpDiffWithCeilWithPrecisionMaskedFloat32x8(v)
+	case OpDiffWithCeilWithPrecisionMaskedFloat64x2:
+		return rewriteValueAMD64_OpDiffWithCeilWithPrecisionMaskedFloat64x2(v)
+	case OpDiffWithCeilWithPrecisionMaskedFloat64x4:
+		return rewriteValueAMD64_OpDiffWithCeilWithPrecisionMaskedFloat64x4(v)
+	case OpDiffWithCeilWithPrecisionMaskedFloat64x8:
+		return rewriteValueAMD64_OpDiffWithCeilWithPrecisionMaskedFloat64x8(v)
+	case OpDiffWithFloorWithPrecisionFloat32x16:
+		return rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat32x16(v)
+	case OpDiffWithFloorWithPrecisionFloat32x4:
+		return rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat32x4(v)
+	case OpDiffWithFloorWithPrecisionFloat32x8:
+		return rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat32x8(v)
+	case OpDiffWithFloorWithPrecisionFloat64x2:
+		return rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat64x2(v)
+	case OpDiffWithFloorWithPrecisionFloat64x4:
+		return rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat64x4(v)
+	case OpDiffWithFloorWithPrecisionFloat64x8:
+		return rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat64x8(v)
+	case OpDiffWithFloorWithPrecisionMaskedFloat32x16:
+		return rewriteValueAMD64_OpDiffWithFloorWithPrecisionMaskedFloat32x16(v)
+	case OpDiffWithFloorWithPrecisionMaskedFloat32x4:
+		return rewriteValueAMD64_OpDiffWithFloorWithPrecisionMaskedFloat32x4(v)
+	case OpDiffWithFloorWithPrecisionMaskedFloat32x8:
+		return rewriteValueAMD64_OpDiffWithFloorWithPrecisionMaskedFloat32x8(v)
+	case OpDiffWithFloorWithPrecisionMaskedFloat64x2:
+		return rewriteValueAMD64_OpDiffWithFloorWithPrecisionMaskedFloat64x2(v)
+	case OpDiffWithFloorWithPrecisionMaskedFloat64x4:
+		return rewriteValueAMD64_OpDiffWithFloorWithPrecisionMaskedFloat64x4(v)
+	case OpDiffWithFloorWithPrecisionMaskedFloat64x8:
+		return rewriteValueAMD64_OpDiffWithFloorWithPrecisionMaskedFloat64x8(v)
+	case OpDiffWithRoundWithPrecisionFloat32x16:
+		return rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat32x16(v)
+	case OpDiffWithRoundWithPrecisionFloat32x4:
+		return rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat32x4(v)
+	case OpDiffWithRoundWithPrecisionFloat32x8:
+		return rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat32x8(v)
+	case OpDiffWithRoundWithPrecisionFloat64x2:
+		return rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat64x2(v)
+	case OpDiffWithRoundWithPrecisionFloat64x4:
+		return rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat64x4(v)
+	case OpDiffWithRoundWithPrecisionFloat64x8:
+		return rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat64x8(v)
+	case OpDiffWithRoundWithPrecisionMaskedFloat32x16:
+		return rewriteValueAMD64_OpDiffWithRoundWithPrecisionMaskedFloat32x16(v)
+	case OpDiffWithRoundWithPrecisionMaskedFloat32x4:
+		return rewriteValueAMD64_OpDiffWithRoundWithPrecisionMaskedFloat32x4(v)
+	case OpDiffWithRoundWithPrecisionMaskedFloat32x8:
+		return rewriteValueAMD64_OpDiffWithRoundWithPrecisionMaskedFloat32x8(v)
+	case OpDiffWithRoundWithPrecisionMaskedFloat64x2:
+		return rewriteValueAMD64_OpDiffWithRoundWithPrecisionMaskedFloat64x2(v)
+	case OpDiffWithRoundWithPrecisionMaskedFloat64x4:
+		return rewriteValueAMD64_OpDiffWithRoundWithPrecisionMaskedFloat64x4(v)
+	case OpDiffWithRoundWithPrecisionMaskedFloat64x8:
+		return rewriteValueAMD64_OpDiffWithRoundWithPrecisionMaskedFloat64x8(v)
+	case OpDiffWithTruncWithPrecisionFloat32x16:
+		return rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat32x16(v)
+	case OpDiffWithTruncWithPrecisionFloat32x4:
+		return rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat32x4(v)
+	case OpDiffWithTruncWithPrecisionFloat32x8:
+		return rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat32x8(v)
+	case OpDiffWithTruncWithPrecisionFloat64x2:
+		return rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat64x2(v)
+	case OpDiffWithTruncWithPrecisionFloat64x4:
+		return rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat64x4(v)
+	case OpDiffWithTruncWithPrecisionFloat64x8:
+		return rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat64x8(v)
+	case OpDiffWithTruncWithPrecisionMaskedFloat32x16:
+		return rewriteValueAMD64_OpDiffWithTruncWithPrecisionMaskedFloat32x16(v)
+	case OpDiffWithTruncWithPrecisionMaskedFloat32x4:
+		return rewriteValueAMD64_OpDiffWithTruncWithPrecisionMaskedFloat32x4(v)
+	case OpDiffWithTruncWithPrecisionMaskedFloat32x8:
+		return rewriteValueAMD64_OpDiffWithTruncWithPrecisionMaskedFloat32x8(v)
+	case OpDiffWithTruncWithPrecisionMaskedFloat64x2:
+		return rewriteValueAMD64_OpDiffWithTruncWithPrecisionMaskedFloat64x2(v)
+	case OpDiffWithTruncWithPrecisionMaskedFloat64x4:
+		return rewriteValueAMD64_OpDiffWithTruncWithPrecisionMaskedFloat64x4(v)
+	case OpDiffWithTruncWithPrecisionMaskedFloat64x8:
+		return rewriteValueAMD64_OpDiffWithTruncWithPrecisionMaskedFloat64x8(v)
 	case OpDiv128u:
 		v.Op = OpAMD64DIVQU2
 		return true
@@ -745,6 +1437,42 @@ func rewriteValueAMD64(v *Value) bool {
 		return rewriteValueAMD64_OpDiv8(v)
 	case OpDiv8u:
 		return rewriteValueAMD64_OpDiv8u(v)
+	case OpDivFloat32x16:
+		v.Op = OpAMD64VDIVPS512
+		return true
+	case OpDivFloat32x4:
+		v.Op = OpAMD64VDIVPS128
+		return true
+	case OpDivFloat32x8:
+		v.Op = OpAMD64VDIVPS256
+		return true
+	case OpDivFloat64x2:
+		v.Op = OpAMD64VDIVPD128
+		return true
+	case OpDivFloat64x4:
+		v.Op = OpAMD64VDIVPD256
+		return true
+	case OpDivFloat64x8:
+		v.Op = OpAMD64VDIVPD512
+		return true
+	case OpDivMaskedFloat32x16:
+		return rewriteValueAMD64_OpDivMaskedFloat32x16(v)
+	case OpDivMaskedFloat32x4:
+		return rewriteValueAMD64_OpDivMaskedFloat32x4(v)
+	case OpDivMaskedFloat32x8:
+		return rewriteValueAMD64_OpDivMaskedFloat32x8(v)
+	case OpDivMaskedFloat64x2:
+		return rewriteValueAMD64_OpDivMaskedFloat64x2(v)
+	case OpDivMaskedFloat64x4:
+		return rewriteValueAMD64_OpDivMaskedFloat64x4(v)
+	case OpDivMaskedFloat64x8:
+		return rewriteValueAMD64_OpDivMaskedFloat64x8(v)
+	case OpDotProdBroadcastFloat32x4:
+		return rewriteValueAMD64_OpDotProdBroadcastFloat32x4(v)
+	case OpDotProdBroadcastFloat32x8:
+		return rewriteValueAMD64_OpDotProdBroadcastFloat32x8(v)
+	case OpDotProdBroadcastFloat64x2:
+		return rewriteValueAMD64_OpDotProdBroadcastFloat64x2(v)
 	case OpEq16:
 		return rewriteValueAMD64_OpEq16(v)
 	case OpEq32:
@@ -761,10 +1489,343 @@ func rewriteValueAMD64(v *Value) bool {
 		return rewriteValueAMD64_OpEqB(v)
 	case OpEqPtr:
 		return rewriteValueAMD64_OpEqPtr(v)
+	case OpEqualFloat32x16:
+		return rewriteValueAMD64_OpEqualFloat32x16(v)
+	case OpEqualFloat32x4:
+		return rewriteValueAMD64_OpEqualFloat32x4(v)
+	case OpEqualFloat32x8:
+		return rewriteValueAMD64_OpEqualFloat32x8(v)
+	case OpEqualFloat64x2:
+		return rewriteValueAMD64_OpEqualFloat64x2(v)
+	case OpEqualFloat64x4:
+		return rewriteValueAMD64_OpEqualFloat64x4(v)
+	case OpEqualFloat64x8:
+		return rewriteValueAMD64_OpEqualFloat64x8(v)
+	case OpEqualInt16x16:
+		v.Op = OpAMD64VPCMPEQW256
+		return true
+	case OpEqualInt16x32:
+		return rewriteValueAMD64_OpEqualInt16x32(v)
+	case OpEqualInt16x8:
+		v.Op = OpAMD64VPCMPEQW128
+		return true
+	case OpEqualInt32x16:
+		return rewriteValueAMD64_OpEqualInt32x16(v)
+	case OpEqualInt32x4:
+		v.Op = OpAMD64VPCMPEQD128
+		return true
+	case OpEqualInt32x8:
+		v.Op = OpAMD64VPCMPEQD256
+		return true
+	case OpEqualInt64x2:
+		v.Op = OpAMD64VPCMPEQQ128
+		return true
+	case OpEqualInt64x4:
+		v.Op = OpAMD64VPCMPEQQ256
+		return true
+	case OpEqualInt64x8:
+		return rewriteValueAMD64_OpEqualInt64x8(v)
+	case OpEqualInt8x16:
+		v.Op = OpAMD64VPCMPEQB128
+		return true
+	case OpEqualInt8x32:
+		v.Op = OpAMD64VPCMPEQB256
+		return true
+	case OpEqualInt8x64:
+		return rewriteValueAMD64_OpEqualInt8x64(v)
+	case OpEqualMaskedFloat32x16:
+		return rewriteValueAMD64_OpEqualMaskedFloat32x16(v)
+	case OpEqualMaskedFloat32x4:
+		return rewriteValueAMD64_OpEqualMaskedFloat32x4(v)
+	case OpEqualMaskedFloat32x8:
+		return rewriteValueAMD64_OpEqualMaskedFloat32x8(v)
+	case OpEqualMaskedFloat64x2:
+		return rewriteValueAMD64_OpEqualMaskedFloat64x2(v)
+	case OpEqualMaskedFloat64x4:
+		return rewriteValueAMD64_OpEqualMaskedFloat64x4(v)
+	case OpEqualMaskedFloat64x8:
+		return rewriteValueAMD64_OpEqualMaskedFloat64x8(v)
+	case OpEqualMaskedInt16x16:
+		return rewriteValueAMD64_OpEqualMaskedInt16x16(v)
+	case OpEqualMaskedInt16x32:
+		return rewriteValueAMD64_OpEqualMaskedInt16x32(v)
+	case OpEqualMaskedInt16x8:
+		return rewriteValueAMD64_OpEqualMaskedInt16x8(v)
+	case OpEqualMaskedInt32x16:
+		return rewriteValueAMD64_OpEqualMaskedInt32x16(v)
+	case OpEqualMaskedInt32x4:
+		return rewriteValueAMD64_OpEqualMaskedInt32x4(v)
+	case OpEqualMaskedInt32x8:
+		return rewriteValueAMD64_OpEqualMaskedInt32x8(v)
+	case OpEqualMaskedInt64x2:
+		return rewriteValueAMD64_OpEqualMaskedInt64x2(v)
+	case OpEqualMaskedInt64x4:
+		return rewriteValueAMD64_OpEqualMaskedInt64x4(v)
+	case OpEqualMaskedInt64x8:
+		return rewriteValueAMD64_OpEqualMaskedInt64x8(v)
+	case OpEqualMaskedInt8x16:
+		return rewriteValueAMD64_OpEqualMaskedInt8x16(v)
+	case OpEqualMaskedInt8x32:
+		return rewriteValueAMD64_OpEqualMaskedInt8x32(v)
+	case OpEqualMaskedInt8x64:
+		return rewriteValueAMD64_OpEqualMaskedInt8x64(v)
+	case OpEqualMaskedUint16x16:
+		return rewriteValueAMD64_OpEqualMaskedUint16x16(v)
+	case OpEqualMaskedUint16x32:
+		return rewriteValueAMD64_OpEqualMaskedUint16x32(v)
+	case OpEqualMaskedUint16x8:
+		return rewriteValueAMD64_OpEqualMaskedUint16x8(v)
+	case OpEqualMaskedUint32x16:
+		return rewriteValueAMD64_OpEqualMaskedUint32x16(v)
+	case OpEqualMaskedUint32x4:
+		return rewriteValueAMD64_OpEqualMaskedUint32x4(v)
+	case OpEqualMaskedUint32x8:
+		return rewriteValueAMD64_OpEqualMaskedUint32x8(v)
+	case OpEqualMaskedUint64x2:
+		return rewriteValueAMD64_OpEqualMaskedUint64x2(v)
+	case OpEqualMaskedUint64x4:
+		return rewriteValueAMD64_OpEqualMaskedUint64x4(v)
+	case OpEqualMaskedUint64x8:
+		return rewriteValueAMD64_OpEqualMaskedUint64x8(v)
+	case OpEqualMaskedUint8x16:
+		return rewriteValueAMD64_OpEqualMaskedUint8x16(v)
+	case OpEqualMaskedUint8x32:
+		return rewriteValueAMD64_OpEqualMaskedUint8x32(v)
+	case OpEqualMaskedUint8x64:
+		return rewriteValueAMD64_OpEqualMaskedUint8x64(v)
+	case OpEqualUint16x16:
+		v.Op = OpAMD64VPCMPEQW256
+		return true
+	case OpEqualUint16x32:
+		return rewriteValueAMD64_OpEqualUint16x32(v)
+	case OpEqualUint16x8:
+		v.Op = OpAMD64VPCMPEQW128
+		return true
+	case OpEqualUint32x16:
+		return rewriteValueAMD64_OpEqualUint32x16(v)
+	case OpEqualUint32x4:
+		v.Op = OpAMD64VPCMPEQD128
+		return true
+	case OpEqualUint32x8:
+		v.Op = OpAMD64VPCMPEQD256
+		return true
+	case OpEqualUint64x2:
+		v.Op = OpAMD64VPCMPEQQ128
+		return true
+	case OpEqualUint64x4:
+		v.Op = OpAMD64VPCMPEQQ256
+		return true
+	case OpEqualUint64x8:
+		return rewriteValueAMD64_OpEqualUint64x8(v)
+	case OpEqualUint8x16:
+		v.Op = OpAMD64VPCMPEQB128
+		return true
+	case OpEqualUint8x32:
+		v.Op = OpAMD64VPCMPEQB256
+		return true
+	case OpEqualUint8x64:
+		return rewriteValueAMD64_OpEqualUint8x64(v)
 	case OpFMA:
 		return rewriteValueAMD64_OpFMA(v)
 	case OpFloor:
 		return rewriteValueAMD64_OpFloor(v)
+	case OpFloorFloat32x4:
+		return rewriteValueAMD64_OpFloorFloat32x4(v)
+	case OpFloorFloat32x8:
+		return rewriteValueAMD64_OpFloorFloat32x8(v)
+	case OpFloorFloat64x2:
+		return rewriteValueAMD64_OpFloorFloat64x2(v)
+	case OpFloorFloat64x4:
+		return rewriteValueAMD64_OpFloorFloat64x4(v)
+	case OpFloorWithPrecisionFloat32x16:
+		return rewriteValueAMD64_OpFloorWithPrecisionFloat32x16(v)
+	case OpFloorWithPrecisionFloat32x4:
+		return rewriteValueAMD64_OpFloorWithPrecisionFloat32x4(v)
+	case OpFloorWithPrecisionFloat32x8:
+		return rewriteValueAMD64_OpFloorWithPrecisionFloat32x8(v)
+	case OpFloorWithPrecisionFloat64x2:
+		return rewriteValueAMD64_OpFloorWithPrecisionFloat64x2(v)
+	case OpFloorWithPrecisionFloat64x4:
+		return rewriteValueAMD64_OpFloorWithPrecisionFloat64x4(v)
+	case OpFloorWithPrecisionFloat64x8:
+		return rewriteValueAMD64_OpFloorWithPrecisionFloat64x8(v)
+	case OpFloorWithPrecisionMaskedFloat32x16:
+		return rewriteValueAMD64_OpFloorWithPrecisionMaskedFloat32x16(v)
+	case OpFloorWithPrecisionMaskedFloat32x4:
+		return rewriteValueAMD64_OpFloorWithPrecisionMaskedFloat32x4(v)
+	case OpFloorWithPrecisionMaskedFloat32x8:
+		return rewriteValueAMD64_OpFloorWithPrecisionMaskedFloat32x8(v)
+	case OpFloorWithPrecisionMaskedFloat64x2:
+		return rewriteValueAMD64_OpFloorWithPrecisionMaskedFloat64x2(v)
+	case OpFloorWithPrecisionMaskedFloat64x4:
+		return rewriteValueAMD64_OpFloorWithPrecisionMaskedFloat64x4(v)
+	case OpFloorWithPrecisionMaskedFloat64x8:
+		return rewriteValueAMD64_OpFloorWithPrecisionMaskedFloat64x8(v)
+	case OpFusedMultiplyAddFloat32x16:
+		v.Op = OpAMD64VFMADD213PS512
+		return true
+	case OpFusedMultiplyAddFloat32x4:
+		v.Op = OpAMD64VFMADD213PS128
+		return true
+	case OpFusedMultiplyAddFloat32x8:
+		v.Op = OpAMD64VFMADD213PS256
+		return true
+	case OpFusedMultiplyAddFloat64x2:
+		v.Op = OpAMD64VFMADD213PD128
+		return true
+	case OpFusedMultiplyAddFloat64x4:
+		v.Op = OpAMD64VFMADD213PD256
+		return true
+	case OpFusedMultiplyAddFloat64x8:
+		v.Op = OpAMD64VFMADD213PD512
+		return true
+	case OpFusedMultiplyAddMaskedFloat32x16:
+		return rewriteValueAMD64_OpFusedMultiplyAddMaskedFloat32x16(v)
+	case OpFusedMultiplyAddMaskedFloat32x4:
+		return rewriteValueAMD64_OpFusedMultiplyAddMaskedFloat32x4(v)
+	case OpFusedMultiplyAddMaskedFloat32x8:
+		return rewriteValueAMD64_OpFusedMultiplyAddMaskedFloat32x8(v)
+	case OpFusedMultiplyAddMaskedFloat64x2:
+		return rewriteValueAMD64_OpFusedMultiplyAddMaskedFloat64x2(v)
+	case OpFusedMultiplyAddMaskedFloat64x4:
+		return rewriteValueAMD64_OpFusedMultiplyAddMaskedFloat64x4(v)
+	case OpFusedMultiplyAddMaskedFloat64x8:
+		return rewriteValueAMD64_OpFusedMultiplyAddMaskedFloat64x8(v)
+	case OpFusedMultiplyAddSubFloat32x16:
+		v.Op = OpAMD64VFMADDSUB213PS512
+		return true
+	case OpFusedMultiplyAddSubFloat32x4:
+		v.Op = OpAMD64VFMADDSUB213PS128
+		return true
+	case OpFusedMultiplyAddSubFloat32x8:
+		v.Op = OpAMD64VFMADDSUB213PS256
+		return true
+	case OpFusedMultiplyAddSubFloat64x2:
+		v.Op = OpAMD64VFMADDSUB213PD128
+		return true
+	case OpFusedMultiplyAddSubFloat64x4:
+		v.Op = OpAMD64VFMADDSUB213PD256
+		return true
+	case OpFusedMultiplyAddSubFloat64x8:
+		v.Op = OpAMD64VFMADDSUB213PD512
+		return true
+	case OpFusedMultiplyAddSubMaskedFloat32x16:
+		return rewriteValueAMD64_OpFusedMultiplyAddSubMaskedFloat32x16(v)
+	case OpFusedMultiplyAddSubMaskedFloat32x4:
+		return rewriteValueAMD64_OpFusedMultiplyAddSubMaskedFloat32x4(v)
+	case OpFusedMultiplyAddSubMaskedFloat32x8:
+		return rewriteValueAMD64_OpFusedMultiplyAddSubMaskedFloat32x8(v)
+	case OpFusedMultiplyAddSubMaskedFloat64x2:
+		return rewriteValueAMD64_OpFusedMultiplyAddSubMaskedFloat64x2(v)
+	case OpFusedMultiplyAddSubMaskedFloat64x4:
+		return rewriteValueAMD64_OpFusedMultiplyAddSubMaskedFloat64x4(v)
+	case OpFusedMultiplyAddSubMaskedFloat64x8:
+		return rewriteValueAMD64_OpFusedMultiplyAddSubMaskedFloat64x8(v)
+	case OpFusedMultiplySubAddFloat32x16:
+		v.Op = OpAMD64VFMSUBADD213PS512
+		return true
+	case OpFusedMultiplySubAddFloat32x4:
+		v.Op = OpAMD64VFMSUBADD213PS128
+		return true
+	case OpFusedMultiplySubAddFloat32x8:
+		v.Op = OpAMD64VFMSUBADD213PS256
+		return true
+	case OpFusedMultiplySubAddFloat64x2:
+		v.Op = OpAMD64VFMSUBADD213PD128
+		return true
+	case OpFusedMultiplySubAddFloat64x4:
+		v.Op = OpAMD64VFMSUBADD213PD256
+		return true
+	case OpFusedMultiplySubAddFloat64x8:
+		v.Op = OpAMD64VFMSUBADD213PD512
+		return true
+	case OpFusedMultiplySubAddMaskedFloat32x16:
+		return rewriteValueAMD64_OpFusedMultiplySubAddMaskedFloat32x16(v)
+	case OpFusedMultiplySubAddMaskedFloat32x4:
+		return rewriteValueAMD64_OpFusedMultiplySubAddMaskedFloat32x4(v)
+	case OpFusedMultiplySubAddMaskedFloat32x8:
+		return rewriteValueAMD64_OpFusedMultiplySubAddMaskedFloat32x8(v)
+	case OpFusedMultiplySubAddMaskedFloat64x2:
+		return rewriteValueAMD64_OpFusedMultiplySubAddMaskedFloat64x2(v)
+	case OpFusedMultiplySubAddMaskedFloat64x4:
+		return rewriteValueAMD64_OpFusedMultiplySubAddMaskedFloat64x4(v)
+	case OpFusedMultiplySubAddMaskedFloat64x8:
+		return rewriteValueAMD64_OpFusedMultiplySubAddMaskedFloat64x8(v)
+	case OpGaloisFieldAffineTransformInverseMaskedUint8x16:
+		return rewriteValueAMD64_OpGaloisFieldAffineTransformInverseMaskedUint8x16(v)
+	case OpGaloisFieldAffineTransformInverseMaskedUint8x32:
+		return rewriteValueAMD64_OpGaloisFieldAffineTransformInverseMaskedUint8x32(v)
+	case OpGaloisFieldAffineTransformInverseMaskedUint8x64:
+		return rewriteValueAMD64_OpGaloisFieldAffineTransformInverseMaskedUint8x64(v)
+	case OpGaloisFieldAffineTransformInverseUint8x16:
+		v.Op = OpAMD64VGF2P8AFFINEINVQB128
+		return true
+	case OpGaloisFieldAffineTransformInverseUint8x32:
+		v.Op = OpAMD64VGF2P8AFFINEINVQB256
+		return true
+	case OpGaloisFieldAffineTransformInverseUint8x64:
+		v.Op = OpAMD64VGF2P8AFFINEINVQB512
+		return true
+	case OpGaloisFieldAffineTransformMaskedUint8x16:
+		return rewriteValueAMD64_OpGaloisFieldAffineTransformMaskedUint8x16(v)
+	case OpGaloisFieldAffineTransformMaskedUint8x32:
+		return rewriteValueAMD64_OpGaloisFieldAffineTransformMaskedUint8x32(v)
+	case OpGaloisFieldAffineTransformMaskedUint8x64:
+		return rewriteValueAMD64_OpGaloisFieldAffineTransformMaskedUint8x64(v)
+	case OpGaloisFieldAffineTransformUint8x16:
+		v.Op = OpAMD64VGF2P8AFFINEQB128
+		return true
+	case OpGaloisFieldAffineTransformUint8x32:
+		v.Op = OpAMD64VGF2P8AFFINEQB256
+		return true
+	case OpGaloisFieldAffineTransformUint8x64:
+		v.Op = OpAMD64VGF2P8AFFINEQB512
+		return true
+	case OpGaloisFieldMulMaskedUint8x16:
+		return rewriteValueAMD64_OpGaloisFieldMulMaskedUint8x16(v)
+	case OpGaloisFieldMulMaskedUint8x32:
+		return rewriteValueAMD64_OpGaloisFieldMulMaskedUint8x32(v)
+	case OpGaloisFieldMulMaskedUint8x64:
+		return rewriteValueAMD64_OpGaloisFieldMulMaskedUint8x64(v)
+	case OpGaloisFieldMulUint8x16:
+		v.Op = OpAMD64VGF2P8MULB128
+		return true
+	case OpGaloisFieldMulUint8x32:
+		v.Op = OpAMD64VGF2P8MULB256
+		return true
+	case OpGaloisFieldMulUint8x64:
+		v.Op = OpAMD64VGF2P8MULB512
+		return true
+	case OpGet128Float32x8:
+		v.Op = OpAMD64VEXTRACTF128128
+		return true
+	case OpGet128Float64x4:
+		v.Op = OpAMD64VEXTRACTF128128
+		return true
+	case OpGet128Int16x16:
+		v.Op = OpAMD64VEXTRACTI128128
+		return true
+	case OpGet128Int32x8:
+		v.Op = OpAMD64VEXTRACTI128128
+		return true
+	case OpGet128Int64x4:
+		v.Op = OpAMD64VEXTRACTI128128
+		return true
+	case OpGet128Int8x32:
+		v.Op = OpAMD64VEXTRACTI128128
+		return true
+	case OpGet128Uint16x16:
+		v.Op = OpAMD64VEXTRACTI128128
+		return true
+	case OpGet128Uint32x8:
+		v.Op = OpAMD64VEXTRACTI128128
+		return true
+	case OpGet128Uint64x4:
+		v.Op = OpAMD64VEXTRACTI128128
+		return true
+	case OpGet128Uint8x32:
+		v.Op = OpAMD64VEXTRACTI128128
+		return true
 	case OpGetCallerPC:
 		v.Op = OpAMD64LoweredGetCallerPC
 		return true
@@ -774,8 +1835,280 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpGetClosurePtr:
 		v.Op = OpAMD64LoweredGetClosurePtr
 		return true
+	case OpGetElemInt16x8:
+		v.Op = OpAMD64VPEXTRW128
+		return true
+	case OpGetElemInt32x4:
+		v.Op = OpAMD64VPEXTRD128
+		return true
+	case OpGetElemInt64x2:
+		v.Op = OpAMD64VPEXTRQ128
+		return true
+	case OpGetElemInt8x16:
+		v.Op = OpAMD64VPEXTRB128
+		return true
+	case OpGetElemUint16x8:
+		v.Op = OpAMD64VPEXTRW128
+		return true
+	case OpGetElemUint32x4:
+		v.Op = OpAMD64VPEXTRD128
+		return true
+	case OpGetElemUint64x2:
+		v.Op = OpAMD64VPEXTRQ128
+		return true
+	case OpGetElemUint8x16:
+		v.Op = OpAMD64VPEXTRB128
+		return true
 	case OpGetG:
 		return rewriteValueAMD64_OpGetG(v)
+	case OpGreaterEqualFloat32x16:
+		return rewriteValueAMD64_OpGreaterEqualFloat32x16(v)
+	case OpGreaterEqualFloat32x4:
+		return rewriteValueAMD64_OpGreaterEqualFloat32x4(v)
+	case OpGreaterEqualFloat32x8:
+		return rewriteValueAMD64_OpGreaterEqualFloat32x8(v)
+	case OpGreaterEqualFloat64x2:
+		return rewriteValueAMD64_OpGreaterEqualFloat64x2(v)
+	case OpGreaterEqualFloat64x4:
+		return rewriteValueAMD64_OpGreaterEqualFloat64x4(v)
+	case OpGreaterEqualFloat64x8:
+		return rewriteValueAMD64_OpGreaterEqualFloat64x8(v)
+	case OpGreaterEqualInt16x16:
+		return rewriteValueAMD64_OpGreaterEqualInt16x16(v)
+	case OpGreaterEqualInt16x32:
+		return rewriteValueAMD64_OpGreaterEqualInt16x32(v)
+	case OpGreaterEqualInt16x8:
+		return rewriteValueAMD64_OpGreaterEqualInt16x8(v)
+	case OpGreaterEqualInt32x16:
+		return rewriteValueAMD64_OpGreaterEqualInt32x16(v)
+	case OpGreaterEqualInt32x4:
+		return rewriteValueAMD64_OpGreaterEqualInt32x4(v)
+	case OpGreaterEqualInt32x8:
+		return rewriteValueAMD64_OpGreaterEqualInt32x8(v)
+	case OpGreaterEqualInt64x2:
+		return rewriteValueAMD64_OpGreaterEqualInt64x2(v)
+	case OpGreaterEqualInt64x4:
+		return rewriteValueAMD64_OpGreaterEqualInt64x4(v)
+	case OpGreaterEqualInt64x8:
+		return rewriteValueAMD64_OpGreaterEqualInt64x8(v)
+	case OpGreaterEqualInt8x16:
+		return rewriteValueAMD64_OpGreaterEqualInt8x16(v)
+	case OpGreaterEqualInt8x32:
+		return rewriteValueAMD64_OpGreaterEqualInt8x32(v)
+	case OpGreaterEqualInt8x64:
+		return rewriteValueAMD64_OpGreaterEqualInt8x64(v)
+	case OpGreaterEqualMaskedFloat32x16:
+		return rewriteValueAMD64_OpGreaterEqualMaskedFloat32x16(v)
+	case OpGreaterEqualMaskedFloat32x4:
+		return rewriteValueAMD64_OpGreaterEqualMaskedFloat32x4(v)
+	case OpGreaterEqualMaskedFloat32x8:
+		return rewriteValueAMD64_OpGreaterEqualMaskedFloat32x8(v)
+	case OpGreaterEqualMaskedFloat64x2:
+		return rewriteValueAMD64_OpGreaterEqualMaskedFloat64x2(v)
+	case OpGreaterEqualMaskedFloat64x4:
+		return rewriteValueAMD64_OpGreaterEqualMaskedFloat64x4(v)
+	case OpGreaterEqualMaskedFloat64x8:
+		return rewriteValueAMD64_OpGreaterEqualMaskedFloat64x8(v)
+	case OpGreaterEqualMaskedInt16x16:
+		return rewriteValueAMD64_OpGreaterEqualMaskedInt16x16(v)
+	case OpGreaterEqualMaskedInt16x32:
+		return rewriteValueAMD64_OpGreaterEqualMaskedInt16x32(v)
+	case OpGreaterEqualMaskedInt16x8:
+		return rewriteValueAMD64_OpGreaterEqualMaskedInt16x8(v)
+	case OpGreaterEqualMaskedInt32x16:
+		return rewriteValueAMD64_OpGreaterEqualMaskedInt32x16(v)
+	case OpGreaterEqualMaskedInt32x4:
+		return rewriteValueAMD64_OpGreaterEqualMaskedInt32x4(v)
+	case OpGreaterEqualMaskedInt32x8:
+		return rewriteValueAMD64_OpGreaterEqualMaskedInt32x8(v)
+	case OpGreaterEqualMaskedInt64x2:
+		return rewriteValueAMD64_OpGreaterEqualMaskedInt64x2(v)
+	case OpGreaterEqualMaskedInt64x4:
+		return rewriteValueAMD64_OpGreaterEqualMaskedInt64x4(v)
+	case OpGreaterEqualMaskedInt64x8:
+		return rewriteValueAMD64_OpGreaterEqualMaskedInt64x8(v)
+	case OpGreaterEqualMaskedInt8x16:
+		return rewriteValueAMD64_OpGreaterEqualMaskedInt8x16(v)
+	case OpGreaterEqualMaskedInt8x32:
+		return rewriteValueAMD64_OpGreaterEqualMaskedInt8x32(v)
+	case OpGreaterEqualMaskedInt8x64:
+		return rewriteValueAMD64_OpGreaterEqualMaskedInt8x64(v)
+	case OpGreaterEqualMaskedUint16x16:
+		return rewriteValueAMD64_OpGreaterEqualMaskedUint16x16(v)
+	case OpGreaterEqualMaskedUint16x32:
+		return rewriteValueAMD64_OpGreaterEqualMaskedUint16x32(v)
+	case OpGreaterEqualMaskedUint16x8:
+		return rewriteValueAMD64_OpGreaterEqualMaskedUint16x8(v)
+	case OpGreaterEqualMaskedUint32x16:
+		return rewriteValueAMD64_OpGreaterEqualMaskedUint32x16(v)
+	case OpGreaterEqualMaskedUint32x4:
+		return rewriteValueAMD64_OpGreaterEqualMaskedUint32x4(v)
+	case OpGreaterEqualMaskedUint32x8:
+		return rewriteValueAMD64_OpGreaterEqualMaskedUint32x8(v)
+	case OpGreaterEqualMaskedUint64x2:
+		return rewriteValueAMD64_OpGreaterEqualMaskedUint64x2(v)
+	case OpGreaterEqualMaskedUint64x4:
+		return rewriteValueAMD64_OpGreaterEqualMaskedUint64x4(v)
+	case OpGreaterEqualMaskedUint64x8:
+		return rewriteValueAMD64_OpGreaterEqualMaskedUint64x8(v)
+	case OpGreaterEqualMaskedUint8x16:
+		return rewriteValueAMD64_OpGreaterEqualMaskedUint8x16(v)
+	case OpGreaterEqualMaskedUint8x32:
+		return rewriteValueAMD64_OpGreaterEqualMaskedUint8x32(v)
+	case OpGreaterEqualMaskedUint8x64:
+		return rewriteValueAMD64_OpGreaterEqualMaskedUint8x64(v)
+	case OpGreaterEqualUint16x16:
+		return rewriteValueAMD64_OpGreaterEqualUint16x16(v)
+	case OpGreaterEqualUint16x32:
+		return rewriteValueAMD64_OpGreaterEqualUint16x32(v)
+	case OpGreaterEqualUint16x8:
+		return rewriteValueAMD64_OpGreaterEqualUint16x8(v)
+	case OpGreaterEqualUint32x16:
+		return rewriteValueAMD64_OpGreaterEqualUint32x16(v)
+	case OpGreaterEqualUint32x4:
+		return rewriteValueAMD64_OpGreaterEqualUint32x4(v)
+	case OpGreaterEqualUint32x8:
+		return rewriteValueAMD64_OpGreaterEqualUint32x8(v)
+	case OpGreaterEqualUint64x2:
+		return rewriteValueAMD64_OpGreaterEqualUint64x2(v)
+	case OpGreaterEqualUint64x4:
+		return rewriteValueAMD64_OpGreaterEqualUint64x4(v)
+	case OpGreaterEqualUint64x8:
+		return rewriteValueAMD64_OpGreaterEqualUint64x8(v)
+	case OpGreaterEqualUint8x16:
+		return rewriteValueAMD64_OpGreaterEqualUint8x16(v)
+	case OpGreaterEqualUint8x32:
+		return rewriteValueAMD64_OpGreaterEqualUint8x32(v)
+	case OpGreaterEqualUint8x64:
+		return rewriteValueAMD64_OpGreaterEqualUint8x64(v)
+	case OpGreaterFloat32x16:
+		return rewriteValueAMD64_OpGreaterFloat32x16(v)
+	case OpGreaterFloat32x4:
+		return rewriteValueAMD64_OpGreaterFloat32x4(v)
+	case OpGreaterFloat32x8:
+		return rewriteValueAMD64_OpGreaterFloat32x8(v)
+	case OpGreaterFloat64x2:
+		return rewriteValueAMD64_OpGreaterFloat64x2(v)
+	case OpGreaterFloat64x4:
+		return rewriteValueAMD64_OpGreaterFloat64x4(v)
+	case OpGreaterFloat64x8:
+		return rewriteValueAMD64_OpGreaterFloat64x8(v)
+	case OpGreaterInt16x16:
+		v.Op = OpAMD64VPCMPGTW256
+		return true
+	case OpGreaterInt16x32:
+		return rewriteValueAMD64_OpGreaterInt16x32(v)
+	case OpGreaterInt16x8:
+		v.Op = OpAMD64VPCMPGTW128
+		return true
+	case OpGreaterInt32x16:
+		return rewriteValueAMD64_OpGreaterInt32x16(v)
+	case OpGreaterInt32x4:
+		v.Op = OpAMD64VPCMPGTD128
+		return true
+	case OpGreaterInt32x8:
+		v.Op = OpAMD64VPCMPGTD256
+		return true
+	case OpGreaterInt64x2:
+		v.Op = OpAMD64VPCMPGTQ128
+		return true
+	case OpGreaterInt64x4:
+		v.Op = OpAMD64VPCMPGTQ256
+		return true
+	case OpGreaterInt64x8:
+		return rewriteValueAMD64_OpGreaterInt64x8(v)
+	case OpGreaterInt8x16:
+		v.Op = OpAMD64VPCMPGTB128
+		return true
+	case OpGreaterInt8x32:
+		v.Op = OpAMD64VPCMPGTB256
+		return true
+	case OpGreaterInt8x64:
+		return rewriteValueAMD64_OpGreaterInt8x64(v)
+	case OpGreaterMaskedFloat32x16:
+		return rewriteValueAMD64_OpGreaterMaskedFloat32x16(v)
+	case OpGreaterMaskedFloat32x4:
+		return rewriteValueAMD64_OpGreaterMaskedFloat32x4(v)
+	case OpGreaterMaskedFloat32x8:
+		return rewriteValueAMD64_OpGreaterMaskedFloat32x8(v)
+	case OpGreaterMaskedFloat64x2:
+		return rewriteValueAMD64_OpGreaterMaskedFloat64x2(v)
+	case OpGreaterMaskedFloat64x4:
+		return rewriteValueAMD64_OpGreaterMaskedFloat64x4(v)
+	case OpGreaterMaskedFloat64x8:
+		return rewriteValueAMD64_OpGreaterMaskedFloat64x8(v)
+	case OpGreaterMaskedInt16x16:
+		return rewriteValueAMD64_OpGreaterMaskedInt16x16(v)
+	case OpGreaterMaskedInt16x32:
+		return rewriteValueAMD64_OpGreaterMaskedInt16x32(v)
+	case OpGreaterMaskedInt16x8:
+		return rewriteValueAMD64_OpGreaterMaskedInt16x8(v)
+	case OpGreaterMaskedInt32x16:
+		return rewriteValueAMD64_OpGreaterMaskedInt32x16(v)
+	case OpGreaterMaskedInt32x4:
+		return rewriteValueAMD64_OpGreaterMaskedInt32x4(v)
+	case OpGreaterMaskedInt32x8:
+		return rewriteValueAMD64_OpGreaterMaskedInt32x8(v)
+	case OpGreaterMaskedInt64x2:
+		return rewriteValueAMD64_OpGreaterMaskedInt64x2(v)
+	case OpGreaterMaskedInt64x4:
+		return rewriteValueAMD64_OpGreaterMaskedInt64x4(v)
+	case OpGreaterMaskedInt64x8:
+		return rewriteValueAMD64_OpGreaterMaskedInt64x8(v)
+	case OpGreaterMaskedInt8x16:
+		return rewriteValueAMD64_OpGreaterMaskedInt8x16(v)
+	case OpGreaterMaskedInt8x32:
+		return rewriteValueAMD64_OpGreaterMaskedInt8x32(v)
+	case OpGreaterMaskedInt8x64:
+		return rewriteValueAMD64_OpGreaterMaskedInt8x64(v)
+	case OpGreaterMaskedUint16x16:
+		return rewriteValueAMD64_OpGreaterMaskedUint16x16(v)
+	case OpGreaterMaskedUint16x32:
+		return rewriteValueAMD64_OpGreaterMaskedUint16x32(v)
+	case OpGreaterMaskedUint16x8:
+		return rewriteValueAMD64_OpGreaterMaskedUint16x8(v)
+	case OpGreaterMaskedUint32x16:
+		return rewriteValueAMD64_OpGreaterMaskedUint32x16(v)
+	case OpGreaterMaskedUint32x4:
+		return rewriteValueAMD64_OpGreaterMaskedUint32x4(v)
+	case OpGreaterMaskedUint32x8:
+		return rewriteValueAMD64_OpGreaterMaskedUint32x8(v)
+	case OpGreaterMaskedUint64x2:
+		return rewriteValueAMD64_OpGreaterMaskedUint64x2(v)
+	case OpGreaterMaskedUint64x4:
+		return rewriteValueAMD64_OpGreaterMaskedUint64x4(v)
+	case OpGreaterMaskedUint64x8:
+		return rewriteValueAMD64_OpGreaterMaskedUint64x8(v)
+	case OpGreaterMaskedUint8x16:
+		return rewriteValueAMD64_OpGreaterMaskedUint8x16(v)
+	case OpGreaterMaskedUint8x32:
+		return rewriteValueAMD64_OpGreaterMaskedUint8x32(v)
+	case OpGreaterMaskedUint8x64:
+		return rewriteValueAMD64_OpGreaterMaskedUint8x64(v)
+	case OpGreaterUint16x16:
+		return rewriteValueAMD64_OpGreaterUint16x16(v)
+	case OpGreaterUint16x32:
+		return rewriteValueAMD64_OpGreaterUint16x32(v)
+	case OpGreaterUint16x8:
+		return rewriteValueAMD64_OpGreaterUint16x8(v)
+	case OpGreaterUint32x16:
+		return rewriteValueAMD64_OpGreaterUint32x16(v)
+	case OpGreaterUint32x4:
+		return rewriteValueAMD64_OpGreaterUint32x4(v)
+	case OpGreaterUint32x8:
+		return rewriteValueAMD64_OpGreaterUint32x8(v)
+	case OpGreaterUint64x2:
+		return rewriteValueAMD64_OpGreaterUint64x2(v)
+	case OpGreaterUint64x4:
+		return rewriteValueAMD64_OpGreaterUint64x4(v)
+	case OpGreaterUint64x8:
+		return rewriteValueAMD64_OpGreaterUint64x8(v)
+	case OpGreaterUint8x16:
+		return rewriteValueAMD64_OpGreaterUint8x16(v)
+	case OpGreaterUint8x32:
+		return rewriteValueAMD64_OpGreaterUint8x32(v)
+	case OpGreaterUint8x64:
+		return rewriteValueAMD64_OpGreaterUint8x64(v)
 	case OpHasCPUFeature:
 		return rewriteValueAMD64_OpHasCPUFeature(v)
 	case OpHmul32:
@@ -795,6 +2128,30 @@ func rewriteValueAMD64(v *Value) bool {
 		return true
 	case OpIsInBounds:
 		return rewriteValueAMD64_OpIsInBounds(v)
+	case OpIsNanFloat32x16:
+		return rewriteValueAMD64_OpIsNanFloat32x16(v)
+	case OpIsNanFloat32x4:
+		return rewriteValueAMD64_OpIsNanFloat32x4(v)
+	case OpIsNanFloat32x8:
+		return rewriteValueAMD64_OpIsNanFloat32x8(v)
+	case OpIsNanFloat64x2:
+		return rewriteValueAMD64_OpIsNanFloat64x2(v)
+	case OpIsNanFloat64x4:
+		return rewriteValueAMD64_OpIsNanFloat64x4(v)
+	case OpIsNanFloat64x8:
+		return rewriteValueAMD64_OpIsNanFloat64x8(v)
+	case OpIsNanMaskedFloat32x16:
+		return rewriteValueAMD64_OpIsNanMaskedFloat32x16(v)
+	case OpIsNanMaskedFloat32x4:
+		return rewriteValueAMD64_OpIsNanMaskedFloat32x4(v)
+	case OpIsNanMaskedFloat32x8:
+		return rewriteValueAMD64_OpIsNanMaskedFloat32x8(v)
+	case OpIsNanMaskedFloat64x2:
+		return rewriteValueAMD64_OpIsNanMaskedFloat64x2(v)
+	case OpIsNanMaskedFloat64x4:
+		return rewriteValueAMD64_OpIsNanMaskedFloat64x4(v)
+	case OpIsNanMaskedFloat64x8:
+		return rewriteValueAMD64_OpIsNanMaskedFloat64x8(v)
 	case OpIsNonNil:
 		return rewriteValueAMD64_OpIsNonNil(v)
 	case OpIsSliceInBounds:
@@ -839,6 +2196,246 @@ func rewriteValueAMD64(v *Value) bool {
 		return rewriteValueAMD64_OpLess8(v)
 	case OpLess8U:
 		return rewriteValueAMD64_OpLess8U(v)
+	case OpLessEqualFloat32x16:
+		return rewriteValueAMD64_OpLessEqualFloat32x16(v)
+	case OpLessEqualFloat32x4:
+		return rewriteValueAMD64_OpLessEqualFloat32x4(v)
+	case OpLessEqualFloat32x8:
+		return rewriteValueAMD64_OpLessEqualFloat32x8(v)
+	case OpLessEqualFloat64x2:
+		return rewriteValueAMD64_OpLessEqualFloat64x2(v)
+	case OpLessEqualFloat64x4:
+		return rewriteValueAMD64_OpLessEqualFloat64x4(v)
+	case OpLessEqualFloat64x8:
+		return rewriteValueAMD64_OpLessEqualFloat64x8(v)
+	case OpLessEqualInt16x16:
+		return rewriteValueAMD64_OpLessEqualInt16x16(v)
+	case OpLessEqualInt16x32:
+		return rewriteValueAMD64_OpLessEqualInt16x32(v)
+	case OpLessEqualInt16x8:
+		return rewriteValueAMD64_OpLessEqualInt16x8(v)
+	case OpLessEqualInt32x16:
+		return rewriteValueAMD64_OpLessEqualInt32x16(v)
+	case OpLessEqualInt32x4:
+		return rewriteValueAMD64_OpLessEqualInt32x4(v)
+	case OpLessEqualInt32x8:
+		return rewriteValueAMD64_OpLessEqualInt32x8(v)
+	case OpLessEqualInt64x2:
+		return rewriteValueAMD64_OpLessEqualInt64x2(v)
+	case OpLessEqualInt64x4:
+		return rewriteValueAMD64_OpLessEqualInt64x4(v)
+	case OpLessEqualInt64x8:
+		return rewriteValueAMD64_OpLessEqualInt64x8(v)
+	case OpLessEqualInt8x16:
+		return rewriteValueAMD64_OpLessEqualInt8x16(v)
+	case OpLessEqualInt8x32:
+		return rewriteValueAMD64_OpLessEqualInt8x32(v)
+	case OpLessEqualInt8x64:
+		return rewriteValueAMD64_OpLessEqualInt8x64(v)
+	case OpLessEqualMaskedFloat32x16:
+		return rewriteValueAMD64_OpLessEqualMaskedFloat32x16(v)
+	case OpLessEqualMaskedFloat32x4:
+		return rewriteValueAMD64_OpLessEqualMaskedFloat32x4(v)
+	case OpLessEqualMaskedFloat32x8:
+		return rewriteValueAMD64_OpLessEqualMaskedFloat32x8(v)
+	case OpLessEqualMaskedFloat64x2:
+		return rewriteValueAMD64_OpLessEqualMaskedFloat64x2(v)
+	case OpLessEqualMaskedFloat64x4:
+		return rewriteValueAMD64_OpLessEqualMaskedFloat64x4(v)
+	case OpLessEqualMaskedFloat64x8:
+		return rewriteValueAMD64_OpLessEqualMaskedFloat64x8(v)
+	case OpLessEqualMaskedInt16x16:
+		return rewriteValueAMD64_OpLessEqualMaskedInt16x16(v)
+	case OpLessEqualMaskedInt16x32:
+		return rewriteValueAMD64_OpLessEqualMaskedInt16x32(v)
+	case OpLessEqualMaskedInt16x8:
+		return rewriteValueAMD64_OpLessEqualMaskedInt16x8(v)
+	case OpLessEqualMaskedInt32x16:
+		return rewriteValueAMD64_OpLessEqualMaskedInt32x16(v)
+	case OpLessEqualMaskedInt32x4:
+		return rewriteValueAMD64_OpLessEqualMaskedInt32x4(v)
+	case OpLessEqualMaskedInt32x8:
+		return rewriteValueAMD64_OpLessEqualMaskedInt32x8(v)
+	case OpLessEqualMaskedInt64x2:
+		return rewriteValueAMD64_OpLessEqualMaskedInt64x2(v)
+	case OpLessEqualMaskedInt64x4:
+		return rewriteValueAMD64_OpLessEqualMaskedInt64x4(v)
+	case OpLessEqualMaskedInt64x8:
+		return rewriteValueAMD64_OpLessEqualMaskedInt64x8(v)
+	case OpLessEqualMaskedInt8x16:
+		return rewriteValueAMD64_OpLessEqualMaskedInt8x16(v)
+	case OpLessEqualMaskedInt8x32:
+		return rewriteValueAMD64_OpLessEqualMaskedInt8x32(v)
+	case OpLessEqualMaskedInt8x64:
+		return rewriteValueAMD64_OpLessEqualMaskedInt8x64(v)
+	case OpLessEqualMaskedUint16x16:
+		return rewriteValueAMD64_OpLessEqualMaskedUint16x16(v)
+	case OpLessEqualMaskedUint16x32:
+		return rewriteValueAMD64_OpLessEqualMaskedUint16x32(v)
+	case OpLessEqualMaskedUint16x8:
+		return rewriteValueAMD64_OpLessEqualMaskedUint16x8(v)
+	case OpLessEqualMaskedUint32x16:
+		return rewriteValueAMD64_OpLessEqualMaskedUint32x16(v)
+	case OpLessEqualMaskedUint32x4:
+		return rewriteValueAMD64_OpLessEqualMaskedUint32x4(v)
+	case OpLessEqualMaskedUint32x8:
+		return rewriteValueAMD64_OpLessEqualMaskedUint32x8(v)
+	case OpLessEqualMaskedUint64x2:
+		return rewriteValueAMD64_OpLessEqualMaskedUint64x2(v)
+	case OpLessEqualMaskedUint64x4:
+		return rewriteValueAMD64_OpLessEqualMaskedUint64x4(v)
+	case OpLessEqualMaskedUint64x8:
+		return rewriteValueAMD64_OpLessEqualMaskedUint64x8(v)
+	case OpLessEqualMaskedUint8x16:
+		return rewriteValueAMD64_OpLessEqualMaskedUint8x16(v)
+	case OpLessEqualMaskedUint8x32:
+		return rewriteValueAMD64_OpLessEqualMaskedUint8x32(v)
+	case OpLessEqualMaskedUint8x64:
+		return rewriteValueAMD64_OpLessEqualMaskedUint8x64(v)
+	case OpLessEqualUint16x16:
+		return rewriteValueAMD64_OpLessEqualUint16x16(v)
+	case OpLessEqualUint16x32:
+		return rewriteValueAMD64_OpLessEqualUint16x32(v)
+	case OpLessEqualUint16x8:
+		return rewriteValueAMD64_OpLessEqualUint16x8(v)
+	case OpLessEqualUint32x16:
+		return rewriteValueAMD64_OpLessEqualUint32x16(v)
+	case OpLessEqualUint32x4:
+		return rewriteValueAMD64_OpLessEqualUint32x4(v)
+	case OpLessEqualUint32x8:
+		return rewriteValueAMD64_OpLessEqualUint32x8(v)
+	case OpLessEqualUint64x2:
+		return rewriteValueAMD64_OpLessEqualUint64x2(v)
+	case OpLessEqualUint64x4:
+		return rewriteValueAMD64_OpLessEqualUint64x4(v)
+	case OpLessEqualUint64x8:
+		return rewriteValueAMD64_OpLessEqualUint64x8(v)
+	case OpLessEqualUint8x16:
+		return rewriteValueAMD64_OpLessEqualUint8x16(v)
+	case OpLessEqualUint8x32:
+		return rewriteValueAMD64_OpLessEqualUint8x32(v)
+	case OpLessEqualUint8x64:
+		return rewriteValueAMD64_OpLessEqualUint8x64(v)
+	case OpLessFloat32x16:
+		return rewriteValueAMD64_OpLessFloat32x16(v)
+	case OpLessFloat32x4:
+		return rewriteValueAMD64_OpLessFloat32x4(v)
+	case OpLessFloat32x8:
+		return rewriteValueAMD64_OpLessFloat32x8(v)
+	case OpLessFloat64x2:
+		return rewriteValueAMD64_OpLessFloat64x2(v)
+	case OpLessFloat64x4:
+		return rewriteValueAMD64_OpLessFloat64x4(v)
+	case OpLessFloat64x8:
+		return rewriteValueAMD64_OpLessFloat64x8(v)
+	case OpLessInt16x16:
+		return rewriteValueAMD64_OpLessInt16x16(v)
+	case OpLessInt16x32:
+		return rewriteValueAMD64_OpLessInt16x32(v)
+	case OpLessInt16x8:
+		return rewriteValueAMD64_OpLessInt16x8(v)
+	case OpLessInt32x16:
+		return rewriteValueAMD64_OpLessInt32x16(v)
+	case OpLessInt32x4:
+		return rewriteValueAMD64_OpLessInt32x4(v)
+	case OpLessInt32x8:
+		return rewriteValueAMD64_OpLessInt32x8(v)
+	case OpLessInt64x2:
+		return rewriteValueAMD64_OpLessInt64x2(v)
+	case OpLessInt64x4:
+		return rewriteValueAMD64_OpLessInt64x4(v)
+	case OpLessInt64x8:
+		return rewriteValueAMD64_OpLessInt64x8(v)
+	case OpLessInt8x16:
+		return rewriteValueAMD64_OpLessInt8x16(v)
+	case OpLessInt8x32:
+		return rewriteValueAMD64_OpLessInt8x32(v)
+	case OpLessInt8x64:
+		return rewriteValueAMD64_OpLessInt8x64(v)
+	case OpLessMaskedFloat32x16:
+		return rewriteValueAMD64_OpLessMaskedFloat32x16(v)
+	case OpLessMaskedFloat32x4:
+		return rewriteValueAMD64_OpLessMaskedFloat32x4(v)
+	case OpLessMaskedFloat32x8:
+		return rewriteValueAMD64_OpLessMaskedFloat32x8(v)
+	case OpLessMaskedFloat64x2:
+		return rewriteValueAMD64_OpLessMaskedFloat64x2(v)
+	case OpLessMaskedFloat64x4:
+		return rewriteValueAMD64_OpLessMaskedFloat64x4(v)
+	case OpLessMaskedFloat64x8:
+		return rewriteValueAMD64_OpLessMaskedFloat64x8(v)
+	case OpLessMaskedInt16x16:
+		return rewriteValueAMD64_OpLessMaskedInt16x16(v)
+	case OpLessMaskedInt16x32:
+		return rewriteValueAMD64_OpLessMaskedInt16x32(v)
+	case OpLessMaskedInt16x8:
+		return rewriteValueAMD64_OpLessMaskedInt16x8(v)
+	case OpLessMaskedInt32x16:
+		return rewriteValueAMD64_OpLessMaskedInt32x16(v)
+	case OpLessMaskedInt32x4:
+		return rewriteValueAMD64_OpLessMaskedInt32x4(v)
+	case OpLessMaskedInt32x8:
+		return rewriteValueAMD64_OpLessMaskedInt32x8(v)
+	case OpLessMaskedInt64x2:
+		return rewriteValueAMD64_OpLessMaskedInt64x2(v)
+	case OpLessMaskedInt64x4:
+		return rewriteValueAMD64_OpLessMaskedInt64x4(v)
+	case OpLessMaskedInt64x8:
+		return rewriteValueAMD64_OpLessMaskedInt64x8(v)
+	case OpLessMaskedInt8x16:
+		return rewriteValueAMD64_OpLessMaskedInt8x16(v)
+	case OpLessMaskedInt8x32:
+		return rewriteValueAMD64_OpLessMaskedInt8x32(v)
+	case OpLessMaskedInt8x64:
+		return rewriteValueAMD64_OpLessMaskedInt8x64(v)
+	case OpLessMaskedUint16x16:
+		return rewriteValueAMD64_OpLessMaskedUint16x16(v)
+	case OpLessMaskedUint16x32:
+		return rewriteValueAMD64_OpLessMaskedUint16x32(v)
+	case OpLessMaskedUint16x8:
+		return rewriteValueAMD64_OpLessMaskedUint16x8(v)
+	case OpLessMaskedUint32x16:
+		return rewriteValueAMD64_OpLessMaskedUint32x16(v)
+	case OpLessMaskedUint32x4:
+		return rewriteValueAMD64_OpLessMaskedUint32x4(v)
+	case OpLessMaskedUint32x8:
+		return rewriteValueAMD64_OpLessMaskedUint32x8(v)
+	case OpLessMaskedUint64x2:
+		return rewriteValueAMD64_OpLessMaskedUint64x2(v)
+	case OpLessMaskedUint64x4:
+		return rewriteValueAMD64_OpLessMaskedUint64x4(v)
+	case OpLessMaskedUint64x8:
+		return rewriteValueAMD64_OpLessMaskedUint64x8(v)
+	case OpLessMaskedUint8x16:
+		return rewriteValueAMD64_OpLessMaskedUint8x16(v)
+	case OpLessMaskedUint8x32:
+		return rewriteValueAMD64_OpLessMaskedUint8x32(v)
+	case OpLessMaskedUint8x64:
+		return rewriteValueAMD64_OpLessMaskedUint8x64(v)
+	case OpLessUint16x16:
+		return rewriteValueAMD64_OpLessUint16x16(v)
+	case OpLessUint16x32:
+		return rewriteValueAMD64_OpLessUint16x32(v)
+	case OpLessUint16x8:
+		return rewriteValueAMD64_OpLessUint16x8(v)
+	case OpLessUint32x16:
+		return rewriteValueAMD64_OpLessUint32x16(v)
+	case OpLessUint32x4:
+		return rewriteValueAMD64_OpLessUint32x4(v)
+	case OpLessUint32x8:
+		return rewriteValueAMD64_OpLessUint32x8(v)
+	case OpLessUint64x2:
+		return rewriteValueAMD64_OpLessUint64x2(v)
+	case OpLessUint64x4:
+		return rewriteValueAMD64_OpLessUint64x4(v)
+	case OpLessUint64x8:
+		return rewriteValueAMD64_OpLessUint64x8(v)
+	case OpLessUint8x16:
+		return rewriteValueAMD64_OpLessUint8x16(v)
+	case OpLessUint8x32:
+		return rewriteValueAMD64_OpLessUint8x32(v)
+	case OpLessUint8x64:
+		return rewriteValueAMD64_OpLessUint8x64(v)
 	case OpLoad:
 		return rewriteValueAMD64_OpLoad(v)
 	case OpLocalAddr:
@@ -879,10 +2476,310 @@ func rewriteValueAMD64(v *Value) bool {
 		return rewriteValueAMD64_OpMax32F(v)
 	case OpMax64F:
 		return rewriteValueAMD64_OpMax64F(v)
+	case OpMaxFloat32x16:
+		v.Op = OpAMD64VMAXPS512
+		return true
+	case OpMaxFloat32x4:
+		v.Op = OpAMD64VMAXPS128
+		return true
+	case OpMaxFloat32x8:
+		v.Op = OpAMD64VMAXPS256
+		return true
+	case OpMaxFloat64x2:
+		v.Op = OpAMD64VMAXPD128
+		return true
+	case OpMaxFloat64x4:
+		v.Op = OpAMD64VMAXPD256
+		return true
+	case OpMaxFloat64x8:
+		v.Op = OpAMD64VMAXPD512
+		return true
+	case OpMaxInt16x16:
+		v.Op = OpAMD64VPMAXSW256
+		return true
+	case OpMaxInt16x32:
+		v.Op = OpAMD64VPMAXSW512
+		return true
+	case OpMaxInt16x8:
+		v.Op = OpAMD64VPMAXSW128
+		return true
+	case OpMaxInt32x16:
+		v.Op = OpAMD64VPMAXSD512
+		return true
+	case OpMaxInt32x4:
+		v.Op = OpAMD64VPMAXSD128
+		return true
+	case OpMaxInt32x8:
+		v.Op = OpAMD64VPMAXSD256
+		return true
+	case OpMaxInt64x2:
+		v.Op = OpAMD64VPMAXSQ128
+		return true
+	case OpMaxInt64x4:
+		v.Op = OpAMD64VPMAXSQ256
+		return true
+	case OpMaxInt64x8:
+		v.Op = OpAMD64VPMAXSQ512
+		return true
+	case OpMaxInt8x16:
+		v.Op = OpAMD64VPMAXSB128
+		return true
+	case OpMaxInt8x32:
+		v.Op = OpAMD64VPMAXSB256
+		return true
+	case OpMaxInt8x64:
+		v.Op = OpAMD64VPMAXSB512
+		return true
+	case OpMaxMaskedFloat32x16:
+		return rewriteValueAMD64_OpMaxMaskedFloat32x16(v)
+	case OpMaxMaskedFloat32x4:
+		return rewriteValueAMD64_OpMaxMaskedFloat32x4(v)
+	case OpMaxMaskedFloat32x8:
+		return rewriteValueAMD64_OpMaxMaskedFloat32x8(v)
+	case OpMaxMaskedFloat64x2:
+		return rewriteValueAMD64_OpMaxMaskedFloat64x2(v)
+	case OpMaxMaskedFloat64x4:
+		return rewriteValueAMD64_OpMaxMaskedFloat64x4(v)
+	case OpMaxMaskedFloat64x8:
+		return rewriteValueAMD64_OpMaxMaskedFloat64x8(v)
+	case OpMaxMaskedInt16x16:
+		return rewriteValueAMD64_OpMaxMaskedInt16x16(v)
+	case OpMaxMaskedInt16x32:
+		return rewriteValueAMD64_OpMaxMaskedInt16x32(v)
+	case OpMaxMaskedInt16x8:
+		return rewriteValueAMD64_OpMaxMaskedInt16x8(v)
+	case OpMaxMaskedInt32x16:
+		return rewriteValueAMD64_OpMaxMaskedInt32x16(v)
+	case OpMaxMaskedInt32x4:
+		return rewriteValueAMD64_OpMaxMaskedInt32x4(v)
+	case OpMaxMaskedInt32x8:
+		return rewriteValueAMD64_OpMaxMaskedInt32x8(v)
+	case OpMaxMaskedInt64x2:
+		return rewriteValueAMD64_OpMaxMaskedInt64x2(v)
+	case OpMaxMaskedInt64x4:
+		return rewriteValueAMD64_OpMaxMaskedInt64x4(v)
+	case OpMaxMaskedInt64x8:
+		return rewriteValueAMD64_OpMaxMaskedInt64x8(v)
+	case OpMaxMaskedInt8x16:
+		return rewriteValueAMD64_OpMaxMaskedInt8x16(v)
+	case OpMaxMaskedInt8x32:
+		return rewriteValueAMD64_OpMaxMaskedInt8x32(v)
+	case OpMaxMaskedInt8x64:
+		return rewriteValueAMD64_OpMaxMaskedInt8x64(v)
+	case OpMaxMaskedUint16x16:
+		return rewriteValueAMD64_OpMaxMaskedUint16x16(v)
+	case OpMaxMaskedUint16x32:
+		return rewriteValueAMD64_OpMaxMaskedUint16x32(v)
+	case OpMaxMaskedUint16x8:
+		return rewriteValueAMD64_OpMaxMaskedUint16x8(v)
+	case OpMaxMaskedUint32x16:
+		return rewriteValueAMD64_OpMaxMaskedUint32x16(v)
+	case OpMaxMaskedUint32x4:
+		return rewriteValueAMD64_OpMaxMaskedUint32x4(v)
+	case OpMaxMaskedUint32x8:
+		return rewriteValueAMD64_OpMaxMaskedUint32x8(v)
+	case OpMaxMaskedUint64x2:
+		return rewriteValueAMD64_OpMaxMaskedUint64x2(v)
+	case OpMaxMaskedUint64x4:
+		return rewriteValueAMD64_OpMaxMaskedUint64x4(v)
+	case OpMaxMaskedUint64x8:
+		return rewriteValueAMD64_OpMaxMaskedUint64x8(v)
+	case OpMaxMaskedUint8x16:
+		return rewriteValueAMD64_OpMaxMaskedUint8x16(v)
+	case OpMaxMaskedUint8x32:
+		return rewriteValueAMD64_OpMaxMaskedUint8x32(v)
+	case OpMaxMaskedUint8x64:
+		return rewriteValueAMD64_OpMaxMaskedUint8x64(v)
+	case OpMaxUint16x16:
+		v.Op = OpAMD64VPMAXUW256
+		return true
+	case OpMaxUint16x32:
+		v.Op = OpAMD64VPMAXUW512
+		return true
+	case OpMaxUint16x8:
+		v.Op = OpAMD64VPMAXUW128
+		return true
+	case OpMaxUint32x16:
+		v.Op = OpAMD64VPMAXUD512
+		return true
+	case OpMaxUint32x4:
+		v.Op = OpAMD64VPMAXUD128
+		return true
+	case OpMaxUint32x8:
+		v.Op = OpAMD64VPMAXUD256
+		return true
+	case OpMaxUint64x2:
+		v.Op = OpAMD64VPMAXUQ128
+		return true
+	case OpMaxUint64x4:
+		v.Op = OpAMD64VPMAXUQ256
+		return true
+	case OpMaxUint64x8:
+		v.Op = OpAMD64VPMAXUQ512
+		return true
+	case OpMaxUint8x16:
+		v.Op = OpAMD64VPMAXUB128
+		return true
+	case OpMaxUint8x32:
+		v.Op = OpAMD64VPMAXUB256
+		return true
+	case OpMaxUint8x64:
+		v.Op = OpAMD64VPMAXUB512
+		return true
 	case OpMin32F:
 		return rewriteValueAMD64_OpMin32F(v)
 	case OpMin64F:
 		return rewriteValueAMD64_OpMin64F(v)
+	case OpMinFloat32x16:
+		v.Op = OpAMD64VMINPS512
+		return true
+	case OpMinFloat32x4:
+		v.Op = OpAMD64VMINPS128
+		return true
+	case OpMinFloat32x8:
+		v.Op = OpAMD64VMINPS256
+		return true
+	case OpMinFloat64x2:
+		v.Op = OpAMD64VMINPD128
+		return true
+	case OpMinFloat64x4:
+		v.Op = OpAMD64VMINPD256
+		return true
+	case OpMinFloat64x8:
+		v.Op = OpAMD64VMINPD512
+		return true
+	case OpMinInt16x16:
+		v.Op = OpAMD64VPMINSW256
+		return true
+	case OpMinInt16x32:
+		v.Op = OpAMD64VPMINSW512
+		return true
+	case OpMinInt16x8:
+		v.Op = OpAMD64VPMINSW128
+		return true
+	case OpMinInt32x16:
+		v.Op = OpAMD64VPMINSD512
+		return true
+	case OpMinInt32x4:
+		v.Op = OpAMD64VPMINSD128
+		return true
+	case OpMinInt32x8:
+		v.Op = OpAMD64VPMINSD256
+		return true
+	case OpMinInt64x2:
+		v.Op = OpAMD64VPMINSQ128
+		return true
+	case OpMinInt64x4:
+		v.Op = OpAMD64VPMINSQ256
+		return true
+	case OpMinInt64x8:
+		v.Op = OpAMD64VPMINSQ512
+		return true
+	case OpMinInt8x16:
+		v.Op = OpAMD64VPMINSB128
+		return true
+	case OpMinInt8x32:
+		v.Op = OpAMD64VPMINSB256
+		return true
+	case OpMinInt8x64:
+		v.Op = OpAMD64VPMINSB512
+		return true
+	case OpMinMaskedFloat32x16:
+		return rewriteValueAMD64_OpMinMaskedFloat32x16(v)
+	case OpMinMaskedFloat32x4:
+		return rewriteValueAMD64_OpMinMaskedFloat32x4(v)
+	case OpMinMaskedFloat32x8:
+		return rewriteValueAMD64_OpMinMaskedFloat32x8(v)
+	case OpMinMaskedFloat64x2:
+		return rewriteValueAMD64_OpMinMaskedFloat64x2(v)
+	case OpMinMaskedFloat64x4:
+		return rewriteValueAMD64_OpMinMaskedFloat64x4(v)
+	case OpMinMaskedFloat64x8:
+		return rewriteValueAMD64_OpMinMaskedFloat64x8(v)
+	case OpMinMaskedInt16x16:
+		return rewriteValueAMD64_OpMinMaskedInt16x16(v)
+	case OpMinMaskedInt16x32:
+		return rewriteValueAMD64_OpMinMaskedInt16x32(v)
+	case OpMinMaskedInt16x8:
+		return rewriteValueAMD64_OpMinMaskedInt16x8(v)
+	case OpMinMaskedInt32x16:
+		return rewriteValueAMD64_OpMinMaskedInt32x16(v)
+	case OpMinMaskedInt32x4:
+		return rewriteValueAMD64_OpMinMaskedInt32x4(v)
+	case OpMinMaskedInt32x8:
+		return rewriteValueAMD64_OpMinMaskedInt32x8(v)
+	case OpMinMaskedInt64x2:
+		return rewriteValueAMD64_OpMinMaskedInt64x2(v)
+	case OpMinMaskedInt64x4:
+		return rewriteValueAMD64_OpMinMaskedInt64x4(v)
+	case OpMinMaskedInt64x8:
+		return rewriteValueAMD64_OpMinMaskedInt64x8(v)
+	case OpMinMaskedInt8x16:
+		return rewriteValueAMD64_OpMinMaskedInt8x16(v)
+	case OpMinMaskedInt8x32:
+		return rewriteValueAMD64_OpMinMaskedInt8x32(v)
+	case OpMinMaskedInt8x64:
+		return rewriteValueAMD64_OpMinMaskedInt8x64(v)
+	case OpMinMaskedUint16x16:
+		return rewriteValueAMD64_OpMinMaskedUint16x16(v)
+	case OpMinMaskedUint16x32:
+		return rewriteValueAMD64_OpMinMaskedUint16x32(v)
+	case OpMinMaskedUint16x8:
+		return rewriteValueAMD64_OpMinMaskedUint16x8(v)
+	case OpMinMaskedUint32x16:
+		return rewriteValueAMD64_OpMinMaskedUint32x16(v)
+	case OpMinMaskedUint32x4:
+		return rewriteValueAMD64_OpMinMaskedUint32x4(v)
+	case OpMinMaskedUint32x8:
+		return rewriteValueAMD64_OpMinMaskedUint32x8(v)
+	case OpMinMaskedUint64x2:
+		return rewriteValueAMD64_OpMinMaskedUint64x2(v)
+	case OpMinMaskedUint64x4:
+		return rewriteValueAMD64_OpMinMaskedUint64x4(v)
+	case OpMinMaskedUint64x8:
+		return rewriteValueAMD64_OpMinMaskedUint64x8(v)
+	case OpMinMaskedUint8x16:
+		return rewriteValueAMD64_OpMinMaskedUint8x16(v)
+	case OpMinMaskedUint8x32:
+		return rewriteValueAMD64_OpMinMaskedUint8x32(v)
+	case OpMinMaskedUint8x64:
+		return rewriteValueAMD64_OpMinMaskedUint8x64(v)
+	case OpMinUint16x16:
+		v.Op = OpAMD64VPMINUW256
+		return true
+	case OpMinUint16x32:
+		v.Op = OpAMD64VPMINUW512
+		return true
+	case OpMinUint16x8:
+		v.Op = OpAMD64VPMINUW128
+		return true
+	case OpMinUint32x16:
+		v.Op = OpAMD64VPMINUD512
+		return true
+	case OpMinUint32x4:
+		v.Op = OpAMD64VPMINUD128
+		return true
+	case OpMinUint32x8:
+		v.Op = OpAMD64VPMINUD256
+		return true
+	case OpMinUint64x2:
+		v.Op = OpAMD64VPMINUQ128
+		return true
+	case OpMinUint64x4:
+		v.Op = OpAMD64VPMINUQ256
+		return true
+	case OpMinUint64x8:
+		v.Op = OpAMD64VPMINUQ512
+		return true
+	case OpMinUint8x16:
+		v.Op = OpAMD64VPMINUB128
+		return true
+	case OpMinUint8x32:
+		v.Op = OpAMD64VPMINUB256
+		return true
+	case OpMinUint8x64:
+		v.Op = OpAMD64VPMINUB512
+		return true
 	case OpMod16:
 		return rewriteValueAMD64_OpMod16(v)
 	case OpMod16u:
@@ -922,6 +2819,183 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpMul8:
 		v.Op = OpAMD64MULL
 		return true
+	case OpMulByPowOf2Float32x16:
+		v.Op = OpAMD64VSCALEFPS512
+		return true
+	case OpMulByPowOf2Float32x4:
+		v.Op = OpAMD64VSCALEFPS128
+		return true
+	case OpMulByPowOf2Float32x8:
+		v.Op = OpAMD64VSCALEFPS256
+		return true
+	case OpMulByPowOf2Float64x2:
+		v.Op = OpAMD64VSCALEFPD128
+		return true
+	case OpMulByPowOf2Float64x4:
+		v.Op = OpAMD64VSCALEFPD256
+		return true
+	case OpMulByPowOf2Float64x8:
+		v.Op = OpAMD64VSCALEFPD512
+		return true
+	case OpMulByPowOf2MaskedFloat32x16:
+		return rewriteValueAMD64_OpMulByPowOf2MaskedFloat32x16(v)
+	case OpMulByPowOf2MaskedFloat32x4:
+		return rewriteValueAMD64_OpMulByPowOf2MaskedFloat32x4(v)
+	case OpMulByPowOf2MaskedFloat32x8:
+		return rewriteValueAMD64_OpMulByPowOf2MaskedFloat32x8(v)
+	case OpMulByPowOf2MaskedFloat64x2:
+		return rewriteValueAMD64_OpMulByPowOf2MaskedFloat64x2(v)
+	case OpMulByPowOf2MaskedFloat64x4:
+		return rewriteValueAMD64_OpMulByPowOf2MaskedFloat64x4(v)
+	case OpMulByPowOf2MaskedFloat64x8:
+		return rewriteValueAMD64_OpMulByPowOf2MaskedFloat64x8(v)
+	case OpMulEvenWidenInt32x4:
+		v.Op = OpAMD64VPMULDQ128
+		return true
+	case OpMulEvenWidenInt32x8:
+		v.Op = OpAMD64VPMULDQ256
+		return true
+	case OpMulEvenWidenInt64x2:
+		v.Op = OpAMD64VPMULDQ128
+		return true
+	case OpMulEvenWidenInt64x4:
+		v.Op = OpAMD64VPMULDQ256
+		return true
+	case OpMulEvenWidenInt64x8:
+		v.Op = OpAMD64VPMULDQ512
+		return true
+	case OpMulEvenWidenMaskedInt64x2:
+		return rewriteValueAMD64_OpMulEvenWidenMaskedInt64x2(v)
+	case OpMulEvenWidenMaskedInt64x4:
+		return rewriteValueAMD64_OpMulEvenWidenMaskedInt64x4(v)
+	case OpMulEvenWidenMaskedInt64x8:
+		return rewriteValueAMD64_OpMulEvenWidenMaskedInt64x8(v)
+	case OpMulEvenWidenMaskedUint64x2:
+		return rewriteValueAMD64_OpMulEvenWidenMaskedUint64x2(v)
+	case OpMulEvenWidenMaskedUint64x4:
+		return rewriteValueAMD64_OpMulEvenWidenMaskedUint64x4(v)
+	case OpMulEvenWidenMaskedUint64x8:
+		return rewriteValueAMD64_OpMulEvenWidenMaskedUint64x8(v)
+	case OpMulEvenWidenUint32x4:
+		v.Op = OpAMD64VPMULUDQ128
+		return true
+	case OpMulEvenWidenUint32x8:
+		v.Op = OpAMD64VPMULUDQ256
+		return true
+	case OpMulEvenWidenUint64x2:
+		v.Op = OpAMD64VPMULUDQ128
+		return true
+	case OpMulEvenWidenUint64x4:
+		v.Op = OpAMD64VPMULUDQ256
+		return true
+	case OpMulEvenWidenUint64x8:
+		v.Op = OpAMD64VPMULUDQ512
+		return true
+	case OpMulFloat32x16:
+		v.Op = OpAMD64VMULPS512
+		return true
+	case OpMulFloat32x4:
+		v.Op = OpAMD64VMULPS128
+		return true
+	case OpMulFloat32x8:
+		v.Op = OpAMD64VMULPS256
+		return true
+	case OpMulFloat64x2:
+		v.Op = OpAMD64VMULPD128
+		return true
+	case OpMulFloat64x4:
+		v.Op = OpAMD64VMULPD256
+		return true
+	case OpMulFloat64x8:
+		v.Op = OpAMD64VMULPD512
+		return true
+	case OpMulHighInt16x16:
+		v.Op = OpAMD64VPMULHW256
+		return true
+	case OpMulHighInt16x32:
+		v.Op = OpAMD64VPMULHW512
+		return true
+	case OpMulHighInt16x8:
+		v.Op = OpAMD64VPMULHW128
+		return true
+	case OpMulHighMaskedInt16x16:
+		return rewriteValueAMD64_OpMulHighMaskedInt16x16(v)
+	case OpMulHighMaskedInt16x32:
+		return rewriteValueAMD64_OpMulHighMaskedInt16x32(v)
+	case OpMulHighMaskedInt16x8:
+		return rewriteValueAMD64_OpMulHighMaskedInt16x8(v)
+	case OpMulHighMaskedUint16x16:
+		return rewriteValueAMD64_OpMulHighMaskedUint16x16(v)
+	case OpMulHighMaskedUint16x32:
+		return rewriteValueAMD64_OpMulHighMaskedUint16x32(v)
+	case OpMulHighMaskedUint16x8:
+		return rewriteValueAMD64_OpMulHighMaskedUint16x8(v)
+	case OpMulHighUint16x16:
+		v.Op = OpAMD64VPMULHUW256
+		return true
+	case OpMulHighUint16x32:
+		v.Op = OpAMD64VPMULHUW512
+		return true
+	case OpMulHighUint16x8:
+		v.Op = OpAMD64VPMULHUW128
+		return true
+	case OpMulLowInt16x16:
+		v.Op = OpAMD64VPMULLW256
+		return true
+	case OpMulLowInt16x32:
+		v.Op = OpAMD64VPMULLW512
+		return true
+	case OpMulLowInt16x8:
+		v.Op = OpAMD64VPMULLW128
+		return true
+	case OpMulLowInt32x16:
+		v.Op = OpAMD64VPMULLD512
+		return true
+	case OpMulLowInt32x4:
+		v.Op = OpAMD64VPMULLD128
+		return true
+	case OpMulLowInt32x8:
+		v.Op = OpAMD64VPMULLD256
+		return true
+	case OpMulLowInt64x2:
+		v.Op = OpAMD64VPMULLQ128
+		return true
+	case OpMulLowInt64x4:
+		v.Op = OpAMD64VPMULLQ256
+		return true
+	case OpMulLowInt64x8:
+		v.Op = OpAMD64VPMULLQ512
+		return true
+	case OpMulLowMaskedInt16x16:
+		return rewriteValueAMD64_OpMulLowMaskedInt16x16(v)
+	case OpMulLowMaskedInt16x32:
+		return rewriteValueAMD64_OpMulLowMaskedInt16x32(v)
+	case OpMulLowMaskedInt16x8:
+		return rewriteValueAMD64_OpMulLowMaskedInt16x8(v)
+	case OpMulLowMaskedInt32x16:
+		return rewriteValueAMD64_OpMulLowMaskedInt32x16(v)
+	case OpMulLowMaskedInt32x4:
+		return rewriteValueAMD64_OpMulLowMaskedInt32x4(v)
+	case OpMulLowMaskedInt32x8:
+		return rewriteValueAMD64_OpMulLowMaskedInt32x8(v)
+	case OpMulLowMaskedInt64x2:
+		return rewriteValueAMD64_OpMulLowMaskedInt64x2(v)
+	case OpMulLowMaskedInt64x4:
+		return rewriteValueAMD64_OpMulLowMaskedInt64x4(v)
+	case OpMulLowMaskedInt64x8:
+		return rewriteValueAMD64_OpMulLowMaskedInt64x8(v)
+	case OpMulMaskedFloat32x16:
+		return rewriteValueAMD64_OpMulMaskedFloat32x16(v)
+	case OpMulMaskedFloat32x4:
+		return rewriteValueAMD64_OpMulMaskedFloat32x4(v)
+	case OpMulMaskedFloat32x8:
+		return rewriteValueAMD64_OpMulMaskedFloat32x8(v)
+	case OpMulMaskedFloat64x2:
+		return rewriteValueAMD64_OpMulMaskedFloat64x2(v)
+	case OpMulMaskedFloat64x4:
+		return rewriteValueAMD64_OpMulMaskedFloat64x4(v)
+	case OpMulMaskedFloat64x8:
+		return rewriteValueAMD64_OpMulMaskedFloat64x8(v)
 	case OpNeg16:
 		v.Op = OpAMD64NEGL
 		return true
@@ -959,6 +3033,126 @@ func rewriteValueAMD64(v *Value) bool {
 		return true
 	case OpNot:
 		return rewriteValueAMD64_OpNot(v)
+	case OpNotEqualFloat32x16:
+		return rewriteValueAMD64_OpNotEqualFloat32x16(v)
+	case OpNotEqualFloat32x4:
+		return rewriteValueAMD64_OpNotEqualFloat32x4(v)
+	case OpNotEqualFloat32x8:
+		return rewriteValueAMD64_OpNotEqualFloat32x8(v)
+	case OpNotEqualFloat64x2:
+		return rewriteValueAMD64_OpNotEqualFloat64x2(v)
+	case OpNotEqualFloat64x4:
+		return rewriteValueAMD64_OpNotEqualFloat64x4(v)
+	case OpNotEqualFloat64x8:
+		return rewriteValueAMD64_OpNotEqualFloat64x8(v)
+	case OpNotEqualInt16x16:
+		return rewriteValueAMD64_OpNotEqualInt16x16(v)
+	case OpNotEqualInt16x32:
+		return rewriteValueAMD64_OpNotEqualInt16x32(v)
+	case OpNotEqualInt16x8:
+		return rewriteValueAMD64_OpNotEqualInt16x8(v)
+	case OpNotEqualInt32x16:
+		return rewriteValueAMD64_OpNotEqualInt32x16(v)
+	case OpNotEqualInt32x4:
+		return rewriteValueAMD64_OpNotEqualInt32x4(v)
+	case OpNotEqualInt32x8:
+		return rewriteValueAMD64_OpNotEqualInt32x8(v)
+	case OpNotEqualInt64x2:
+		return rewriteValueAMD64_OpNotEqualInt64x2(v)
+	case OpNotEqualInt64x4:
+		return rewriteValueAMD64_OpNotEqualInt64x4(v)
+	case OpNotEqualInt64x8:
+		return rewriteValueAMD64_OpNotEqualInt64x8(v)
+	case OpNotEqualInt8x16:
+		return rewriteValueAMD64_OpNotEqualInt8x16(v)
+	case OpNotEqualInt8x32:
+		return rewriteValueAMD64_OpNotEqualInt8x32(v)
+	case OpNotEqualInt8x64:
+		return rewriteValueAMD64_OpNotEqualInt8x64(v)
+	case OpNotEqualMaskedFloat32x16:
+		return rewriteValueAMD64_OpNotEqualMaskedFloat32x16(v)
+	case OpNotEqualMaskedFloat32x4:
+		return rewriteValueAMD64_OpNotEqualMaskedFloat32x4(v)
+	case OpNotEqualMaskedFloat32x8:
+		return rewriteValueAMD64_OpNotEqualMaskedFloat32x8(v)
+	case OpNotEqualMaskedFloat64x2:
+		return rewriteValueAMD64_OpNotEqualMaskedFloat64x2(v)
+	case OpNotEqualMaskedFloat64x4:
+		return rewriteValueAMD64_OpNotEqualMaskedFloat64x4(v)
+	case OpNotEqualMaskedFloat64x8:
+		return rewriteValueAMD64_OpNotEqualMaskedFloat64x8(v)
+	case OpNotEqualMaskedInt16x16:
+		return rewriteValueAMD64_OpNotEqualMaskedInt16x16(v)
+	case OpNotEqualMaskedInt16x32:
+		return rewriteValueAMD64_OpNotEqualMaskedInt16x32(v)
+	case OpNotEqualMaskedInt16x8:
+		return rewriteValueAMD64_OpNotEqualMaskedInt16x8(v)
+	case OpNotEqualMaskedInt32x16:
+		return rewriteValueAMD64_OpNotEqualMaskedInt32x16(v)
+	case OpNotEqualMaskedInt32x4:
+		return rewriteValueAMD64_OpNotEqualMaskedInt32x4(v)
+	case OpNotEqualMaskedInt32x8:
+		return rewriteValueAMD64_OpNotEqualMaskedInt32x8(v)
+	case OpNotEqualMaskedInt64x2:
+		return rewriteValueAMD64_OpNotEqualMaskedInt64x2(v)
+	case OpNotEqualMaskedInt64x4:
+		return rewriteValueAMD64_OpNotEqualMaskedInt64x4(v)
+	case OpNotEqualMaskedInt64x8:
+		return rewriteValueAMD64_OpNotEqualMaskedInt64x8(v)
+	case OpNotEqualMaskedInt8x16:
+		return rewriteValueAMD64_OpNotEqualMaskedInt8x16(v)
+	case OpNotEqualMaskedInt8x32:
+		return rewriteValueAMD64_OpNotEqualMaskedInt8x32(v)
+	case OpNotEqualMaskedInt8x64:
+		return rewriteValueAMD64_OpNotEqualMaskedInt8x64(v)
+	case OpNotEqualMaskedUint16x16:
+		return rewriteValueAMD64_OpNotEqualMaskedUint16x16(v)
+	case OpNotEqualMaskedUint16x32:
+		return rewriteValueAMD64_OpNotEqualMaskedUint16x32(v)
+	case OpNotEqualMaskedUint16x8:
+		return rewriteValueAMD64_OpNotEqualMaskedUint16x8(v)
+	case OpNotEqualMaskedUint32x16:
+		return rewriteValueAMD64_OpNotEqualMaskedUint32x16(v)
+	case OpNotEqualMaskedUint32x4:
+		return rewriteValueAMD64_OpNotEqualMaskedUint32x4(v)
+	case OpNotEqualMaskedUint32x8:
+		return rewriteValueAMD64_OpNotEqualMaskedUint32x8(v)
+	case OpNotEqualMaskedUint64x2:
+		return rewriteValueAMD64_OpNotEqualMaskedUint64x2(v)
+	case OpNotEqualMaskedUint64x4:
+		return rewriteValueAMD64_OpNotEqualMaskedUint64x4(v)
+	case OpNotEqualMaskedUint64x8:
+		return rewriteValueAMD64_OpNotEqualMaskedUint64x8(v)
+	case OpNotEqualMaskedUint8x16:
+		return rewriteValueAMD64_OpNotEqualMaskedUint8x16(v)
+	case OpNotEqualMaskedUint8x32:
+		return rewriteValueAMD64_OpNotEqualMaskedUint8x32(v)
+	case OpNotEqualMaskedUint8x64:
+		return rewriteValueAMD64_OpNotEqualMaskedUint8x64(v)
+	case OpNotEqualUint16x16:
+		return rewriteValueAMD64_OpNotEqualUint16x16(v)
+	case OpNotEqualUint16x32:
+		return rewriteValueAMD64_OpNotEqualUint16x32(v)
+	case OpNotEqualUint16x8:
+		return rewriteValueAMD64_OpNotEqualUint16x8(v)
+	case OpNotEqualUint32x16:
+		return rewriteValueAMD64_OpNotEqualUint32x16(v)
+	case OpNotEqualUint32x4:
+		return rewriteValueAMD64_OpNotEqualUint32x4(v)
+	case OpNotEqualUint32x8:
+		return rewriteValueAMD64_OpNotEqualUint32x8(v)
+	case OpNotEqualUint64x2:
+		return rewriteValueAMD64_OpNotEqualUint64x2(v)
+	case OpNotEqualUint64x4:
+		return rewriteValueAMD64_OpNotEqualUint64x4(v)
+	case OpNotEqualUint64x8:
+		return rewriteValueAMD64_OpNotEqualUint64x8(v)
+	case OpNotEqualUint8x16:
+		return rewriteValueAMD64_OpNotEqualUint8x16(v)
+	case OpNotEqualUint8x32:
+		return rewriteValueAMD64_OpNotEqualUint8x32(v)
+	case OpNotEqualUint8x64:
+		return rewriteValueAMD64_OpNotEqualUint8x64(v)
 	case OpOffPtr:
 		return rewriteValueAMD64_OpOffPtr(v)
 	case OpOr16:
@@ -976,8 +3170,464 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpOrB:
 		v.Op = OpAMD64ORL
 		return true
+	case OpOrInt16x16:
+		v.Op = OpAMD64VPOR256
+		return true
+	case OpOrInt16x8:
+		v.Op = OpAMD64VPOR128
+		return true
+	case OpOrInt32x16:
+		v.Op = OpAMD64VPORD512
+		return true
+	case OpOrInt32x4:
+		v.Op = OpAMD64VPOR128
+		return true
+	case OpOrInt32x8:
+		v.Op = OpAMD64VPOR256
+		return true
+	case OpOrInt64x2:
+		v.Op = OpAMD64VPOR128
+		return true
+	case OpOrInt64x4:
+		v.Op = OpAMD64VPOR256
+		return true
+	case OpOrInt64x8:
+		v.Op = OpAMD64VPORQ512
+		return true
+	case OpOrInt8x16:
+		v.Op = OpAMD64VPOR128
+		return true
+	case OpOrInt8x32:
+		v.Op = OpAMD64VPOR256
+		return true
+	case OpOrMaskedInt32x16:
+		return rewriteValueAMD64_OpOrMaskedInt32x16(v)
+	case OpOrMaskedInt32x4:
+		return rewriteValueAMD64_OpOrMaskedInt32x4(v)
+	case OpOrMaskedInt32x8:
+		return rewriteValueAMD64_OpOrMaskedInt32x8(v)
+	case OpOrMaskedInt64x2:
+		return rewriteValueAMD64_OpOrMaskedInt64x2(v)
+	case OpOrMaskedInt64x4:
+		return rewriteValueAMD64_OpOrMaskedInt64x4(v)
+	case OpOrMaskedInt64x8:
+		return rewriteValueAMD64_OpOrMaskedInt64x8(v)
+	case OpOrMaskedUint32x16:
+		return rewriteValueAMD64_OpOrMaskedUint32x16(v)
+	case OpOrMaskedUint32x4:
+		return rewriteValueAMD64_OpOrMaskedUint32x4(v)
+	case OpOrMaskedUint32x8:
+		return rewriteValueAMD64_OpOrMaskedUint32x8(v)
+	case OpOrMaskedUint64x2:
+		return rewriteValueAMD64_OpOrMaskedUint64x2(v)
+	case OpOrMaskedUint64x4:
+		return rewriteValueAMD64_OpOrMaskedUint64x4(v)
+	case OpOrMaskedUint64x8:
+		return rewriteValueAMD64_OpOrMaskedUint64x8(v)
+	case OpOrUint16x16:
+		v.Op = OpAMD64VPOR256
+		return true
+	case OpOrUint16x8:
+		v.Op = OpAMD64VPOR128
+		return true
+	case OpOrUint32x16:
+		v.Op = OpAMD64VPORD512
+		return true
+	case OpOrUint32x4:
+		v.Op = OpAMD64VPOR128
+		return true
+	case OpOrUint32x8:
+		v.Op = OpAMD64VPOR256
+		return true
+	case OpOrUint64x2:
+		v.Op = OpAMD64VPOR128
+		return true
+	case OpOrUint64x4:
+		v.Op = OpAMD64VPOR256
+		return true
+	case OpOrUint64x8:
+		v.Op = OpAMD64VPORQ512
+		return true
+	case OpOrUint8x16:
+		v.Op = OpAMD64VPOR128
+		return true
+	case OpOrUint8x32:
+		v.Op = OpAMD64VPOR256
+		return true
+	case OpPairDotProdAccumulateInt32x16:
+		v.Op = OpAMD64VPDPWSSD512
+		return true
+	case OpPairDotProdAccumulateInt32x4:
+		v.Op = OpAMD64VPDPWSSD128
+		return true
+	case OpPairDotProdAccumulateInt32x8:
+		v.Op = OpAMD64VPDPWSSD256
+		return true
+	case OpPairDotProdAccumulateMaskedInt32x16:
+		return rewriteValueAMD64_OpPairDotProdAccumulateMaskedInt32x16(v)
+	case OpPairDotProdAccumulateMaskedInt32x4:
+		return rewriteValueAMD64_OpPairDotProdAccumulateMaskedInt32x4(v)
+	case OpPairDotProdAccumulateMaskedInt32x8:
+		return rewriteValueAMD64_OpPairDotProdAccumulateMaskedInt32x8(v)
+	case OpPairDotProdInt16x16:
+		v.Op = OpAMD64VPMADDWD256
+		return true
+	case OpPairDotProdInt16x32:
+		v.Op = OpAMD64VPMADDWD512
+		return true
+	case OpPairDotProdInt16x8:
+		v.Op = OpAMD64VPMADDWD128
+		return true
+	case OpPairDotProdMaskedInt16x16:
+		return rewriteValueAMD64_OpPairDotProdMaskedInt16x16(v)
+	case OpPairDotProdMaskedInt16x32:
+		return rewriteValueAMD64_OpPairDotProdMaskedInt16x32(v)
+	case OpPairDotProdMaskedInt16x8:
+		return rewriteValueAMD64_OpPairDotProdMaskedInt16x8(v)
+	case OpPairwiseAddFloat32x4:
+		v.Op = OpAMD64VHADDPS128
+		return true
+	case OpPairwiseAddFloat32x8:
+		v.Op = OpAMD64VHADDPS256
+		return true
+	case OpPairwiseAddFloat64x2:
+		v.Op = OpAMD64VHADDPD128
+		return true
+	case OpPairwiseAddFloat64x4:
+		v.Op = OpAMD64VHADDPD256
+		return true
+	case OpPairwiseAddInt16x16:
+		v.Op = OpAMD64VPHADDW256
+		return true
+	case OpPairwiseAddInt16x8:
+		v.Op = OpAMD64VPHADDW128
+		return true
+	case OpPairwiseAddInt32x4:
+		v.Op = OpAMD64VPHADDD128
+		return true
+	case OpPairwiseAddInt32x8:
+		v.Op = OpAMD64VPHADDD256
+		return true
+	case OpPairwiseAddUint16x16:
+		v.Op = OpAMD64VPHADDW256
+		return true
+	case OpPairwiseAddUint16x8:
+		v.Op = OpAMD64VPHADDW128
+		return true
+	case OpPairwiseAddUint32x4:
+		v.Op = OpAMD64VPHADDD128
+		return true
+	case OpPairwiseAddUint32x8:
+		v.Op = OpAMD64VPHADDD256
+		return true
+	case OpPairwiseSubFloat32x4:
+		v.Op = OpAMD64VHSUBPS128
+		return true
+	case OpPairwiseSubFloat32x8:
+		v.Op = OpAMD64VHSUBPS256
+		return true
+	case OpPairwiseSubFloat64x2:
+		v.Op = OpAMD64VHSUBPD128
+		return true
+	case OpPairwiseSubFloat64x4:
+		v.Op = OpAMD64VHSUBPD256
+		return true
+	case OpPairwiseSubInt16x16:
+		v.Op = OpAMD64VPHSUBW256
+		return true
+	case OpPairwiseSubInt16x8:
+		v.Op = OpAMD64VPHSUBW128
+		return true
+	case OpPairwiseSubInt32x4:
+		v.Op = OpAMD64VPHSUBD128
+		return true
+	case OpPairwiseSubInt32x8:
+		v.Op = OpAMD64VPHSUBD256
+		return true
+	case OpPairwiseSubUint16x16:
+		v.Op = OpAMD64VPHSUBW256
+		return true
+	case OpPairwiseSubUint16x8:
+		v.Op = OpAMD64VPHSUBW128
+		return true
+	case OpPairwiseSubUint32x4:
+		v.Op = OpAMD64VPHSUBD128
+		return true
+	case OpPairwiseSubUint32x8:
+		v.Op = OpAMD64VPHSUBD256
+		return true
 	case OpPanicBounds:
 		return rewriteValueAMD64_OpPanicBounds(v)
+	case OpPermute2Float32x16:
+		v.Op = OpAMD64VPERMI2PS512
+		return true
+	case OpPermute2Float32x4:
+		v.Op = OpAMD64VPERMI2PS128
+		return true
+	case OpPermute2Float32x8:
+		v.Op = OpAMD64VPERMI2PS256
+		return true
+	case OpPermute2Float64x2:
+		v.Op = OpAMD64VPERMI2PD128
+		return true
+	case OpPermute2Float64x4:
+		v.Op = OpAMD64VPERMI2PD256
+		return true
+	case OpPermute2Float64x8:
+		v.Op = OpAMD64VPERMI2PD512
+		return true
+	case OpPermute2Int16x16:
+		v.Op = OpAMD64VPERMI2W256
+		return true
+	case OpPermute2Int16x32:
+		v.Op = OpAMD64VPERMI2W512
+		return true
+	case OpPermute2Int16x8:
+		v.Op = OpAMD64VPERMI2W128
+		return true
+	case OpPermute2Int32x16:
+		v.Op = OpAMD64VPERMI2D512
+		return true
+	case OpPermute2Int32x4:
+		v.Op = OpAMD64VPERMI2D128
+		return true
+	case OpPermute2Int32x8:
+		v.Op = OpAMD64VPERMI2D256
+		return true
+	case OpPermute2Int64x2:
+		v.Op = OpAMD64VPERMI2Q128
+		return true
+	case OpPermute2Int64x4:
+		v.Op = OpAMD64VPERMI2Q256
+		return true
+	case OpPermute2Int64x8:
+		v.Op = OpAMD64VPERMI2Q512
+		return true
+	case OpPermute2Int8x16:
+		v.Op = OpAMD64VPERMI2B128
+		return true
+	case OpPermute2Int8x32:
+		v.Op = OpAMD64VPERMI2B256
+		return true
+	case OpPermute2Int8x64:
+		v.Op = OpAMD64VPERMI2B512
+		return true
+	case OpPermute2MaskedFloat32x16:
+		return rewriteValueAMD64_OpPermute2MaskedFloat32x16(v)
+	case OpPermute2MaskedFloat32x4:
+		return rewriteValueAMD64_OpPermute2MaskedFloat32x4(v)
+	case OpPermute2MaskedFloat32x8:
+		return rewriteValueAMD64_OpPermute2MaskedFloat32x8(v)
+	case OpPermute2MaskedFloat64x2:
+		return rewriteValueAMD64_OpPermute2MaskedFloat64x2(v)
+	case OpPermute2MaskedFloat64x4:
+		return rewriteValueAMD64_OpPermute2MaskedFloat64x4(v)
+	case OpPermute2MaskedFloat64x8:
+		return rewriteValueAMD64_OpPermute2MaskedFloat64x8(v)
+	case OpPermute2MaskedInt16x16:
+		return rewriteValueAMD64_OpPermute2MaskedInt16x16(v)
+	case OpPermute2MaskedInt16x32:
+		return rewriteValueAMD64_OpPermute2MaskedInt16x32(v)
+	case OpPermute2MaskedInt16x8:
+		return rewriteValueAMD64_OpPermute2MaskedInt16x8(v)
+	case OpPermute2MaskedInt32x16:
+		return rewriteValueAMD64_OpPermute2MaskedInt32x16(v)
+	case OpPermute2MaskedInt32x4:
+		return rewriteValueAMD64_OpPermute2MaskedInt32x4(v)
+	case OpPermute2MaskedInt32x8:
+		return rewriteValueAMD64_OpPermute2MaskedInt32x8(v)
+	case OpPermute2MaskedInt64x2:
+		return rewriteValueAMD64_OpPermute2MaskedInt64x2(v)
+	case OpPermute2MaskedInt64x4:
+		return rewriteValueAMD64_OpPermute2MaskedInt64x4(v)
+	case OpPermute2MaskedInt64x8:
+		return rewriteValueAMD64_OpPermute2MaskedInt64x8(v)
+	case OpPermute2MaskedInt8x16:
+		return rewriteValueAMD64_OpPermute2MaskedInt8x16(v)
+	case OpPermute2MaskedInt8x32:
+		return rewriteValueAMD64_OpPermute2MaskedInt8x32(v)
+	case OpPermute2MaskedInt8x64:
+		return rewriteValueAMD64_OpPermute2MaskedInt8x64(v)
+	case OpPermute2MaskedUint16x16:
+		return rewriteValueAMD64_OpPermute2MaskedUint16x16(v)
+	case OpPermute2MaskedUint16x32:
+		return rewriteValueAMD64_OpPermute2MaskedUint16x32(v)
+	case OpPermute2MaskedUint16x8:
+		return rewriteValueAMD64_OpPermute2MaskedUint16x8(v)
+	case OpPermute2MaskedUint32x16:
+		return rewriteValueAMD64_OpPermute2MaskedUint32x16(v)
+	case OpPermute2MaskedUint32x4:
+		return rewriteValueAMD64_OpPermute2MaskedUint32x4(v)
+	case OpPermute2MaskedUint32x8:
+		return rewriteValueAMD64_OpPermute2MaskedUint32x8(v)
+	case OpPermute2MaskedUint64x2:
+		return rewriteValueAMD64_OpPermute2MaskedUint64x2(v)
+	case OpPermute2MaskedUint64x4:
+		return rewriteValueAMD64_OpPermute2MaskedUint64x4(v)
+	case OpPermute2MaskedUint64x8:
+		return rewriteValueAMD64_OpPermute2MaskedUint64x8(v)
+	case OpPermute2MaskedUint8x16:
+		return rewriteValueAMD64_OpPermute2MaskedUint8x16(v)
+	case OpPermute2MaskedUint8x32:
+		return rewriteValueAMD64_OpPermute2MaskedUint8x32(v)
+	case OpPermute2MaskedUint8x64:
+		return rewriteValueAMD64_OpPermute2MaskedUint8x64(v)
+	case OpPermute2Uint16x16:
+		v.Op = OpAMD64VPERMI2W256
+		return true
+	case OpPermute2Uint16x32:
+		v.Op = OpAMD64VPERMI2W512
+		return true
+	case OpPermute2Uint16x8:
+		v.Op = OpAMD64VPERMI2W128
+		return true
+	case OpPermute2Uint32x16:
+		v.Op = OpAMD64VPERMI2D512
+		return true
+	case OpPermute2Uint32x4:
+		v.Op = OpAMD64VPERMI2D128
+		return true
+	case OpPermute2Uint32x8:
+		v.Op = OpAMD64VPERMI2D256
+		return true
+	case OpPermute2Uint64x2:
+		v.Op = OpAMD64VPERMI2Q128
+		return true
+	case OpPermute2Uint64x4:
+		v.Op = OpAMD64VPERMI2Q256
+		return true
+	case OpPermute2Uint64x8:
+		v.Op = OpAMD64VPERMI2Q512
+		return true
+	case OpPermute2Uint8x16:
+		v.Op = OpAMD64VPERMI2B128
+		return true
+	case OpPermute2Uint8x32:
+		v.Op = OpAMD64VPERMI2B256
+		return true
+	case OpPermute2Uint8x64:
+		v.Op = OpAMD64VPERMI2B512
+		return true
+	case OpPermuteFloat32x16:
+		v.Op = OpAMD64VPERMPS512
+		return true
+	case OpPermuteFloat32x8:
+		v.Op = OpAMD64VPERMPS256
+		return true
+	case OpPermuteFloat64x4:
+		v.Op = OpAMD64VPERMPD256
+		return true
+	case OpPermuteFloat64x8:
+		v.Op = OpAMD64VPERMPD512
+		return true
+	case OpPermuteInt16x16:
+		v.Op = OpAMD64VPERMW256
+		return true
+	case OpPermuteInt16x32:
+		v.Op = OpAMD64VPERMW512
+		return true
+	case OpPermuteInt16x8:
+		v.Op = OpAMD64VPERMW128
+		return true
+	case OpPermuteInt32x16:
+		v.Op = OpAMD64VPERMD512
+		return true
+	case OpPermuteInt32x8:
+		v.Op = OpAMD64VPERMD256
+		return true
+	case OpPermuteInt64x4:
+		v.Op = OpAMD64VPERMQ256
+		return true
+	case OpPermuteInt64x8:
+		v.Op = OpAMD64VPERMQ512
+		return true
+	case OpPermuteInt8x16:
+		v.Op = OpAMD64VPERMB128
+		return true
+	case OpPermuteInt8x32:
+		v.Op = OpAMD64VPERMB256
+		return true
+	case OpPermuteInt8x64:
+		v.Op = OpAMD64VPERMB512
+		return true
+	case OpPermuteMaskedFloat32x16:
+		return rewriteValueAMD64_OpPermuteMaskedFloat32x16(v)
+	case OpPermuteMaskedFloat32x8:
+		return rewriteValueAMD64_OpPermuteMaskedFloat32x8(v)
+	case OpPermuteMaskedFloat64x4:
+		return rewriteValueAMD64_OpPermuteMaskedFloat64x4(v)
+	case OpPermuteMaskedFloat64x8:
+		return rewriteValueAMD64_OpPermuteMaskedFloat64x8(v)
+	case OpPermuteMaskedInt16x16:
+		return rewriteValueAMD64_OpPermuteMaskedInt16x16(v)
+	case OpPermuteMaskedInt16x32:
+		return rewriteValueAMD64_OpPermuteMaskedInt16x32(v)
+	case OpPermuteMaskedInt16x8:
+		return rewriteValueAMD64_OpPermuteMaskedInt16x8(v)
+	case OpPermuteMaskedInt32x16:
+		return rewriteValueAMD64_OpPermuteMaskedInt32x16(v)
+	case OpPermuteMaskedInt32x8:
+		return rewriteValueAMD64_OpPermuteMaskedInt32x8(v)
+	case OpPermuteMaskedInt64x4:
+		return rewriteValueAMD64_OpPermuteMaskedInt64x4(v)
+	case OpPermuteMaskedInt64x8:
+		return rewriteValueAMD64_OpPermuteMaskedInt64x8(v)
+	case OpPermuteMaskedInt8x16:
+		return rewriteValueAMD64_OpPermuteMaskedInt8x16(v)
+	case OpPermuteMaskedInt8x32:
+		return rewriteValueAMD64_OpPermuteMaskedInt8x32(v)
+	case OpPermuteMaskedInt8x64:
+		return rewriteValueAMD64_OpPermuteMaskedInt8x64(v)
+	case OpPermuteMaskedUint16x16:
+		return rewriteValueAMD64_OpPermuteMaskedUint16x16(v)
+	case OpPermuteMaskedUint16x32:
+		return rewriteValueAMD64_OpPermuteMaskedUint16x32(v)
+	case OpPermuteMaskedUint16x8:
+		return rewriteValueAMD64_OpPermuteMaskedUint16x8(v)
+	case OpPermuteMaskedUint32x16:
+		return rewriteValueAMD64_OpPermuteMaskedUint32x16(v)
+	case OpPermuteMaskedUint32x8:
+		return rewriteValueAMD64_OpPermuteMaskedUint32x8(v)
+	case OpPermuteMaskedUint64x4:
+		return rewriteValueAMD64_OpPermuteMaskedUint64x4(v)
+	case OpPermuteMaskedUint64x8:
+		return rewriteValueAMD64_OpPermuteMaskedUint64x8(v)
+	case OpPermuteMaskedUint8x16:
+		return rewriteValueAMD64_OpPermuteMaskedUint8x16(v)
+	case OpPermuteMaskedUint8x32:
+		return rewriteValueAMD64_OpPermuteMaskedUint8x32(v)
+	case OpPermuteMaskedUint8x64:
+		return rewriteValueAMD64_OpPermuteMaskedUint8x64(v)
+	case OpPermuteUint16x16:
+		v.Op = OpAMD64VPERMW256
+		return true
+	case OpPermuteUint16x32:
+		v.Op = OpAMD64VPERMW512
+		return true
+	case OpPermuteUint16x8:
+		v.Op = OpAMD64VPERMW128
+		return true
+	case OpPermuteUint32x16:
+		v.Op = OpAMD64VPERMD512
+		return true
+	case OpPermuteUint32x8:
+		v.Op = OpAMD64VPERMD256
+		return true
+	case OpPermuteUint64x4:
+		v.Op = OpAMD64VPERMQ256
+		return true
+	case OpPermuteUint64x8:
+		v.Op = OpAMD64VPERMQ512
+		return true
+	case OpPermuteUint8x16:
+		v.Op = OpAMD64VPERMB128
+		return true
+	case OpPermuteUint8x32:
+		v.Op = OpAMD64VPERMB256
+		return true
+	case OpPermuteUint8x64:
+		v.Op = OpAMD64VPERMB512
+		return true
 	case OpPopCount16:
 		return rewriteValueAMD64_OpPopCount16(v)
 	case OpPopCount32:
@@ -988,12 +3638,252 @@ func rewriteValueAMD64(v *Value) bool {
 		return true
 	case OpPopCount8:
 		return rewriteValueAMD64_OpPopCount8(v)
+	case OpPopCountInt16x16:
+		v.Op = OpAMD64VPOPCNTW256
+		return true
+	case OpPopCountInt16x32:
+		v.Op = OpAMD64VPOPCNTW512
+		return true
+	case OpPopCountInt16x8:
+		v.Op = OpAMD64VPOPCNTW128
+		return true
+	case OpPopCountInt32x16:
+		v.Op = OpAMD64VPOPCNTD512
+		return true
+	case OpPopCountInt32x4:
+		v.Op = OpAMD64VPOPCNTD128
+		return true
+	case OpPopCountInt32x8:
+		v.Op = OpAMD64VPOPCNTD256
+		return true
+	case OpPopCountInt64x2:
+		v.Op = OpAMD64VPOPCNTQ128
+		return true
+	case OpPopCountInt64x4:
+		v.Op = OpAMD64VPOPCNTQ256
+		return true
+	case OpPopCountInt64x8:
+		v.Op = OpAMD64VPOPCNTQ512
+		return true
+	case OpPopCountInt8x16:
+		v.Op = OpAMD64VPOPCNTB128
+		return true
+	case OpPopCountInt8x32:
+		v.Op = OpAMD64VPOPCNTB256
+		return true
+	case OpPopCountInt8x64:
+		v.Op = OpAMD64VPOPCNTB512
+		return true
+	case OpPopCountMaskedInt16x16:
+		return rewriteValueAMD64_OpPopCountMaskedInt16x16(v)
+	case OpPopCountMaskedInt16x32:
+		return rewriteValueAMD64_OpPopCountMaskedInt16x32(v)
+	case OpPopCountMaskedInt16x8:
+		return rewriteValueAMD64_OpPopCountMaskedInt16x8(v)
+	case OpPopCountMaskedInt32x16:
+		return rewriteValueAMD64_OpPopCountMaskedInt32x16(v)
+	case OpPopCountMaskedInt32x4:
+		return rewriteValueAMD64_OpPopCountMaskedInt32x4(v)
+	case OpPopCountMaskedInt32x8:
+		return rewriteValueAMD64_OpPopCountMaskedInt32x8(v)
+	case OpPopCountMaskedInt64x2:
+		return rewriteValueAMD64_OpPopCountMaskedInt64x2(v)
+	case OpPopCountMaskedInt64x4:
+		return rewriteValueAMD64_OpPopCountMaskedInt64x4(v)
+	case OpPopCountMaskedInt64x8:
+		return rewriteValueAMD64_OpPopCountMaskedInt64x8(v)
+	case OpPopCountMaskedInt8x16:
+		return rewriteValueAMD64_OpPopCountMaskedInt8x16(v)
+	case OpPopCountMaskedInt8x32:
+		return rewriteValueAMD64_OpPopCountMaskedInt8x32(v)
+	case OpPopCountMaskedInt8x64:
+		return rewriteValueAMD64_OpPopCountMaskedInt8x64(v)
+	case OpPopCountMaskedUint16x16:
+		return rewriteValueAMD64_OpPopCountMaskedUint16x16(v)
+	case OpPopCountMaskedUint16x32:
+		return rewriteValueAMD64_OpPopCountMaskedUint16x32(v)
+	case OpPopCountMaskedUint16x8:
+		return rewriteValueAMD64_OpPopCountMaskedUint16x8(v)
+	case OpPopCountMaskedUint32x16:
+		return rewriteValueAMD64_OpPopCountMaskedUint32x16(v)
+	case OpPopCountMaskedUint32x4:
+		return rewriteValueAMD64_OpPopCountMaskedUint32x4(v)
+	case OpPopCountMaskedUint32x8:
+		return rewriteValueAMD64_OpPopCountMaskedUint32x8(v)
+	case OpPopCountMaskedUint64x2:
+		return rewriteValueAMD64_OpPopCountMaskedUint64x2(v)
+	case OpPopCountMaskedUint64x4:
+		return rewriteValueAMD64_OpPopCountMaskedUint64x4(v)
+	case OpPopCountMaskedUint64x8:
+		return rewriteValueAMD64_OpPopCountMaskedUint64x8(v)
+	case OpPopCountMaskedUint8x16:
+		return rewriteValueAMD64_OpPopCountMaskedUint8x16(v)
+	case OpPopCountMaskedUint8x32:
+		return rewriteValueAMD64_OpPopCountMaskedUint8x32(v)
+	case OpPopCountMaskedUint8x64:
+		return rewriteValueAMD64_OpPopCountMaskedUint8x64(v)
+	case OpPopCountUint16x16:
+		v.Op = OpAMD64VPOPCNTW256
+		return true
+	case OpPopCountUint16x32:
+		v.Op = OpAMD64VPOPCNTW512
+		return true
+	case OpPopCountUint16x8:
+		v.Op = OpAMD64VPOPCNTW128
+		return true
+	case OpPopCountUint32x16:
+		v.Op = OpAMD64VPOPCNTD512
+		return true
+	case OpPopCountUint32x4:
+		v.Op = OpAMD64VPOPCNTD128
+		return true
+	case OpPopCountUint32x8:
+		v.Op = OpAMD64VPOPCNTD256
+		return true
+	case OpPopCountUint64x2:
+		v.Op = OpAMD64VPOPCNTQ128
+		return true
+	case OpPopCountUint64x4:
+		v.Op = OpAMD64VPOPCNTQ256
+		return true
+	case OpPopCountUint64x8:
+		v.Op = OpAMD64VPOPCNTQ512
+		return true
+	case OpPopCountUint8x16:
+		v.Op = OpAMD64VPOPCNTB128
+		return true
+	case OpPopCountUint8x32:
+		v.Op = OpAMD64VPOPCNTB256
+		return true
+	case OpPopCountUint8x64:
+		v.Op = OpAMD64VPOPCNTB512
+		return true
 	case OpPrefetchCache:
 		v.Op = OpAMD64PrefetchT0
 		return true
 	case OpPrefetchCacheStreamed:
 		v.Op = OpAMD64PrefetchNTA
 		return true
+	case OpRotateAllLeftInt32x16:
+		v.Op = OpAMD64VPROLD512
+		return true
+	case OpRotateAllLeftInt32x4:
+		v.Op = OpAMD64VPROLD128
+		return true
+	case OpRotateAllLeftInt32x8:
+		v.Op = OpAMD64VPROLD256
+		return true
+	case OpRotateAllLeftInt64x2:
+		v.Op = OpAMD64VPROLQ128
+		return true
+	case OpRotateAllLeftInt64x4:
+		v.Op = OpAMD64VPROLQ256
+		return true
+	case OpRotateAllLeftInt64x8:
+		v.Op = OpAMD64VPROLQ512
+		return true
+	case OpRotateAllLeftMaskedInt32x16:
+		return rewriteValueAMD64_OpRotateAllLeftMaskedInt32x16(v)
+	case OpRotateAllLeftMaskedInt32x4:
+		return rewriteValueAMD64_OpRotateAllLeftMaskedInt32x4(v)
+	case OpRotateAllLeftMaskedInt32x8:
+		return rewriteValueAMD64_OpRotateAllLeftMaskedInt32x8(v)
+	case OpRotateAllLeftMaskedInt64x2:
+		return rewriteValueAMD64_OpRotateAllLeftMaskedInt64x2(v)
+	case OpRotateAllLeftMaskedInt64x4:
+		return rewriteValueAMD64_OpRotateAllLeftMaskedInt64x4(v)
+	case OpRotateAllLeftMaskedInt64x8:
+		return rewriteValueAMD64_OpRotateAllLeftMaskedInt64x8(v)
+	case OpRotateAllLeftMaskedUint32x16:
+		return rewriteValueAMD64_OpRotateAllLeftMaskedUint32x16(v)
+	case OpRotateAllLeftMaskedUint32x4:
+		return rewriteValueAMD64_OpRotateAllLeftMaskedUint32x4(v)
+	case OpRotateAllLeftMaskedUint32x8:
+		return rewriteValueAMD64_OpRotateAllLeftMaskedUint32x8(v)
+	case OpRotateAllLeftMaskedUint64x2:
+		return rewriteValueAMD64_OpRotateAllLeftMaskedUint64x2(v)
+	case OpRotateAllLeftMaskedUint64x4:
+		return rewriteValueAMD64_OpRotateAllLeftMaskedUint64x4(v)
+	case OpRotateAllLeftMaskedUint64x8:
+		return rewriteValueAMD64_OpRotateAllLeftMaskedUint64x8(v)
+	case OpRotateAllLeftUint32x16:
+		v.Op = OpAMD64VPROLD512
+		return true
+	case OpRotateAllLeftUint32x4:
+		v.Op = OpAMD64VPROLD128
+		return true
+	case OpRotateAllLeftUint32x8:
+		v.Op = OpAMD64VPROLD256
+		return true
+	case OpRotateAllLeftUint64x2:
+		v.Op = OpAMD64VPROLQ128
+		return true
+	case OpRotateAllLeftUint64x4:
+		v.Op = OpAMD64VPROLQ256
+		return true
+	case OpRotateAllLeftUint64x8:
+		v.Op = OpAMD64VPROLQ512
+		return true
+	case OpRotateAllRightInt32x16:
+		v.Op = OpAMD64VPRORD512
+		return true
+	case OpRotateAllRightInt32x4:
+		v.Op = OpAMD64VPRORD128
+		return true
+	case OpRotateAllRightInt32x8:
+		v.Op = OpAMD64VPRORD256
+		return true
+	case OpRotateAllRightInt64x2:
+		v.Op = OpAMD64VPRORQ128
+		return true
+	case OpRotateAllRightInt64x4:
+		v.Op = OpAMD64VPRORQ256
+		return true
+	case OpRotateAllRightInt64x8:
+		v.Op = OpAMD64VPRORQ512
+		return true
+	case OpRotateAllRightMaskedInt32x16:
+		return rewriteValueAMD64_OpRotateAllRightMaskedInt32x16(v)
+	case OpRotateAllRightMaskedInt32x4:
+		return rewriteValueAMD64_OpRotateAllRightMaskedInt32x4(v)
+	case OpRotateAllRightMaskedInt32x8:
+		return rewriteValueAMD64_OpRotateAllRightMaskedInt32x8(v)
+	case OpRotateAllRightMaskedInt64x2:
+		return rewriteValueAMD64_OpRotateAllRightMaskedInt64x2(v)
+	case OpRotateAllRightMaskedInt64x4:
+		return rewriteValueAMD64_OpRotateAllRightMaskedInt64x4(v)
+	case OpRotateAllRightMaskedInt64x8:
+		return rewriteValueAMD64_OpRotateAllRightMaskedInt64x8(v)
+	case OpRotateAllRightMaskedUint32x16:
+		return rewriteValueAMD64_OpRotateAllRightMaskedUint32x16(v)
+	case OpRotateAllRightMaskedUint32x4:
+		return rewriteValueAMD64_OpRotateAllRightMaskedUint32x4(v)
+	case OpRotateAllRightMaskedUint32x8:
+		return rewriteValueAMD64_OpRotateAllRightMaskedUint32x8(v)
+	case OpRotateAllRightMaskedUint64x2:
+		return rewriteValueAMD64_OpRotateAllRightMaskedUint64x2(v)
+	case OpRotateAllRightMaskedUint64x4:
+		return rewriteValueAMD64_OpRotateAllRightMaskedUint64x4(v)
+	case OpRotateAllRightMaskedUint64x8:
+		return rewriteValueAMD64_OpRotateAllRightMaskedUint64x8(v)
+	case OpRotateAllRightUint32x16:
+		v.Op = OpAMD64VPRORD512
+		return true
+	case OpRotateAllRightUint32x4:
+		v.Op = OpAMD64VPRORD128
+		return true
+	case OpRotateAllRightUint32x8:
+		v.Op = OpAMD64VPRORD256
+		return true
+	case OpRotateAllRightUint64x2:
+		v.Op = OpAMD64VPRORQ128
+		return true
+	case OpRotateAllRightUint64x4:
+		v.Op = OpAMD64VPRORQ256
+		return true
+	case OpRotateAllRightUint64x8:
+		v.Op = OpAMD64VPRORQ512
+		return true
 	case OpRotateLeft16:
 		v.Op = OpAMD64ROLW
 		return true
@@ -1006,14 +3896,166 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpRotateLeft8:
 		v.Op = OpAMD64ROLB
 		return true
+	case OpRotateLeftInt32x16:
+		v.Op = OpAMD64VPROLVD512
+		return true
+	case OpRotateLeftInt32x4:
+		v.Op = OpAMD64VPROLVD128
+		return true
+	case OpRotateLeftInt32x8:
+		v.Op = OpAMD64VPROLVD256
+		return true
+	case OpRotateLeftInt64x2:
+		v.Op = OpAMD64VPROLVQ128
+		return true
+	case OpRotateLeftInt64x4:
+		v.Op = OpAMD64VPROLVQ256
+		return true
+	case OpRotateLeftInt64x8:
+		v.Op = OpAMD64VPROLVQ512
+		return true
+	case OpRotateLeftMaskedInt32x16:
+		return rewriteValueAMD64_OpRotateLeftMaskedInt32x16(v)
+	case OpRotateLeftMaskedInt32x4:
+		return rewriteValueAMD64_OpRotateLeftMaskedInt32x4(v)
+	case OpRotateLeftMaskedInt32x8:
+		return rewriteValueAMD64_OpRotateLeftMaskedInt32x8(v)
+	case OpRotateLeftMaskedInt64x2:
+		return rewriteValueAMD64_OpRotateLeftMaskedInt64x2(v)
+	case OpRotateLeftMaskedInt64x4:
+		return rewriteValueAMD64_OpRotateLeftMaskedInt64x4(v)
+	case OpRotateLeftMaskedInt64x8:
+		return rewriteValueAMD64_OpRotateLeftMaskedInt64x8(v)
+	case OpRotateLeftMaskedUint32x16:
+		return rewriteValueAMD64_OpRotateLeftMaskedUint32x16(v)
+	case OpRotateLeftMaskedUint32x4:
+		return rewriteValueAMD64_OpRotateLeftMaskedUint32x4(v)
+	case OpRotateLeftMaskedUint32x8:
+		return rewriteValueAMD64_OpRotateLeftMaskedUint32x8(v)
+	case OpRotateLeftMaskedUint64x2:
+		return rewriteValueAMD64_OpRotateLeftMaskedUint64x2(v)
+	case OpRotateLeftMaskedUint64x4:
+		return rewriteValueAMD64_OpRotateLeftMaskedUint64x4(v)
+	case OpRotateLeftMaskedUint64x8:
+		return rewriteValueAMD64_OpRotateLeftMaskedUint64x8(v)
+	case OpRotateLeftUint32x16:
+		v.Op = OpAMD64VPROLVD512
+		return true
+	case OpRotateLeftUint32x4:
+		v.Op = OpAMD64VPROLVD128
+		return true
+	case OpRotateLeftUint32x8:
+		v.Op = OpAMD64VPROLVD256
+		return true
+	case OpRotateLeftUint64x2:
+		v.Op = OpAMD64VPROLVQ128
+		return true
+	case OpRotateLeftUint64x4:
+		v.Op = OpAMD64VPROLVQ256
+		return true
+	case OpRotateLeftUint64x8:
+		v.Op = OpAMD64VPROLVQ512
+		return true
+	case OpRotateRightInt32x16:
+		v.Op = OpAMD64VPRORVD512
+		return true
+	case OpRotateRightInt32x4:
+		v.Op = OpAMD64VPRORVD128
+		return true
+	case OpRotateRightInt32x8:
+		v.Op = OpAMD64VPRORVD256
+		return true
+	case OpRotateRightInt64x2:
+		v.Op = OpAMD64VPRORVQ128
+		return true
+	case OpRotateRightInt64x4:
+		v.Op = OpAMD64VPRORVQ256
+		return true
+	case OpRotateRightInt64x8:
+		v.Op = OpAMD64VPRORVQ512
+		return true
+	case OpRotateRightMaskedInt32x16:
+		return rewriteValueAMD64_OpRotateRightMaskedInt32x16(v)
+	case OpRotateRightMaskedInt32x4:
+		return rewriteValueAMD64_OpRotateRightMaskedInt32x4(v)
+	case OpRotateRightMaskedInt32x8:
+		return rewriteValueAMD64_OpRotateRightMaskedInt32x8(v)
+	case OpRotateRightMaskedInt64x2:
+		return rewriteValueAMD64_OpRotateRightMaskedInt64x2(v)
+	case OpRotateRightMaskedInt64x4:
+		return rewriteValueAMD64_OpRotateRightMaskedInt64x4(v)
+	case OpRotateRightMaskedInt64x8:
+		return rewriteValueAMD64_OpRotateRightMaskedInt64x8(v)
+	case OpRotateRightMaskedUint32x16:
+		return rewriteValueAMD64_OpRotateRightMaskedUint32x16(v)
+	case OpRotateRightMaskedUint32x4:
+		return rewriteValueAMD64_OpRotateRightMaskedUint32x4(v)
+	case OpRotateRightMaskedUint32x8:
+		return rewriteValueAMD64_OpRotateRightMaskedUint32x8(v)
+	case OpRotateRightMaskedUint64x2:
+		return rewriteValueAMD64_OpRotateRightMaskedUint64x2(v)
+	case OpRotateRightMaskedUint64x4:
+		return rewriteValueAMD64_OpRotateRightMaskedUint64x4(v)
+	case OpRotateRightMaskedUint64x8:
+		return rewriteValueAMD64_OpRotateRightMaskedUint64x8(v)
+	case OpRotateRightUint32x16:
+		v.Op = OpAMD64VPRORVD512
+		return true
+	case OpRotateRightUint32x4:
+		v.Op = OpAMD64VPRORVD128
+		return true
+	case OpRotateRightUint32x8:
+		v.Op = OpAMD64VPRORVD256
+		return true
+	case OpRotateRightUint64x2:
+		v.Op = OpAMD64VPRORVQ128
+		return true
+	case OpRotateRightUint64x4:
+		v.Op = OpAMD64VPRORVQ256
+		return true
+	case OpRotateRightUint64x8:
+		v.Op = OpAMD64VPRORVQ512
+		return true
 	case OpRound32F:
 		v.Op = OpAMD64LoweredRound32F
 		return true
 	case OpRound64F:
 		v.Op = OpAMD64LoweredRound64F
 		return true
+	case OpRoundFloat32x4:
+		return rewriteValueAMD64_OpRoundFloat32x4(v)
+	case OpRoundFloat32x8:
+		return rewriteValueAMD64_OpRoundFloat32x8(v)
+	case OpRoundFloat64x2:
+		return rewriteValueAMD64_OpRoundFloat64x2(v)
+	case OpRoundFloat64x4:
+		return rewriteValueAMD64_OpRoundFloat64x4(v)
 	case OpRoundToEven:
 		return rewriteValueAMD64_OpRoundToEven(v)
+	case OpRoundWithPrecisionFloat32x16:
+		return rewriteValueAMD64_OpRoundWithPrecisionFloat32x16(v)
+	case OpRoundWithPrecisionFloat32x4:
+		return rewriteValueAMD64_OpRoundWithPrecisionFloat32x4(v)
+	case OpRoundWithPrecisionFloat32x8:
+		return rewriteValueAMD64_OpRoundWithPrecisionFloat32x8(v)
+	case OpRoundWithPrecisionFloat64x2:
+		return rewriteValueAMD64_OpRoundWithPrecisionFloat64x2(v)
+	case OpRoundWithPrecisionFloat64x4:
+		return rewriteValueAMD64_OpRoundWithPrecisionFloat64x4(v)
+	case OpRoundWithPrecisionFloat64x8:
+		return rewriteValueAMD64_OpRoundWithPrecisionFloat64x8(v)
+	case OpRoundWithPrecisionMaskedFloat32x16:
+		return rewriteValueAMD64_OpRoundWithPrecisionMaskedFloat32x16(v)
+	case OpRoundWithPrecisionMaskedFloat32x4:
+		return rewriteValueAMD64_OpRoundWithPrecisionMaskedFloat32x4(v)
+	case OpRoundWithPrecisionMaskedFloat32x8:
+		return rewriteValueAMD64_OpRoundWithPrecisionMaskedFloat32x8(v)
+	case OpRoundWithPrecisionMaskedFloat64x2:
+		return rewriteValueAMD64_OpRoundWithPrecisionMaskedFloat64x2(v)
+	case OpRoundWithPrecisionMaskedFloat64x4:
+		return rewriteValueAMD64_OpRoundWithPrecisionMaskedFloat64x4(v)
+	case OpRoundWithPrecisionMaskedFloat64x8:
+		return rewriteValueAMD64_OpRoundWithPrecisionMaskedFloat64x8(v)
 	case OpRsh16Ux16:
 		return rewriteValueAMD64_OpRsh16Ux16(v)
 	case OpRsh16Ux32:
@@ -1078,12 +4120,963 @@ func rewriteValueAMD64(v *Value) bool {
 		return rewriteValueAMD64_OpRsh8x64(v)
 	case OpRsh8x8:
 		return rewriteValueAMD64_OpRsh8x8(v)
+	case OpSaturatedAddInt16x16:
+		v.Op = OpAMD64VPADDSW256
+		return true
+	case OpSaturatedAddInt16x32:
+		v.Op = OpAMD64VPADDSW512
+		return true
+	case OpSaturatedAddInt16x8:
+		v.Op = OpAMD64VPADDSW128
+		return true
+	case OpSaturatedAddInt8x16:
+		v.Op = OpAMD64VPADDSB128
+		return true
+	case OpSaturatedAddInt8x32:
+		v.Op = OpAMD64VPADDSB256
+		return true
+	case OpSaturatedAddInt8x64:
+		v.Op = OpAMD64VPADDSB512
+		return true
+	case OpSaturatedAddMaskedInt16x16:
+		return rewriteValueAMD64_OpSaturatedAddMaskedInt16x16(v)
+	case OpSaturatedAddMaskedInt16x32:
+		return rewriteValueAMD64_OpSaturatedAddMaskedInt16x32(v)
+	case OpSaturatedAddMaskedInt16x8:
+		return rewriteValueAMD64_OpSaturatedAddMaskedInt16x8(v)
+	case OpSaturatedAddMaskedInt8x16:
+		return rewriteValueAMD64_OpSaturatedAddMaskedInt8x16(v)
+	case OpSaturatedAddMaskedInt8x32:
+		return rewriteValueAMD64_OpSaturatedAddMaskedInt8x32(v)
+	case OpSaturatedAddMaskedInt8x64:
+		return rewriteValueAMD64_OpSaturatedAddMaskedInt8x64(v)
+	case OpSaturatedAddMaskedUint16x16:
+		return rewriteValueAMD64_OpSaturatedAddMaskedUint16x16(v)
+	case OpSaturatedAddMaskedUint16x32:
+		return rewriteValueAMD64_OpSaturatedAddMaskedUint16x32(v)
+	case OpSaturatedAddMaskedUint16x8:
+		return rewriteValueAMD64_OpSaturatedAddMaskedUint16x8(v)
+	case OpSaturatedAddMaskedUint8x16:
+		return rewriteValueAMD64_OpSaturatedAddMaskedUint8x16(v)
+	case OpSaturatedAddMaskedUint8x32:
+		return rewriteValueAMD64_OpSaturatedAddMaskedUint8x32(v)
+	case OpSaturatedAddMaskedUint8x64:
+		return rewriteValueAMD64_OpSaturatedAddMaskedUint8x64(v)
+	case OpSaturatedAddUint16x16:
+		v.Op = OpAMD64VPADDSW256
+		return true
+	case OpSaturatedAddUint16x32:
+		v.Op = OpAMD64VPADDSW512
+		return true
+	case OpSaturatedAddUint16x8:
+		v.Op = OpAMD64VPADDSW128
+		return true
+	case OpSaturatedAddUint8x16:
+		v.Op = OpAMD64VPADDSB128
+		return true
+	case OpSaturatedAddUint8x32:
+		v.Op = OpAMD64VPADDSB256
+		return true
+	case OpSaturatedAddUint8x64:
+		v.Op = OpAMD64VPADDSB512
+		return true
+	case OpSaturatedPairDotProdAccumulateInt32x16:
+		v.Op = OpAMD64VPDPWSSDS512
+		return true
+	case OpSaturatedPairDotProdAccumulateInt32x4:
+		v.Op = OpAMD64VPDPWSSDS128
+		return true
+	case OpSaturatedPairDotProdAccumulateInt32x8:
+		v.Op = OpAMD64VPDPWSSDS256
+		return true
+	case OpSaturatedPairDotProdAccumulateMaskedInt32x16:
+		return rewriteValueAMD64_OpSaturatedPairDotProdAccumulateMaskedInt32x16(v)
+	case OpSaturatedPairDotProdAccumulateMaskedInt32x4:
+		return rewriteValueAMD64_OpSaturatedPairDotProdAccumulateMaskedInt32x4(v)
+	case OpSaturatedPairDotProdAccumulateMaskedInt32x8:
+		return rewriteValueAMD64_OpSaturatedPairDotProdAccumulateMaskedInt32x8(v)
+	case OpSaturatedPairwiseAddInt16x16:
+		v.Op = OpAMD64VPHADDSW256
+		return true
+	case OpSaturatedPairwiseAddInt16x8:
+		v.Op = OpAMD64VPHADDSW128
+		return true
+	case OpSaturatedPairwiseSubInt16x16:
+		v.Op = OpAMD64VPHSUBSW256
+		return true
+	case OpSaturatedPairwiseSubInt16x8:
+		v.Op = OpAMD64VPHSUBSW128
+		return true
+	case OpSaturatedSubInt16x16:
+		v.Op = OpAMD64VPSUBSW256
+		return true
+	case OpSaturatedSubInt16x32:
+		v.Op = OpAMD64VPSUBSW512
+		return true
+	case OpSaturatedSubInt16x8:
+		v.Op = OpAMD64VPSUBSW128
+		return true
+	case OpSaturatedSubInt8x16:
+		v.Op = OpAMD64VPSUBSB128
+		return true
+	case OpSaturatedSubInt8x32:
+		v.Op = OpAMD64VPSUBSB256
+		return true
+	case OpSaturatedSubInt8x64:
+		v.Op = OpAMD64VPSUBSB512
+		return true
+	case OpSaturatedSubMaskedInt16x16:
+		return rewriteValueAMD64_OpSaturatedSubMaskedInt16x16(v)
+	case OpSaturatedSubMaskedInt16x32:
+		return rewriteValueAMD64_OpSaturatedSubMaskedInt16x32(v)
+	case OpSaturatedSubMaskedInt16x8:
+		return rewriteValueAMD64_OpSaturatedSubMaskedInt16x8(v)
+	case OpSaturatedSubMaskedInt8x16:
+		return rewriteValueAMD64_OpSaturatedSubMaskedInt8x16(v)
+	case OpSaturatedSubMaskedInt8x32:
+		return rewriteValueAMD64_OpSaturatedSubMaskedInt8x32(v)
+	case OpSaturatedSubMaskedInt8x64:
+		return rewriteValueAMD64_OpSaturatedSubMaskedInt8x64(v)
+	case OpSaturatedSubMaskedUint16x16:
+		return rewriteValueAMD64_OpSaturatedSubMaskedUint16x16(v)
+	case OpSaturatedSubMaskedUint16x32:
+		return rewriteValueAMD64_OpSaturatedSubMaskedUint16x32(v)
+	case OpSaturatedSubMaskedUint16x8:
+		return rewriteValueAMD64_OpSaturatedSubMaskedUint16x8(v)
+	case OpSaturatedSubMaskedUint8x16:
+		return rewriteValueAMD64_OpSaturatedSubMaskedUint8x16(v)
+	case OpSaturatedSubMaskedUint8x32:
+		return rewriteValueAMD64_OpSaturatedSubMaskedUint8x32(v)
+	case OpSaturatedSubMaskedUint8x64:
+		return rewriteValueAMD64_OpSaturatedSubMaskedUint8x64(v)
+	case OpSaturatedSubUint16x16:
+		v.Op = OpAMD64VPSUBSW256
+		return true
+	case OpSaturatedSubUint16x32:
+		v.Op = OpAMD64VPSUBSW512
+		return true
+	case OpSaturatedSubUint16x8:
+		v.Op = OpAMD64VPSUBSW128
+		return true
+	case OpSaturatedSubUint8x16:
+		v.Op = OpAMD64VPSUBSB128
+		return true
+	case OpSaturatedSubUint8x32:
+		v.Op = OpAMD64VPSUBSB256
+		return true
+	case OpSaturatedSubUint8x64:
+		v.Op = OpAMD64VPSUBSB512
+		return true
+	case OpSaturatedUnsignedSignedPairDotProdMaskedUint8x16:
+		return rewriteValueAMD64_OpSaturatedUnsignedSignedPairDotProdMaskedUint8x16(v)
+	case OpSaturatedUnsignedSignedPairDotProdMaskedUint8x32:
+		return rewriteValueAMD64_OpSaturatedUnsignedSignedPairDotProdMaskedUint8x32(v)
+	case OpSaturatedUnsignedSignedPairDotProdMaskedUint8x64:
+		return rewriteValueAMD64_OpSaturatedUnsignedSignedPairDotProdMaskedUint8x64(v)
+	case OpSaturatedUnsignedSignedPairDotProdUint8x16:
+		v.Op = OpAMD64VPMADDUBSW128
+		return true
+	case OpSaturatedUnsignedSignedPairDotProdUint8x32:
+		v.Op = OpAMD64VPMADDUBSW256
+		return true
+	case OpSaturatedUnsignedSignedPairDotProdUint8x64:
+		v.Op = OpAMD64VPMADDUBSW512
+		return true
+	case OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16:
+		v.Op = OpAMD64VPDPBUSDS512
+		return true
+	case OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4:
+		v.Op = OpAMD64VPDPBUSDS128
+		return true
+	case OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8:
+		v.Op = OpAMD64VPDPBUSDS256
+		return true
+	case OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x16:
+		return rewriteValueAMD64_OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x16(v)
+	case OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4:
+		return rewriteValueAMD64_OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4(v)
+	case OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x8:
+		return rewriteValueAMD64_OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x8(v)
 	case OpSelect0:
 		return rewriteValueAMD64_OpSelect0(v)
 	case OpSelect1:
 		return rewriteValueAMD64_OpSelect1(v)
 	case OpSelectN:
 		return rewriteValueAMD64_OpSelectN(v)
+	case OpSet128Float32x8:
+		v.Op = OpAMD64VINSERTF128256
+		return true
+	case OpSet128Float64x4:
+		v.Op = OpAMD64VINSERTF128256
+		return true
+	case OpSet128Int16x16:
+		v.Op = OpAMD64VINSERTI128256
+		return true
+	case OpSet128Int32x8:
+		v.Op = OpAMD64VINSERTI128256
+		return true
+	case OpSet128Int64x4:
+		v.Op = OpAMD64VINSERTI128256
+		return true
+	case OpSet128Int8x32:
+		v.Op = OpAMD64VINSERTI128256
+		return true
+	case OpSet128Uint16x16:
+		v.Op = OpAMD64VINSERTI128256
+		return true
+	case OpSet128Uint32x8:
+		v.Op = OpAMD64VINSERTI128256
+		return true
+	case OpSet128Uint64x4:
+		v.Op = OpAMD64VINSERTI128256
+		return true
+	case OpSet128Uint8x32:
+		v.Op = OpAMD64VINSERTI128256
+		return true
+	case OpSetElemInt16x8:
+		v.Op = OpAMD64VPINSRW128
+		return true
+	case OpSetElemInt32x4:
+		v.Op = OpAMD64VPINSRD128
+		return true
+	case OpSetElemInt64x2:
+		v.Op = OpAMD64VPINSRQ128
+		return true
+	case OpSetElemInt8x16:
+		v.Op = OpAMD64VPINSRB128
+		return true
+	case OpSetElemUint16x8:
+		v.Op = OpAMD64VPINSRW128
+		return true
+	case OpSetElemUint32x4:
+		v.Op = OpAMD64VPINSRD128
+		return true
+	case OpSetElemUint64x2:
+		v.Op = OpAMD64VPINSRQ128
+		return true
+	case OpSetElemUint8x16:
+		v.Op = OpAMD64VPINSRB128
+		return true
+	case OpShiftAllLeftAndFillUpperFromInt16x16:
+		v.Op = OpAMD64VPSHLDW256
+		return true
+	case OpShiftAllLeftAndFillUpperFromInt16x32:
+		v.Op = OpAMD64VPSHLDW512
+		return true
+	case OpShiftAllLeftAndFillUpperFromInt16x8:
+		v.Op = OpAMD64VPSHLDW128
+		return true
+	case OpShiftAllLeftAndFillUpperFromInt32x16:
+		v.Op = OpAMD64VPSHLDD512
+		return true
+	case OpShiftAllLeftAndFillUpperFromInt32x4:
+		v.Op = OpAMD64VPSHLDD128
+		return true
+	case OpShiftAllLeftAndFillUpperFromInt32x8:
+		v.Op = OpAMD64VPSHLDD256
+		return true
+	case OpShiftAllLeftAndFillUpperFromInt64x2:
+		v.Op = OpAMD64VPSHLDQ128
+		return true
+	case OpShiftAllLeftAndFillUpperFromInt64x4:
+		v.Op = OpAMD64VPSHLDQ256
+		return true
+	case OpShiftAllLeftAndFillUpperFromInt64x8:
+		v.Op = OpAMD64VPSHLDQ512
+		return true
+	case OpShiftAllLeftAndFillUpperFromMaskedInt16x16:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt16x16(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedInt16x32:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt16x32(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedInt16x8:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt16x8(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedInt32x16:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt32x16(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedInt32x4:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt32x4(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedInt32x8:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt32x8(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedInt64x2:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt64x2(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedInt64x4:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt64x4(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedInt64x8:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt64x8(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedUint16x16:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint16x16(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedUint16x32:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint16x32(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedUint16x8:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint16x8(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedUint32x16:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint32x16(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedUint32x4:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint32x4(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedUint32x8:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint32x8(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedUint64x2:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint64x2(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedUint64x4:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint64x4(v)
+	case OpShiftAllLeftAndFillUpperFromMaskedUint64x8:
+		return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint64x8(v)
+	case OpShiftAllLeftAndFillUpperFromUint16x16:
+		v.Op = OpAMD64VPSHLDW256
+		return true
+	case OpShiftAllLeftAndFillUpperFromUint16x32:
+		v.Op = OpAMD64VPSHLDW512
+		return true
+	case OpShiftAllLeftAndFillUpperFromUint16x8:
+		v.Op = OpAMD64VPSHLDW128
+		return true
+	case OpShiftAllLeftAndFillUpperFromUint32x16:
+		v.Op = OpAMD64VPSHLDD512
+		return true
+	case OpShiftAllLeftAndFillUpperFromUint32x4:
+		v.Op = OpAMD64VPSHLDD128
+		return true
+	case OpShiftAllLeftAndFillUpperFromUint32x8:
+		v.Op = OpAMD64VPSHLDD256
+		return true
+	case OpShiftAllLeftAndFillUpperFromUint64x2:
+		v.Op = OpAMD64VPSHLDQ128
+		return true
+	case OpShiftAllLeftAndFillUpperFromUint64x4:
+		v.Op = OpAMD64VPSHLDQ256
+		return true
+	case OpShiftAllLeftAndFillUpperFromUint64x8:
+		v.Op = OpAMD64VPSHLDQ512
+		return true
+	case OpShiftAllLeftInt16x16:
+		v.Op = OpAMD64VPSLLW256
+		return true
+	case OpShiftAllLeftInt16x32:
+		v.Op = OpAMD64VPSLLW512
+		return true
+	case OpShiftAllLeftInt16x8:
+		v.Op = OpAMD64VPSLLW128
+		return true
+	case OpShiftAllLeftInt32x16:
+		v.Op = OpAMD64VPSLLD512
+		return true
+	case OpShiftAllLeftInt32x4:
+		v.Op = OpAMD64VPSLLD128
+		return true
+	case OpShiftAllLeftInt32x8:
+		v.Op = OpAMD64VPSLLD256
+		return true
+	case OpShiftAllLeftInt64x2:
+		v.Op = OpAMD64VPSLLQ128
+		return true
+	case OpShiftAllLeftInt64x4:
+		v.Op = OpAMD64VPSLLQ256
+		return true
+	case OpShiftAllLeftInt64x8:
+		v.Op = OpAMD64VPSLLQ512
+		return true
+	case OpShiftAllLeftMaskedInt16x16:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedInt16x16(v)
+	case OpShiftAllLeftMaskedInt16x32:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedInt16x32(v)
+	case OpShiftAllLeftMaskedInt16x8:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedInt16x8(v)
+	case OpShiftAllLeftMaskedInt32x16:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedInt32x16(v)
+	case OpShiftAllLeftMaskedInt32x4:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedInt32x4(v)
+	case OpShiftAllLeftMaskedInt32x8:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedInt32x8(v)
+	case OpShiftAllLeftMaskedInt64x2:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedInt64x2(v)
+	case OpShiftAllLeftMaskedInt64x4:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedInt64x4(v)
+	case OpShiftAllLeftMaskedInt64x8:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedInt64x8(v)
+	case OpShiftAllLeftMaskedUint16x16:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedUint16x16(v)
+	case OpShiftAllLeftMaskedUint16x32:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedUint16x32(v)
+	case OpShiftAllLeftMaskedUint16x8:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedUint16x8(v)
+	case OpShiftAllLeftMaskedUint32x16:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedUint32x16(v)
+	case OpShiftAllLeftMaskedUint32x4:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedUint32x4(v)
+	case OpShiftAllLeftMaskedUint32x8:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedUint32x8(v)
+	case OpShiftAllLeftMaskedUint64x2:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedUint64x2(v)
+	case OpShiftAllLeftMaskedUint64x4:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedUint64x4(v)
+	case OpShiftAllLeftMaskedUint64x8:
+		return rewriteValueAMD64_OpShiftAllLeftMaskedUint64x8(v)
+	case OpShiftAllLeftUint16x16:
+		v.Op = OpAMD64VPSLLW256
+		return true
+	case OpShiftAllLeftUint16x32:
+		v.Op = OpAMD64VPSLLW512
+		return true
+	case OpShiftAllLeftUint16x8:
+		v.Op = OpAMD64VPSLLW128
+		return true
+	case OpShiftAllLeftUint32x16:
+		v.Op = OpAMD64VPSLLD512
+		return true
+	case OpShiftAllLeftUint32x4:
+		v.Op = OpAMD64VPSLLD128
+		return true
+	case OpShiftAllLeftUint32x8:
+		v.Op = OpAMD64VPSLLD256
+		return true
+	case OpShiftAllLeftUint64x2:
+		v.Op = OpAMD64VPSLLQ128
+		return true
+	case OpShiftAllLeftUint64x4:
+		v.Op = OpAMD64VPSLLQ256
+		return true
+	case OpShiftAllLeftUint64x8:
+		v.Op = OpAMD64VPSLLQ512
+		return true
+	case OpShiftAllRightAndFillUpperFromInt16x16:
+		v.Op = OpAMD64VPSHRDW256
+		return true
+	case OpShiftAllRightAndFillUpperFromInt16x32:
+		v.Op = OpAMD64VPSHRDW512
+		return true
+	case OpShiftAllRightAndFillUpperFromInt16x8:
+		v.Op = OpAMD64VPSHRDW128
+		return true
+	case OpShiftAllRightAndFillUpperFromInt32x16:
+		v.Op = OpAMD64VPSHRDD512
+		return true
+	case OpShiftAllRightAndFillUpperFromInt32x4:
+		v.Op = OpAMD64VPSHRDD128
+		return true
+	case OpShiftAllRightAndFillUpperFromInt32x8:
+		v.Op = OpAMD64VPSHRDD256
+		return true
+	case OpShiftAllRightAndFillUpperFromInt64x2:
+		v.Op = OpAMD64VPSHRDQ128
+		return true
+	case OpShiftAllRightAndFillUpperFromInt64x4:
+		v.Op = OpAMD64VPSHRDQ256
+		return true
+	case OpShiftAllRightAndFillUpperFromInt64x8:
+		v.Op = OpAMD64VPSHRDQ512
+		return true
+	case OpShiftAllRightAndFillUpperFromMaskedInt16x16:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt16x16(v)
+	case OpShiftAllRightAndFillUpperFromMaskedInt16x32:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt16x32(v)
+	case OpShiftAllRightAndFillUpperFromMaskedInt16x8:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt16x8(v)
+	case OpShiftAllRightAndFillUpperFromMaskedInt32x16:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt32x16(v)
+	case OpShiftAllRightAndFillUpperFromMaskedInt32x4:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt32x4(v)
+	case OpShiftAllRightAndFillUpperFromMaskedInt32x8:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt32x8(v)
+	case OpShiftAllRightAndFillUpperFromMaskedInt64x2:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt64x2(v)
+	case OpShiftAllRightAndFillUpperFromMaskedInt64x4:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt64x4(v)
+	case OpShiftAllRightAndFillUpperFromMaskedInt64x8:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt64x8(v)
+	case OpShiftAllRightAndFillUpperFromMaskedUint16x16:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint16x16(v)
+	case OpShiftAllRightAndFillUpperFromMaskedUint16x32:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint16x32(v)
+	case OpShiftAllRightAndFillUpperFromMaskedUint16x8:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint16x8(v)
+	case OpShiftAllRightAndFillUpperFromMaskedUint32x16:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint32x16(v)
+	case OpShiftAllRightAndFillUpperFromMaskedUint32x4:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint32x4(v)
+	case OpShiftAllRightAndFillUpperFromMaskedUint32x8:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint32x8(v)
+	case OpShiftAllRightAndFillUpperFromMaskedUint64x2:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint64x2(v)
+	case OpShiftAllRightAndFillUpperFromMaskedUint64x4:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint64x4(v)
+	case OpShiftAllRightAndFillUpperFromMaskedUint64x8:
+		return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint64x8(v)
+	case OpShiftAllRightAndFillUpperFromUint16x16:
+		v.Op = OpAMD64VPSHRDW256
+		return true
+	case OpShiftAllRightAndFillUpperFromUint16x32:
+		v.Op = OpAMD64VPSHRDW512
+		return true
+	case OpShiftAllRightAndFillUpperFromUint16x8:
+		v.Op = OpAMD64VPSHRDW128
+		return true
+	case OpShiftAllRightAndFillUpperFromUint32x16:
+		v.Op = OpAMD64VPSHRDD512
+		return true
+	case OpShiftAllRightAndFillUpperFromUint32x4:
+		v.Op = OpAMD64VPSHRDD128
+		return true
+	case OpShiftAllRightAndFillUpperFromUint32x8:
+		v.Op = OpAMD64VPSHRDD256
+		return true
+	case OpShiftAllRightAndFillUpperFromUint64x2:
+		v.Op = OpAMD64VPSHRDQ128
+		return true
+	case OpShiftAllRightAndFillUpperFromUint64x4:
+		v.Op = OpAMD64VPSHRDQ256
+		return true
+	case OpShiftAllRightAndFillUpperFromUint64x8:
+		v.Op = OpAMD64VPSHRDQ512
+		return true
+	case OpShiftAllRightInt16x16:
+		v.Op = OpAMD64VPSRAW256
+		return true
+	case OpShiftAllRightInt16x32:
+		v.Op = OpAMD64VPSRAW512
+		return true
+	case OpShiftAllRightInt16x8:
+		v.Op = OpAMD64VPSRAW128
+		return true
+	case OpShiftAllRightInt32x16:
+		v.Op = OpAMD64VPSRAD512
+		return true
+	case OpShiftAllRightInt32x4:
+		v.Op = OpAMD64VPSRAD128
+		return true
+	case OpShiftAllRightInt32x8:
+		v.Op = OpAMD64VPSRAD256
+		return true
+	case OpShiftAllRightInt64x2:
+		v.Op = OpAMD64VPSRAQ128
+		return true
+	case OpShiftAllRightInt64x4:
+		v.Op = OpAMD64VPSRAQ256
+		return true
+	case OpShiftAllRightInt64x8:
+		v.Op = OpAMD64VPSRAQ512
+		return true
+	case OpShiftAllRightMaskedInt16x16:
+		return rewriteValueAMD64_OpShiftAllRightMaskedInt16x16(v)
+	case OpShiftAllRightMaskedInt16x32:
+		return rewriteValueAMD64_OpShiftAllRightMaskedInt16x32(v)
+	case OpShiftAllRightMaskedInt16x8:
+		return rewriteValueAMD64_OpShiftAllRightMaskedInt16x8(v)
+	case OpShiftAllRightMaskedInt32x16:
+		return rewriteValueAMD64_OpShiftAllRightMaskedInt32x16(v)
+	case OpShiftAllRightMaskedInt32x4:
+		return rewriteValueAMD64_OpShiftAllRightMaskedInt32x4(v)
+	case OpShiftAllRightMaskedInt32x8:
+		return rewriteValueAMD64_OpShiftAllRightMaskedInt32x8(v)
+	case OpShiftAllRightMaskedInt64x2:
+		return rewriteValueAMD64_OpShiftAllRightMaskedInt64x2(v)
+	case OpShiftAllRightMaskedInt64x4:
+		return rewriteValueAMD64_OpShiftAllRightMaskedInt64x4(v)
+	case OpShiftAllRightMaskedInt64x8:
+		return rewriteValueAMD64_OpShiftAllRightMaskedInt64x8(v)
+	case OpShiftAllRightMaskedUint16x16:
+		return rewriteValueAMD64_OpShiftAllRightMaskedUint16x16(v)
+	case OpShiftAllRightMaskedUint16x32:
+		return rewriteValueAMD64_OpShiftAllRightMaskedUint16x32(v)
+	case OpShiftAllRightMaskedUint16x8:
+		return rewriteValueAMD64_OpShiftAllRightMaskedUint16x8(v)
+	case OpShiftAllRightMaskedUint32x16:
+		return rewriteValueAMD64_OpShiftAllRightMaskedUint32x16(v)
+	case OpShiftAllRightMaskedUint32x4:
+		return rewriteValueAMD64_OpShiftAllRightMaskedUint32x4(v)
+	case OpShiftAllRightMaskedUint32x8:
+		return rewriteValueAMD64_OpShiftAllRightMaskedUint32x8(v)
+	case OpShiftAllRightMaskedUint64x2:
+		return rewriteValueAMD64_OpShiftAllRightMaskedUint64x2(v)
+	case OpShiftAllRightMaskedUint64x4:
+		return rewriteValueAMD64_OpShiftAllRightMaskedUint64x4(v)
+	case OpShiftAllRightMaskedUint64x8:
+		return rewriteValueAMD64_OpShiftAllRightMaskedUint64x8(v)
+	case OpShiftAllRightUint16x16:
+		v.Op = OpAMD64VPSRLW256
+		return true
+	case OpShiftAllRightUint16x32:
+		v.Op = OpAMD64VPSRLW512
+		return true
+	case OpShiftAllRightUint16x8:
+		v.Op = OpAMD64VPSRLW128
+		return true
+	case OpShiftAllRightUint32x16:
+		v.Op = OpAMD64VPSRLD512
+		return true
+	case OpShiftAllRightUint32x4:
+		v.Op = OpAMD64VPSRLD128
+		return true
+	case OpShiftAllRightUint32x8:
+		v.Op = OpAMD64VPSRLD256
+		return true
+	case OpShiftAllRightUint64x2:
+		v.Op = OpAMD64VPSRLQ128
+		return true
+	case OpShiftAllRightUint64x4:
+		v.Op = OpAMD64VPSRLQ256
+		return true
+	case OpShiftAllRightUint64x8:
+		v.Op = OpAMD64VPSRLQ512
+		return true
+	case OpShiftLeftAndFillUpperFromInt16x16:
+		v.Op = OpAMD64VPSHLDVW256
+		return true
+	case OpShiftLeftAndFillUpperFromInt16x32:
+		v.Op = OpAMD64VPSHLDVW512
+		return true
+	case OpShiftLeftAndFillUpperFromInt16x8:
+		v.Op = OpAMD64VPSHLDVW128
+		return true
+	case OpShiftLeftAndFillUpperFromInt32x16:
+		v.Op = OpAMD64VPSHLDVD512
+		return true
+	case OpShiftLeftAndFillUpperFromInt32x4:
+		v.Op = OpAMD64VPSHLDVD128
+		return true
+	case OpShiftLeftAndFillUpperFromInt32x8:
+		v.Op = OpAMD64VPSHLDVD256
+		return true
+	case OpShiftLeftAndFillUpperFromInt64x2:
+		v.Op = OpAMD64VPSHLDVQ128
+		return true
+	case OpShiftLeftAndFillUpperFromInt64x4:
+		v.Op = OpAMD64VPSHLDVQ256
+		return true
+	case OpShiftLeftAndFillUpperFromInt64x8:
+		v.Op = OpAMD64VPSHLDVQ512
+		return true
+	case OpShiftLeftAndFillUpperFromMaskedInt16x16:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt16x16(v)
+	case OpShiftLeftAndFillUpperFromMaskedInt16x32:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt16x32(v)
+	case OpShiftLeftAndFillUpperFromMaskedInt16x8:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt16x8(v)
+	case OpShiftLeftAndFillUpperFromMaskedInt32x16:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt32x16(v)
+	case OpShiftLeftAndFillUpperFromMaskedInt32x4:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt32x4(v)
+	case OpShiftLeftAndFillUpperFromMaskedInt32x8:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt32x8(v)
+	case OpShiftLeftAndFillUpperFromMaskedInt64x2:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt64x2(v)
+	case OpShiftLeftAndFillUpperFromMaskedInt64x4:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt64x4(v)
+	case OpShiftLeftAndFillUpperFromMaskedInt64x8:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt64x8(v)
+	case OpShiftLeftAndFillUpperFromMaskedUint16x16:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint16x16(v)
+	case OpShiftLeftAndFillUpperFromMaskedUint16x32:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint16x32(v)
+	case OpShiftLeftAndFillUpperFromMaskedUint16x8:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint16x8(v)
+	case OpShiftLeftAndFillUpperFromMaskedUint32x16:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint32x16(v)
+	case OpShiftLeftAndFillUpperFromMaskedUint32x4:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint32x4(v)
+	case OpShiftLeftAndFillUpperFromMaskedUint32x8:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint32x8(v)
+	case OpShiftLeftAndFillUpperFromMaskedUint64x2:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint64x2(v)
+	case OpShiftLeftAndFillUpperFromMaskedUint64x4:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint64x4(v)
+	case OpShiftLeftAndFillUpperFromMaskedUint64x8:
+		return rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint64x8(v)
+	case OpShiftLeftAndFillUpperFromUint16x16:
+		v.Op = OpAMD64VPSHLDVW256
+		return true
+	case OpShiftLeftAndFillUpperFromUint16x32:
+		v.Op = OpAMD64VPSHLDVW512
+		return true
+	case OpShiftLeftAndFillUpperFromUint16x8:
+		v.Op = OpAMD64VPSHLDVW128
+		return true
+	case OpShiftLeftAndFillUpperFromUint32x16:
+		v.Op = OpAMD64VPSHLDVD512
+		return true
+	case OpShiftLeftAndFillUpperFromUint32x4:
+		v.Op = OpAMD64VPSHLDVD128
+		return true
+	case OpShiftLeftAndFillUpperFromUint32x8:
+		v.Op = OpAMD64VPSHLDVD256
+		return true
+	case OpShiftLeftAndFillUpperFromUint64x2:
+		v.Op = OpAMD64VPSHLDVQ128
+		return true
+	case OpShiftLeftAndFillUpperFromUint64x4:
+		v.Op = OpAMD64VPSHLDVQ256
+		return true
+	case OpShiftLeftAndFillUpperFromUint64x8:
+		v.Op = OpAMD64VPSHLDVQ512
+		return true
+	case OpShiftLeftInt16x16:
+		v.Op = OpAMD64VPSLLVW256
+		return true
+	case OpShiftLeftInt16x32:
+		v.Op = OpAMD64VPSLLVW512
+		return true
+	case OpShiftLeftInt16x8:
+		v.Op = OpAMD64VPSLLVW128
+		return true
+	case OpShiftLeftInt32x16:
+		v.Op = OpAMD64VPSLLVD512
+		return true
+	case OpShiftLeftInt32x4:
+		v.Op = OpAMD64VPSLLVD128
+		return true
+	case OpShiftLeftInt32x8:
+		v.Op = OpAMD64VPSLLVD256
+		return true
+	case OpShiftLeftInt64x2:
+		v.Op = OpAMD64VPSLLVQ128
+		return true
+	case OpShiftLeftInt64x4:
+		v.Op = OpAMD64VPSLLVQ256
+		return true
+	case OpShiftLeftInt64x8:
+		v.Op = OpAMD64VPSLLVQ512
+		return true
+	case OpShiftLeftMaskedInt16x16:
+		return rewriteValueAMD64_OpShiftLeftMaskedInt16x16(v)
+	case OpShiftLeftMaskedInt16x32:
+		return rewriteValueAMD64_OpShiftLeftMaskedInt16x32(v)
+	case OpShiftLeftMaskedInt16x8:
+		return rewriteValueAMD64_OpShiftLeftMaskedInt16x8(v)
+	case OpShiftLeftMaskedInt32x16:
+		return rewriteValueAMD64_OpShiftLeftMaskedInt32x16(v)
+	case OpShiftLeftMaskedInt32x4:
+		return rewriteValueAMD64_OpShiftLeftMaskedInt32x4(v)
+	case OpShiftLeftMaskedInt32x8:
+		return rewriteValueAMD64_OpShiftLeftMaskedInt32x8(v)
+	case OpShiftLeftMaskedInt64x2:
+		return rewriteValueAMD64_OpShiftLeftMaskedInt64x2(v)
+	case OpShiftLeftMaskedInt64x4:
+		return rewriteValueAMD64_OpShiftLeftMaskedInt64x4(v)
+	case OpShiftLeftMaskedInt64x8:
+		return rewriteValueAMD64_OpShiftLeftMaskedInt64x8(v)
+	case OpShiftLeftMaskedUint16x16:
+		return rewriteValueAMD64_OpShiftLeftMaskedUint16x16(v)
+	case OpShiftLeftMaskedUint16x32:
+		return rewriteValueAMD64_OpShiftLeftMaskedUint16x32(v)
+	case OpShiftLeftMaskedUint16x8:
+		return rewriteValueAMD64_OpShiftLeftMaskedUint16x8(v)
+	case OpShiftLeftMaskedUint32x16:
+		return rewriteValueAMD64_OpShiftLeftMaskedUint32x16(v)
+	case OpShiftLeftMaskedUint32x4:
+		return rewriteValueAMD64_OpShiftLeftMaskedUint32x4(v)
+	case OpShiftLeftMaskedUint32x8:
+		return rewriteValueAMD64_OpShiftLeftMaskedUint32x8(v)
+	case OpShiftLeftMaskedUint64x2:
+		return rewriteValueAMD64_OpShiftLeftMaskedUint64x2(v)
+	case OpShiftLeftMaskedUint64x4:
+		return rewriteValueAMD64_OpShiftLeftMaskedUint64x4(v)
+	case OpShiftLeftMaskedUint64x8:
+		return rewriteValueAMD64_OpShiftLeftMaskedUint64x8(v)
+	case OpShiftLeftUint16x16:
+		v.Op = OpAMD64VPSLLVW256
+		return true
+	case OpShiftLeftUint16x32:
+		v.Op = OpAMD64VPSLLVW512
+		return true
+	case OpShiftLeftUint16x8:
+		v.Op = OpAMD64VPSLLVW128
+		return true
+	case OpShiftLeftUint32x16:
+		v.Op = OpAMD64VPSLLVD512
+		return true
+	case OpShiftLeftUint32x4:
+		v.Op = OpAMD64VPSLLVD128
+		return true
+	case OpShiftLeftUint32x8:
+		v.Op = OpAMD64VPSLLVD256
+		return true
+	case OpShiftLeftUint64x2:
+		v.Op = OpAMD64VPSLLVQ128
+		return true
+	case OpShiftLeftUint64x4:
+		v.Op = OpAMD64VPSLLVQ256
+		return true
+	case OpShiftLeftUint64x8:
+		v.Op = OpAMD64VPSLLVQ512
+		return true
+	case OpShiftRightAndFillUpperFromInt16x16:
+		v.Op = OpAMD64VPSHRDVW256
+		return true
+	case OpShiftRightAndFillUpperFromInt16x32:
+		v.Op = OpAMD64VPSHRDVW512
+		return true
+	case OpShiftRightAndFillUpperFromInt16x8:
+		v.Op = OpAMD64VPSHRDVW128
+		return true
+	case OpShiftRightAndFillUpperFromInt32x16:
+		v.Op = OpAMD64VPSHRDVD512
+		return true
+	case OpShiftRightAndFillUpperFromInt32x4:
+		v.Op = OpAMD64VPSHRDVD128
+		return true
+	case OpShiftRightAndFillUpperFromInt32x8:
+		v.Op = OpAMD64VPSHRDVD256
+		return true
+	case OpShiftRightAndFillUpperFromInt64x2:
+		v.Op = OpAMD64VPSHRDVQ128
+		return true
+	case OpShiftRightAndFillUpperFromInt64x4:
+		v.Op = OpAMD64VPSHRDVQ256
+		return true
+	case OpShiftRightAndFillUpperFromInt64x8:
+		v.Op = OpAMD64VPSHRDVQ512
+		return true
+	case OpShiftRightAndFillUpperFromMaskedInt16x16:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt16x16(v)
+	case OpShiftRightAndFillUpperFromMaskedInt16x32:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt16x32(v)
+	case OpShiftRightAndFillUpperFromMaskedInt16x8:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt16x8(v)
+	case OpShiftRightAndFillUpperFromMaskedInt32x16:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt32x16(v)
+	case OpShiftRightAndFillUpperFromMaskedInt32x4:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt32x4(v)
+	case OpShiftRightAndFillUpperFromMaskedInt32x8:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt32x8(v)
+	case OpShiftRightAndFillUpperFromMaskedInt64x2:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt64x2(v)
+	case OpShiftRightAndFillUpperFromMaskedInt64x4:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt64x4(v)
+	case OpShiftRightAndFillUpperFromMaskedInt64x8:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt64x8(v)
+	case OpShiftRightAndFillUpperFromMaskedUint16x16:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint16x16(v)
+	case OpShiftRightAndFillUpperFromMaskedUint16x32:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint16x32(v)
+	case OpShiftRightAndFillUpperFromMaskedUint16x8:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint16x8(v)
+	case OpShiftRightAndFillUpperFromMaskedUint32x16:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint32x16(v)
+	case OpShiftRightAndFillUpperFromMaskedUint32x4:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint32x4(v)
+	case OpShiftRightAndFillUpperFromMaskedUint32x8:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint32x8(v)
+	case OpShiftRightAndFillUpperFromMaskedUint64x2:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint64x2(v)
+	case OpShiftRightAndFillUpperFromMaskedUint64x4:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint64x4(v)
+	case OpShiftRightAndFillUpperFromMaskedUint64x8:
+		return rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint64x8(v)
+	case OpShiftRightAndFillUpperFromUint16x16:
+		v.Op = OpAMD64VPSHRDVW256
+		return true
+	case OpShiftRightAndFillUpperFromUint16x32:
+		v.Op = OpAMD64VPSHRDVW512
+		return true
+	case OpShiftRightAndFillUpperFromUint16x8:
+		v.Op = OpAMD64VPSHRDVW128
+		return true
+	case OpShiftRightAndFillUpperFromUint32x16:
+		v.Op = OpAMD64VPSHRDVD512
+		return true
+	case OpShiftRightAndFillUpperFromUint32x4:
+		v.Op = OpAMD64VPSHRDVD128
+		return true
+	case OpShiftRightAndFillUpperFromUint32x8:
+		v.Op = OpAMD64VPSHRDVD256
+		return true
+	case OpShiftRightAndFillUpperFromUint64x2:
+		v.Op = OpAMD64VPSHRDVQ128
+		return true
+	case OpShiftRightAndFillUpperFromUint64x4:
+		v.Op = OpAMD64VPSHRDVQ256
+		return true
+	case OpShiftRightAndFillUpperFromUint64x8:
+		v.Op = OpAMD64VPSHRDVQ512
+		return true
+	case OpShiftRightInt16x16:
+		v.Op = OpAMD64VPSRAVW256
+		return true
+	case OpShiftRightInt16x32:
+		v.Op = OpAMD64VPSRAVW512
+		return true
+	case OpShiftRightInt16x8:
+		v.Op = OpAMD64VPSRAVW128
+		return true
+	case OpShiftRightInt32x16:
+		v.Op = OpAMD64VPSRAVD512
+		return true
+	case OpShiftRightInt32x4:
+		v.Op = OpAMD64VPSRAVD128
+		return true
+	case OpShiftRightInt32x8:
+		v.Op = OpAMD64VPSRAVD256
+		return true
+	case OpShiftRightInt64x2:
+		v.Op = OpAMD64VPSRAVQ128
+		return true
+	case OpShiftRightInt64x4:
+		v.Op = OpAMD64VPSRAVQ256
+		return true
+	case OpShiftRightInt64x8:
+		v.Op = OpAMD64VPSRAVQ512
+		return true
+	case OpShiftRightMaskedInt16x16:
+		return rewriteValueAMD64_OpShiftRightMaskedInt16x16(v)
+	case OpShiftRightMaskedInt16x32:
+		return rewriteValueAMD64_OpShiftRightMaskedInt16x32(v)
+	case OpShiftRightMaskedInt16x8:
+		return rewriteValueAMD64_OpShiftRightMaskedInt16x8(v)
+	case OpShiftRightMaskedInt32x16:
+		return rewriteValueAMD64_OpShiftRightMaskedInt32x16(v)
+	case OpShiftRightMaskedInt32x4:
+		return rewriteValueAMD64_OpShiftRightMaskedInt32x4(v)
+	case OpShiftRightMaskedInt32x8:
+		return rewriteValueAMD64_OpShiftRightMaskedInt32x8(v)
+	case OpShiftRightMaskedInt64x2:
+		return rewriteValueAMD64_OpShiftRightMaskedInt64x2(v)
+	case OpShiftRightMaskedInt64x4:
+		return rewriteValueAMD64_OpShiftRightMaskedInt64x4(v)
+	case OpShiftRightMaskedInt64x8:
+		return rewriteValueAMD64_OpShiftRightMaskedInt64x8(v)
+	case OpShiftRightMaskedUint16x16:
+		return rewriteValueAMD64_OpShiftRightMaskedUint16x16(v)
+	case OpShiftRightMaskedUint16x32:
+		return rewriteValueAMD64_OpShiftRightMaskedUint16x32(v)
+	case OpShiftRightMaskedUint16x8:
+		return rewriteValueAMD64_OpShiftRightMaskedUint16x8(v)
+	case OpShiftRightMaskedUint32x16:
+		return rewriteValueAMD64_OpShiftRightMaskedUint32x16(v)
+	case OpShiftRightMaskedUint32x4:
+		return rewriteValueAMD64_OpShiftRightMaskedUint32x4(v)
+	case OpShiftRightMaskedUint32x8:
+		return rewriteValueAMD64_OpShiftRightMaskedUint32x8(v)
+	case OpShiftRightMaskedUint64x2:
+		return rewriteValueAMD64_OpShiftRightMaskedUint64x2(v)
+	case OpShiftRightMaskedUint64x4:
+		return rewriteValueAMD64_OpShiftRightMaskedUint64x4(v)
+	case OpShiftRightMaskedUint64x8:
+		return rewriteValueAMD64_OpShiftRightMaskedUint64x8(v)
+	case OpShiftRightUint16x16:
+		v.Op = OpAMD64VPSRLVW256
+		return true
+	case OpShiftRightUint16x32:
+		v.Op = OpAMD64VPSRLVW512
+		return true
+	case OpShiftRightUint16x8:
+		v.Op = OpAMD64VPSRLVW128
+		return true
+	case OpShiftRightUint32x16:
+		v.Op = OpAMD64VPSRLVD512
+		return true
+	case OpShiftRightUint32x4:
+		v.Op = OpAMD64VPSRLVD128
+		return true
+	case OpShiftRightUint32x8:
+		v.Op = OpAMD64VPSRLVD256
+		return true
+	case OpShiftRightUint64x2:
+		v.Op = OpAMD64VPSRLVQ128
+		return true
+	case OpShiftRightUint64x4:
+		v.Op = OpAMD64VPSRLVQ256
+		return true
+	case OpShiftRightUint64x8:
+		v.Op = OpAMD64VPSRLVQ512
+		return true
 	case OpSignExt16to32:
 		v.Op = OpAMD64MOVWQSX
 		return true
@@ -1102,6 +5095,24 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpSignExt8to64:
 		v.Op = OpAMD64MOVBQSX
 		return true
+	case OpSignInt16x16:
+		v.Op = OpAMD64VPSIGNW256
+		return true
+	case OpSignInt16x8:
+		v.Op = OpAMD64VPSIGNW128
+		return true
+	case OpSignInt32x4:
+		v.Op = OpAMD64VPSIGND128
+		return true
+	case OpSignInt32x8:
+		v.Op = OpAMD64VPSIGND256
+		return true
+	case OpSignInt8x16:
+		v.Op = OpAMD64VPSIGNB128
+		return true
+	case OpSignInt8x32:
+		v.Op = OpAMD64VPSIGNB256
+		return true
 	case OpSlicemask:
 		return rewriteValueAMD64_OpSlicemask(v)
 	case OpSpectreIndex:
@@ -1114,6 +5125,36 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpSqrt32:
 		v.Op = OpAMD64SQRTSS
 		return true
+	case OpSqrtFloat32x16:
+		v.Op = OpAMD64VSQRTPS512
+		return true
+	case OpSqrtFloat32x4:
+		v.Op = OpAMD64VSQRTPS128
+		return true
+	case OpSqrtFloat32x8:
+		v.Op = OpAMD64VSQRTPS256
+		return true
+	case OpSqrtFloat64x2:
+		v.Op = OpAMD64VSQRTPD128
+		return true
+	case OpSqrtFloat64x4:
+		v.Op = OpAMD64VSQRTPD256
+		return true
+	case OpSqrtFloat64x8:
+		v.Op = OpAMD64VSQRTPD512
+		return true
+	case OpSqrtMaskedFloat32x16:
+		return rewriteValueAMD64_OpSqrtMaskedFloat32x16(v)
+	case OpSqrtMaskedFloat32x4:
+		return rewriteValueAMD64_OpSqrtMaskedFloat32x4(v)
+	case OpSqrtMaskedFloat32x8:
+		return rewriteValueAMD64_OpSqrtMaskedFloat32x8(v)
+	case OpSqrtMaskedFloat64x2:
+		return rewriteValueAMD64_OpSqrtMaskedFloat64x2(v)
+	case OpSqrtMaskedFloat64x4:
+		return rewriteValueAMD64_OpSqrtMaskedFloat64x4(v)
+	case OpSqrtMaskedFloat64x8:
+		return rewriteValueAMD64_OpSqrtMaskedFloat64x8(v)
 	case OpStaticCall:
 		v.Op = OpAMD64CALLstatic
 		return true
@@ -1137,9 +5178,159 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpSub8:
 		v.Op = OpAMD64SUBL
 		return true
+	case OpSubFloat32x16:
+		v.Op = OpAMD64VSUBPS512
+		return true
+	case OpSubFloat32x4:
+		v.Op = OpAMD64VSUBPS128
+		return true
+	case OpSubFloat32x8:
+		v.Op = OpAMD64VSUBPS256
+		return true
+	case OpSubFloat64x2:
+		v.Op = OpAMD64VSUBPD128
+		return true
+	case OpSubFloat64x4:
+		v.Op = OpAMD64VSUBPD256
+		return true
+	case OpSubFloat64x8:
+		v.Op = OpAMD64VSUBPD512
+		return true
+	case OpSubInt16x16:
+		v.Op = OpAMD64VPSUBW256
+		return true
+	case OpSubInt16x32:
+		v.Op = OpAMD64VPSUBW512
+		return true
+	case OpSubInt16x8:
+		v.Op = OpAMD64VPSUBW128
+		return true
+	case OpSubInt32x16:
+		v.Op = OpAMD64VPSUBD512
+		return true
+	case OpSubInt32x4:
+		v.Op = OpAMD64VPSUBD128
+		return true
+	case OpSubInt32x8:
+		v.Op = OpAMD64VPSUBD256
+		return true
+	case OpSubInt64x2:
+		v.Op = OpAMD64VPSUBQ128
+		return true
+	case OpSubInt64x4:
+		v.Op = OpAMD64VPSUBQ256
+		return true
+	case OpSubInt64x8:
+		v.Op = OpAMD64VPSUBQ512
+		return true
+	case OpSubInt8x16:
+		v.Op = OpAMD64VPSUBB128
+		return true
+	case OpSubInt8x32:
+		v.Op = OpAMD64VPSUBB256
+		return true
+	case OpSubInt8x64:
+		v.Op = OpAMD64VPSUBB512
+		return true
+	case OpSubMaskedFloat32x16:
+		return rewriteValueAMD64_OpSubMaskedFloat32x16(v)
+	case OpSubMaskedFloat32x4:
+		return rewriteValueAMD64_OpSubMaskedFloat32x4(v)
+	case OpSubMaskedFloat32x8:
+		return rewriteValueAMD64_OpSubMaskedFloat32x8(v)
+	case OpSubMaskedFloat64x2:
+		return rewriteValueAMD64_OpSubMaskedFloat64x2(v)
+	case OpSubMaskedFloat64x4:
+		return rewriteValueAMD64_OpSubMaskedFloat64x4(v)
+	case OpSubMaskedFloat64x8:
+		return rewriteValueAMD64_OpSubMaskedFloat64x8(v)
+	case OpSubMaskedInt16x16:
+		return rewriteValueAMD64_OpSubMaskedInt16x16(v)
+	case OpSubMaskedInt16x32:
+		return rewriteValueAMD64_OpSubMaskedInt16x32(v)
+	case OpSubMaskedInt16x8:
+		return rewriteValueAMD64_OpSubMaskedInt16x8(v)
+	case OpSubMaskedInt32x16:
+		return rewriteValueAMD64_OpSubMaskedInt32x16(v)
+	case OpSubMaskedInt32x4:
+		return rewriteValueAMD64_OpSubMaskedInt32x4(v)
+	case OpSubMaskedInt32x8:
+		return rewriteValueAMD64_OpSubMaskedInt32x8(v)
+	case OpSubMaskedInt64x2:
+		return rewriteValueAMD64_OpSubMaskedInt64x2(v)
+	case OpSubMaskedInt64x4:
+		return rewriteValueAMD64_OpSubMaskedInt64x4(v)
+	case OpSubMaskedInt64x8:
+		return rewriteValueAMD64_OpSubMaskedInt64x8(v)
+	case OpSubMaskedInt8x16:
+		return rewriteValueAMD64_OpSubMaskedInt8x16(v)
+	case OpSubMaskedInt8x32:
+		return rewriteValueAMD64_OpSubMaskedInt8x32(v)
+	case OpSubMaskedInt8x64:
+		return rewriteValueAMD64_OpSubMaskedInt8x64(v)
+	case OpSubMaskedUint16x16:
+		return rewriteValueAMD64_OpSubMaskedUint16x16(v)
+	case OpSubMaskedUint16x32:
+		return rewriteValueAMD64_OpSubMaskedUint16x32(v)
+	case OpSubMaskedUint16x8:
+		return rewriteValueAMD64_OpSubMaskedUint16x8(v)
+	case OpSubMaskedUint32x16:
+		return rewriteValueAMD64_OpSubMaskedUint32x16(v)
+	case OpSubMaskedUint32x4:
+		return rewriteValueAMD64_OpSubMaskedUint32x4(v)
+	case OpSubMaskedUint32x8:
+		return rewriteValueAMD64_OpSubMaskedUint32x8(v)
+	case OpSubMaskedUint64x2:
+		return rewriteValueAMD64_OpSubMaskedUint64x2(v)
+	case OpSubMaskedUint64x4:
+		return rewriteValueAMD64_OpSubMaskedUint64x4(v)
+	case OpSubMaskedUint64x8:
+		return rewriteValueAMD64_OpSubMaskedUint64x8(v)
+	case OpSubMaskedUint8x16:
+		return rewriteValueAMD64_OpSubMaskedUint8x16(v)
+	case OpSubMaskedUint8x32:
+		return rewriteValueAMD64_OpSubMaskedUint8x32(v)
+	case OpSubMaskedUint8x64:
+		return rewriteValueAMD64_OpSubMaskedUint8x64(v)
 	case OpSubPtr:
 		v.Op = OpAMD64SUBQ
 		return true
+	case OpSubUint16x16:
+		v.Op = OpAMD64VPSUBW256
+		return true
+	case OpSubUint16x32:
+		v.Op = OpAMD64VPSUBW512
+		return true
+	case OpSubUint16x8:
+		v.Op = OpAMD64VPSUBW128
+		return true
+	case OpSubUint32x16:
+		v.Op = OpAMD64VPSUBD512
+		return true
+	case OpSubUint32x4:
+		v.Op = OpAMD64VPSUBD128
+		return true
+	case OpSubUint32x8:
+		v.Op = OpAMD64VPSUBD256
+		return true
+	case OpSubUint64x2:
+		v.Op = OpAMD64VPSUBQ128
+		return true
+	case OpSubUint64x4:
+		v.Op = OpAMD64VPSUBQ256
+		return true
+	case OpSubUint64x8:
+		v.Op = OpAMD64VPSUBQ512
+		return true
+	case OpSubUint8x16:
+		v.Op = OpAMD64VPSUBB128
+		return true
+	case OpSubUint8x32:
+		v.Op = OpAMD64VPSUBB256
+		return true
+	case OpSubUint8x64:
+		v.Op = OpAMD64VPSUBB512
+		return true
 	case OpTailCall:
 		v.Op = OpAMD64CALLtail
 		return true
@@ -1163,6 +5354,53 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpTrunc64to8:
 		v.Op = OpCopy
 		return true
+	case OpTruncFloat32x4:
+		return rewriteValueAMD64_OpTruncFloat32x4(v)
+	case OpTruncFloat32x8:
+		return rewriteValueAMD64_OpTruncFloat32x8(v)
+	case OpTruncFloat64x2:
+		return rewriteValueAMD64_OpTruncFloat64x2(v)
+	case OpTruncFloat64x4:
+		return rewriteValueAMD64_OpTruncFloat64x4(v)
+	case OpTruncWithPrecisionFloat32x16:
+		return rewriteValueAMD64_OpTruncWithPrecisionFloat32x16(v)
+	case OpTruncWithPrecisionFloat32x4:
+		return rewriteValueAMD64_OpTruncWithPrecisionFloat32x4(v)
+	case OpTruncWithPrecisionFloat32x8:
+		return rewriteValueAMD64_OpTruncWithPrecisionFloat32x8(v)
+	case OpTruncWithPrecisionFloat64x2:
+		return rewriteValueAMD64_OpTruncWithPrecisionFloat64x2(v)
+	case OpTruncWithPrecisionFloat64x4:
+		return rewriteValueAMD64_OpTruncWithPrecisionFloat64x4(v)
+	case OpTruncWithPrecisionFloat64x8:
+		return rewriteValueAMD64_OpTruncWithPrecisionFloat64x8(v)
+	case OpTruncWithPrecisionMaskedFloat32x16:
+		return rewriteValueAMD64_OpTruncWithPrecisionMaskedFloat32x16(v)
+	case OpTruncWithPrecisionMaskedFloat32x4:
+		return rewriteValueAMD64_OpTruncWithPrecisionMaskedFloat32x4(v)
+	case OpTruncWithPrecisionMaskedFloat32x8:
+		return rewriteValueAMD64_OpTruncWithPrecisionMaskedFloat32x8(v)
+	case OpTruncWithPrecisionMaskedFloat64x2:
+		return rewriteValueAMD64_OpTruncWithPrecisionMaskedFloat64x2(v)
+	case OpTruncWithPrecisionMaskedFloat64x4:
+		return rewriteValueAMD64_OpTruncWithPrecisionMaskedFloat64x4(v)
+	case OpTruncWithPrecisionMaskedFloat64x8:
+		return rewriteValueAMD64_OpTruncWithPrecisionMaskedFloat64x8(v)
+	case OpUnsignedSignedQuadDotProdAccumulateInt32x16:
+		v.Op = OpAMD64VPDPBUSD512
+		return true
+	case OpUnsignedSignedQuadDotProdAccumulateInt32x4:
+		v.Op = OpAMD64VPDPBUSD128
+		return true
+	case OpUnsignedSignedQuadDotProdAccumulateInt32x8:
+		v.Op = OpAMD64VPDPBUSD256
+		return true
+	case OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x16:
+		return rewriteValueAMD64_OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x16(v)
+	case OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x4:
+		return rewriteValueAMD64_OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x4(v)
+	case OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x8:
+		return rewriteValueAMD64_OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x8(v)
 	case OpWB:
 		v.Op = OpAMD64LoweredWB
 		return true
@@ -1178,6 +5416,90 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpXor8:
 		v.Op = OpAMD64XORL
 		return true
+	case OpXorInt16x16:
+		v.Op = OpAMD64VPXOR256
+		return true
+	case OpXorInt16x8:
+		v.Op = OpAMD64VPXOR128
+		return true
+	case OpXorInt32x16:
+		v.Op = OpAMD64VPXORD512
+		return true
+	case OpXorInt32x4:
+		v.Op = OpAMD64VPXOR128
+		return true
+	case OpXorInt32x8:
+		v.Op = OpAMD64VPXOR256
+		return true
+	case OpXorInt64x2:
+		v.Op = OpAMD64VPXOR128
+		return true
+	case OpXorInt64x4:
+		v.Op = OpAMD64VPXOR256
+		return true
+	case OpXorInt64x8:
+		v.Op = OpAMD64VPXORQ512
+		return true
+	case OpXorInt8x16:
+		v.Op = OpAMD64VPXOR128
+		return true
+	case OpXorInt8x32:
+		v.Op = OpAMD64VPXOR256
+		return true
+	case OpXorMaskedInt32x16:
+		return rewriteValueAMD64_OpXorMaskedInt32x16(v)
+	case OpXorMaskedInt32x4:
+		return rewriteValueAMD64_OpXorMaskedInt32x4(v)
+	case OpXorMaskedInt32x8:
+		return rewriteValueAMD64_OpXorMaskedInt32x8(v)
+	case OpXorMaskedInt64x2:
+		return rewriteValueAMD64_OpXorMaskedInt64x2(v)
+	case OpXorMaskedInt64x4:
+		return rewriteValueAMD64_OpXorMaskedInt64x4(v)
+	case OpXorMaskedInt64x8:
+		return rewriteValueAMD64_OpXorMaskedInt64x8(v)
+	case OpXorMaskedUint32x16:
+		return rewriteValueAMD64_OpXorMaskedUint32x16(v)
+	case OpXorMaskedUint32x4:
+		return rewriteValueAMD64_OpXorMaskedUint32x4(v)
+	case OpXorMaskedUint32x8:
+		return rewriteValueAMD64_OpXorMaskedUint32x8(v)
+	case OpXorMaskedUint64x2:
+		return rewriteValueAMD64_OpXorMaskedUint64x2(v)
+	case OpXorMaskedUint64x4:
+		return rewriteValueAMD64_OpXorMaskedUint64x4(v)
+	case OpXorMaskedUint64x8:
+		return rewriteValueAMD64_OpXorMaskedUint64x8(v)
+	case OpXorUint16x16:
+		v.Op = OpAMD64VPXOR256
+		return true
+	case OpXorUint16x8:
+		v.Op = OpAMD64VPXOR128
+		return true
+	case OpXorUint32x16:
+		v.Op = OpAMD64VPXORD512
+		return true
+	case OpXorUint32x4:
+		v.Op = OpAMD64VPXOR128
+		return true
+	case OpXorUint32x8:
+		v.Op = OpAMD64VPXOR256
+		return true
+	case OpXorUint64x2:
+		v.Op = OpAMD64VPXOR128
+		return true
+	case OpXorUint64x4:
+		v.Op = OpAMD64VPXOR256
+		return true
+	case OpXorUint64x8:
+		v.Op = OpAMD64VPXORQ512
+		return true
+	case OpXorUint8x16:
+		v.Op = OpAMD64VPXOR128
+		return true
+	case OpXorUint8x32:
+		v.Op = OpAMD64VPXOR256
+		return true
 	case OpZero:
 		return rewriteValueAMD64_OpZero(v)
 	case OpZeroExt16to32:
@@ -1198,6 +5520,8 @@ func rewriteValueAMD64(v *Value) bool {
 	case OpZeroExt8to64:
 		v.Op = OpAMD64MOVBQZX
 		return true
+	case OpZeroSIMD:
+		return rewriteValueAMD64_OpZeroSIMD(v)
 	}
 	return false
 }
@@ -22812,6 +27136,174 @@ func rewriteValueAMD64_OpAMD64TESTWconst(v *Value) bool {
 	}
 	return false
 }
+func rewriteValueAMD64_OpAMD64VPMOVVec16x16ToM(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (VPMOVVec16x16ToM (VPMOVMToVec16x16 x))
+	// result: x
+	for {
+		if v_0.Op != OpAMD64VPMOVMToVec16x16 {
+			break
+		}
+		x := v_0.Args[0]
+		v.copyOf(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpAMD64VPMOVVec16x32ToM(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (VPMOVVec16x32ToM (VPMOVMToVec16x32 x))
+	// result: x
+	for {
+		if v_0.Op != OpAMD64VPMOVMToVec16x32 {
+			break
+		}
+		x := v_0.Args[0]
+		v.copyOf(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpAMD64VPMOVVec16x8ToM(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (VPMOVVec16x8ToM (VPMOVMToVec16x8 x))
+	// result: x
+	for {
+		if v_0.Op != OpAMD64VPMOVMToVec16x8 {
+			break
+		}
+		x := v_0.Args[0]
+		v.copyOf(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpAMD64VPMOVVec32x16ToM(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (VPMOVVec32x16ToM (VPMOVMToVec32x16 x))
+	// result: x
+	for {
+		if v_0.Op != OpAMD64VPMOVMToVec32x16 {
+			break
+		}
+		x := v_0.Args[0]
+		v.copyOf(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpAMD64VPMOVVec32x4ToM(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (VPMOVVec32x4ToM (VPMOVMToVec32x4 x))
+	// result: x
+	for {
+		if v_0.Op != OpAMD64VPMOVMToVec32x4 {
+			break
+		}
+		x := v_0.Args[0]
+		v.copyOf(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpAMD64VPMOVVec32x8ToM(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (VPMOVVec32x8ToM (VPMOVMToVec32x8 x))
+	// result: x
+	for {
+		if v_0.Op != OpAMD64VPMOVMToVec32x8 {
+			break
+		}
+		x := v_0.Args[0]
+		v.copyOf(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpAMD64VPMOVVec64x2ToM(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (VPMOVVec64x2ToM (VPMOVMToVec64x2 x))
+	// result: x
+	for {
+		if v_0.Op != OpAMD64VPMOVMToVec64x2 {
+			break
+		}
+		x := v_0.Args[0]
+		v.copyOf(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpAMD64VPMOVVec64x4ToM(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (VPMOVVec64x4ToM (VPMOVMToVec64x4 x))
+	// result: x
+	for {
+		if v_0.Op != OpAMD64VPMOVMToVec64x4 {
+			break
+		}
+		x := v_0.Args[0]
+		v.copyOf(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpAMD64VPMOVVec64x8ToM(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (VPMOVVec64x8ToM (VPMOVMToVec64x8 x))
+	// result: x
+	for {
+		if v_0.Op != OpAMD64VPMOVMToVec64x8 {
+			break
+		}
+		x := v_0.Args[0]
+		v.copyOf(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpAMD64VPMOVVec8x16ToM(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (VPMOVVec8x16ToM (VPMOVMToVec8x16 x))
+	// result: x
+	for {
+		if v_0.Op != OpAMD64VPMOVMToVec8x16 {
+			break
+		}
+		x := v_0.Args[0]
+		v.copyOf(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpAMD64VPMOVVec8x32ToM(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (VPMOVVec8x32ToM (VPMOVMToVec8x32 x))
+	// result: x
+	for {
+		if v_0.Op != OpAMD64VPMOVMToVec8x32 {
+			break
+		}
+		x := v_0.Args[0]
+		v.copyOf(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpAMD64VPMOVVec8x64ToM(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (VPMOVVec8x64ToM (VPMOVMToVec8x64 x))
+	// result: x
+	for {
+		if v_0.Op != OpAMD64VPMOVMToVec8x64 {
+			break
+		}
+		x := v_0.Args[0]
+		v.copyOf(x)
+		return true
+	}
+	return false
+}
 func rewriteValueAMD64_OpAMD64XADDLlock(v *Value) bool {
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
@@ -23712,6069 +28204,25898 @@ func rewriteValueAMD64_OpAMD64XORQmodify(v *Value) bool {
 	}
 	return false
 }
-func rewriteValueAMD64_OpAddr(v *Value) bool {
+func rewriteValueAMD64_OpAbsoluteMaskedInt16x16(v *Value) bool {
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (Addr {sym} base)
-	// result: (LEAQ {sym} base)
+	b := v.Block
+	// match: (AbsoluteMaskedInt16x16 x mask)
+	// result: (VPABSWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		sym := auxToSym(v.Aux)
-		base := v_0
-		v.reset(OpAMD64LEAQ)
-		v.Aux = symToAux(sym)
-		v.AddArg(base)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPABSWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicAdd32(v *Value) bool {
-	v_2 := v.Args[2]
+func rewriteValueAMD64_OpAbsoluteMaskedInt16x32(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (AtomicAdd32 ptr val mem)
-	// result: (AddTupleFirst32 val (XADDLlock val ptr mem))
+	// match: (AbsoluteMaskedInt16x32 x mask)
+	// result: (VPABSWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpAMD64AddTupleFirst32)
-		v0 := b.NewValue0(v.Pos, OpAMD64XADDLlock, types.NewTuple(typ.UInt32, types.TypeMem))
-		v0.AddArg3(val, ptr, mem)
-		v.AddArg2(val, v0)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPABSWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicAdd64(v *Value) bool {
-	v_2 := v.Args[2]
+func rewriteValueAMD64_OpAbsoluteMaskedInt16x8(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (AtomicAdd64 ptr val mem)
-	// result: (AddTupleFirst64 val (XADDQlock val ptr mem))
+	// match: (AbsoluteMaskedInt16x8 x mask)
+	// result: (VPABSWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpAMD64AddTupleFirst64)
-		v0 := b.NewValue0(v.Pos, OpAMD64XADDQlock, types.NewTuple(typ.UInt64, types.TypeMem))
-		v0.AddArg3(val, ptr, mem)
-		v.AddArg2(val, v0)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPABSWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicAnd32(v *Value) bool {
-	v_2 := v.Args[2]
+func rewriteValueAMD64_OpAbsoluteMaskedInt32x16(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicAnd32 ptr val mem)
-	// result: (ANDLlock ptr val mem)
+	b := v.Block
+	// match: (AbsoluteMaskedInt32x16 x mask)
+	// result: (VPABSDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpAMD64ANDLlock)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPABSDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicAnd32value(v *Value) bool {
-	v_2 := v.Args[2]
+func rewriteValueAMD64_OpAbsoluteMaskedInt32x4(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicAnd32value ptr val mem)
-	// result: (LoweredAtomicAnd32 ptr val mem)
+	b := v.Block
+	// match: (AbsoluteMaskedInt32x4 x mask)
+	// result: (VPABSDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpAMD64LoweredAtomicAnd32)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPABSDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicAnd64value(v *Value) bool {
-	v_2 := v.Args[2]
+func rewriteValueAMD64_OpAbsoluteMaskedInt32x8(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicAnd64value ptr val mem)
-	// result: (LoweredAtomicAnd64 ptr val mem)
+	b := v.Block
+	// match: (AbsoluteMaskedInt32x8 x mask)
+	// result: (VPABSDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpAMD64LoweredAtomicAnd64)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPABSDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicAnd8(v *Value) bool {
-	v_2 := v.Args[2]
+func rewriteValueAMD64_OpAbsoluteMaskedInt64x2(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicAnd8 ptr val mem)
-	// result: (ANDBlock ptr val mem)
+	b := v.Block
+	// match: (AbsoluteMaskedInt64x2 x mask)
+	// result: (VPABSQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpAMD64ANDBlock)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPABSQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicCompareAndSwap32(v *Value) bool {
-	v_3 := v.Args[3]
-	v_2 := v.Args[2]
+func rewriteValueAMD64_OpAbsoluteMaskedInt64x4(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicCompareAndSwap32 ptr old new_ mem)
-	// result: (CMPXCHGLlock ptr old new_ mem)
+	b := v.Block
+	// match: (AbsoluteMaskedInt64x4 x mask)
+	// result: (VPABSQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		old := v_1
-		new_ := v_2
-		mem := v_3
-		v.reset(OpAMD64CMPXCHGLlock)
-		v.AddArg4(ptr, old, new_, mem)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPABSQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicCompareAndSwap64(v *Value) bool {
-	v_3 := v.Args[3]
-	v_2 := v.Args[2]
+func rewriteValueAMD64_OpAbsoluteMaskedInt64x8(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicCompareAndSwap64 ptr old new_ mem)
-	// result: (CMPXCHGQlock ptr old new_ mem)
+	b := v.Block
+	// match: (AbsoluteMaskedInt64x8 x mask)
+	// result: (VPABSQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		old := v_1
-		new_ := v_2
-		mem := v_3
-		v.reset(OpAMD64CMPXCHGQlock)
-		v.AddArg4(ptr, old, new_, mem)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPABSQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicExchange32(v *Value) bool {
-	v_2 := v.Args[2]
+func rewriteValueAMD64_OpAbsoluteMaskedInt8x16(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicExchange32 ptr val mem)
-	// result: (XCHGL val ptr mem)
+	b := v.Block
+	// match: (AbsoluteMaskedInt8x16 x mask)
+	// result: (VPABSBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpAMD64XCHGL)
-		v.AddArg3(val, ptr, mem)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPABSBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicExchange64(v *Value) bool {
-	v_2 := v.Args[2]
+func rewriteValueAMD64_OpAbsoluteMaskedInt8x32(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicExchange64 ptr val mem)
-	// result: (XCHGQ val ptr mem)
+	b := v.Block
+	// match: (AbsoluteMaskedInt8x32 x mask)
+	// result: (VPABSBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpAMD64XCHGQ)
-		v.AddArg3(val, ptr, mem)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPABSBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicExchange8(v *Value) bool {
-	v_2 := v.Args[2]
+func rewriteValueAMD64_OpAbsoluteMaskedInt8x64(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicExchange8 ptr val mem)
-	// result: (XCHGB val ptr mem)
+	b := v.Block
+	// match: (AbsoluteMaskedInt8x64 x mask)
+	// result: (VPABSBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpAMD64XCHGB)
-		v.AddArg3(val, ptr, mem)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPABSBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicLoad32(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicLoad32 ptr mem)
-	// result: (MOVLatomicload ptr mem)
+	b := v.Block
+	// match: (AddMaskedFloat32x16 x y mask)
+	// result: (VADDPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		mem := v_1
-		v.reset(OpAMD64MOVLatomicload)
-		v.AddArg2(ptr, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VADDPSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicLoad64(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicLoad64 ptr mem)
-	// result: (MOVQatomicload ptr mem)
+	b := v.Block
+	// match: (AddMaskedFloat32x4 x y mask)
+	// result: (VADDPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		mem := v_1
-		v.reset(OpAMD64MOVQatomicload)
-		v.AddArg2(ptr, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VADDPSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicLoad8(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicLoad8 ptr mem)
-	// result: (MOVBatomicload ptr mem)
+	b := v.Block
+	// match: (AddMaskedFloat32x8 x y mask)
+	// result: (VADDPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		mem := v_1
-		v.reset(OpAMD64MOVBatomicload)
-		v.AddArg2(ptr, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VADDPSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicLoadPtr(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicLoadPtr ptr mem)
-	// result: (MOVQatomicload ptr mem)
+	b := v.Block
+	// match: (AddMaskedFloat64x2 x y mask)
+	// result: (VADDPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		mem := v_1
-		v.reset(OpAMD64MOVQatomicload)
-		v.AddArg2(ptr, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VADDPDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicOr32(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedFloat64x4(v *Value) bool {
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicOr32 ptr val mem)
-	// result: (ORLlock ptr val mem)
+	b := v.Block
+	// match: (AddMaskedFloat64x4 x y mask)
+	// result: (VADDPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpAMD64ORLlock)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VADDPDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicOr32value(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedFloat64x8(v *Value) bool {
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicOr32value ptr val mem)
-	// result: (LoweredAtomicOr32 ptr val mem)
+	b := v.Block
+	// match: (AddMaskedFloat64x8 x y mask)
+	// result: (VADDPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpAMD64LoweredAtomicOr32)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VADDPDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicOr64value(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedInt16x16(v *Value) bool {
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicOr64value ptr val mem)
-	// result: (LoweredAtomicOr64 ptr val mem)
+	b := v.Block
+	// match: (AddMaskedInt16x16 x y mask)
+	// result: (VPADDWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpAMD64LoweredAtomicOr64)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicOr8(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedInt16x32(v *Value) bool {
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (AtomicOr8 ptr val mem)
-	// result: (ORBlock ptr val mem)
+	b := v.Block
+	// match: (AddMaskedInt16x32 x y mask)
+	// result: (VPADDWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpAMD64ORBlock)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicStore32(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedInt16x8(v *Value) bool {
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (AtomicStore32 ptr val mem)
-	// result: (Select1 (XCHGL <types.NewTuple(typ.UInt32,types.TypeMem)> val ptr mem))
+	// match: (AddMaskedInt16x8 x y mask)
+	// result: (VPADDWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpSelect1)
-		v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem))
-		v0.AddArg3(val, ptr, mem)
-		v.AddArg(v0)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicStore64(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedInt32x16(v *Value) bool {
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (AtomicStore64 ptr val mem)
-	// result: (Select1 (XCHGQ <types.NewTuple(typ.UInt64,types.TypeMem)> val ptr mem))
+	// match: (AddMaskedInt32x16 x y mask)
+	// result: (VPADDDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpSelect1)
-		v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem))
-		v0.AddArg3(val, ptr, mem)
-		v.AddArg(v0)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicStore8(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedInt32x4(v *Value) bool {
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (AtomicStore8 ptr val mem)
-	// result: (Select1 (XCHGB <types.NewTuple(typ.UInt8,types.TypeMem)> val ptr mem))
+	// match: (AddMaskedInt32x4 x y mask)
+	// result: (VPADDDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpSelect1)
-		v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem))
-		v0.AddArg3(val, ptr, mem)
-		v.AddArg(v0)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpAtomicStorePtrNoWB(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedInt32x8(v *Value) bool {
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (AtomicStorePtrNoWB ptr val mem)
-	// result: (Select1 (XCHGQ <types.NewTuple(typ.BytePtr,types.TypeMem)> val ptr mem))
+	// match: (AddMaskedInt32x8 x y mask)
+	// result: (VPADDDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		v.reset(OpSelect1)
-		v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem))
-		v0.AddArg3(val, ptr, mem)
-		v.AddArg(v0)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpBitLen16(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (BitLen16 x)
-	// cond: buildcfg.GOAMD64 < 3
-	// result: (BSRL (LEAL1 <typ.UInt32> [1] (MOVWQZX <typ.UInt32> x) (MOVWQZX <typ.UInt32> x)))
+	// match: (AddMaskedInt64x2 x y mask)
+	// result: (VPADDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		if !(buildcfg.GOAMD64 < 3) {
-			break
-		}
-		v.reset(OpAMD64BSRL)
-		v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32)
-		v0.AuxInt = int32ToAuxInt(1)
-		v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32)
-		v1.AddArg(x)
-		v0.AddArg2(v1, v1)
-		v.AddArg(v0)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (BitLen16 <t> x)
-	// cond: buildcfg.GOAMD64 >= 3
-	// result: (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVWQZX <x.Type> x))))
+}
+func rewriteValueAMD64_OpAddMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AddMaskedInt64x4 x y mask)
+	// result: (VPADDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
-		if !(buildcfg.GOAMD64 >= 3) {
-			break
-		}
-		v.reset(OpAMD64NEGQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t)
-		v0.AuxInt = int32ToAuxInt(-32)
-		v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, x.Type)
-		v2.AddArg(x)
-		v1.AddArg(v2)
-		v0.AddArg(v1)
-		v.AddArg(v0)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpBitLen32(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (BitLen32 x)
-	// cond: buildcfg.GOAMD64 < 3
-	// result: (Select0 (BSRQ (LEAQ1 <typ.UInt64> [1] (MOVLQZX <typ.UInt64> x) (MOVLQZX <typ.UInt64> x))))
+	// match: (AddMaskedInt64x8 x y mask)
+	// result: (VPADDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		if !(buildcfg.GOAMD64 < 3) {
-			break
-		}
-		v.reset(OpSelect0)
-		v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags))
-		v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64)
-		v1.AuxInt = int32ToAuxInt(1)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64)
-		v2.AddArg(x)
-		v1.AddArg2(v2, v2)
-		v0.AddArg(v1)
-		v.AddArg(v0)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (BitLen32 <t> x)
-	// cond: buildcfg.GOAMD64 >= 3
-	// result: (NEGQ (ADDQconst <t> [-32] (LZCNTL x)))
+}
+func rewriteValueAMD64_OpAddMaskedInt8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AddMaskedInt8x16 x y mask)
+	// result: (VPADDBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
-		if !(buildcfg.GOAMD64 >= 3) {
-			break
-		}
-		v.reset(OpAMD64NEGQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t)
-		v0.AuxInt = int32ToAuxInt(-32)
-		v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32)
-		v1.AddArg(x)
-		v0.AddArg(v1)
-		v.AddArg(v0)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpBitLen64(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedInt8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (BitLen64 <t> x)
-	// cond: buildcfg.GOAMD64 < 3
-	// result: (ADDQconst [1] (CMOVQEQ <t> (Select0 <t> (BSRQ x)) (MOVQconst <t> [-1]) (Select1 <types.TypeFlags> (BSRQ x))))
+	// match: (AddMaskedInt8x32 x y mask)
+	// result: (VPADDBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
-		if !(buildcfg.GOAMD64 < 3) {
-			break
-		}
-		v.reset(OpAMD64ADDQconst)
-		v.AuxInt = int32ToAuxInt(1)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t)
-		v1 := b.NewValue0(v.Pos, OpSelect0, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags))
-		v2.AddArg(x)
-		v1.AddArg(v2)
-		v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t)
-		v3.AuxInt = int64ToAuxInt(-1)
-		v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
-		v4.AddArg(v2)
-		v0.AddArg3(v1, v3, v4)
-		v.AddArg(v0)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (BitLen64 <t> x)
-	// cond: buildcfg.GOAMD64 >= 3
-	// result: (NEGQ (ADDQconst <t> [-64] (LZCNTQ x)))
+}
+func rewriteValueAMD64_OpAddMaskedInt8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AddMaskedInt8x64 x y mask)
+	// result: (VPADDBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
-		if !(buildcfg.GOAMD64 >= 3) {
-			break
-		}
-		v.reset(OpAMD64NEGQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t)
-		v0.AuxInt = int32ToAuxInt(-64)
-		v1 := b.NewValue0(v.Pos, OpAMD64LZCNTQ, typ.UInt64)
-		v1.AddArg(x)
-		v0.AddArg(v1)
-		v.AddArg(v0)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpBitLen8(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (BitLen8 x)
-	// cond: buildcfg.GOAMD64 < 3
-	// result: (BSRL (LEAL1 <typ.UInt32> [1] (MOVBQZX <typ.UInt32> x) (MOVBQZX <typ.UInt32> x)))
+	// match: (AddMaskedUint16x16 x y mask)
+	// result: (VPADDWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		if !(buildcfg.GOAMD64 < 3) {
-			break
-		}
-		v.reset(OpAMD64BSRL)
-		v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32)
-		v0.AuxInt = int32ToAuxInt(1)
-		v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32)
-		v1.AddArg(x)
-		v0.AddArg2(v1, v1)
-		v.AddArg(v0)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (BitLen8 <t> x)
-	// cond: buildcfg.GOAMD64 >= 3
-	// result: (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVBQZX <x.Type> x))))
+}
+func rewriteValueAMD64_OpAddMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AddMaskedUint16x32 x y mask)
+	// result: (VPADDWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
-		if !(buildcfg.GOAMD64 >= 3) {
-			break
-		}
-		v.reset(OpAMD64NEGQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t)
-		v0.AuxInt = int32ToAuxInt(-32)
-		v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, x.Type)
-		v2.AddArg(x)
-		v1.AddArg(v2)
-		v0.AddArg(v1)
-		v.AddArg(v0)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpBswap16(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (Bswap16 x)
-	// result: (ROLWconst [8] x)
+	b := v.Block
+	// match: (AddMaskedUint16x8 x y mask)
+	// result: (VPADDWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		v.reset(OpAMD64ROLWconst)
-		v.AuxInt = int8ToAuxInt(8)
-		v.AddArg(x)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpCeil(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (Ceil x)
-	// result: (ROUNDSD [2] x)
+	b := v.Block
+	// match: (AddMaskedUint32x16 x y mask)
+	// result: (VPADDDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		v.reset(OpAMD64ROUNDSD)
-		v.AuxInt = int8ToAuxInt(2)
-		v.AddArg(x)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpCondSelect(v *Value) bool {
+func rewriteValueAMD64_OpAddMaskedUint32x4(v *Value) bool {
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (CondSelect <t> x y (SETEQ cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQEQ y x cond)
+	// match: (AddMaskedUint32x4 x y mask)
+	// result: (VPADDDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETEQ {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQEQ)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPADDDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETNE cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQNE y x cond)
+}
+func rewriteValueAMD64_OpAddMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AddMaskedUint32x8 x y mask)
+	// result: (VPADDDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETNE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQNE)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPADDDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETL cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQLT y x cond)
+}
+func rewriteValueAMD64_OpAddMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AddMaskedUint64x2 x y mask)
+	// result: (VPADDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETL {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQLT)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPADDQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETG cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQGT y x cond)
+}
+func rewriteValueAMD64_OpAddMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AddMaskedUint64x4 x y mask)
+	// result: (VPADDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETG {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQGT)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPADDQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETLE cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQLE y x cond)
+}
+func rewriteValueAMD64_OpAddMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AddMaskedUint64x8 x y mask)
+	// result: (VPADDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETLE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQLE)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPADDQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETGE cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQGE y x cond)
+}
+func rewriteValueAMD64_OpAddMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AddMaskedUint8x16 x y mask)
+	// result: (VPADDBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETGE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQGE)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPADDBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETA cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQHI y x cond)
+}
+func rewriteValueAMD64_OpAddMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AddMaskedUint8x32 x y mask)
+	// result: (VPADDBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETA {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQHI)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPADDBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETB cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQCS y x cond)
+}
+func rewriteValueAMD64_OpAddMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AddMaskedUint8x64 x y mask)
+	// result: (VPADDBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETB {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQCS)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPADDBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETAE cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQCC y x cond)
+}
+func rewriteValueAMD64_OpAddr(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (Addr {sym} base)
+	// result: (LEAQ {sym} base)
 	for {
-		t := v.Type
-		x := v_0
-		y := v_1
-		if v_2.Op != OpAMD64SETAE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQCC)
-		v.AddArg3(y, x, cond)
+		sym := auxToSym(v.Aux)
+		base := v_0
+		v.reset(OpAMD64LEAQ)
+		v.Aux = symToAux(sym)
+		v.AddArg(base)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETBE cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQLS y x cond)
+}
+func rewriteValueAMD64_OpAndMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndMaskedInt32x16 x y mask)
+	// result: (VPANDDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETBE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQLS)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETEQF cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQEQF y x cond)
+}
+func rewriteValueAMD64_OpAndMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndMaskedInt32x4 x y mask)
+	// result: (VPANDDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETEQF {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQEQF)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETNEF cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQNEF y x cond)
+}
+func rewriteValueAMD64_OpAndMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndMaskedInt32x8 x y mask)
+	// result: (VPANDDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETNEF {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQNEF)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETGF cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQGTF y x cond)
+}
+func rewriteValueAMD64_OpAndMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndMaskedInt64x2 x y mask)
+	// result: (VPANDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETGF {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQGTF)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETGEF cond))
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQGEF y x cond)
+}
+func rewriteValueAMD64_OpAndMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndMaskedInt64x4 x y mask)
+	// result: (VPANDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETGEF {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVQGEF)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETEQ cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLEQ y x cond)
+}
+func rewriteValueAMD64_OpAndMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndMaskedInt64x8 x y mask)
+	// result: (VPANDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETEQ {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLEQ)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETNE cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLNE y x cond)
+}
+func rewriteValueAMD64_OpAndMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndMaskedUint32x16 x y mask)
+	// result: (VPANDDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETNE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLNE)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETL cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLLT y x cond)
+}
+func rewriteValueAMD64_OpAndMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndMaskedUint32x4 x y mask)
+	// result: (VPANDDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETL {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLLT)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETG cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLGT y x cond)
+}
+func rewriteValueAMD64_OpAndMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndMaskedUint32x8 x y mask)
+	// result: (VPANDDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETG {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLGT)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETLE cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLLE y x cond)
+}
+func rewriteValueAMD64_OpAndMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndMaskedUint64x2 x y mask)
+	// result: (VPANDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETLE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLLE)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETGE cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLGE y x cond)
+}
+func rewriteValueAMD64_OpAndMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndMaskedUint64x4 x y mask)
+	// result: (VPANDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETGE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLGE)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETA cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLHI y x cond)
+}
+func rewriteValueAMD64_OpAndMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndMaskedUint64x8 x y mask)
+	// result: (VPANDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETA {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLHI)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETB cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLCS y x cond)
+}
+func rewriteValueAMD64_OpAndNotMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndNotMaskedInt32x16 x y mask)
+	// result: (VPANDNDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETB {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLCS)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDNDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETAE cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLCC y x cond)
+}
+func rewriteValueAMD64_OpAndNotMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndNotMaskedInt32x4 x y mask)
+	// result: (VPANDNDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETAE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLCC)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDNDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETBE cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLLS y x cond)
+}
+func rewriteValueAMD64_OpAndNotMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndNotMaskedInt32x8 x y mask)
+	// result: (VPANDNDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETBE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLLS)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDNDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETEQF cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLEQF y x cond)
+}
+func rewriteValueAMD64_OpAndNotMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndNotMaskedInt64x2 x y mask)
+	// result: (VPANDNQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETEQF {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLEQF)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDNQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETNEF cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLNEF y x cond)
+}
+func rewriteValueAMD64_OpAndNotMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndNotMaskedInt64x4 x y mask)
+	// result: (VPANDNQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETNEF {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLNEF)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDNQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETGF cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLGTF y x cond)
+}
+func rewriteValueAMD64_OpAndNotMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndNotMaskedInt64x8 x y mask)
+	// result: (VPANDNQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETGF {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLGTF)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPANDNQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETGEF cond))
-	// cond: is32BitInt(t)
-	// result: (CMOVLGEF y x cond)
-	for {
-		t := v.Type
+}
+func rewriteValueAMD64_OpAndNotMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndNotMaskedUint32x16 x y mask)
+	// result: (VPANDNDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPANDNDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAndNotMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndNotMaskedUint32x4 x y mask)
+	// result: (VPANDNDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPANDNDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAndNotMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndNotMaskedUint32x8 x y mask)
+	// result: (VPANDNDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPANDNDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAndNotMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndNotMaskedUint64x2 x y mask)
+	// result: (VPANDNQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPANDNQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAndNotMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndNotMaskedUint64x4 x y mask)
+	// result: (VPANDNQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPANDNQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAndNotMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AndNotMaskedUint64x8 x y mask)
+	// result: (VPANDNQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPANDNQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpApproximateReciprocalMaskedFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ApproximateReciprocalMaskedFloat32x16 x mask)
+	// result: (VRCP14PSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRCP14PSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpApproximateReciprocalMaskedFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ApproximateReciprocalMaskedFloat32x4 x mask)
+	// result: (VRCP14PSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRCP14PSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpApproximateReciprocalMaskedFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ApproximateReciprocalMaskedFloat32x8 x mask)
+	// result: (VRCP14PSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRCP14PSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpApproximateReciprocalMaskedFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ApproximateReciprocalMaskedFloat64x2 x mask)
+	// result: (VRCP14PDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRCP14PDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpApproximateReciprocalMaskedFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ApproximateReciprocalMaskedFloat64x4 x mask)
+	// result: (VRCP14PDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRCP14PDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpApproximateReciprocalMaskedFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ApproximateReciprocalMaskedFloat64x8 x mask)
+	// result: (VRCP14PDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRCP14PDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpApproximateReciprocalOfSqrtMaskedFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ApproximateReciprocalOfSqrtMaskedFloat32x16 x mask)
+	// result: (VRSQRT14PSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRSQRT14PSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpApproximateReciprocalOfSqrtMaskedFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ApproximateReciprocalOfSqrtMaskedFloat32x4 x mask)
+	// result: (VRSQRT14PSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRSQRT14PSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpApproximateReciprocalOfSqrtMaskedFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ApproximateReciprocalOfSqrtMaskedFloat32x8 x mask)
+	// result: (VRSQRT14PSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRSQRT14PSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpApproximateReciprocalOfSqrtMaskedFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ApproximateReciprocalOfSqrtMaskedFloat64x2 x mask)
+	// result: (VRSQRT14PDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRSQRT14PDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpApproximateReciprocalOfSqrtMaskedFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ApproximateReciprocalOfSqrtMaskedFloat64x4 x mask)
+	// result: (VRSQRT14PDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRSQRT14PDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpApproximateReciprocalOfSqrtMaskedFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ApproximateReciprocalOfSqrtMaskedFloat64x8 x mask)
+	// result: (VRSQRT14PDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRSQRT14PDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicAdd32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (AtomicAdd32 ptr val mem)
+	// result: (AddTupleFirst32 val (XADDLlock val ptr mem))
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpAMD64AddTupleFirst32)
+		v0 := b.NewValue0(v.Pos, OpAMD64XADDLlock, types.NewTuple(typ.UInt32, types.TypeMem))
+		v0.AddArg3(val, ptr, mem)
+		v.AddArg2(val, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicAdd64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (AtomicAdd64 ptr val mem)
+	// result: (AddTupleFirst64 val (XADDQlock val ptr mem))
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpAMD64AddTupleFirst64)
+		v0 := b.NewValue0(v.Pos, OpAMD64XADDQlock, types.NewTuple(typ.UInt64, types.TypeMem))
+		v0.AddArg3(val, ptr, mem)
+		v.AddArg2(val, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicAnd32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicAnd32 ptr val mem)
+	// result: (ANDLlock ptr val mem)
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpAMD64ANDLlock)
+		v.AddArg3(ptr, val, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicAnd32value(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicAnd32value ptr val mem)
+	// result: (LoweredAtomicAnd32 ptr val mem)
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpAMD64LoweredAtomicAnd32)
+		v.AddArg3(ptr, val, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicAnd64value(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicAnd64value ptr val mem)
+	// result: (LoweredAtomicAnd64 ptr val mem)
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpAMD64LoweredAtomicAnd64)
+		v.AddArg3(ptr, val, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicAnd8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicAnd8 ptr val mem)
+	// result: (ANDBlock ptr val mem)
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpAMD64ANDBlock)
+		v.AddArg3(ptr, val, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicCompareAndSwap32(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicCompareAndSwap32 ptr old new_ mem)
+	// result: (CMPXCHGLlock ptr old new_ mem)
+	for {
+		ptr := v_0
+		old := v_1
+		new_ := v_2
+		mem := v_3
+		v.reset(OpAMD64CMPXCHGLlock)
+		v.AddArg4(ptr, old, new_, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicCompareAndSwap64(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicCompareAndSwap64 ptr old new_ mem)
+	// result: (CMPXCHGQlock ptr old new_ mem)
+	for {
+		ptr := v_0
+		old := v_1
+		new_ := v_2
+		mem := v_3
+		v.reset(OpAMD64CMPXCHGQlock)
+		v.AddArg4(ptr, old, new_, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicExchange32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicExchange32 ptr val mem)
+	// result: (XCHGL val ptr mem)
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpAMD64XCHGL)
+		v.AddArg3(val, ptr, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicExchange64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicExchange64 ptr val mem)
+	// result: (XCHGQ val ptr mem)
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpAMD64XCHGQ)
+		v.AddArg3(val, ptr, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicExchange8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicExchange8 ptr val mem)
+	// result: (XCHGB val ptr mem)
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpAMD64XCHGB)
+		v.AddArg3(val, ptr, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicLoad32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicLoad32 ptr mem)
+	// result: (MOVLatomicload ptr mem)
+	for {
+		ptr := v_0
+		mem := v_1
+		v.reset(OpAMD64MOVLatomicload)
+		v.AddArg2(ptr, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicLoad64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicLoad64 ptr mem)
+	// result: (MOVQatomicload ptr mem)
+	for {
+		ptr := v_0
+		mem := v_1
+		v.reset(OpAMD64MOVQatomicload)
+		v.AddArg2(ptr, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicLoad8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicLoad8 ptr mem)
+	// result: (MOVBatomicload ptr mem)
+	for {
+		ptr := v_0
+		mem := v_1
+		v.reset(OpAMD64MOVBatomicload)
+		v.AddArg2(ptr, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicLoadPtr(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicLoadPtr ptr mem)
+	// result: (MOVQatomicload ptr mem)
+	for {
+		ptr := v_0
+		mem := v_1
+		v.reset(OpAMD64MOVQatomicload)
+		v.AddArg2(ptr, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicOr32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicOr32 ptr val mem)
+	// result: (ORLlock ptr val mem)
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpAMD64ORLlock)
+		v.AddArg3(ptr, val, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicOr32value(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicOr32value ptr val mem)
+	// result: (LoweredAtomicOr32 ptr val mem)
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpAMD64LoweredAtomicOr32)
+		v.AddArg3(ptr, val, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicOr64value(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicOr64value ptr val mem)
+	// result: (LoweredAtomicOr64 ptr val mem)
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpAMD64LoweredAtomicOr64)
+		v.AddArg3(ptr, val, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicOr8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (AtomicOr8 ptr val mem)
+	// result: (ORBlock ptr val mem)
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpAMD64ORBlock)
+		v.AddArg3(ptr, val, mem)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicStore32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (AtomicStore32 ptr val mem)
+	// result: (Select1 (XCHGL <types.NewTuple(typ.UInt32,types.TypeMem)> val ptr mem))
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpSelect1)
+		v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem))
+		v0.AddArg3(val, ptr, mem)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicStore64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (AtomicStore64 ptr val mem)
+	// result: (Select1 (XCHGQ <types.NewTuple(typ.UInt64,types.TypeMem)> val ptr mem))
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpSelect1)
+		v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem))
+		v0.AddArg3(val, ptr, mem)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicStore8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (AtomicStore8 ptr val mem)
+	// result: (Select1 (XCHGB <types.NewTuple(typ.UInt8,types.TypeMem)> val ptr mem))
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpSelect1)
+		v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem))
+		v0.AddArg3(val, ptr, mem)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAtomicStorePtrNoWB(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (AtomicStorePtrNoWB ptr val mem)
+	// result: (Select1 (XCHGQ <types.NewTuple(typ.BytePtr,types.TypeMem)> val ptr mem))
+	for {
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		v.reset(OpSelect1)
+		v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem))
+		v0.AddArg3(val, ptr, mem)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAverageMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AverageMaskedUint16x16 x y mask)
+	// result: (VPAVGWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPAVGWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAverageMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AverageMaskedUint16x32 x y mask)
+	// result: (VPAVGWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPAVGWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAverageMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AverageMaskedUint16x8 x y mask)
+	// result: (VPAVGWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPAVGWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAverageMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AverageMaskedUint8x16 x y mask)
+	// result: (VPAVGBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPAVGBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAverageMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AverageMaskedUint8x32 x y mask)
+	// result: (VPAVGBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPAVGBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpAverageMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (AverageMaskedUint8x64 x y mask)
+	// result: (VPAVGBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPAVGBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpBitLen16(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (BitLen16 x)
+	// cond: buildcfg.GOAMD64 < 3
+	// result: (BSRL (LEAL1 <typ.UInt32> [1] (MOVWQZX <typ.UInt32> x) (MOVWQZX <typ.UInt32> x)))
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 < 3) {
+			break
+		}
+		v.reset(OpAMD64BSRL)
+		v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32)
+		v0.AuxInt = int32ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32)
+		v1.AddArg(x)
+		v0.AddArg2(v1, v1)
+		v.AddArg(v0)
+		return true
+	}
+	// match: (BitLen16 <t> x)
+	// cond: buildcfg.GOAMD64 >= 3
+	// result: (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVWQZX <x.Type> x))))
+	for {
+		t := v.Type
+		x := v_0
+		if !(buildcfg.GOAMD64 >= 3) {
+			break
+		}
+		v.reset(OpAMD64NEGQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t)
+		v0.AuxInt = int32ToAuxInt(-32)
+		v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, x.Type)
+		v2.AddArg(x)
+		v1.AddArg(v2)
+		v0.AddArg(v1)
+		v.AddArg(v0)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpBitLen32(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (BitLen32 x)
+	// cond: buildcfg.GOAMD64 < 3
+	// result: (Select0 (BSRQ (LEAQ1 <typ.UInt64> [1] (MOVLQZX <typ.UInt64> x) (MOVLQZX <typ.UInt64> x))))
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 < 3) {
+			break
+		}
+		v.reset(OpSelect0)
+		v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags))
+		v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64)
+		v1.AuxInt = int32ToAuxInt(1)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64)
+		v2.AddArg(x)
+		v1.AddArg2(v2, v2)
+		v0.AddArg(v1)
+		v.AddArg(v0)
+		return true
+	}
+	// match: (BitLen32 <t> x)
+	// cond: buildcfg.GOAMD64 >= 3
+	// result: (NEGQ (ADDQconst <t> [-32] (LZCNTL x)))
+	for {
+		t := v.Type
+		x := v_0
+		if !(buildcfg.GOAMD64 >= 3) {
+			break
+		}
+		v.reset(OpAMD64NEGQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t)
+		v0.AuxInt = int32ToAuxInt(-32)
+		v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32)
+		v1.AddArg(x)
+		v0.AddArg(v1)
+		v.AddArg(v0)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpBitLen64(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (BitLen64 <t> x)
+	// cond: buildcfg.GOAMD64 < 3
+	// result: (ADDQconst [1] (CMOVQEQ <t> (Select0 <t> (BSRQ x)) (MOVQconst <t> [-1]) (Select1 <types.TypeFlags> (BSRQ x))))
+	for {
+		t := v.Type
+		x := v_0
+		if !(buildcfg.GOAMD64 < 3) {
+			break
+		}
+		v.reset(OpAMD64ADDQconst)
+		v.AuxInt = int32ToAuxInt(1)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t)
+		v1 := b.NewValue0(v.Pos, OpSelect0, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags))
+		v2.AddArg(x)
+		v1.AddArg(v2)
+		v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t)
+		v3.AuxInt = int64ToAuxInt(-1)
+		v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
+		v4.AddArg(v2)
+		v0.AddArg3(v1, v3, v4)
+		v.AddArg(v0)
+		return true
+	}
+	// match: (BitLen64 <t> x)
+	// cond: buildcfg.GOAMD64 >= 3
+	// result: (NEGQ (ADDQconst <t> [-64] (LZCNTQ x)))
+	for {
+		t := v.Type
+		x := v_0
+		if !(buildcfg.GOAMD64 >= 3) {
+			break
+		}
+		v.reset(OpAMD64NEGQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t)
+		v0.AuxInt = int32ToAuxInt(-64)
+		v1 := b.NewValue0(v.Pos, OpAMD64LZCNTQ, typ.UInt64)
+		v1.AddArg(x)
+		v0.AddArg(v1)
+		v.AddArg(v0)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpBitLen8(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (BitLen8 x)
+	// cond: buildcfg.GOAMD64 < 3
+	// result: (BSRL (LEAL1 <typ.UInt32> [1] (MOVBQZX <typ.UInt32> x) (MOVBQZX <typ.UInt32> x)))
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 < 3) {
+			break
+		}
+		v.reset(OpAMD64BSRL)
+		v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32)
+		v0.AuxInt = int32ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32)
+		v1.AddArg(x)
+		v0.AddArg2(v1, v1)
+		v.AddArg(v0)
+		return true
+	}
+	// match: (BitLen8 <t> x)
+	// cond: buildcfg.GOAMD64 >= 3
+	// result: (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVBQZX <x.Type> x))))
+	for {
+		t := v.Type
+		x := v_0
+		if !(buildcfg.GOAMD64 >= 3) {
+			break
+		}
+		v.reset(OpAMD64NEGQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t)
+		v0.AuxInt = int32ToAuxInt(-32)
+		v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, x.Type)
+		v2.AddArg(x)
+		v1.AddArg(v2)
+		v0.AddArg(v1)
+		v.AddArg(v0)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpBswap16(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (Bswap16 x)
+	// result: (ROLWconst [8] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64ROLWconst)
+		v.AuxInt = int8ToAuxInt(8)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeil(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (Ceil x)
+	// result: (ROUNDSD [2] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64ROUNDSD)
+		v.AuxInt = int8ToAuxInt(2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilFloat32x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (CeilFloat32x4 x)
+	// result: (VROUNDPS128 [2] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64VROUNDPS128)
+		v.AuxInt = int8ToAuxInt(2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilFloat32x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (CeilFloat32x8 x)
+	// result: (VROUNDPS256 [2] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64VROUNDPS256)
+		v.AuxInt = int8ToAuxInt(2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilFloat64x2(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (CeilFloat64x2 x)
+	// result: (VROUNDPD128 [2] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64VROUNDPD128)
+		v.AuxInt = int8ToAuxInt(2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilFloat64x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (CeilFloat64x4 x)
+	// result: (VROUNDPD256 [2] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64VROUNDPD256)
+		v.AuxInt = int8ToAuxInt(2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilWithPrecisionFloat32x16(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (CeilWithPrecisionFloat32x16 [a] x)
+	// result: (VRNDSCALEPS512 [a+2] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPS512)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilWithPrecisionFloat32x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (CeilWithPrecisionFloat32x4 [a] x)
+	// result: (VRNDSCALEPS128 [a+2] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPS128)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilWithPrecisionFloat32x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (CeilWithPrecisionFloat32x8 [a] x)
+	// result: (VRNDSCALEPS256 [a+2] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPS256)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilWithPrecisionFloat64x2(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (CeilWithPrecisionFloat64x2 [a] x)
+	// result: (VRNDSCALEPD128 [a+2] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPD128)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilWithPrecisionFloat64x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (CeilWithPrecisionFloat64x4 [a] x)
+	// result: (VRNDSCALEPD256 [a+2] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPD256)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilWithPrecisionFloat64x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (CeilWithPrecisionFloat64x8 [a] x)
+	// result: (VRNDSCALEPD512 [a+2] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPD512)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilWithPrecisionMaskedFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CeilWithPrecisionMaskedFloat32x16 [a] x mask)
+	// result: (VRNDSCALEPSMasked512 [a+2] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPSMasked512)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilWithPrecisionMaskedFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CeilWithPrecisionMaskedFloat32x4 [a] x mask)
+	// result: (VRNDSCALEPSMasked128 [a+2] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPSMasked128)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilWithPrecisionMaskedFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CeilWithPrecisionMaskedFloat32x8 [a] x mask)
+	// result: (VRNDSCALEPSMasked256 [a+2] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPSMasked256)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilWithPrecisionMaskedFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CeilWithPrecisionMaskedFloat64x2 [a] x mask)
+	// result: (VRNDSCALEPDMasked128 [a+2] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPDMasked128)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilWithPrecisionMaskedFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CeilWithPrecisionMaskedFloat64x4 [a] x mask)
+	// result: (VRNDSCALEPDMasked256 [a+2] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPDMasked256)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCeilWithPrecisionMaskedFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CeilWithPrecisionMaskedFloat64x8 [a] x mask)
+	// result: (VRNDSCALEPDMasked512 [a+2] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPDMasked512)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressFloat32x16 x mask)
+	// result: (VCOMPRESSPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VCOMPRESSPSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressFloat32x4 x mask)
+	// result: (VCOMPRESSPSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VCOMPRESSPSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressFloat32x8 x mask)
+	// result: (VCOMPRESSPSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VCOMPRESSPSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressFloat64x2 x mask)
+	// result: (VCOMPRESSPDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VCOMPRESSPDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressFloat64x4 x mask)
+	// result: (VCOMPRESSPDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VCOMPRESSPDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressFloat64x8 x mask)
+	// result: (VCOMPRESSPDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VCOMPRESSPDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressInt16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressInt16x16 x mask)
+	// result: (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressInt16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressInt16x32 x mask)
+	// result: (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressInt16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressInt16x8 x mask)
+	// result: (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressInt32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressInt32x16 x mask)
+	// result: (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressInt32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressInt32x4 x mask)
+	// result: (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressInt32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressInt32x8 x mask)
+	// result: (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressInt64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressInt64x2 x mask)
+	// result: (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressInt64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressInt64x4 x mask)
+	// result: (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressInt64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressInt64x8 x mask)
+	// result: (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressInt8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressInt8x16 x mask)
+	// result: (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressInt8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressInt8x32 x mask)
+	// result: (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressInt8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressInt8x64 x mask)
+	// result: (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressUint16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressUint16x16 x mask)
+	// result: (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressUint16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressUint16x32 x mask)
+	// result: (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressUint16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressUint16x8 x mask)
+	// result: (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressUint32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressUint32x16 x mask)
+	// result: (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressUint32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressUint32x4 x mask)
+	// result: (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressUint32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressUint32x8 x mask)
+	// result: (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressUint64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressUint64x2 x mask)
+	// result: (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressUint64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressUint64x4 x mask)
+	// result: (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressUint64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressUint64x8 x mask)
+	// result: (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressUint8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressUint8x16 x mask)
+	// result: (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressUint8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressUint8x32 x mask)
+	// result: (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCompressUint8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (CompressUint8x64 x mask)
+	// result: (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPCOMPRESSBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCondSelect(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (CondSelect <t> x y (SETEQ cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQEQ y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETEQ {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQEQ)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETNE cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQNE y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETNE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQNE)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETL cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQLT y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETL {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQLT)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETG cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQGT y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETG {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQGT)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETLE cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQLE y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETLE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQLE)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETGE cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQGE y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETGE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQGE)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETA cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQHI y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETA {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQHI)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETB cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQCS y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETB {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQCS)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETAE cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQCC y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETAE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQCC)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETBE cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQLS y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETBE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQLS)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETEQF cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQEQF y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETEQF {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQEQF)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETNEF cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQNEF y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETNEF {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQNEF)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETGF cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQGTF y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETGF {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQGTF)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETGEF cond))
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQGEF y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETGEF {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVQGEF)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETEQ cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLEQ y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETEQ {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLEQ)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETNE cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLNE y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETNE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLNE)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETL cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLLT y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETL {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLLT)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETG cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLGT y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETG {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLGT)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETLE cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLLE y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETLE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLLE)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETGE cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLGE y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETGE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLGE)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETA cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLHI y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETA {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLHI)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETB cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLCS y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETB {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLCS)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETAE cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLCC y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETAE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLCC)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETBE cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLLS y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETBE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLLS)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETEQF cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLEQF y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETEQF {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLEQF)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETNEF cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLNEF y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETNEF {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLNEF)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETGF cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLGTF y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETGF {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLGTF)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETGEF cond))
+	// cond: is32BitInt(t)
+	// result: (CMOVLGEF y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETGEF {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLGEF)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETEQ cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWEQ y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETEQ {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWEQ)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETNE cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWNE y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETNE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWNE)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETL cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWLT y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETL {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWLT)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETG cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWGT y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETG {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWGT)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETLE cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWLE y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETLE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWLE)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETGE cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWGE y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETGE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWGE)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETA cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWHI y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETA {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWHI)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETB cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWCS y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETB {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWCS)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETAE cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWCC y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETAE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWCC)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETBE cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWLS y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETBE {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWLS)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETEQF cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWEQF y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETEQF {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWEQF)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETNEF cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWNEF y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETNEF {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWNEF)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETGF cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWGTF y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETGF {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWGTF)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y (SETGEF cond))
+	// cond: is16BitInt(t)
+	// result: (CMOVWGEF y x cond)
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if v_2.Op != OpAMD64SETGEF {
+			break
+		}
+		cond := v_2.Args[0]
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWGEF)
+		v.AddArg3(y, x, cond)
+		return true
+	}
+	// match: (CondSelect <t> x y check)
+	// cond: !check.Type.IsFlags() && check.Type.Size() == 1
+	// result: (CondSelect <t> x y (MOVBQZX <typ.UInt64> check))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		check := v_2
+		if !(!check.Type.IsFlags() && check.Type.Size() == 1) {
+			break
+		}
+		v.reset(OpCondSelect)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64)
+		v0.AddArg(check)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+	// match: (CondSelect <t> x y check)
+	// cond: !check.Type.IsFlags() && check.Type.Size() == 2
+	// result: (CondSelect <t> x y (MOVWQZX <typ.UInt64> check))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		check := v_2
+		if !(!check.Type.IsFlags() && check.Type.Size() == 2) {
+			break
+		}
+		v.reset(OpCondSelect)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64)
+		v0.AddArg(check)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+	// match: (CondSelect <t> x y check)
+	// cond: !check.Type.IsFlags() && check.Type.Size() == 4
+	// result: (CondSelect <t> x y (MOVLQZX <typ.UInt64> check))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		check := v_2
+		if !(!check.Type.IsFlags() && check.Type.Size() == 4) {
+			break
+		}
+		v.reset(OpCondSelect)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64)
+		v0.AddArg(check)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+	// match: (CondSelect <t> x y check)
+	// cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))
+	// result: (CMOVQNE y x (CMPQconst [0] check))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		check := v_2
+		if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) {
+			break
+		}
+		v.reset(OpAMD64CMOVQNE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v0.AuxInt = int32ToAuxInt(0)
+		v0.AddArg(check)
+		v.AddArg3(y, x, v0)
+		return true
+	}
+	// match: (CondSelect <t> x y check)
+	// cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)
+	// result: (CMOVLNE y x (CMPQconst [0] check))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		check := v_2
+		if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVLNE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v0.AuxInt = int32ToAuxInt(0)
+		v0.AddArg(check)
+		v.AddArg3(y, x, v0)
+		return true
+	}
+	// match: (CondSelect <t> x y check)
+	// cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)
+	// result: (CMOVWNE y x (CMPQconst [0] check))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		check := v_2
+		if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64CMOVWNE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v0.AuxInt = int32ToAuxInt(0)
+		v0.AddArg(check)
+		v.AddArg3(y, x, v0)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpConst16(v *Value) bool {
+	// match: (Const16 [c])
+	// result: (MOVLconst [int32(c)])
+	for {
+		c := auxIntToInt16(v.AuxInt)
+		v.reset(OpAMD64MOVLconst)
+		v.AuxInt = int32ToAuxInt(int32(c))
+		return true
+	}
+}
+func rewriteValueAMD64_OpConst8(v *Value) bool {
+	// match: (Const8 [c])
+	// result: (MOVLconst [int32(c)])
+	for {
+		c := auxIntToInt8(v.AuxInt)
+		v.reset(OpAMD64MOVLconst)
+		v.AuxInt = int32ToAuxInt(int32(c))
+		return true
+	}
+}
+func rewriteValueAMD64_OpConstBool(v *Value) bool {
+	// match: (ConstBool [c])
+	// result: (MOVLconst [b2i32(c)])
+	for {
+		c := auxIntToBool(v.AuxInt)
+		v.reset(OpAMD64MOVLconst)
+		v.AuxInt = int32ToAuxInt(b2i32(c))
+		return true
+	}
+}
+func rewriteValueAMD64_OpConstNil(v *Value) bool {
+	// match: (ConstNil )
+	// result: (MOVQconst [0])
+	for {
+		v.reset(OpAMD64MOVQconst)
+		v.AuxInt = int64ToAuxInt(0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCtz16(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Ctz16 x)
+	// result: (BSFL (ORLconst <typ.UInt32> [1<<16] x))
+	for {
+		x := v_0
+		v.reset(OpAMD64BSFL)
+		v0 := b.NewValue0(v.Pos, OpAMD64ORLconst, typ.UInt32)
+		v0.AuxInt = int32ToAuxInt(1 << 16)
+		v0.AddArg(x)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCtz16NonZero(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (Ctz16NonZero x)
+	// cond: buildcfg.GOAMD64 >= 3
+	// result: (TZCNTL x)
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 >= 3) {
+			break
+		}
+		v.reset(OpAMD64TZCNTL)
+		v.AddArg(x)
+		return true
+	}
+	// match: (Ctz16NonZero x)
+	// cond: buildcfg.GOAMD64 < 3
+	// result: (BSFL x)
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 < 3) {
+			break
+		}
+		v.reset(OpAMD64BSFL)
+		v.AddArg(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpCtz32(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Ctz32 x)
+	// cond: buildcfg.GOAMD64 >= 3
+	// result: (TZCNTL x)
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 >= 3) {
+			break
+		}
+		v.reset(OpAMD64TZCNTL)
+		v.AddArg(x)
+		return true
+	}
+	// match: (Ctz32 x)
+	// cond: buildcfg.GOAMD64 < 3
+	// result: (Select0 (BSFQ (BTSQconst <typ.UInt64> [32] x)))
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 < 3) {
+			break
+		}
+		v.reset(OpSelect0)
+		v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
+		v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64)
+		v1.AuxInt = int8ToAuxInt(32)
+		v1.AddArg(x)
+		v0.AddArg(v1)
+		v.AddArg(v0)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpCtz32NonZero(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (Ctz32NonZero x)
+	// cond: buildcfg.GOAMD64 >= 3
+	// result: (TZCNTL x)
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 >= 3) {
+			break
+		}
+		v.reset(OpAMD64TZCNTL)
+		v.AddArg(x)
+		return true
+	}
+	// match: (Ctz32NonZero x)
+	// cond: buildcfg.GOAMD64 < 3
+	// result: (BSFL x)
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 < 3) {
+			break
+		}
+		v.reset(OpAMD64BSFL)
+		v.AddArg(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpCtz64(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Ctz64 x)
+	// cond: buildcfg.GOAMD64 >= 3
+	// result: (TZCNTQ x)
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 >= 3) {
+			break
+		}
+		v.reset(OpAMD64TZCNTQ)
+		v.AddArg(x)
+		return true
+	}
+	// match: (Ctz64 <t> x)
+	// cond: buildcfg.GOAMD64 < 3
+	// result: (CMOVQEQ (Select0 <t> (BSFQ x)) (MOVQconst <t> [64]) (Select1 <types.TypeFlags> (BSFQ x)))
+	for {
+		t := v.Type
+		x := v_0
+		if !(buildcfg.GOAMD64 < 3) {
+			break
+		}
+		v.reset(OpAMD64CMOVQEQ)
+		v0 := b.NewValue0(v.Pos, OpSelect0, t)
+		v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
+		v1.AddArg(x)
+		v0.AddArg(v1)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t)
+		v2.AuxInt = int64ToAuxInt(64)
+		v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
+		v3.AddArg(v1)
+		v.AddArg3(v0, v2, v3)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpCtz64NonZero(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Ctz64NonZero x)
+	// cond: buildcfg.GOAMD64 >= 3
+	// result: (TZCNTQ x)
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 >= 3) {
+			break
+		}
+		v.reset(OpAMD64TZCNTQ)
+		v.AddArg(x)
+		return true
+	}
+	// match: (Ctz64NonZero x)
+	// cond: buildcfg.GOAMD64 < 3
+	// result: (Select0 (BSFQ x))
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 < 3) {
+			break
+		}
+		v.reset(OpSelect0)
+		v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
+		v0.AddArg(x)
+		v.AddArg(v0)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpCtz8(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Ctz8 x)
+	// result: (BSFL (ORLconst <typ.UInt32> [1<<8 ] x))
+	for {
+		x := v_0
+		v.reset(OpAMD64BSFL)
+		v0 := b.NewValue0(v.Pos, OpAMD64ORLconst, typ.UInt32)
+		v0.AuxInt = int32ToAuxInt(1 << 8)
+		v0.AddArg(x)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (Ctz8NonZero x)
+	// cond: buildcfg.GOAMD64 >= 3
+	// result: (TZCNTL x)
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 >= 3) {
+			break
+		}
+		v.reset(OpAMD64TZCNTL)
+		v.AddArg(x)
+		return true
+	}
+	// match: (Ctz8NonZero x)
+	// cond: buildcfg.GOAMD64 < 3
+	// result: (BSFL x)
+	for {
+		x := v_0
+		if !(buildcfg.GOAMD64 < 3) {
+			break
+		}
+		v.reset(OpAMD64BSFL)
+		v.AddArg(x)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat32x16(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithCeilWithPrecisionFloat32x16 [a] x)
+	// result: (VREDUCEPS512 [a+2] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPS512)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat32x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithCeilWithPrecisionFloat32x4 [a] x)
+	// result: (VREDUCEPS128 [a+2] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPS128)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat32x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithCeilWithPrecisionFloat32x8 [a] x)
+	// result: (VREDUCEPS256 [a+2] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPS256)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat64x2(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithCeilWithPrecisionFloat64x2 [a] x)
+	// result: (VREDUCEPD128 [a+2] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPD128)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat64x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithCeilWithPrecisionFloat64x4 [a] x)
+	// result: (VREDUCEPD256 [a+2] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPD256)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat64x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithCeilWithPrecisionFloat64x8 [a] x)
+	// result: (VREDUCEPD512 [a+2] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPD512)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithCeilWithPrecisionMaskedFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithCeilWithPrecisionMaskedFloat32x16 [a] x mask)
+	// result: (VREDUCEPSMasked512 [a+2] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPSMasked512)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithCeilWithPrecisionMaskedFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithCeilWithPrecisionMaskedFloat32x4 [a] x mask)
+	// result: (VREDUCEPSMasked128 [a+2] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPSMasked128)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithCeilWithPrecisionMaskedFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithCeilWithPrecisionMaskedFloat32x8 [a] x mask)
+	// result: (VREDUCEPSMasked256 [a+2] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPSMasked256)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithCeilWithPrecisionMaskedFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithCeilWithPrecisionMaskedFloat64x2 [a] x mask)
+	// result: (VREDUCEPDMasked128 [a+2] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPDMasked128)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithCeilWithPrecisionMaskedFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithCeilWithPrecisionMaskedFloat64x4 [a] x mask)
+	// result: (VREDUCEPDMasked256 [a+2] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPDMasked256)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithCeilWithPrecisionMaskedFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithCeilWithPrecisionMaskedFloat64x8 [a] x mask)
+	// result: (VREDUCEPDMasked512 [a+2] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPDMasked512)
+		v.AuxInt = int8ToAuxInt(a + 2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat32x16(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithFloorWithPrecisionFloat32x16 [a] x)
+	// result: (VREDUCEPS512 [a+1] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPS512)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat32x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithFloorWithPrecisionFloat32x4 [a] x)
+	// result: (VREDUCEPS128 [a+1] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPS128)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat32x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithFloorWithPrecisionFloat32x8 [a] x)
+	// result: (VREDUCEPS256 [a+1] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPS256)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat64x2(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithFloorWithPrecisionFloat64x2 [a] x)
+	// result: (VREDUCEPD128 [a+1] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPD128)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat64x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithFloorWithPrecisionFloat64x4 [a] x)
+	// result: (VREDUCEPD256 [a+1] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPD256)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat64x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithFloorWithPrecisionFloat64x8 [a] x)
+	// result: (VREDUCEPD512 [a+1] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPD512)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithFloorWithPrecisionMaskedFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithFloorWithPrecisionMaskedFloat32x16 [a] x mask)
+	// result: (VREDUCEPSMasked512 [a+1] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPSMasked512)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithFloorWithPrecisionMaskedFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithFloorWithPrecisionMaskedFloat32x4 [a] x mask)
+	// result: (VREDUCEPSMasked128 [a+1] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPSMasked128)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithFloorWithPrecisionMaskedFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithFloorWithPrecisionMaskedFloat32x8 [a] x mask)
+	// result: (VREDUCEPSMasked256 [a+1] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPSMasked256)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithFloorWithPrecisionMaskedFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithFloorWithPrecisionMaskedFloat64x2 [a] x mask)
+	// result: (VREDUCEPDMasked128 [a+1] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPDMasked128)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithFloorWithPrecisionMaskedFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithFloorWithPrecisionMaskedFloat64x4 [a] x mask)
+	// result: (VREDUCEPDMasked256 [a+1] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPDMasked256)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithFloorWithPrecisionMaskedFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithFloorWithPrecisionMaskedFloat64x8 [a] x mask)
+	// result: (VREDUCEPDMasked512 [a+1] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPDMasked512)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat32x16(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithRoundWithPrecisionFloat32x16 [a] x)
+	// result: (VREDUCEPS512 [a+0] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPS512)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat32x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithRoundWithPrecisionFloat32x4 [a] x)
+	// result: (VREDUCEPS128 [a+0] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPS128)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat32x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithRoundWithPrecisionFloat32x8 [a] x)
+	// result: (VREDUCEPS256 [a+0] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPS256)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat64x2(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithRoundWithPrecisionFloat64x2 [a] x)
+	// result: (VREDUCEPD128 [a+0] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPD128)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat64x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithRoundWithPrecisionFloat64x4 [a] x)
+	// result: (VREDUCEPD256 [a+0] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPD256)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat64x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithRoundWithPrecisionFloat64x8 [a] x)
+	// result: (VREDUCEPD512 [a+0] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPD512)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithRoundWithPrecisionMaskedFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithRoundWithPrecisionMaskedFloat32x16 [a] x mask)
+	// result: (VREDUCEPSMasked512 [a+0] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPSMasked512)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithRoundWithPrecisionMaskedFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithRoundWithPrecisionMaskedFloat32x4 [a] x mask)
+	// result: (VREDUCEPSMasked128 [a+0] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPSMasked128)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithRoundWithPrecisionMaskedFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithRoundWithPrecisionMaskedFloat32x8 [a] x mask)
+	// result: (VREDUCEPSMasked256 [a+0] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPSMasked256)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithRoundWithPrecisionMaskedFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithRoundWithPrecisionMaskedFloat64x2 [a] x mask)
+	// result: (VREDUCEPDMasked128 [a+0] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPDMasked128)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithRoundWithPrecisionMaskedFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithRoundWithPrecisionMaskedFloat64x4 [a] x mask)
+	// result: (VREDUCEPDMasked256 [a+0] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPDMasked256)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithRoundWithPrecisionMaskedFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithRoundWithPrecisionMaskedFloat64x8 [a] x mask)
+	// result: (VREDUCEPDMasked512 [a+0] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPDMasked512)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat32x16(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithTruncWithPrecisionFloat32x16 [a] x)
+	// result: (VREDUCEPS512 [a+3] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPS512)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat32x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithTruncWithPrecisionFloat32x4 [a] x)
+	// result: (VREDUCEPS128 [a+3] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPS128)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat32x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithTruncWithPrecisionFloat32x8 [a] x)
+	// result: (VREDUCEPS256 [a+3] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPS256)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat64x2(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithTruncWithPrecisionFloat64x2 [a] x)
+	// result: (VREDUCEPD128 [a+3] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPD128)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat64x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithTruncWithPrecisionFloat64x4 [a] x)
+	// result: (VREDUCEPD256 [a+3] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPD256)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat64x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (DiffWithTruncWithPrecisionFloat64x8 [a] x)
+	// result: (VREDUCEPD512 [a+3] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VREDUCEPD512)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithTruncWithPrecisionMaskedFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithTruncWithPrecisionMaskedFloat32x16 [a] x mask)
+	// result: (VREDUCEPSMasked512 [a+3] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPSMasked512)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithTruncWithPrecisionMaskedFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithTruncWithPrecisionMaskedFloat32x4 [a] x mask)
+	// result: (VREDUCEPSMasked128 [a+3] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPSMasked128)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithTruncWithPrecisionMaskedFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithTruncWithPrecisionMaskedFloat32x8 [a] x mask)
+	// result: (VREDUCEPSMasked256 [a+3] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPSMasked256)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithTruncWithPrecisionMaskedFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithTruncWithPrecisionMaskedFloat64x2 [a] x mask)
+	// result: (VREDUCEPDMasked128 [a+3] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPDMasked128)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithTruncWithPrecisionMaskedFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithTruncWithPrecisionMaskedFloat64x4 [a] x mask)
+	// result: (VREDUCEPDMasked256 [a+3] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPDMasked256)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiffWithTruncWithPrecisionMaskedFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DiffWithTruncWithPrecisionMaskedFloat64x8 [a] x mask)
+	// result: (VREDUCEPDMasked512 [a+3] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VREDUCEPDMasked512)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiv16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Div16 [a] x y)
+	// result: (Select0 (DIVW [a] x y))
+	for {
+		a := auxIntToBool(v.AuxInt)
+		x := v_0
+		y := v_1
+		v.reset(OpSelect0)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
+		v0.AuxInt = boolToAuxInt(a)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiv16u(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Div16u x y)
+	// result: (Select0 (DIVWU x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpSelect0)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiv32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Div32 [a] x y)
+	// result: (Select0 (DIVL [a] x y))
+	for {
+		a := auxIntToBool(v.AuxInt)
+		x := v_0
+		y := v_1
+		v.reset(OpSelect0)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32))
+		v0.AuxInt = boolToAuxInt(a)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiv32u(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Div32u x y)
+	// result: (Select0 (DIVLU x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpSelect0)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32))
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiv64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Div64 [a] x y)
+	// result: (Select0 (DIVQ [a] x y))
+	for {
+		a := auxIntToBool(v.AuxInt)
+		x := v_0
+		y := v_1
+		v.reset(OpSelect0)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64))
+		v0.AuxInt = boolToAuxInt(a)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiv64u(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Div64u x y)
+	// result: (Select0 (DIVQU x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpSelect0)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64))
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiv8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Div8 x y)
+	// result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpSelect0)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
+		v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
+		v1.AddArg(x)
+		v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
+		v2.AddArg(y)
+		v0.AddArg2(v1, v2)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDiv8u(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Div8u x y)
+	// result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpSelect0)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
+		v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
+		v1.AddArg(x)
+		v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
+		v2.AddArg(y)
+		v0.AddArg2(v1, v2)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDivMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DivMaskedFloat32x16 x y mask)
+	// result: (VDIVPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VDIVPSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDivMaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DivMaskedFloat32x4 x y mask)
+	// result: (VDIVPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VDIVPSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDivMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DivMaskedFloat32x8 x y mask)
+	// result: (VDIVPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VDIVPSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDivMaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DivMaskedFloat64x2 x y mask)
+	// result: (VDIVPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VDIVPDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDivMaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DivMaskedFloat64x4 x y mask)
+	// result: (VDIVPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VDIVPDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDivMaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (DivMaskedFloat64x8 x y mask)
+	// result: (VDIVPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VDIVPDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDotProdBroadcastFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (DotProdBroadcastFloat32x4 x y)
+	// result: (VDPPS128 [127] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VDPPS128)
+		v.AuxInt = int8ToAuxInt(127)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDotProdBroadcastFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (DotProdBroadcastFloat32x8 x y)
+	// result: (VDPPS256 [127] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VDPPS256)
+		v.AuxInt = int8ToAuxInt(127)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpDotProdBroadcastFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (DotProdBroadcastFloat64x2 x y)
+	// result: (VDPPD128 [127] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VDPPD128)
+		v.AuxInt = int8ToAuxInt(127)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEq16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Eq16 x y)
+	// result: (SETEQ (CMPW x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETEQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEq32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Eq32 x y)
+	// result: (SETEQ (CMPL x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETEQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEq32F(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Eq32F x y)
+	// result: (SETEQF (UCOMISS x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETEQF)
+		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEq64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Eq64 x y)
+	// result: (SETEQ (CMPQ x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETEQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEq64F(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Eq64F x y)
+	// result: (SETEQF (UCOMISD x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETEQF)
+		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEq8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Eq8 x y)
+	// result: (SETEQ (CMPB x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETEQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqB(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (EqB x y)
+	// result: (SETEQ (CMPB x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETEQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqPtr(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (EqPtr x y)
+	// result: (SETEQ (CMPQ x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETEQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualFloat32x16 x y)
+	// result: (VPMOVMToVec32x16 (VCMPPS512 [0] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (EqualFloat32x4 x y)
+	// result: (VCMPPS128 [0] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS128)
+		v.AuxInt = int8ToAuxInt(0)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (EqualFloat32x8 x y)
+	// result: (VCMPPS256 [0] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS256)
+		v.AuxInt = int8ToAuxInt(0)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (EqualFloat64x2 x y)
+	// result: (VCMPPD128 [0] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD128)
+		v.AuxInt = int8ToAuxInt(0)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (EqualFloat64x4 x y)
+	// result: (VCMPPD256 [0] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD256)
+		v.AuxInt = int8ToAuxInt(0)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualFloat64x8 x y)
+	// result: (VPMOVMToVec64x8 (VCMPPD512 [0] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualInt16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualInt16x32 x y)
+	// result: (VPMOVMToVec16x32 (VPCMPW512 [0] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualInt32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualInt32x16 x y)
+	// result: (VPMOVMToVec32x16 (VPCMPD512 [0] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualInt64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualInt64x8 x y)
+	// result: (VPMOVMToVec64x8 (VPCMPQ512 [0] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualInt8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualInt8x64 x y)
+	// result: (VPMOVMToVec8x64 (VPCMPB512 [0] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedFloat32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VCMPPSMasked512 [0] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedFloat32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VCMPPSMasked128 [0] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedFloat32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VCMPPSMasked256 [0] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedFloat64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VCMPPDMasked128 [0] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedFloat64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VCMPPDMasked256 [0] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedFloat64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VCMPPDMasked512 [0] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedInt16x16 x y mask)
+	// result: (VPMOVMToVec16x16 (VPCMPWMasked256 [0] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedInt16x32 x y mask)
+	// result: (VPMOVMToVec16x32 (VPCMPWMasked512 [0] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedInt16x8 x y mask)
+	// result: (VPMOVMToVec16x8 (VPCMPWMasked128 [0] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedInt32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VPCMPDMasked512 [0] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedInt32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VPCMPDMasked128 [0] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedInt32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VPCMPDMasked256 [0] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedInt64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VPCMPQMasked128 [0] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedInt64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VPCMPQMasked256 [0] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedInt64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VPCMPQMasked512 [0] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedInt8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedInt8x16 x y mask)
+	// result: (VPMOVMToVec8x16 (VPCMPBMasked128 [0] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedInt8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedInt8x32 x y mask)
+	// result: (VPMOVMToVec8x32 (VPCMPBMasked256 [0] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedInt8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedInt8x64 x y mask)
+	// result: (VPMOVMToVec8x64 (VPCMPBMasked512 [0] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedUint16x16 x y mask)
+	// result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [0] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedUint16x32 x y mask)
+	// result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [0] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedUint16x8 x y mask)
+	// result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [0] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedUint32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [0] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedUint32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [0] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedUint32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [0] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedUint64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [0] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedUint64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [0] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedUint64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [0] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedUint8x16 x y mask)
+	// result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [0] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedUint8x32 x y mask)
+	// result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [0] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualMaskedUint8x64 x y mask)
+	// result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [0] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualUint16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualUint16x32 x y)
+	// result: (VPMOVMToVec16x32 (VPCMPUW512 [0] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualUint32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualUint32x16 x y)
+	// result: (VPMOVMToVec32x16 (VPCMPUD512 [0] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualUint64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualUint64x8 x y)
+	// result: (VPMOVMToVec64x8 (VPCMPUQ512 [0] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpEqualUint8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (EqualUint8x64 x y)
+	// result: (VPMOVMToVec8x64 (VPCMPUB512 [0] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(0)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFMA(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (FMA x y z)
+	// result: (VFMADD231SD z x y)
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		v.reset(OpAMD64VFMADD231SD)
+		v.AddArg3(z, x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloor(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (Floor x)
+	// result: (ROUNDSD [1] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64ROUNDSD)
+		v.AuxInt = int8ToAuxInt(1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorFloat32x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (FloorFloat32x4 x)
+	// result: (VROUNDPS128 [1] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64VROUNDPS128)
+		v.AuxInt = int8ToAuxInt(1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorFloat32x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (FloorFloat32x8 x)
+	// result: (VROUNDPS256 [1] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64VROUNDPS256)
+		v.AuxInt = int8ToAuxInt(1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorFloat64x2(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (FloorFloat64x2 x)
+	// result: (VROUNDPD128 [1] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64VROUNDPD128)
+		v.AuxInt = int8ToAuxInt(1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorFloat64x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (FloorFloat64x4 x)
+	// result: (VROUNDPD256 [1] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64VROUNDPD256)
+		v.AuxInt = int8ToAuxInt(1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorWithPrecisionFloat32x16(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (FloorWithPrecisionFloat32x16 [a] x)
+	// result: (VRNDSCALEPS512 [a+1] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPS512)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorWithPrecisionFloat32x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (FloorWithPrecisionFloat32x4 [a] x)
+	// result: (VRNDSCALEPS128 [a+1] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPS128)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorWithPrecisionFloat32x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (FloorWithPrecisionFloat32x8 [a] x)
+	// result: (VRNDSCALEPS256 [a+1] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPS256)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorWithPrecisionFloat64x2(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (FloorWithPrecisionFloat64x2 [a] x)
+	// result: (VRNDSCALEPD128 [a+1] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPD128)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorWithPrecisionFloat64x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (FloorWithPrecisionFloat64x4 [a] x)
+	// result: (VRNDSCALEPD256 [a+1] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPD256)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorWithPrecisionFloat64x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (FloorWithPrecisionFloat64x8 [a] x)
+	// result: (VRNDSCALEPD512 [a+1] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPD512)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorWithPrecisionMaskedFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FloorWithPrecisionMaskedFloat32x16 [a] x mask)
+	// result: (VRNDSCALEPSMasked512 [a+1] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPSMasked512)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorWithPrecisionMaskedFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FloorWithPrecisionMaskedFloat32x4 [a] x mask)
+	// result: (VRNDSCALEPSMasked128 [a+1] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPSMasked128)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorWithPrecisionMaskedFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FloorWithPrecisionMaskedFloat32x8 [a] x mask)
+	// result: (VRNDSCALEPSMasked256 [a+1] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPSMasked256)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorWithPrecisionMaskedFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FloorWithPrecisionMaskedFloat64x2 [a] x mask)
+	// result: (VRNDSCALEPDMasked128 [a+1] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPDMasked128)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorWithPrecisionMaskedFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FloorWithPrecisionMaskedFloat64x4 [a] x mask)
+	// result: (VRNDSCALEPDMasked256 [a+1] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPDMasked256)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFloorWithPrecisionMaskedFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FloorWithPrecisionMaskedFloat64x8 [a] x mask)
+	// result: (VRNDSCALEPDMasked512 [a+1] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPDMasked512)
+		v.AuxInt = int8ToAuxInt(a + 1)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplyAddMaskedFloat32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplyAddMaskedFloat32x16 x y z mask)
+	// result: (VFMADD213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMADD213PSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplyAddMaskedFloat32x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplyAddMaskedFloat32x4 x y z mask)
+	// result: (VFMADD213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMADD213PSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplyAddMaskedFloat32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplyAddMaskedFloat32x8 x y z mask)
+	// result: (VFMADD213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMADD213PSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplyAddMaskedFloat64x2(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplyAddMaskedFloat64x2 x y z mask)
+	// result: (VFMADD213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMADD213PDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplyAddMaskedFloat64x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplyAddMaskedFloat64x4 x y z mask)
+	// result: (VFMADD213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMADD213PDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplyAddMaskedFloat64x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplyAddMaskedFloat64x8 x y z mask)
+	// result: (VFMADD213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMADD213PDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplyAddSubMaskedFloat32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplyAddSubMaskedFloat32x16 x y z mask)
+	// result: (VFMADDSUB213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMADDSUB213PSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplyAddSubMaskedFloat32x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplyAddSubMaskedFloat32x4 x y z mask)
+	// result: (VFMADDSUB213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMADDSUB213PSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplyAddSubMaskedFloat32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplyAddSubMaskedFloat32x8 x y z mask)
+	// result: (VFMADDSUB213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMADDSUB213PSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplyAddSubMaskedFloat64x2(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplyAddSubMaskedFloat64x2 x y z mask)
+	// result: (VFMADDSUB213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMADDSUB213PDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplyAddSubMaskedFloat64x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplyAddSubMaskedFloat64x4 x y z mask)
+	// result: (VFMADDSUB213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMADDSUB213PDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplyAddSubMaskedFloat64x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplyAddSubMaskedFloat64x8 x y z mask)
+	// result: (VFMADDSUB213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMADDSUB213PDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplySubAddMaskedFloat32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplySubAddMaskedFloat32x16 x y z mask)
+	// result: (VFMSUBADD213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMSUBADD213PSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplySubAddMaskedFloat32x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplySubAddMaskedFloat32x4 x y z mask)
+	// result: (VFMSUBADD213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMSUBADD213PSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplySubAddMaskedFloat32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplySubAddMaskedFloat32x8 x y z mask)
+	// result: (VFMSUBADD213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMSUBADD213PSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplySubAddMaskedFloat64x2(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplySubAddMaskedFloat64x2 x y z mask)
+	// result: (VFMSUBADD213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMSUBADD213PDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplySubAddMaskedFloat64x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplySubAddMaskedFloat64x4 x y z mask)
+	// result: (VFMSUBADD213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMSUBADD213PDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpFusedMultiplySubAddMaskedFloat64x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (FusedMultiplySubAddMaskedFloat64x8 x y z mask)
+	// result: (VFMSUBADD213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VFMSUBADD213PDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGaloisFieldAffineTransformInverseMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (GaloisFieldAffineTransformInverseMaskedUint8x16 [a] x y mask)
+	// result: (VGF2P8AFFINEINVQBMasked128 [a] x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VGF2P8AFFINEINVQBMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGaloisFieldAffineTransformInverseMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (GaloisFieldAffineTransformInverseMaskedUint8x32 [a] x y mask)
+	// result: (VGF2P8AFFINEINVQBMasked256 [a] x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VGF2P8AFFINEINVQBMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGaloisFieldAffineTransformInverseMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (GaloisFieldAffineTransformInverseMaskedUint8x64 [a] x y mask)
+	// result: (VGF2P8AFFINEINVQBMasked512 [a] x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VGF2P8AFFINEINVQBMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGaloisFieldAffineTransformMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (GaloisFieldAffineTransformMaskedUint8x16 [a] x y mask)
+	// result: (VGF2P8AFFINEQBMasked128 [a] x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VGF2P8AFFINEQBMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGaloisFieldAffineTransformMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (GaloisFieldAffineTransformMaskedUint8x32 [a] x y mask)
+	// result: (VGF2P8AFFINEQBMasked256 [a] x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VGF2P8AFFINEQBMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGaloisFieldAffineTransformMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (GaloisFieldAffineTransformMaskedUint8x64 [a] x y mask)
+	// result: (VGF2P8AFFINEQBMasked512 [a] x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VGF2P8AFFINEQBMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGaloisFieldMulMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (GaloisFieldMulMaskedUint8x16 x y mask)
+	// result: (VGF2P8MULBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VGF2P8MULBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGaloisFieldMulMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (GaloisFieldMulMaskedUint8x32 x y mask)
+	// result: (VGF2P8MULBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VGF2P8MULBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGaloisFieldMulMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (GaloisFieldMulMaskedUint8x64 x y mask)
+	// result: (VGF2P8MULBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VGF2P8MULBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGetG(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (GetG mem)
+	// cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal
+	// result: (LoweredGetG mem)
+	for {
+		mem := v_0
+		if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) {
+			break
+		}
+		v.reset(OpAMD64LoweredGetG)
+		v.AddArg(mem)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpGreaterEqualFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualFloat32x16 x y)
+	// result: (VPMOVMToVec32x16 (VCMPPS512 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (GreaterEqualFloat32x4 x y)
+	// result: (VCMPPS128 [13] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS128)
+		v.AuxInt = int8ToAuxInt(13)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (GreaterEqualFloat32x8 x y)
+	// result: (VCMPPS256 [13] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS256)
+		v.AuxInt = int8ToAuxInt(13)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (GreaterEqualFloat64x2 x y)
+	// result: (VCMPPD128 [13] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD128)
+		v.AuxInt = int8ToAuxInt(13)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (GreaterEqualFloat64x4 x y)
+	// result: (VCMPPD256 [13] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD256)
+		v.AuxInt = int8ToAuxInt(13)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualFloat64x8 x y)
+	// result: (VPMOVMToVec64x8 (VCMPPD512 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualInt16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualInt16x16 x y)
+	// result: (VPMOVMToVec16x16 (VPCMPW256 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualInt16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualInt16x32 x y)
+	// result: (VPMOVMToVec16x32 (VPCMPW512 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualInt16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualInt16x8 x y)
+	// result: (VPMOVMToVec16x8 (VPCMPW128 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualInt32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualInt32x16 x y)
+	// result: (VPMOVMToVec32x16 (VPCMPD512 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualInt32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualInt32x4 x y)
+	// result: (VPMOVMToVec32x4 (VPCMPD128 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualInt32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualInt32x8 x y)
+	// result: (VPMOVMToVec32x8 (VPCMPD256 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualInt64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualInt64x2 x y)
+	// result: (VPMOVMToVec64x2 (VPCMPQ128 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualInt64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualInt64x4 x y)
+	// result: (VPMOVMToVec64x4 (VPCMPQ256 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualInt64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualInt64x8 x y)
+	// result: (VPMOVMToVec64x8 (VPCMPQ512 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualInt8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualInt8x16 x y)
+	// result: (VPMOVMToVec8x16 (VPCMPB128 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualInt8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualInt8x32 x y)
+	// result: (VPMOVMToVec8x32 (VPCMPB256 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualInt8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualInt8x64 x y)
+	// result: (VPMOVMToVec8x64 (VPCMPB512 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedFloat32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VCMPPSMasked512 [13] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedFloat32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VCMPPSMasked128 [13] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedFloat32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VCMPPSMasked256 [13] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedFloat64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VCMPPDMasked128 [13] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedFloat64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VCMPPDMasked256 [13] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedFloat64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VCMPPDMasked512 [13] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedInt16x16 x y mask)
+	// result: (VPMOVMToVec16x16 (VPCMPWMasked256 [13] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedInt16x32 x y mask)
+	// result: (VPMOVMToVec16x32 (VPCMPWMasked512 [13] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedInt16x8 x y mask)
+	// result: (VPMOVMToVec16x8 (VPCMPWMasked128 [13] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedInt32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VPCMPDMasked512 [13] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedInt32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VPCMPDMasked128 [13] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedInt32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VPCMPDMasked256 [13] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedInt64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VPCMPQMasked128 [13] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedInt64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VPCMPQMasked256 [13] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedInt64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VPCMPQMasked512 [13] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedInt8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedInt8x16 x y mask)
+	// result: (VPMOVMToVec8x16 (VPCMPBMasked128 [13] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedInt8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedInt8x32 x y mask)
+	// result: (VPMOVMToVec8x32 (VPCMPBMasked256 [13] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedInt8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedInt8x64 x y mask)
+	// result: (VPMOVMToVec8x64 (VPCMPBMasked512 [13] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedUint16x16 x y mask)
+	// result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [13] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedUint16x32 x y mask)
+	// result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [13] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedUint16x8 x y mask)
+	// result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [13] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedUint32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [13] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedUint32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [13] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedUint32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [13] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedUint64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [13] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedUint64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [13] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedUint64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [13] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedUint8x16 x y mask)
+	// result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [13] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedUint8x32 x y mask)
+	// result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [13] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualMaskedUint8x64 x y mask)
+	// result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [13] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualUint16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualUint16x16 x y)
+	// result: (VPMOVMToVec16x16 (VPCMPUW256 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualUint16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualUint16x32 x y)
+	// result: (VPMOVMToVec16x32 (VPCMPUW512 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualUint16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualUint16x8 x y)
+	// result: (VPMOVMToVec16x8 (VPCMPUW128 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualUint32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualUint32x16 x y)
+	// result: (VPMOVMToVec32x16 (VPCMPUD512 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualUint32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualUint32x4 x y)
+	// result: (VPMOVMToVec32x4 (VPCMPUD128 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualUint32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualUint32x8 x y)
+	// result: (VPMOVMToVec32x8 (VPCMPUD256 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualUint64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualUint64x2 x y)
+	// result: (VPMOVMToVec64x2 (VPCMPUQ128 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualUint64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualUint64x4 x y)
+	// result: (VPMOVMToVec64x4 (VPCMPUQ256 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualUint64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualUint64x8 x y)
+	// result: (VPMOVMToVec64x8 (VPCMPUQ512 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualUint8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualUint8x16 x y)
+	// result: (VPMOVMToVec8x16 (VPCMPUB128 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualUint8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualUint8x32 x y)
+	// result: (VPMOVMToVec8x32 (VPCMPUB256 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterEqualUint8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterEqualUint8x64 x y)
+	// result: (VPMOVMToVec8x64 (VPCMPUB512 [13] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(13)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterFloat32x16 x y)
+	// result: (VPMOVMToVec32x16 (VCMPPS512 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (GreaterFloat32x4 x y)
+	// result: (VCMPPS128 [14] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS128)
+		v.AuxInt = int8ToAuxInt(14)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (GreaterFloat32x8 x y)
+	// result: (VCMPPS256 [14] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS256)
+		v.AuxInt = int8ToAuxInt(14)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (GreaterFloat64x2 x y)
+	// result: (VCMPPD128 [14] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD128)
+		v.AuxInt = int8ToAuxInt(14)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (GreaterFloat64x4 x y)
+	// result: (VCMPPD256 [14] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD256)
+		v.AuxInt = int8ToAuxInt(14)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterFloat64x8 x y)
+	// result: (VPMOVMToVec64x8 (VCMPPD512 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterInt16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterInt16x32 x y)
+	// result: (VPMOVMToVec16x32 (VPCMPW512 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterInt32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterInt32x16 x y)
+	// result: (VPMOVMToVec32x16 (VPCMPD512 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterInt64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterInt64x8 x y)
+	// result: (VPMOVMToVec64x8 (VPCMPQ512 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterInt8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterInt8x64 x y)
+	// result: (VPMOVMToVec8x64 (VPCMPB512 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedFloat32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VCMPPSMasked512 [14] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedFloat32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VCMPPSMasked128 [14] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedFloat32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VCMPPSMasked256 [14] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedFloat64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VCMPPDMasked128 [14] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedFloat64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VCMPPDMasked256 [14] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedFloat64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VCMPPDMasked512 [14] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedInt16x16 x y mask)
+	// result: (VPMOVMToVec16x16 (VPCMPWMasked256 [14] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedInt16x32 x y mask)
+	// result: (VPMOVMToVec16x32 (VPCMPWMasked512 [14] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedInt16x8 x y mask)
+	// result: (VPMOVMToVec16x8 (VPCMPWMasked128 [14] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedInt32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VPCMPDMasked512 [14] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedInt32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VPCMPDMasked128 [14] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedInt32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VPCMPDMasked256 [14] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedInt64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VPCMPQMasked128 [14] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedInt64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VPCMPQMasked256 [14] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedInt64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VPCMPQMasked512 [14] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedInt8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedInt8x16 x y mask)
+	// result: (VPMOVMToVec8x16 (VPCMPBMasked128 [14] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedInt8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedInt8x32 x y mask)
+	// result: (VPMOVMToVec8x32 (VPCMPBMasked256 [14] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedInt8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedInt8x64 x y mask)
+	// result: (VPMOVMToVec8x64 (VPCMPBMasked512 [14] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedUint16x16 x y mask)
+	// result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [14] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedUint16x32 x y mask)
+	// result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [14] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedUint16x8 x y mask)
+	// result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [14] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedUint32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [14] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedUint32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [14] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedUint32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [14] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedUint64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [14] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedUint64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [14] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedUint64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [14] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedUint8x16 x y mask)
+	// result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [14] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedUint8x32 x y mask)
+	// result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [14] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterMaskedUint8x64 x y mask)
+	// result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [14] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterUint16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterUint16x16 x y)
+	// result: (VPMOVMToVec16x16 (VPCMPUW256 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterUint16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterUint16x32 x y)
+	// result: (VPMOVMToVec16x32 (VPCMPUW512 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterUint16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterUint16x8 x y)
+	// result: (VPMOVMToVec16x8 (VPCMPUW128 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterUint32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterUint32x16 x y)
+	// result: (VPMOVMToVec32x16 (VPCMPUD512 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterUint32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterUint32x4 x y)
+	// result: (VPMOVMToVec32x4 (VPCMPUD128 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterUint32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterUint32x8 x y)
+	// result: (VPMOVMToVec32x8 (VPCMPUD256 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterUint64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterUint64x2 x y)
+	// result: (VPMOVMToVec64x2 (VPCMPUQ128 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterUint64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterUint64x4 x y)
+	// result: (VPMOVMToVec64x4 (VPCMPUQ256 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterUint64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterUint64x8 x y)
+	// result: (VPMOVMToVec64x8 (VPCMPUQ512 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterUint8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterUint8x16 x y)
+	// result: (VPMOVMToVec8x16 (VPCMPUB128 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterUint8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterUint8x32 x y)
+	// result: (VPMOVMToVec8x32 (VPCMPUB256 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpGreaterUint8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (GreaterUint8x64 x y)
+	// result: (VPMOVMToVec8x64 (VPCMPUB512 [14] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(14)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool {
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (HasCPUFeature {s})
+	// result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s})))
+	for {
+		s := auxToSym(v.Aux)
+		v.reset(OpAMD64SETNE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
+		v0.AuxInt = int32ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64)
+		v1.Aux = symToAux(s)
+		v0.AddArg(v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsInBounds(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (IsInBounds idx len)
+	// result: (SETB (CMPQ idx len))
+	for {
+		idx := v_0
+		len := v_1
+		v.reset(OpAMD64SETB)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
+		v0.AddArg2(idx, len)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsNanFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (IsNanFloat32x16 x y)
+	// result: (VPMOVMToVec32x16 (VCMPPS512 [3] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(3)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsNanFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (IsNanFloat32x4 x y)
+	// result: (VCMPPS128 [3] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS128)
+		v.AuxInt = int8ToAuxInt(3)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsNanFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (IsNanFloat32x8 x y)
+	// result: (VCMPPS256 [3] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS256)
+		v.AuxInt = int8ToAuxInt(3)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsNanFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (IsNanFloat64x2 x y)
+	// result: (VCMPPD128 [3] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD128)
+		v.AuxInt = int8ToAuxInt(3)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsNanFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (IsNanFloat64x4 x y)
+	// result: (VCMPPD256 [3] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD256)
+		v.AuxInt = int8ToAuxInt(3)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsNanFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (IsNanFloat64x8 x y)
+	// result: (VPMOVMToVec64x8 (VCMPPD512 [3] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(3)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsNanMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (IsNanMaskedFloat32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VCMPPSMasked512 [3] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(3)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsNanMaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (IsNanMaskedFloat32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VCMPPSMasked128 [3] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(3)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsNanMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (IsNanMaskedFloat32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VCMPPSMasked256 [3] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(3)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsNanMaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (IsNanMaskedFloat64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VCMPPDMasked128 [3] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(3)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsNanMaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (IsNanMaskedFloat64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VCMPPDMasked256 [3] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(3)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsNanMaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (IsNanMaskedFloat64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VCMPPDMasked512 [3] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(3)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsNonNil(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (IsNonNil p)
+	// result: (SETNE (TESTQ p p))
+	for {
+		p := v_0
+		v.reset(OpAMD64SETNE)
+		v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags)
+		v0.AddArg2(p, p)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (IsSliceInBounds idx len)
+	// result: (SETBE (CMPQ idx len))
+	for {
+		idx := v_0
+		len := v_1
+		v.reset(OpAMD64SETBE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
+		v0.AddArg2(idx, len)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLeq16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Leq16 x y)
+	// result: (SETLE (CMPW x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETLE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLeq16U(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Leq16U x y)
+	// result: (SETBE (CMPW x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETBE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLeq32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Leq32 x y)
+	// result: (SETLE (CMPL x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETLE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLeq32F(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Leq32F x y)
+	// result: (SETGEF (UCOMISS y x))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETGEF)
+		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
+		v0.AddArg2(y, x)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLeq32U(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Leq32U x y)
+	// result: (SETBE (CMPL x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETBE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLeq64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Leq64 x y)
+	// result: (SETLE (CMPQ x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETLE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLeq64F(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Leq64F x y)
+	// result: (SETGEF (UCOMISD y x))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETGEF)
+		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
+		v0.AddArg2(y, x)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLeq64U(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Leq64U x y)
+	// result: (SETBE (CMPQ x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETBE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLeq8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Leq8 x y)
+	// result: (SETLE (CMPB x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETLE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLeq8U(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Leq8U x y)
+	// result: (SETBE (CMPB x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETBE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLess16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Less16 x y)
+	// result: (SETL (CMPW x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETL)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLess16U(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Less16U x y)
+	// result: (SETB (CMPW x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETB)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLess32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Less32 x y)
+	// result: (SETL (CMPL x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETL)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLess32F(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Less32F x y)
+	// result: (SETGF (UCOMISS y x))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETGF)
+		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
+		v0.AddArg2(y, x)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLess32U(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Less32U x y)
+	// result: (SETB (CMPL x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETB)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLess64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Less64 x y)
+	// result: (SETL (CMPQ x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETL)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLess64F(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Less64F x y)
+	// result: (SETGF (UCOMISD y x))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETGF)
+		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
+		v0.AddArg2(y, x)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLess64U(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Less64U x y)
+	// result: (SETB (CMPQ x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETB)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLess8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Less8 x y)
+	// result: (SETL (CMPB x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETL)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLess8U(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Less8U x y)
+	// result: (SETB (CMPB x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETB)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualFloat32x16 x y)
+	// result: (VPMOVMToVec32x16 (VCMPPS512 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (LessEqualFloat32x4 x y)
+	// result: (VCMPPS128 [2] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS128)
+		v.AuxInt = int8ToAuxInt(2)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (LessEqualFloat32x8 x y)
+	// result: (VCMPPS256 [2] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS256)
+		v.AuxInt = int8ToAuxInt(2)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (LessEqualFloat64x2 x y)
+	// result: (VCMPPD128 [2] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD128)
+		v.AuxInt = int8ToAuxInt(2)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (LessEqualFloat64x4 x y)
+	// result: (VCMPPD256 [2] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD256)
+		v.AuxInt = int8ToAuxInt(2)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualFloat64x8 x y)
+	// result: (VPMOVMToVec64x8 (VCMPPD512 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualInt16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualInt16x16 x y)
+	// result: (VPMOVMToVec16x16 (VPCMPW256 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualInt16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualInt16x32 x y)
+	// result: (VPMOVMToVec16x32 (VPCMPW512 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualInt16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualInt16x8 x y)
+	// result: (VPMOVMToVec16x8 (VPCMPW128 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualInt32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualInt32x16 x y)
+	// result: (VPMOVMToVec32x16 (VPCMPD512 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualInt32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualInt32x4 x y)
+	// result: (VPMOVMToVec32x4 (VPCMPD128 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualInt32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualInt32x8 x y)
+	// result: (VPMOVMToVec32x8 (VPCMPD256 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualInt64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualInt64x2 x y)
+	// result: (VPMOVMToVec64x2 (VPCMPQ128 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualInt64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualInt64x4 x y)
+	// result: (VPMOVMToVec64x4 (VPCMPQ256 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualInt64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualInt64x8 x y)
+	// result: (VPMOVMToVec64x8 (VPCMPQ512 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualInt8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualInt8x16 x y)
+	// result: (VPMOVMToVec8x16 (VPCMPB128 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualInt8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualInt8x32 x y)
+	// result: (VPMOVMToVec8x32 (VPCMPB256 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualInt8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualInt8x64 x y)
+	// result: (VPMOVMToVec8x64 (VPCMPB512 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedFloat32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VCMPPSMasked512 [2] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedFloat32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VCMPPSMasked128 [2] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedFloat32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VCMPPSMasked256 [2] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedFloat64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VCMPPDMasked128 [2] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedFloat64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VCMPPDMasked256 [2] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedFloat64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VCMPPDMasked512 [2] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedInt16x16 x y mask)
+	// result: (VPMOVMToVec16x16 (VPCMPWMasked256 [2] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedInt16x32 x y mask)
+	// result: (VPMOVMToVec16x32 (VPCMPWMasked512 [2] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedInt16x8 x y mask)
+	// result: (VPMOVMToVec16x8 (VPCMPWMasked128 [2] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedInt32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VPCMPDMasked512 [2] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedInt32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VPCMPDMasked128 [2] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedInt32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VPCMPDMasked256 [2] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedInt64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VPCMPQMasked128 [2] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedInt64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VPCMPQMasked256 [2] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedInt64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VPCMPQMasked512 [2] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedInt8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedInt8x16 x y mask)
+	// result: (VPMOVMToVec8x16 (VPCMPBMasked128 [2] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedInt8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedInt8x32 x y mask)
+	// result: (VPMOVMToVec8x32 (VPCMPBMasked256 [2] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedInt8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedInt8x64 x y mask)
+	// result: (VPMOVMToVec8x64 (VPCMPBMasked512 [2] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedUint16x16 x y mask)
+	// result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [2] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedUint16x32 x y mask)
+	// result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [2] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedUint16x8 x y mask)
+	// result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [2] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedUint32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [2] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedUint32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [2] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedUint32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [2] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedUint64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [2] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedUint64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [2] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedUint64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [2] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedUint8x16 x y mask)
+	// result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [2] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedUint8x32 x y mask)
+	// result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [2] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualMaskedUint8x64 x y mask)
+	// result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [2] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualUint16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualUint16x16 x y)
+	// result: (VPMOVMToVec16x16 (VPCMPUW256 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualUint16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualUint16x32 x y)
+	// result: (VPMOVMToVec16x32 (VPCMPUW512 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualUint16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualUint16x8 x y)
+	// result: (VPMOVMToVec16x8 (VPCMPUW128 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualUint32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualUint32x16 x y)
+	// result: (VPMOVMToVec32x16 (VPCMPUD512 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualUint32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualUint32x4 x y)
+	// result: (VPMOVMToVec32x4 (VPCMPUD128 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualUint32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualUint32x8 x y)
+	// result: (VPMOVMToVec32x8 (VPCMPUD256 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualUint64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualUint64x2 x y)
+	// result: (VPMOVMToVec64x2 (VPCMPUQ128 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualUint64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualUint64x4 x y)
+	// result: (VPMOVMToVec64x4 (VPCMPUQ256 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualUint64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualUint64x8 x y)
+	// result: (VPMOVMToVec64x8 (VPCMPUQ512 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualUint8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualUint8x16 x y)
+	// result: (VPMOVMToVec8x16 (VPCMPUB128 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualUint8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualUint8x32 x y)
+	// result: (VPMOVMToVec8x32 (VPCMPUB256 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessEqualUint8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessEqualUint8x64 x y)
+	// result: (VPMOVMToVec8x64 (VPCMPUB512 [2] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(2)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessFloat32x16 x y)
+	// result: (VPMOVMToVec32x16 (VCMPPS512 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (LessFloat32x4 x y)
+	// result: (VCMPPS128 [1] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS128)
+		v.AuxInt = int8ToAuxInt(1)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (LessFloat32x8 x y)
+	// result: (VCMPPS256 [1] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS256)
+		v.AuxInt = int8ToAuxInt(1)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (LessFloat64x2 x y)
+	// result: (VCMPPD128 [1] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD128)
+		v.AuxInt = int8ToAuxInt(1)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (LessFloat64x4 x y)
+	// result: (VCMPPD256 [1] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD256)
+		v.AuxInt = int8ToAuxInt(1)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessFloat64x8 x y)
+	// result: (VPMOVMToVec64x8 (VCMPPD512 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessInt16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessInt16x16 x y)
+	// result: (VPMOVMToVec16x16 (VPCMPW256 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessInt16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessInt16x32 x y)
+	// result: (VPMOVMToVec16x32 (VPCMPW512 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessInt16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessInt16x8 x y)
+	// result: (VPMOVMToVec16x8 (VPCMPW128 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessInt32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessInt32x16 x y)
+	// result: (VPMOVMToVec32x16 (VPCMPD512 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessInt32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessInt32x4 x y)
+	// result: (VPMOVMToVec32x4 (VPCMPD128 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessInt32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessInt32x8 x y)
+	// result: (VPMOVMToVec32x8 (VPCMPD256 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessInt64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessInt64x2 x y)
+	// result: (VPMOVMToVec64x2 (VPCMPQ128 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessInt64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessInt64x4 x y)
+	// result: (VPMOVMToVec64x4 (VPCMPQ256 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessInt64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessInt64x8 x y)
+	// result: (VPMOVMToVec64x8 (VPCMPQ512 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessInt8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessInt8x16 x y)
+	// result: (VPMOVMToVec8x16 (VPCMPB128 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessInt8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessInt8x32 x y)
+	// result: (VPMOVMToVec8x32 (VPCMPB256 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessInt8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessInt8x64 x y)
+	// result: (VPMOVMToVec8x64 (VPCMPB512 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedFloat32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VCMPPSMasked512 [1] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedFloat32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VCMPPSMasked128 [1] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedFloat32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VCMPPSMasked256 [1] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedFloat64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VCMPPDMasked128 [1] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedFloat64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VCMPPDMasked256 [1] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedFloat64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VCMPPDMasked512 [1] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedInt16x16 x y mask)
+	// result: (VPMOVMToVec16x16 (VPCMPWMasked256 [1] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedInt16x32 x y mask)
+	// result: (VPMOVMToVec16x32 (VPCMPWMasked512 [1] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedInt16x8 x y mask)
+	// result: (VPMOVMToVec16x8 (VPCMPWMasked128 [1] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedInt32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VPCMPDMasked512 [1] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedInt32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VPCMPDMasked128 [1] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedInt32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VPCMPDMasked256 [1] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedInt64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VPCMPQMasked128 [1] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedInt64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VPCMPQMasked256 [1] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedInt64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VPCMPQMasked512 [1] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedInt8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedInt8x16 x y mask)
+	// result: (VPMOVMToVec8x16 (VPCMPBMasked128 [1] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedInt8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedInt8x32 x y mask)
+	// result: (VPMOVMToVec8x32 (VPCMPBMasked256 [1] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedInt8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedInt8x64 x y mask)
+	// result: (VPMOVMToVec8x64 (VPCMPBMasked512 [1] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedUint16x16 x y mask)
+	// result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [1] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedUint16x32 x y mask)
+	// result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [1] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedUint16x8 x y mask)
+	// result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [1] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedUint32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [1] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedUint32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [1] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedUint32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [1] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedUint64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [1] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedUint64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [1] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedUint64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [1] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedUint8x16 x y mask)
+	// result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [1] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedUint8x32 x y mask)
+	// result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [1] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessMaskedUint8x64 x y mask)
+	// result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [1] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessUint16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessUint16x16 x y)
+	// result: (VPMOVMToVec16x16 (VPCMPUW256 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessUint16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessUint16x32 x y)
+	// result: (VPMOVMToVec16x32 (VPCMPUW512 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessUint16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessUint16x8 x y)
+	// result: (VPMOVMToVec16x8 (VPCMPUW128 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessUint32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessUint32x16 x y)
+	// result: (VPMOVMToVec32x16 (VPCMPUD512 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessUint32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessUint32x4 x y)
+	// result: (VPMOVMToVec32x4 (VPCMPUD128 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessUint32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessUint32x8 x y)
+	// result: (VPMOVMToVec32x8 (VPCMPUD256 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessUint64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessUint64x2 x y)
+	// result: (VPMOVMToVec64x2 (VPCMPUQ128 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessUint64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessUint64x4 x y)
+	// result: (VPMOVMToVec64x4 (VPCMPUQ256 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessUint64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessUint64x8 x y)
+	// result: (VPMOVMToVec64x8 (VPCMPUQ512 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessUint8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessUint8x16 x y)
+	// result: (VPMOVMToVec8x16 (VPCMPUB128 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessUint8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessUint8x32 x y)
+	// result: (VPMOVMToVec8x32 (VPCMPUB256 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLessUint8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LessUint8x64 x y)
+	// result: (VPMOVMToVec8x64 (VPCMPUB512 [1] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(1)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpLoad(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (Load <t> ptr mem)
+	// cond: (is64BitInt(t) || isPtr(t))
+	// result: (MOVQload ptr mem)
+	for {
+		t := v.Type
+		ptr := v_0
+		mem := v_1
+		if !(is64BitInt(t) || isPtr(t)) {
+			break
+		}
+		v.reset(OpAMD64MOVQload)
+		v.AddArg2(ptr, mem)
+		return true
+	}
+	// match: (Load <t> ptr mem)
+	// cond: is32BitInt(t)
+	// result: (MOVLload ptr mem)
+	for {
+		t := v.Type
+		ptr := v_0
+		mem := v_1
+		if !(is32BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64MOVLload)
+		v.AddArg2(ptr, mem)
+		return true
+	}
+	// match: (Load <t> ptr mem)
+	// cond: is16BitInt(t)
+	// result: (MOVWload ptr mem)
+	for {
+		t := v.Type
+		ptr := v_0
+		mem := v_1
+		if !(is16BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64MOVWload)
+		v.AddArg2(ptr, mem)
+		return true
+	}
+	// match: (Load <t> ptr mem)
+	// cond: (t.IsBoolean() || is8BitInt(t))
+	// result: (MOVBload ptr mem)
+	for {
+		t := v.Type
+		ptr := v_0
+		mem := v_1
+		if !(t.IsBoolean() || is8BitInt(t)) {
+			break
+		}
+		v.reset(OpAMD64MOVBload)
+		v.AddArg2(ptr, mem)
+		return true
+	}
+	// match: (Load <t> ptr mem)
+	// cond: is32BitFloat(t)
+	// result: (MOVSSload ptr mem)
+	for {
+		t := v.Type
+		ptr := v_0
+		mem := v_1
+		if !(is32BitFloat(t)) {
+			break
+		}
+		v.reset(OpAMD64MOVSSload)
+		v.AddArg2(ptr, mem)
+		return true
+	}
+	// match: (Load <t> ptr mem)
+	// cond: is64BitFloat(t)
+	// result: (MOVSDload ptr mem)
+	for {
+		t := v.Type
+		ptr := v_0
+		mem := v_1
+		if !(is64BitFloat(t)) {
+			break
+		}
+		v.reset(OpAMD64MOVSDload)
+		v.AddArg2(ptr, mem)
+		return true
+	}
+	// match: (Load <t> ptr mem)
+	// cond: t.Size() == 16
+	// result: (VMOVDQUload128 ptr mem)
+	for {
+		t := v.Type
+		ptr := v_0
+		mem := v_1
+		if !(t.Size() == 16) {
+			break
+		}
+		v.reset(OpAMD64VMOVDQUload128)
+		v.AddArg2(ptr, mem)
+		return true
+	}
+	// match: (Load <t> ptr mem)
+	// cond: t.Size() == 32
+	// result: (VMOVDQUload256 ptr mem)
+	for {
+		t := v.Type
+		ptr := v_0
+		mem := v_1
+		if !(t.Size() == 32) {
+			break
+		}
+		v.reset(OpAMD64VMOVDQUload256)
+		v.AddArg2(ptr, mem)
+		return true
+	}
+	// match: (Load <t> ptr mem)
+	// cond: t.Size() == 64
+	// result: (VMOVDQUload512 ptr mem)
+	for {
+		t := v.Type
+		ptr := v_0
+		mem := v_1
+		if !(t.Size() == 64) {
+			break
+		}
+		v.reset(OpAMD64VMOVDQUload512)
+		v.AddArg2(ptr, mem)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLocalAddr(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (LocalAddr <t> {sym} base mem)
+	// cond: t.Elem().HasPointers()
+	// result: (LEAQ {sym} (SPanchored base mem))
+	for {
+		t := v.Type
+		sym := auxToSym(v.Aux)
+		base := v_0
+		mem := v_1
+		if !(t.Elem().HasPointers()) {
+			break
+		}
+		v.reset(OpAMD64LEAQ)
+		v.Aux = symToAux(sym)
+		v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr)
+		v0.AddArg2(base, mem)
+		v.AddArg(v0)
+		return true
+	}
+	// match: (LocalAddr <t> {sym} base _)
+	// cond: !t.Elem().HasPointers()
+	// result: (LEAQ {sym} base)
+	for {
+		t := v.Type
+		sym := auxToSym(v.Aux)
+		base := v_0
+		if !(!t.Elem().HasPointers()) {
+			break
+		}
+		v.reset(OpAMD64LEAQ)
+		v.Aux = symToAux(sym)
+		v.AddArg(base)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh16x16 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
+		v2.AuxInt = int16ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh16x16 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh16x32 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh16x32 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh16x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh16x64 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh16x64 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh16x8 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
+		v2.AuxInt = int8ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh16x8 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh32x16 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
+		v2.AuxInt = int16ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh32x16 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh32x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh32x32 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh32x32 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh32x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh32x64 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh32x64 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh32x8 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
+		v2.AuxInt = int8ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh32x8 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh64x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh64x16 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
+		v2.AuxInt = int16ToAuxInt(64)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh64x16 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLQ x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLQ)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh64x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh64x32 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(64)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh64x32 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLQ x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLQ)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh64x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh64x64 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(64)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh64x64 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLQ x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLQ)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh64x8 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
+		v2.AuxInt = int8ToAuxInt(64)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh64x8 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLQ x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLQ)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh8x16 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
+		v2.AuxInt = int16ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh8x16 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh8x32 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh8x32 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh8x64 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh8x64 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpLsh8x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Lsh8x8 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
+		v2.AuxInt = int8ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Lsh8x8 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHLL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHLL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpMax32F(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Max32F <t> x y)
+	// result: (Neg32F <t> (Min32F <t> (Neg32F <t> x) (Neg32F <t> y)))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		v.reset(OpNeg32F)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpMin32F, t)
+		v1 := b.NewValue0(v.Pos, OpNeg32F, t)
+		v1.AddArg(x)
+		v2 := b.NewValue0(v.Pos, OpNeg32F, t)
+		v2.AddArg(y)
+		v0.AddArg2(v1, v2)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMax64F(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Max64F <t> x y)
+	// result: (Neg64F <t> (Min64F <t> (Neg64F <t> x) (Neg64F <t> y)))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		v.reset(OpNeg64F)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpMin64F, t)
+		v1 := b.NewValue0(v.Pos, OpNeg64F, t)
+		v1.AddArg(x)
+		v2 := b.NewValue0(v.Pos, OpNeg64F, t)
+		v2.AddArg(y)
+		v0.AddArg2(v1, v2)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedFloat32x16 x y mask)
+	// result: (VMAXPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMAXPSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedFloat32x4 x y mask)
+	// result: (VMAXPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMAXPSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedFloat32x8 x y mask)
+	// result: (VMAXPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMAXPSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedFloat64x2 x y mask)
+	// result: (VMAXPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMAXPDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedFloat64x4 x y mask)
+	// result: (VMAXPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMAXPDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedFloat64x8 x y mask)
+	// result: (VMAXPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMAXPDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedInt16x16 x y mask)
+	// result: (VPMAXSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXSWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedInt16x32 x y mask)
+	// result: (VPMAXSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXSWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedInt16x8 x y mask)
+	// result: (VPMAXSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXSWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedInt32x16 x y mask)
+	// result: (VPMAXSDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXSDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedInt32x4 x y mask)
+	// result: (VPMAXSDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXSDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedInt32x8 x y mask)
+	// result: (VPMAXSDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXSDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedInt64x2 x y mask)
+	// result: (VPMAXSQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXSQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedInt64x4 x y mask)
+	// result: (VPMAXSQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXSQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedInt64x8 x y mask)
+	// result: (VPMAXSQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXSQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedInt8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedInt8x16 x y mask)
+	// result: (VPMAXSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXSBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedInt8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedInt8x32 x y mask)
+	// result: (VPMAXSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXSBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedInt8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedInt8x64 x y mask)
+	// result: (VPMAXSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXSBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedUint16x16 x y mask)
+	// result: (VPMAXUWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXUWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedUint16x32 x y mask)
+	// result: (VPMAXUWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXUWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedUint16x8 x y mask)
+	// result: (VPMAXUWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXUWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedUint32x16 x y mask)
+	// result: (VPMAXUDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXUDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedUint32x4 x y mask)
+	// result: (VPMAXUDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXUDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedUint32x8 x y mask)
+	// result: (VPMAXUDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXUDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedUint64x2 x y mask)
+	// result: (VPMAXUQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXUQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedUint64x4 x y mask)
+	// result: (VPMAXUQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXUQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedUint64x8 x y mask)
+	// result: (VPMAXUQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXUQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedUint8x16 x y mask)
+	// result: (VPMAXUBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXUBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedUint8x32 x y mask)
+	// result: (VPMAXUBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXUBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMaxMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MaxMaskedUint8x64 x y mask)
+	// result: (VPMAXUBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMAXUBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMin32F(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Min32F <t> x y)
+	// result: (POR (MINSS <t> (MINSS <t> x y) x) (MINSS <t> x y))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64POR)
+		v0 := b.NewValue0(v.Pos, OpAMD64MINSS, t)
+		v1 := b.NewValue0(v.Pos, OpAMD64MINSS, t)
+		v1.AddArg2(x, y)
+		v0.AddArg2(v1, x)
+		v.AddArg2(v0, v1)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMin64F(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Min64F <t> x y)
+	// result: (POR (MINSD <t> (MINSD <t> x y) x) (MINSD <t> x y))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64POR)
+		v0 := b.NewValue0(v.Pos, OpAMD64MINSD, t)
+		v1 := b.NewValue0(v.Pos, OpAMD64MINSD, t)
+		v1.AddArg2(x, y)
+		v0.AddArg2(v1, x)
+		v.AddArg2(v0, v1)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedFloat32x16 x y mask)
+	// result: (VMINPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMINPSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedFloat32x4 x y mask)
+	// result: (VMINPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMINPSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedFloat32x8 x y mask)
+	// result: (VMINPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMINPSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedFloat64x2 x y mask)
+	// result: (VMINPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMINPDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedFloat64x4 x y mask)
+	// result: (VMINPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMINPDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedFloat64x8 x y mask)
+	// result: (VMINPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMINPDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedInt16x16 x y mask)
+	// result: (VPMINSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINSWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedInt16x32 x y mask)
+	// result: (VPMINSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINSWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedInt16x8 x y mask)
+	// result: (VPMINSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINSWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedInt32x16 x y mask)
+	// result: (VPMINSDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINSDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedInt32x4 x y mask)
+	// result: (VPMINSDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINSDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedInt32x8 x y mask)
+	// result: (VPMINSDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINSDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedInt64x2 x y mask)
+	// result: (VPMINSQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINSQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedInt64x4 x y mask)
+	// result: (VPMINSQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINSQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedInt64x8 x y mask)
+	// result: (VPMINSQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINSQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedInt8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedInt8x16 x y mask)
+	// result: (VPMINSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINSBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedInt8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedInt8x32 x y mask)
+	// result: (VPMINSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINSBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedInt8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedInt8x64 x y mask)
+	// result: (VPMINSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINSBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedUint16x16 x y mask)
+	// result: (VPMINUWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINUWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedUint16x32 x y mask)
+	// result: (VPMINUWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINUWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedUint16x8 x y mask)
+	// result: (VPMINUWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINUWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedUint32x16 x y mask)
+	// result: (VPMINUDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINUDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedUint32x4 x y mask)
+	// result: (VPMINUDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINUDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedUint32x8 x y mask)
+	// result: (VPMINUDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINUDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedUint64x2 x y mask)
+	// result: (VPMINUQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINUQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedUint64x4 x y mask)
+	// result: (VPMINUQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINUQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedUint64x8 x y mask)
+	// result: (VPMINUQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINUQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedUint8x16 x y mask)
+	// result: (VPMINUBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINUBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedUint8x32 x y mask)
+	// result: (VPMINUBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINUBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMinMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MinMaskedUint8x64 x y mask)
+	// result: (VPMINUBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMINUBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMod16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Mod16 [a] x y)
+	// result: (Select1 (DIVW [a] x y))
+	for {
+		a := auxIntToBool(v.AuxInt)
+		x := v_0
+		y := v_1
+		v.reset(OpSelect1)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
+		v0.AuxInt = boolToAuxInt(a)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMod16u(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Mod16u x y)
+	// result: (Select1 (DIVWU x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpSelect1)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMod32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Mod32 [a] x y)
+	// result: (Select1 (DIVL [a] x y))
+	for {
+		a := auxIntToBool(v.AuxInt)
+		x := v_0
+		y := v_1
+		v.reset(OpSelect1)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32))
+		v0.AuxInt = boolToAuxInt(a)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMod32u(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Mod32u x y)
+	// result: (Select1 (DIVLU x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpSelect1)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32))
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMod64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Mod64 [a] x y)
+	// result: (Select1 (DIVQ [a] x y))
+	for {
+		a := auxIntToBool(v.AuxInt)
+		x := v_0
+		y := v_1
+		v.reset(OpSelect1)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64))
+		v0.AuxInt = boolToAuxInt(a)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMod64u(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Mod64u x y)
+	// result: (Select1 (DIVQU x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpSelect1)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64))
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMod8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Mod8 x y)
+	// result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpSelect1)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
+		v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
+		v1.AddArg(x)
+		v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
+		v2.AddArg(y)
+		v0.AddArg2(v1, v2)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMod8u(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Mod8u x y)
+	// result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpSelect1)
+		v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
+		v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
+		v1.AddArg(x)
+		v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
+		v2.AddArg(y)
+		v0.AddArg2(v1, v2)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMove(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Move [0] _ _ mem)
+	// result: mem
+	for {
+		if auxIntToInt64(v.AuxInt) != 0 {
+			break
+		}
+		mem := v_2
+		v.copyOf(mem)
+		return true
+	}
+	// match: (Move [1] dst src mem)
+	// result: (MOVBstore dst (MOVBload src mem) mem)
+	for {
+		if auxIntToInt64(v.AuxInt) != 1 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpAMD64MOVBstore)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
+		v0.AddArg2(src, mem)
+		v.AddArg3(dst, v0, mem)
+		return true
+	}
+	// match: (Move [2] dst src mem)
+	// result: (MOVWstore dst (MOVWload src mem) mem)
+	for {
+		if auxIntToInt64(v.AuxInt) != 2 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpAMD64MOVWstore)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
+		v0.AddArg2(src, mem)
+		v.AddArg3(dst, v0, mem)
+		return true
+	}
+	// match: (Move [4] dst src mem)
+	// result: (MOVLstore dst (MOVLload src mem) mem)
+	for {
+		if auxIntToInt64(v.AuxInt) != 4 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpAMD64MOVLstore)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
+		v0.AddArg2(src, mem)
+		v.AddArg3(dst, v0, mem)
+		return true
+	}
+	// match: (Move [8] dst src mem)
+	// result: (MOVQstore dst (MOVQload src mem) mem)
+	for {
+		if auxIntToInt64(v.AuxInt) != 8 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpAMD64MOVQstore)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
+		v0.AddArg2(src, mem)
+		v.AddArg3(dst, v0, mem)
+		return true
+	}
+	// match: (Move [16] dst src mem)
+	// result: (MOVOstore dst (MOVOload src mem) mem)
+	for {
+		if auxIntToInt64(v.AuxInt) != 16 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpAMD64MOVOstore)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128)
+		v0.AddArg2(src, mem)
+		v.AddArg3(dst, v0, mem)
+		return true
+	}
+	// match: (Move [32] dst src mem)
+	// result: (Move [16] (OffPtr <dst.Type> dst [16]) (OffPtr <src.Type> src [16]) (Move [16] dst src mem))
+	for {
+		if auxIntToInt64(v.AuxInt) != 32 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpMove)
+		v.AuxInt = int64ToAuxInt(16)
+		v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
+		v0.AuxInt = int64ToAuxInt(16)
+		v0.AddArg(dst)
+		v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
+		v1.AuxInt = int64ToAuxInt(16)
+		v1.AddArg(src)
+		v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem)
+		v2.AuxInt = int64ToAuxInt(16)
+		v2.AddArg3(dst, src, mem)
+		v.AddArg3(v0, v1, v2)
+		return true
+	}
+	// match: (Move [48] dst src mem)
+	// result: (Move [32] (OffPtr <dst.Type> dst [16]) (OffPtr <src.Type> src [16]) (Move [16] dst src mem))
+	for {
+		if auxIntToInt64(v.AuxInt) != 48 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpMove)
+		v.AuxInt = int64ToAuxInt(32)
+		v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
+		v0.AuxInt = int64ToAuxInt(16)
+		v0.AddArg(dst)
+		v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
+		v1.AuxInt = int64ToAuxInt(16)
+		v1.AddArg(src)
+		v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem)
+		v2.AuxInt = int64ToAuxInt(16)
+		v2.AddArg3(dst, src, mem)
+		v.AddArg3(v0, v1, v2)
+		return true
+	}
+	// match: (Move [64] dst src mem)
+	// result: (Move [32] (OffPtr <dst.Type> dst [32]) (OffPtr <src.Type> src [32]) (Move [32] dst src mem))
+	for {
+		if auxIntToInt64(v.AuxInt) != 64 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpMove)
+		v.AuxInt = int64ToAuxInt(32)
+		v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
+		v0.AuxInt = int64ToAuxInt(32)
+		v0.AddArg(dst)
+		v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
+		v1.AuxInt = int64ToAuxInt(32)
+		v1.AddArg(src)
+		v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem)
+		v2.AuxInt = int64ToAuxInt(32)
+		v2.AddArg3(dst, src, mem)
+		v.AddArg3(v0, v1, v2)
+		return true
+	}
+	// match: (Move [3] dst src mem)
+	// result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem))
+	for {
+		if auxIntToInt64(v.AuxInt) != 3 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpAMD64MOVBstore)
+		v.AuxInt = int32ToAuxInt(2)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
+		v0.AuxInt = int32ToAuxInt(2)
+		v0.AddArg2(src, mem)
+		v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
+		v2.AddArg2(src, mem)
+		v1.AddArg3(dst, v2, mem)
+		v.AddArg3(dst, v0, v1)
+		return true
+	}
+	// match: (Move [5] dst src mem)
+	// result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
+	for {
+		if auxIntToInt64(v.AuxInt) != 5 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpAMD64MOVBstore)
+		v.AuxInt = int32ToAuxInt(4)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
+		v0.AuxInt = int32ToAuxInt(4)
+		v0.AddArg2(src, mem)
+		v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
+		v2.AddArg2(src, mem)
+		v1.AddArg3(dst, v2, mem)
+		v.AddArg3(dst, v0, v1)
+		return true
+	}
+	// match: (Move [6] dst src mem)
+	// result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
+	for {
+		if auxIntToInt64(v.AuxInt) != 6 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpAMD64MOVWstore)
+		v.AuxInt = int32ToAuxInt(4)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
+		v0.AuxInt = int32ToAuxInt(4)
+		v0.AddArg2(src, mem)
+		v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
+		v2.AddArg2(src, mem)
+		v1.AddArg3(dst, v2, mem)
+		v.AddArg3(dst, v0, v1)
+		return true
+	}
+	// match: (Move [7] dst src mem)
+	// result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem))
+	for {
+		if auxIntToInt64(v.AuxInt) != 7 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpAMD64MOVLstore)
+		v.AuxInt = int32ToAuxInt(3)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
+		v0.AuxInt = int32ToAuxInt(3)
+		v0.AddArg2(src, mem)
+		v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
+		v2.AddArg2(src, mem)
+		v1.AddArg3(dst, v2, mem)
+		v.AddArg3(dst, v0, v1)
+		return true
+	}
+	// match: (Move [9] dst src mem)
+	// result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
+	for {
+		if auxIntToInt64(v.AuxInt) != 9 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpAMD64MOVBstore)
+		v.AuxInt = int32ToAuxInt(8)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
+		v0.AuxInt = int32ToAuxInt(8)
+		v0.AddArg2(src, mem)
+		v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
+		v2.AddArg2(src, mem)
+		v1.AddArg3(dst, v2, mem)
+		v.AddArg3(dst, v0, v1)
+		return true
+	}
+	// match: (Move [10] dst src mem)
+	// result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
+	for {
+		if auxIntToInt64(v.AuxInt) != 10 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpAMD64MOVWstore)
+		v.AuxInt = int32ToAuxInt(8)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
+		v0.AuxInt = int32ToAuxInt(8)
+		v0.AddArg2(src, mem)
+		v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
+		v2.AddArg2(src, mem)
+		v1.AddArg3(dst, v2, mem)
+		v.AddArg3(dst, v0, v1)
+		return true
+	}
+	// match: (Move [11] dst src mem)
+	// result: (MOVLstore [7] dst (MOVLload [7] src mem) (MOVQstore dst (MOVQload src mem) mem))
+	for {
+		if auxIntToInt64(v.AuxInt) != 11 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpAMD64MOVLstore)
+		v.AuxInt = int32ToAuxInt(7)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
+		v0.AuxInt = int32ToAuxInt(7)
+		v0.AddArg2(src, mem)
+		v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
+		v2.AddArg2(src, mem)
+		v1.AddArg3(dst, v2, mem)
+		v.AddArg3(dst, v0, v1)
+		return true
+	}
+	// match: (Move [12] dst src mem)
+	// result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
+	for {
+		if auxIntToInt64(v.AuxInt) != 12 {
+			break
+		}
+		dst := v_0
+		src := v_1
+		mem := v_2
+		v.reset(OpAMD64MOVLstore)
+		v.AuxInt = int32ToAuxInt(8)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
+		v0.AuxInt = int32ToAuxInt(8)
+		v0.AddArg2(src, mem)
+		v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
+		v2.AddArg2(src, mem)
+		v1.AddArg3(dst, v2, mem)
+		v.AddArg3(dst, v0, v1)
+		return true
+	}
+	// match: (Move [s] dst src mem)
+	// cond: s >= 13 && s <= 15
+	// result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem))
+	for {
+		s := auxIntToInt64(v.AuxInt)
+		dst := v_0
+		src := v_1
+		mem := v_2
+		if !(s >= 13 && s <= 15) {
+			break
+		}
+		v.reset(OpAMD64MOVQstore)
+		v.AuxInt = int32ToAuxInt(int32(s - 8))
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
+		v0.AuxInt = int32ToAuxInt(int32(s - 8))
+		v0.AddArg2(src, mem)
+		v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
+		v2.AddArg2(src, mem)
+		v1.AddArg3(dst, v2, mem)
+		v.AddArg3(dst, v0, v1)
+		return true
+	}
+	// match: (Move [s] dst src mem)
+	// cond: s > 16 && s%16 != 0 && s%16 <= 8
+	// result: (Move [s-s%16] (OffPtr <dst.Type> dst [s%16]) (OffPtr <src.Type> src [s%16]) (MOVQstore dst (MOVQload src mem) mem))
+	for {
+		s := auxIntToInt64(v.AuxInt)
+		dst := v_0
+		src := v_1
+		mem := v_2
+		if !(s > 16 && s%16 != 0 && s%16 <= 8) {
+			break
+		}
+		v.reset(OpMove)
+		v.AuxInt = int64ToAuxInt(s - s%16)
+		v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
+		v0.AuxInt = int64ToAuxInt(s % 16)
+		v0.AddArg(dst)
+		v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
+		v1.AuxInt = int64ToAuxInt(s % 16)
+		v1.AddArg(src)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
+		v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
+		v3.AddArg2(src, mem)
+		v2.AddArg3(dst, v3, mem)
+		v.AddArg3(v0, v1, v2)
+		return true
+	}
+	// match: (Move [s] dst src mem)
+	// cond: s > 16 && s%16 != 0 && s%16 > 8
+	// result: (Move [s-s%16] (OffPtr <dst.Type> dst [s%16]) (OffPtr <src.Type> src [s%16]) (MOVOstore dst (MOVOload src mem) mem))
+	for {
+		s := auxIntToInt64(v.AuxInt)
+		dst := v_0
+		src := v_1
+		mem := v_2
+		if !(s > 16 && s%16 != 0 && s%16 > 8) {
+			break
+		}
+		v.reset(OpMove)
+		v.AuxInt = int64ToAuxInt(s - s%16)
+		v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
+		v0.AuxInt = int64ToAuxInt(s % 16)
+		v0.AddArg(dst)
+		v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
+		v1.AuxInt = int64ToAuxInt(s % 16)
+		v1.AddArg(src)
+		v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem)
+		v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128)
+		v3.AddArg2(src, mem)
+		v2.AddArg3(dst, v3, mem)
+		v.AddArg3(v0, v1, v2)
+		return true
+	}
+	// match: (Move [s] dst src mem)
+	// cond: s > 64 && s <= 16*64 && s%16 == 0 && logLargeCopy(v, s)
+	// result: (DUFFCOPY [s] dst src mem)
+	for {
+		s := auxIntToInt64(v.AuxInt)
+		dst := v_0
+		src := v_1
+		mem := v_2
+		if !(s > 64 && s <= 16*64 && s%16 == 0 && logLargeCopy(v, s)) {
+			break
+		}
+		v.reset(OpAMD64DUFFCOPY)
+		v.AuxInt = int64ToAuxInt(s)
+		v.AddArg3(dst, src, mem)
+		return true
+	}
+	// match: (Move [s] dst src mem)
+	// cond: s > 16*64 && s%8 == 0 && logLargeCopy(v, s)
+	// result: (REPMOVSQ dst src (MOVQconst [s/8]) mem)
+	for {
+		s := auxIntToInt64(v.AuxInt)
+		dst := v_0
+		src := v_1
+		mem := v_2
+		if !(s > 16*64 && s%8 == 0 && logLargeCopy(v, s)) {
+			break
+		}
+		v.reset(OpAMD64REPMOVSQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
+		v0.AuxInt = int64ToAuxInt(s / 8)
+		v.AddArg4(dst, src, v0, mem)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpMulByPowOf2MaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulByPowOf2MaskedFloat32x16 x y mask)
+	// result: (VSCALEFPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VSCALEFPSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulByPowOf2MaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulByPowOf2MaskedFloat32x4 x y mask)
+	// result: (VSCALEFPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VSCALEFPSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulByPowOf2MaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulByPowOf2MaskedFloat32x8 x y mask)
+	// result: (VSCALEFPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VSCALEFPSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulByPowOf2MaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulByPowOf2MaskedFloat64x2 x y mask)
+	// result: (VSCALEFPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VSCALEFPDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulByPowOf2MaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulByPowOf2MaskedFloat64x4 x y mask)
+	// result: (VSCALEFPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VSCALEFPDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulByPowOf2MaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulByPowOf2MaskedFloat64x8 x y mask)
+	// result: (VSCALEFPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VSCALEFPDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulEvenWidenMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulEvenWidenMaskedInt64x2 x y mask)
+	// result: (VPMULDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULDQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulEvenWidenMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulEvenWidenMaskedInt64x4 x y mask)
+	// result: (VPMULDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULDQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulEvenWidenMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulEvenWidenMaskedInt64x8 x y mask)
+	// result: (VPMULDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULDQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulEvenWidenMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulEvenWidenMaskedUint64x2 x y mask)
+	// result: (VPMULUDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULUDQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulEvenWidenMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulEvenWidenMaskedUint64x4 x y mask)
+	// result: (VPMULUDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULUDQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulEvenWidenMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulEvenWidenMaskedUint64x8 x y mask)
+	// result: (VPMULUDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULUDQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulHighMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulHighMaskedInt16x16 x y mask)
+	// result: (VPMULHWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULHWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulHighMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulHighMaskedInt16x32 x y mask)
+	// result: (VPMULHWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULHWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulHighMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulHighMaskedInt16x8 x y mask)
+	// result: (VPMULHWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULHWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulHighMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulHighMaskedUint16x16 x y mask)
+	// result: (VPMULHUWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULHUWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulHighMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulHighMaskedUint16x32 x y mask)
+	// result: (VPMULHUWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULHUWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulHighMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulHighMaskedUint16x8 x y mask)
+	// result: (VPMULHUWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULHUWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulLowMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulLowMaskedInt16x16 x y mask)
+	// result: (VPMULLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULLWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulLowMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulLowMaskedInt16x32 x y mask)
+	// result: (VPMULLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULLWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulLowMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulLowMaskedInt16x8 x y mask)
+	// result: (VPMULLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULLWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulLowMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulLowMaskedInt32x16 x y mask)
+	// result: (VPMULLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULLDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulLowMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulLowMaskedInt32x4 x y mask)
+	// result: (VPMULLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULLDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulLowMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulLowMaskedInt32x8 x y mask)
+	// result: (VPMULLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULLDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulLowMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulLowMaskedInt64x2 x y mask)
+	// result: (VPMULLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULLQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulLowMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulLowMaskedInt64x4 x y mask)
+	// result: (VPMULLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULLQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulLowMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulLowMaskedInt64x8 x y mask)
+	// result: (VPMULLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMULLQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulMaskedFloat32x16 x y mask)
+	// result: (VMULPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMULPSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulMaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulMaskedFloat32x4 x y mask)
+	// result: (VMULPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMULPSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulMaskedFloat32x8 x y mask)
+	// result: (VMULPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMULPSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulMaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulMaskedFloat64x2 x y mask)
+	// result: (VMULPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMULPDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulMaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulMaskedFloat64x4 x y mask)
+	// result: (VMULPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMULPDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpMulMaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (MulMaskedFloat64x8 x y mask)
+	// result: (VMULPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VMULPDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNeg32F(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Neg32F x)
+	// result: (PXOR x (MOVSSconst <typ.Float32> [float32(math.Copysign(0, -1))]))
+	for {
+		x := v_0
+		v.reset(OpAMD64PXOR)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32)
+		v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1)))
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNeg64F(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Neg64F x)
+	// result: (PXOR x (MOVSDconst <typ.Float64> [math.Copysign(0, -1)]))
+	for {
+		x := v_0
+		v.reset(OpAMD64PXOR)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64)
+		v0.AuxInt = float64ToAuxInt(math.Copysign(0, -1))
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNeq16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Neq16 x y)
+	// result: (SETNE (CMPW x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETNE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNeq32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Neq32 x y)
+	// result: (SETNE (CMPL x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETNE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNeq32F(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Neq32F x y)
+	// result: (SETNEF (UCOMISS x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETNEF)
+		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNeq64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Neq64 x y)
+	// result: (SETNE (CMPQ x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETNE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNeq64F(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Neq64F x y)
+	// result: (SETNEF (UCOMISD x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETNEF)
+		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNeq8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Neq8 x y)
+	// result: (SETNE (CMPB x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETNE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNeqB(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (NeqB x y)
+	// result: (SETNE (CMPB x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETNE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNeqPtr(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (NeqPtr x y)
+	// result: (SETNE (CMPQ x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64SETNE)
+		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNot(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (Not x)
+	// result: (XORLconst [1] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64XORLconst)
+		v.AuxInt = int32ToAuxInt(1)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualFloat32x16 x y)
+	// result: (VPMOVMToVec32x16 (VCMPPS512 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (NotEqualFloat32x4 x y)
+	// result: (VCMPPS128 [4] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS128)
+		v.AuxInt = int8ToAuxInt(4)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (NotEqualFloat32x8 x y)
+	// result: (VCMPPS256 [4] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPS256)
+		v.AuxInt = int8ToAuxInt(4)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (NotEqualFloat64x2 x y)
+	// result: (VCMPPD128 [4] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD128)
+		v.AuxInt = int8ToAuxInt(4)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (NotEqualFloat64x4 x y)
+	// result: (VCMPPD256 [4] x y)
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VCMPPD256)
+		v.AuxInt = int8ToAuxInt(4)
+		v.AddArg2(x, y)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualFloat64x8 x y)
+	// result: (VPMOVMToVec64x8 (VCMPPD512 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualInt16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualInt16x16 x y)
+	// result: (VPMOVMToVec16x16 (VPCMPW256 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualInt16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualInt16x32 x y)
+	// result: (VPMOVMToVec16x32 (VPCMPW512 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualInt16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualInt16x8 x y)
+	// result: (VPMOVMToVec16x8 (VPCMPW128 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualInt32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualInt32x16 x y)
+	// result: (VPMOVMToVec32x16 (VPCMPD512 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualInt32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualInt32x4 x y)
+	// result: (VPMOVMToVec32x4 (VPCMPD128 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualInt32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualInt32x8 x y)
+	// result: (VPMOVMToVec32x8 (VPCMPD256 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualInt64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualInt64x2 x y)
+	// result: (VPMOVMToVec64x2 (VPCMPQ128 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualInt64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualInt64x4 x y)
+	// result: (VPMOVMToVec64x4 (VPCMPQ256 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualInt64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualInt64x8 x y)
+	// result: (VPMOVMToVec64x8 (VPCMPQ512 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualInt8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualInt8x16 x y)
+	// result: (VPMOVMToVec8x16 (VPCMPB128 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualInt8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualInt8x32 x y)
+	// result: (VPMOVMToVec8x32 (VPCMPB256 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualInt8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualInt8x64 x y)
+	// result: (VPMOVMToVec8x64 (VPCMPB512 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedFloat32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VCMPPSMasked512 [4] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedFloat32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VCMPPSMasked128 [4] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedFloat32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VCMPPSMasked256 [4] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedFloat64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VCMPPDMasked128 [4] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedFloat64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VCMPPDMasked256 [4] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedFloat64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VCMPPDMasked512 [4] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedInt16x16 x y mask)
+	// result: (VPMOVMToVec16x16 (VPCMPWMasked256 [4] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedInt16x32 x y mask)
+	// result: (VPMOVMToVec16x32 (VPCMPWMasked512 [4] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedInt16x8 x y mask)
+	// result: (VPMOVMToVec16x8 (VPCMPWMasked128 [4] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedInt32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VPCMPDMasked512 [4] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedInt32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VPCMPDMasked128 [4] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedInt32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VPCMPDMasked256 [4] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedInt64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VPCMPQMasked128 [4] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedInt64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VPCMPQMasked256 [4] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedInt64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VPCMPQMasked512 [4] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedInt8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedInt8x16 x y mask)
+	// result: (VPMOVMToVec8x16 (VPCMPBMasked128 [4] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedInt8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedInt8x32 x y mask)
+	// result: (VPMOVMToVec8x32 (VPCMPBMasked256 [4] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedInt8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedInt8x64 x y mask)
+	// result: (VPMOVMToVec8x64 (VPCMPBMasked512 [4] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedUint16x16 x y mask)
+	// result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [4] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedUint16x32 x y mask)
+	// result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [4] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedUint16x8 x y mask)
+	// result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [4] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedUint32x16 x y mask)
+	// result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [4] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedUint32x4 x y mask)
+	// result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [4] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedUint32x8 x y mask)
+	// result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [4] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedUint64x2 x y mask)
+	// result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [4] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedUint64x4 x y mask)
+	// result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [4] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedUint64x8 x y mask)
+	// result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [4] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedUint8x16 x y mask)
+	// result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [4] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedUint8x32 x y mask)
+	// result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [4] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualMaskedUint8x64 x y mask)
+	// result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [4] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v1.AddArg(mask)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualUint16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualUint16x16 x y)
+	// result: (VPMOVMToVec16x16 (VPCMPUW256 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualUint16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualUint16x32 x y)
+	// result: (VPMOVMToVec16x32 (VPCMPUW512 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualUint16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualUint16x8 x y)
+	// result: (VPMOVMToVec16x8 (VPCMPUW128 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec16x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualUint32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualUint32x16 x y)
+	// result: (VPMOVMToVec32x16 (VPCMPUD512 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualUint32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualUint32x4 x y)
+	// result: (VPMOVMToVec32x4 (VPCMPUD128 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualUint32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualUint32x8 x y)
+	// result: (VPMOVMToVec32x8 (VPCMPUD256 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec32x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualUint64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualUint64x2 x y)
+	// result: (VPMOVMToVec64x2 (VPCMPUQ128 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x2)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualUint64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualUint64x4 x y)
+	// result: (VPMOVMToVec64x4 (VPCMPUQ256 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x4)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualUint64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualUint64x8 x y)
+	// result: (VPMOVMToVec64x8 (VPCMPUQ512 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec64x8)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualUint8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualUint8x16 x y)
+	// result: (VPMOVMToVec8x16 (VPCMPUB128 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x16)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB128, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualUint8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualUint8x32 x y)
+	// result: (VPMOVMToVec8x32 (VPCMPUB256 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x32)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB256, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpNotEqualUint8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (NotEqualUint8x64 x y)
+	// result: (VPMOVMToVec8x64 (VPCMPUB512 [4] x y))
+	for {
+		x := v_0
+		y := v_1
+		v.reset(OpAMD64VPMOVMToVec8x64)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask)
+		v0.AuxInt = int8ToAuxInt(4)
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpOffPtr(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (OffPtr [off] ptr)
+	// cond: is32Bit(off)
+	// result: (ADDQconst [int32(off)] ptr)
+	for {
+		off := auxIntToInt64(v.AuxInt)
+		ptr := v_0
+		if !(is32Bit(off)) {
+			break
+		}
+		v.reset(OpAMD64ADDQconst)
+		v.AuxInt = int32ToAuxInt(int32(off))
+		v.AddArg(ptr)
+		return true
+	}
+	// match: (OffPtr [off] ptr)
+	// result: (ADDQ (MOVQconst [off]) ptr)
+	for {
+		off := auxIntToInt64(v.AuxInt)
+		ptr := v_0
+		v.reset(OpAMD64ADDQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
+		v0.AuxInt = int64ToAuxInt(off)
+		v.AddArg2(v0, ptr)
+		return true
+	}
+}
+func rewriteValueAMD64_OpOrMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (OrMaskedInt32x16 x y mask)
+	// result: (VPORDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPORDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpOrMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (OrMaskedInt32x4 x y mask)
+	// result: (VPORDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPORDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpOrMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (OrMaskedInt32x8 x y mask)
+	// result: (VPORDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPORDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpOrMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (OrMaskedInt64x2 x y mask)
+	// result: (VPORQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPORQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpOrMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (OrMaskedInt64x4 x y mask)
+	// result: (VPORQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPORQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpOrMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (OrMaskedInt64x8 x y mask)
+	// result: (VPORQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPORQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpOrMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (OrMaskedUint32x16 x y mask)
+	// result: (VPORDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPORDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpOrMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (OrMaskedUint32x4 x y mask)
+	// result: (VPORDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPORDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpOrMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (OrMaskedUint32x8 x y mask)
+	// result: (VPORDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPORDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpOrMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (OrMaskedUint64x2 x y mask)
+	// result: (VPORQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPORQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpOrMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (OrMaskedUint64x4 x y mask)
+	// result: (VPORQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPORQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpOrMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (OrMaskedUint64x8 x y mask)
+	// result: (VPORQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPORQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPairDotProdAccumulateMaskedInt32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PairDotProdAccumulateMaskedInt32x16 x y z mask)
+	// result: (VPDPWSSDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPDPWSSDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPairDotProdAccumulateMaskedInt32x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PairDotProdAccumulateMaskedInt32x4 x y z mask)
+	// result: (VPDPWSSDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPDPWSSDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPairDotProdAccumulateMaskedInt32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PairDotProdAccumulateMaskedInt32x8 x y z mask)
+	// result: (VPDPWSSDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPDPWSSDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPairDotProdMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PairDotProdMaskedInt16x16 x y mask)
+	// result: (VPMADDWDMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMADDWDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPairDotProdMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PairDotProdMaskedInt16x32 x y mask)
+	// result: (VPMADDWDMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMADDWDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPairDotProdMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PairDotProdMaskedInt16x8 x y mask)
+	// result: (VPMADDWDMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPMADDWDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPanicBounds(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	// match: (PanicBounds [kind] x y mem)
+	// cond: boundsABI(kind) == 0
+	// result: (LoweredPanicBoundsA [kind] x y mem)
+	for {
+		kind := auxIntToInt64(v.AuxInt)
+		x := v_0
+		y := v_1
+		mem := v_2
+		if !(boundsABI(kind) == 0) {
+			break
+		}
+		v.reset(OpAMD64LoweredPanicBoundsA)
+		v.AuxInt = int64ToAuxInt(kind)
+		v.AddArg3(x, y, mem)
+		return true
+	}
+	// match: (PanicBounds [kind] x y mem)
+	// cond: boundsABI(kind) == 1
+	// result: (LoweredPanicBoundsB [kind] x y mem)
+	for {
+		kind := auxIntToInt64(v.AuxInt)
+		x := v_0
+		y := v_1
+		mem := v_2
+		if !(boundsABI(kind) == 1) {
+			break
+		}
+		v.reset(OpAMD64LoweredPanicBoundsB)
+		v.AuxInt = int64ToAuxInt(kind)
+		v.AddArg3(x, y, mem)
+		return true
+	}
+	// match: (PanicBounds [kind] x y mem)
+	// cond: boundsABI(kind) == 2
+	// result: (LoweredPanicBoundsC [kind] x y mem)
+	for {
+		kind := auxIntToInt64(v.AuxInt)
+		x := v_0
+		y := v_1
+		mem := v_2
+		if !(boundsABI(kind) == 2) {
+			break
+		}
+		v.reset(OpAMD64LoweredPanicBoundsC)
+		v.AuxInt = int64ToAuxInt(kind)
+		v.AddArg3(x, y, mem)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpPermute2MaskedFloat32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedFloat32x16 x y z mask)
+	// result: (VPERMI2PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2PSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedFloat32x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedFloat32x4 x y z mask)
+	// result: (VPERMI2PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2PSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedFloat32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedFloat32x8 x y z mask)
+	// result: (VPERMI2PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2PSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedFloat64x2(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedFloat64x2 x y z mask)
+	// result: (VPERMI2PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2PDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedFloat64x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedFloat64x4 x y z mask)
+	// result: (VPERMI2PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2PDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedFloat64x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedFloat64x8 x y z mask)
+	// result: (VPERMI2PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2PDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedInt16x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedInt16x16 x y z mask)
+	// result: (VPERMI2WMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2WMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedInt16x32(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedInt16x32 x y z mask)
+	// result: (VPERMI2WMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2WMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedInt16x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedInt16x8 x y z mask)
+	// result: (VPERMI2WMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2WMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedInt32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedInt32x16 x y z mask)
+	// result: (VPERMI2DMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2DMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedInt32x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedInt32x4 x y z mask)
+	// result: (VPERMI2DMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2DMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedInt32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedInt32x8 x y z mask)
+	// result: (VPERMI2DMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2DMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedInt64x2(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedInt64x2 x y z mask)
+	// result: (VPERMI2QMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2QMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedInt64x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedInt64x4 x y z mask)
+	// result: (VPERMI2QMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2QMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedInt64x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedInt64x8 x y z mask)
+	// result: (VPERMI2QMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2QMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedInt8x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedInt8x16 x y z mask)
+	// result: (VPERMI2BMasked128 x y z (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2BMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedInt8x32(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedInt8x32 x y z mask)
+	// result: (VPERMI2BMasked256 x y z (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2BMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedInt8x64(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedInt8x64 x y z mask)
+	// result: (VPERMI2BMasked512 x y z (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2BMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedUint16x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedUint16x16 x y z mask)
+	// result: (VPERMI2WMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2WMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedUint16x32(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedUint16x32 x y z mask)
+	// result: (VPERMI2WMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2WMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedUint16x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedUint16x8 x y z mask)
+	// result: (VPERMI2WMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2WMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedUint32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedUint32x16 x y z mask)
+	// result: (VPERMI2DMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2DMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedUint32x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedUint32x4 x y z mask)
+	// result: (VPERMI2DMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2DMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedUint32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedUint32x8 x y z mask)
+	// result: (VPERMI2DMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2DMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedUint64x2(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedUint64x2 x y z mask)
+	// result: (VPERMI2QMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2QMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedUint64x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedUint64x4 x y z mask)
+	// result: (VPERMI2QMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2QMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedUint64x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedUint64x8 x y z mask)
+	// result: (VPERMI2QMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2QMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedUint8x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedUint8x16 x y z mask)
+	// result: (VPERMI2BMasked128 x y z (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2BMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedUint8x32(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedUint8x32 x y z mask)
+	// result: (VPERMI2BMasked256 x y z (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2BMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermute2MaskedUint8x64(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Permute2MaskedUint8x64 x y z mask)
+	// result: (VPERMI2BMasked512 x y z (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPERMI2BMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedFloat32x16 x y mask)
+	// result: (VPERMPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMPSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedFloat32x8 x y mask)
+	// result: (VPERMPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMPSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedFloat64x4 x y mask)
+	// result: (VPERMPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMPDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedFloat64x8 x y mask)
+	// result: (VPERMPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMPDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedInt16x16 x y mask)
+	// result: (VPERMWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedInt16x32 x y mask)
+	// result: (VPERMWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedInt16x8 x y mask)
+	// result: (VPERMWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedInt32x16 x y mask)
+	// result: (VPERMDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedInt32x8 x y mask)
+	// result: (VPERMDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedInt64x4 x y mask)
+	// result: (VPERMQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedInt64x8 x y mask)
+	// result: (VPERMQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedInt8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedInt8x16 x y mask)
+	// result: (VPERMBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedInt8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedInt8x32 x y mask)
+	// result: (VPERMBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedInt8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedInt8x64 x y mask)
+	// result: (VPERMBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedUint16x16 x y mask)
+	// result: (VPERMWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedUint16x32 x y mask)
+	// result: (VPERMWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedUint16x8 x y mask)
+	// result: (VPERMWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedUint32x16 x y mask)
+	// result: (VPERMDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedUint32x8 x y mask)
+	// result: (VPERMDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedUint64x4 x y mask)
+	// result: (VPERMQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedUint64x8 x y mask)
+	// result: (VPERMQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedUint8x16 x y mask)
+	// result: (VPERMBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedUint8x32 x y mask)
+	// result: (VPERMBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPermuteMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PermuteMaskedUint8x64 x y mask)
+	// result: (VPERMBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPERMBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCount16(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (PopCount16 x)
+	// result: (POPCNTL (MOVWQZX <typ.UInt32> x))
+	for {
+		x := v_0
+		v.reset(OpAMD64POPCNTL)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32)
+		v0.AddArg(x)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCount8(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (PopCount8 x)
+	// result: (POPCNTL (MOVBQZX <typ.UInt32> x))
+	for {
+		x := v_0
+		v.reset(OpAMD64POPCNTL)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32)
+		v0.AddArg(x)
+		v.AddArg(v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedInt16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedInt16x16 x mask)
+	// result: (VPOPCNTWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedInt16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedInt16x32 x mask)
+	// result: (VPOPCNTWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedInt16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedInt16x8 x mask)
+	// result: (VPOPCNTWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedInt32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedInt32x16 x mask)
+	// result: (VPOPCNTDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedInt32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedInt32x4 x mask)
+	// result: (VPOPCNTDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedInt32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedInt32x8 x mask)
+	// result: (VPOPCNTDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedInt64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedInt64x2 x mask)
+	// result: (VPOPCNTQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedInt64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedInt64x4 x mask)
+	// result: (VPOPCNTQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedInt64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedInt64x8 x mask)
+	// result: (VPOPCNTQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedInt8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedInt8x16 x mask)
+	// result: (VPOPCNTBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedInt8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedInt8x32 x mask)
+	// result: (VPOPCNTBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedInt8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedInt8x64 x mask)
+	// result: (VPOPCNTBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedUint16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedUint16x16 x mask)
+	// result: (VPOPCNTWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedUint16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedUint16x32 x mask)
+	// result: (VPOPCNTWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedUint16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedUint16x8 x mask)
+	// result: (VPOPCNTWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedUint32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedUint32x16 x mask)
+	// result: (VPOPCNTDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedUint32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedUint32x4 x mask)
+	// result: (VPOPCNTDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedUint32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedUint32x8 x mask)
+	// result: (VPOPCNTDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedUint64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedUint64x2 x mask)
+	// result: (VPOPCNTQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedUint64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedUint64x4 x mask)
+	// result: (VPOPCNTQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedUint64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedUint64x8 x mask)
+	// result: (VPOPCNTQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedUint8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedUint8x16 x mask)
+	// result: (VPOPCNTBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedUint8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedUint8x32 x mask)
+	// result: (VPOPCNTBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpPopCountMaskedUint8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (PopCountMaskedUint8x64 x mask)
+	// result: (VPOPCNTBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPOPCNTBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllLeftMaskedInt32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllLeftMaskedInt32x16 [a] x mask)
+	// result: (VPROLDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPROLDMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllLeftMaskedInt32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllLeftMaskedInt32x4 [a] x mask)
+	// result: (VPROLDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPROLDMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllLeftMaskedInt32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllLeftMaskedInt32x8 [a] x mask)
+	// result: (VPROLDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPROLDMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllLeftMaskedInt64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllLeftMaskedInt64x2 [a] x mask)
+	// result: (VPROLQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPROLQMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllLeftMaskedInt64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllLeftMaskedInt64x4 [a] x mask)
+	// result: (VPROLQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPROLQMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllLeftMaskedInt64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllLeftMaskedInt64x8 [a] x mask)
+	// result: (VPROLQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPROLQMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllLeftMaskedUint32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllLeftMaskedUint32x16 [a] x mask)
+	// result: (VPROLDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPROLDMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllLeftMaskedUint32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllLeftMaskedUint32x4 [a] x mask)
+	// result: (VPROLDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPROLDMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllLeftMaskedUint32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllLeftMaskedUint32x8 [a] x mask)
+	// result: (VPROLDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPROLDMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllLeftMaskedUint64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllLeftMaskedUint64x2 [a] x mask)
+	// result: (VPROLQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPROLQMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllLeftMaskedUint64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllLeftMaskedUint64x4 [a] x mask)
+	// result: (VPROLQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPROLQMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllLeftMaskedUint64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllLeftMaskedUint64x8 [a] x mask)
+	// result: (VPROLQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPROLQMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllRightMaskedInt32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllRightMaskedInt32x16 [a] x mask)
+	// result: (VPRORDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPRORDMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllRightMaskedInt32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllRightMaskedInt32x4 [a] x mask)
+	// result: (VPRORDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPRORDMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllRightMaskedInt32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllRightMaskedInt32x8 [a] x mask)
+	// result: (VPRORDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPRORDMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllRightMaskedInt64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllRightMaskedInt64x2 [a] x mask)
+	// result: (VPRORQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPRORQMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllRightMaskedInt64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllRightMaskedInt64x4 [a] x mask)
+	// result: (VPRORQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPRORQMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllRightMaskedInt64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllRightMaskedInt64x8 [a] x mask)
+	// result: (VPRORQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPRORQMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllRightMaskedUint32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllRightMaskedUint32x16 [a] x mask)
+	// result: (VPRORDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPRORDMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllRightMaskedUint32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllRightMaskedUint32x4 [a] x mask)
+	// result: (VPRORDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPRORDMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllRightMaskedUint32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllRightMaskedUint32x8 [a] x mask)
+	// result: (VPRORDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPRORDMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllRightMaskedUint64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllRightMaskedUint64x2 [a] x mask)
+	// result: (VPRORQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPRORQMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllRightMaskedUint64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllRightMaskedUint64x4 [a] x mask)
+	// result: (VPRORQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPRORQMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateAllRightMaskedUint64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateAllRightMaskedUint64x8 [a] x mask)
+	// result: (VPRORQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VPRORQMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateLeftMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateLeftMaskedInt32x16 x y mask)
+	// result: (VPROLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPROLVDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateLeftMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateLeftMaskedInt32x4 x y mask)
+	// result: (VPROLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPROLVDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateLeftMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateLeftMaskedInt32x8 x y mask)
+	// result: (VPROLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPROLVDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateLeftMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateLeftMaskedInt64x2 x y mask)
+	// result: (VPROLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPROLVQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateLeftMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateLeftMaskedInt64x4 x y mask)
+	// result: (VPROLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPROLVQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateLeftMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateLeftMaskedInt64x8 x y mask)
+	// result: (VPROLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPROLVQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateLeftMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateLeftMaskedUint32x16 x y mask)
+	// result: (VPROLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPROLVDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateLeftMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateLeftMaskedUint32x4 x y mask)
+	// result: (VPROLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPROLVDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateLeftMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateLeftMaskedUint32x8 x y mask)
+	// result: (VPROLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPROLVDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateLeftMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateLeftMaskedUint64x2 x y mask)
+	// result: (VPROLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPROLVQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateLeftMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateLeftMaskedUint64x4 x y mask)
+	// result: (VPROLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPROLVQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateLeftMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateLeftMaskedUint64x8 x y mask)
+	// result: (VPROLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPROLVQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateRightMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateRightMaskedInt32x16 x y mask)
+	// result: (VPRORVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPRORVDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateRightMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateRightMaskedInt32x4 x y mask)
+	// result: (VPRORVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPRORVDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateRightMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateRightMaskedInt32x8 x y mask)
+	// result: (VPRORVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPRORVDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateRightMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateRightMaskedInt64x2 x y mask)
+	// result: (VPRORVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPRORVQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateRightMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateRightMaskedInt64x4 x y mask)
+	// result: (VPRORVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPRORVQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateRightMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateRightMaskedInt64x8 x y mask)
+	// result: (VPRORVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPRORVQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateRightMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateRightMaskedUint32x16 x y mask)
+	// result: (VPRORVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPRORVDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateRightMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateRightMaskedUint32x4 x y mask)
+	// result: (VPRORVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPRORVDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateRightMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateRightMaskedUint32x8 x y mask)
+	// result: (VPRORVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPRORVDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateRightMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateRightMaskedUint64x2 x y mask)
+	// result: (VPRORVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPRORVQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateRightMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateRightMaskedUint64x4 x y mask)
+	// result: (VPRORVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPRORVQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRotateRightMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RotateRightMaskedUint64x8 x y mask)
+	// result: (VPRORVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPRORVQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundFloat32x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (RoundFloat32x4 x)
+	// result: (VROUNDPS128 [0] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64VROUNDPS128)
+		v.AuxInt = int8ToAuxInt(0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundFloat32x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (RoundFloat32x8 x)
+	// result: (VROUNDPS256 [0] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64VROUNDPS256)
+		v.AuxInt = int8ToAuxInt(0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundFloat64x2(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (RoundFloat64x2 x)
+	// result: (VROUNDPD128 [0] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64VROUNDPD128)
+		v.AuxInt = int8ToAuxInt(0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundFloat64x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (RoundFloat64x4 x)
+	// result: (VROUNDPD256 [0] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64VROUNDPD256)
+		v.AuxInt = int8ToAuxInt(0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundToEven(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (RoundToEven x)
+	// result: (ROUNDSD [0] x)
+	for {
+		x := v_0
+		v.reset(OpAMD64ROUNDSD)
+		v.AuxInt = int8ToAuxInt(0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundWithPrecisionFloat32x16(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (RoundWithPrecisionFloat32x16 [a] x)
+	// result: (VRNDSCALEPS512 [a+0] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPS512)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundWithPrecisionFloat32x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (RoundWithPrecisionFloat32x4 [a] x)
+	// result: (VRNDSCALEPS128 [a+0] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPS128)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundWithPrecisionFloat32x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (RoundWithPrecisionFloat32x8 [a] x)
+	// result: (VRNDSCALEPS256 [a+0] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPS256)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundWithPrecisionFloat64x2(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (RoundWithPrecisionFloat64x2 [a] x)
+	// result: (VRNDSCALEPD128 [a+0] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPD128)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundWithPrecisionFloat64x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (RoundWithPrecisionFloat64x4 [a] x)
+	// result: (VRNDSCALEPD256 [a+0] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPD256)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundWithPrecisionFloat64x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (RoundWithPrecisionFloat64x8 [a] x)
+	// result: (VRNDSCALEPD512 [a+0] x)
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPD512)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v.AddArg(x)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundWithPrecisionMaskedFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RoundWithPrecisionMaskedFloat32x16 [a] x mask)
+	// result: (VRNDSCALEPSMasked512 [a+0] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPSMasked512)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundWithPrecisionMaskedFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RoundWithPrecisionMaskedFloat32x4 [a] x mask)
+	// result: (VRNDSCALEPSMasked128 [a+0] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPSMasked128)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundWithPrecisionMaskedFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RoundWithPrecisionMaskedFloat32x8 [a] x mask)
+	// result: (VRNDSCALEPSMasked256 [a+0] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPSMasked256)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundWithPrecisionMaskedFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RoundWithPrecisionMaskedFloat64x2 [a] x mask)
+	// result: (VRNDSCALEPDMasked128 [a+0] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPDMasked128)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundWithPrecisionMaskedFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RoundWithPrecisionMaskedFloat64x4 [a] x mask)
+	// result: (VRNDSCALEPDMasked256 [a+0] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPDMasked256)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRoundWithPrecisionMaskedFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (RoundWithPrecisionMaskedFloat64x8 [a] x mask)
+	// result: (VRNDSCALEPDMasked512 [a+0] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+	for {
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPDMasked512)
+		v.AuxInt = int8ToAuxInt(a + 0)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh16Ux16 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPWconst y [16])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
+		v2.AuxInt = int16ToAuxInt(16)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh16Ux16 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRW x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRW)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh16Ux32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh16Ux32 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPLconst y [16])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(16)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh16Ux32 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRW x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRW)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh16Ux64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh16Ux64 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPQconst y [16])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(16)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh16Ux64 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRW x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRW)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh16Ux8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh16Ux8 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPBconst y [16])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
+		v2.AuxInt = int8ToAuxInt(16)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh16Ux8 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRW x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRW)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh16x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh16x16 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [16])))))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARW)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
+		v3.AuxInt = int16ToAuxInt(16)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
+		return true
+	}
+	// match: (Rsh16x16 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARW x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARW)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh16x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh16x32 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [16])))))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARW)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
+		v3.AuxInt = int32ToAuxInt(16)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
+		return true
+	}
+	// match: (Rsh16x32 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARW x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARW)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh16x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh16x64 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARW <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [16])))))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARW)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v3.AuxInt = int32ToAuxInt(16)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
+		return true
+	}
+	// match: (Rsh16x64 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARW x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARW)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh16x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh16x8 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [16])))))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARW)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
+		v3.AuxInt = int8ToAuxInt(16)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
+		return true
+	}
+	// match: (Rsh16x8 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARW x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARW)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh32Ux16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh32Ux16 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
+		v2.AuxInt = int16ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh32Ux16 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh32Ux32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh32Ux32 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh32Ux32 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh32Ux64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh32Ux64 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh32Ux64 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh32Ux8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh32Ux8 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
+		v2.AuxInt = int8ToAuxInt(32)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh32Ux8 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh32x16 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [32])))))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARL)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
+		v3.AuxInt = int16ToAuxInt(32)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
+		return true
+	}
+	// match: (Rsh32x16 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh32x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh32x32 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [32])))))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARL)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
+		v3.AuxInt = int32ToAuxInt(32)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
+		return true
+	}
+	// match: (Rsh32x32 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh32x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh32x64 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARL <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [32])))))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARL)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v3.AuxInt = int32ToAuxInt(32)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
+		return true
+	}
+	// match: (Rsh32x64 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh32x8 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [32])))))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARL)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
+		v3.AuxInt = int8ToAuxInt(32)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
+		return true
+	}
+	// match: (Rsh32x8 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARL x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARL)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh64Ux16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh64Ux16 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
+		v2.AuxInt = int16ToAuxInt(64)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh64Ux16 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRQ x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRQ)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh64Ux32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh64Ux32 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(64)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh64Ux32 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRQ x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRQ)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh64Ux64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh64Ux64 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(64)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh64Ux64 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRQ x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRQ)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh64Ux8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh64Ux8 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDQ)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
+		v2.AuxInt = int8ToAuxInt(64)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh64Ux8 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRQ x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRQ)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh64x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh64x16 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [64])))))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARQ)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
+		v3.AuxInt = int16ToAuxInt(64)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
+		return true
+	}
+	// match: (Rsh64x16 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARQ x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARQ)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh64x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh64x32 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [64])))))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARQ)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
+		v3.AuxInt = int32ToAuxInt(64)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
+		return true
+	}
+	// match: (Rsh64x32 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARQ x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARQ)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh64x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh64x64 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARQ <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [64])))))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARQ)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v3.AuxInt = int32ToAuxInt(64)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
+		return true
+	}
+	// match: (Rsh64x64 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARQ x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARQ)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh64x8 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [64])))))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARQ)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
+		v3.AuxInt = int8ToAuxInt(64)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
+		return true
+	}
+	// match: (Rsh64x8 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARQ x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SARQ)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh8Ux16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh8Ux16 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPWconst y [8])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
+		v2.AuxInt = int16ToAuxInt(8)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh8Ux16 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRB x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRB)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh8Ux32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh8Ux32 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPLconst y [8])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(8)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh8Ux32 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRB x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRB)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh8Ux64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh8Ux64 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPQconst y [8])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v2.AuxInt = int32ToAuxInt(8)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh8Ux64 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRB x y)
+	for {
+		x := v_0
+		y := v_1
+		if !(shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64SHRB)
+		v.AddArg2(x, y)
+		return true
+	}
+	return false
+}
+func rewriteValueAMD64_OpRsh8Ux8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh8Ux8 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPBconst y [8])))
+	for {
+		t := v.Type
+		x := v_0
+		y := v_1
+		if !(!shiftIsBounded(v)) {
+			break
+		}
+		v.reset(OpAMD64ANDL)
+		v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
+		v0.AddArg2(x, y)
+		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
+		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
+		v2.AuxInt = int8ToAuxInt(8)
+		v2.AddArg(y)
+		v1.AddArg(v2)
+		v.AddArg2(v0, v1)
+		return true
+	}
+	// match: (Rsh8Ux8 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SHRB x y)
+	for {
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETGEF {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is32BitInt(t)) {
+		if !(shiftIsBounded(v)) {
 			break
 		}
-		v.reset(OpAMD64CMOVLGEF)
-		v.AddArg3(y, x, cond)
+		v.reset(OpAMD64SHRB)
+		v.AddArg2(x, y)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETEQ cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWEQ y x cond)
+	return false
+}
+func rewriteValueAMD64_OpRsh8x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh8x16 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [8])))))
 	for {
 		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETEQ {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
+		if !(!shiftIsBounded(v)) {
 			break
 		}
-		v.reset(OpAMD64CMOVWEQ)
-		v.AddArg3(y, x, cond)
+		v.reset(OpAMD64SARB)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
+		v3.AuxInt = int16ToAuxInt(8)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETNE cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWNE y x cond)
+	// match: (Rsh8x16 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARB x y)
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETNE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
+		if !(shiftIsBounded(v)) {
 			break
 		}
-		v.reset(OpAMD64CMOVWNE)
-		v.AddArg3(y, x, cond)
+		v.reset(OpAMD64SARB)
+		v.AddArg2(x, y)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETL cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWLT y x cond)
+	return false
+}
+func rewriteValueAMD64_OpRsh8x32(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh8x32 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [8])))))
 	for {
 		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETL {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
+		if !(!shiftIsBounded(v)) {
 			break
 		}
-		v.reset(OpAMD64CMOVWLT)
-		v.AddArg3(y, x, cond)
+		v.reset(OpAMD64SARB)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
+		v3.AuxInt = int32ToAuxInt(8)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETG cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWGT y x cond)
+	// match: (Rsh8x32 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARB x y)
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETG {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
+		if !(shiftIsBounded(v)) {
 			break
 		}
-		v.reset(OpAMD64CMOVWGT)
-		v.AddArg3(y, x, cond)
+		v.reset(OpAMD64SARB)
+		v.AddArg2(x, y)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETLE cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWLE y x cond)
+	return false
+}
+func rewriteValueAMD64_OpRsh8x64(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh8x64 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARB <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [8])))))
 	for {
 		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETLE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
+		if !(!shiftIsBounded(v)) {
 			break
 		}
-		v.reset(OpAMD64CMOVWLE)
-		v.AddArg3(y, x, cond)
+		v.reset(OpAMD64SARB)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
+		v3.AuxInt = int32ToAuxInt(8)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETGE cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWGE y x cond)
+	// match: (Rsh8x64 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARB x y)
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETGE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
+		if !(shiftIsBounded(v)) {
 			break
 		}
-		v.reset(OpAMD64CMOVWGE)
-		v.AddArg3(y, x, cond)
+		v.reset(OpAMD64SARB)
+		v.AddArg2(x, y)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETA cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWHI y x cond)
+	return false
+}
+func rewriteValueAMD64_OpRsh8x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Rsh8x8 <t> x y)
+	// cond: !shiftIsBounded(v)
+	// result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [8])))))
 	for {
 		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETA {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
+		if !(!shiftIsBounded(v)) {
 			break
 		}
-		v.reset(OpAMD64CMOVWHI)
-		v.AddArg3(y, x, cond)
+		v.reset(OpAMD64SARB)
+		v.Type = t
+		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
+		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
+		v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
+		v3.AuxInt = int8ToAuxInt(8)
+		v3.AddArg(y)
+		v2.AddArg(v3)
+		v1.AddArg(v2)
+		v0.AddArg2(y, v1)
+		v.AddArg2(x, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETB cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWCS y x cond)
+	// match: (Rsh8x8 x y)
+	// cond: shiftIsBounded(v)
+	// result: (SARB x y)
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETB {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
+		if !(shiftIsBounded(v)) {
 			break
 		}
-		v.reset(OpAMD64CMOVWCS)
-		v.AddArg3(y, x, cond)
+		v.reset(OpAMD64SARB)
+		v.AddArg2(x, y)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETAE cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWCC y x cond)
+	return false
+}
+func rewriteValueAMD64_OpSaturatedAddMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedAddMaskedInt16x16 x y mask)
+	// result: (VPADDSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETAE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVWCC)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPADDSWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETBE cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWLS y x cond)
+}
+func rewriteValueAMD64_OpSaturatedAddMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedAddMaskedInt16x32 x y mask)
+	// result: (VPADDSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETBE {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVWLS)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPADDSWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETEQF cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWEQF y x cond)
+}
+func rewriteValueAMD64_OpSaturatedAddMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedAddMaskedInt16x8 x y mask)
+	// result: (VPADDSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETEQF {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVWEQF)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPADDSWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETNEF cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWNEF y x cond)
+}
+func rewriteValueAMD64_OpSaturatedAddMaskedInt8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedAddMaskedInt8x16 x y mask)
+	// result: (VPADDSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDSBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedAddMaskedInt8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedAddMaskedInt8x32 x y mask)
+	// result: (VPADDSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDSBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedAddMaskedInt8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedAddMaskedInt8x64 x y mask)
+	// result: (VPADDSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDSBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedAddMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedAddMaskedUint16x16 x y mask)
+	// result: (VPADDSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDSWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedAddMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedAddMaskedUint16x32 x y mask)
+	// result: (VPADDSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDSWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedAddMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedAddMaskedUint16x8 x y mask)
+	// result: (VPADDSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDSWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedAddMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedAddMaskedUint8x16 x y mask)
+	// result: (VPADDSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDSBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedAddMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedAddMaskedUint8x32 x y mask)
+	// result: (VPADDSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDSBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedAddMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedAddMaskedUint8x64 x y mask)
+	// result: (VPADDSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPADDSBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedPairDotProdAccumulateMaskedInt32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedPairDotProdAccumulateMaskedInt32x16 x y z mask)
+	// result: (VPDPWSSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPDPWSSDSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedPairDotProdAccumulateMaskedInt32x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedPairDotProdAccumulateMaskedInt32x4 x y z mask)
+	// result: (VPDPWSSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPDPWSSDSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedPairDotProdAccumulateMaskedInt32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedPairDotProdAccumulateMaskedInt32x8 x y z mask)
+	// result: (VPDPWSSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPDPWSSDSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedSubMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedSubMaskedInt16x16 x y mask)
+	// result: (VPSUBSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSUBSWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedSubMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedSubMaskedInt16x32 x y mask)
+	// result: (VPSUBSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSUBSWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedSubMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedSubMaskedInt16x8 x y mask)
+	// result: (VPSUBSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSUBSWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedSubMaskedInt8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedSubMaskedInt8x16 x y mask)
+	// result: (VPSUBSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSUBSBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedSubMaskedInt8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedSubMaskedInt8x32 x y mask)
+	// result: (VPSUBSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSUBSBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedSubMaskedInt8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedSubMaskedInt8x64 x y mask)
+	// result: (VPSUBSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSUBSBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedSubMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedSubMaskedUint16x16 x y mask)
+	// result: (VPSUBSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSUBSWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedSubMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedSubMaskedUint16x32 x y mask)
+	// result: (VPSUBSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSUBSWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedSubMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedSubMaskedUint16x8 x y mask)
+	// result: (VPSUBSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSUBSWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSaturatedSubMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedSubMaskedUint8x16 x y mask)
+	// result: (VPSUBSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETNEF {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVWNEF)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPSUBSBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETGF cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWGTF y x cond)
+}
+func rewriteValueAMD64_OpSaturatedSubMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedSubMaskedUint8x32 x y mask)
+	// result: (VPSUBSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETGF {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVWGTF)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPSUBSBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y (SETGEF cond))
-	// cond: is16BitInt(t)
-	// result: (CMOVWGEF y x cond)
+}
+func rewriteValueAMD64_OpSaturatedSubMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedSubMaskedUint8x64 x y mask)
+	// result: (VPSUBSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if v_2.Op != OpAMD64SETGEF {
-			break
-		}
-		cond := v_2.Args[0]
-		if !(is16BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVWGEF)
-		v.AddArg3(y, x, cond)
+		mask := v_2
+		v.reset(OpAMD64VPSUBSBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y check)
-	// cond: !check.Type.IsFlags() && check.Type.Size() == 1
-	// result: (CondSelect <t> x y (MOVBQZX <typ.UInt64> check))
+}
+func rewriteValueAMD64_OpSaturatedUnsignedSignedPairDotProdMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedUnsignedSignedPairDotProdMaskedUint8x16 x y mask)
+	// result: (VPMADDUBSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		check := v_2
-		if !(!check.Type.IsFlags() && check.Type.Size() == 1) {
-			break
-		}
-		v.reset(OpCondSelect)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64)
-		v0.AddArg(check)
+		mask := v_2
+		v.reset(OpAMD64VPMADDUBSWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
 		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y check)
-	// cond: !check.Type.IsFlags() && check.Type.Size() == 2
-	// result: (CondSelect <t> x y (MOVWQZX <typ.UInt64> check))
+}
+func rewriteValueAMD64_OpSaturatedUnsignedSignedPairDotProdMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedUnsignedSignedPairDotProdMaskedUint8x32 x y mask)
+	// result: (VPMADDUBSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		check := v_2
-		if !(!check.Type.IsFlags() && check.Type.Size() == 2) {
-			break
-		}
-		v.reset(OpCondSelect)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64)
-		v0.AddArg(check)
+		mask := v_2
+		v.reset(OpAMD64VPMADDUBSWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
 		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y check)
-	// cond: !check.Type.IsFlags() && check.Type.Size() == 4
-	// result: (CondSelect <t> x y (MOVLQZX <typ.UInt64> check))
+}
+func rewriteValueAMD64_OpSaturatedUnsignedSignedPairDotProdMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedUnsignedSignedPairDotProdMaskedUint8x64 x y mask)
+	// result: (VPMADDUBSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		check := v_2
-		if !(!check.Type.IsFlags() && check.Type.Size() == 4) {
-			break
-		}
-		v.reset(OpCondSelect)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64)
-		v0.AddArg(check)
+		mask := v_2
+		v.reset(OpAMD64VPMADDUBSWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
 		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y check)
-	// cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))
-	// result: (CMOVQNE y x (CMPQconst [0] check))
+}
+func rewriteValueAMD64_OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x16 x y z mask)
+	// result: (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		check := v_2
-		if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) {
-			break
-		}
-		v.reset(OpAMD64CMOVQNE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v0.AuxInt = int32ToAuxInt(0)
-		v0.AddArg(check)
-		v.AddArg3(y, x, v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPDPBUSDSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y check)
-	// cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)
-	// result: (CMOVLNE y x (CMPQconst [0] check))
+}
+func rewriteValueAMD64_OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4 x y z mask)
+	// result: (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		check := v_2
-		if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64CMOVLNE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v0.AuxInt = int32ToAuxInt(0)
-		v0.AddArg(check)
-		v.AddArg3(y, x, v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPDPBUSDSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	// match: (CondSelect <t> x y check)
-	// cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)
-	// result: (CMOVWNE y x (CMPQconst [0] check))
+}
+func rewriteValueAMD64_OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x8 x y z mask)
+	// result: (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		check := v_2
-		if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) {
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPDPBUSDSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
+		return true
+	}
+}
+func rewriteValueAMD64_OpSelect0(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (Select0 (Mul64uover x y))
+	// result: (Select0 <typ.UInt64> (MULQU x y))
+	for {
+		if v_0.Op != OpMul64uover {
 			break
 		}
-		v.reset(OpAMD64CMOVWNE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v0.AuxInt = int32ToAuxInt(0)
-		v0.AddArg(check)
-		v.AddArg3(y, x, v0)
+		y := v_0.Args[1]
+		x := v_0.Args[0]
+		v.reset(OpSelect0)
+		v.Type = typ.UInt64
+		v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags))
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
 		return true
 	}
-	return false
-}
-func rewriteValueAMD64_OpConst16(v *Value) bool {
-	// match: (Const16 [c])
-	// result: (MOVLconst [int32(c)])
+	// match: (Select0 (Mul32uover x y))
+	// result: (Select0 <typ.UInt32> (MULLU x y))
 	for {
-		c := auxIntToInt16(v.AuxInt)
-		v.reset(OpAMD64MOVLconst)
-		v.AuxInt = int32ToAuxInt(int32(c))
+		if v_0.Op != OpMul32uover {
+			break
+		}
+		y := v_0.Args[1]
+		x := v_0.Args[0]
+		v.reset(OpSelect0)
+		v.Type = typ.UInt32
+		v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags))
+		v0.AddArg2(x, y)
+		v.AddArg(v0)
 		return true
 	}
-}
-func rewriteValueAMD64_OpConst8(v *Value) bool {
-	// match: (Const8 [c])
-	// result: (MOVLconst [int32(c)])
+	// match: (Select0 (Add64carry x y c))
+	// result: (Select0 <typ.UInt64> (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
 	for {
-		c := auxIntToInt8(v.AuxInt)
-		v.reset(OpAMD64MOVLconst)
-		v.AuxInt = int32ToAuxInt(int32(c))
+		if v_0.Op != OpAdd64carry {
+			break
+		}
+		c := v_0.Args[2]
+		x := v_0.Args[0]
+		y := v_0.Args[1]
+		v.reset(OpSelect0)
+		v.Type = typ.UInt64
+		v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags))
+		v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
+		v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
+		v2.AddArg(c)
+		v1.AddArg(v2)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
 		return true
 	}
-}
-func rewriteValueAMD64_OpConstBool(v *Value) bool {
-	// match: (ConstBool [c])
-	// result: (MOVLconst [b2i32(c)])
+	// match: (Select0 (Sub64borrow x y c))
+	// result: (Select0 <typ.UInt64> (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
 	for {
-		c := auxIntToBool(v.AuxInt)
-		v.reset(OpAMD64MOVLconst)
-		v.AuxInt = int32ToAuxInt(b2i32(c))
+		if v_0.Op != OpSub64borrow {
+			break
+		}
+		c := v_0.Args[2]
+		x := v_0.Args[0]
+		y := v_0.Args[1]
+		v.reset(OpSelect0)
+		v.Type = typ.UInt64
+		v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags))
+		v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
+		v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
+		v2.AddArg(c)
+		v1.AddArg(v2)
+		v0.AddArg3(x, y, v1)
+		v.AddArg(v0)
 		return true
 	}
-}
-func rewriteValueAMD64_OpConstNil(v *Value) bool {
-	// match: (ConstNil )
-	// result: (MOVQconst [0])
+	// match: (Select0 <t> (AddTupleFirst32 val tuple))
+	// result: (ADDL val (Select0 <t> tuple))
 	for {
-		v.reset(OpAMD64MOVQconst)
-		v.AuxInt = int64ToAuxInt(0)
+		t := v.Type
+		if v_0.Op != OpAMD64AddTupleFirst32 {
+			break
+		}
+		tuple := v_0.Args[1]
+		val := v_0.Args[0]
+		v.reset(OpAMD64ADDL)
+		v0 := b.NewValue0(v.Pos, OpSelect0, t)
+		v0.AddArg(tuple)
+		v.AddArg2(val, v0)
 		return true
 	}
-}
-func rewriteValueAMD64_OpCtz16(v *Value) bool {
-	v_0 := v.Args[0]
-	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Ctz16 x)
-	// result: (BSFL (ORLconst <typ.UInt32> [1<<16] x))
+	// match: (Select0 <t> (AddTupleFirst64 val tuple))
+	// result: (ADDQ val (Select0 <t> tuple))
 	for {
-		x := v_0
-		v.reset(OpAMD64BSFL)
-		v0 := b.NewValue0(v.Pos, OpAMD64ORLconst, typ.UInt32)
-		v0.AuxInt = int32ToAuxInt(1 << 16)
-		v0.AddArg(x)
-		v.AddArg(v0)
+		t := v.Type
+		if v_0.Op != OpAMD64AddTupleFirst64 {
+			break
+		}
+		tuple := v_0.Args[1]
+		val := v_0.Args[0]
+		v.reset(OpAMD64ADDQ)
+		v0 := b.NewValue0(v.Pos, OpSelect0, t)
+		v0.AddArg(tuple)
+		v.AddArg2(val, v0)
 		return true
 	}
-}
-func rewriteValueAMD64_OpCtz16NonZero(v *Value) bool {
-	v_0 := v.Args[0]
-	// match: (Ctz16NonZero x)
-	// cond: buildcfg.GOAMD64 >= 3
-	// result: (TZCNTL x)
+	// match: (Select0 a:(ADDQconstflags [c] x))
+	// cond: a.Uses == 1
+	// result: (ADDQconst [c] x)
 	for {
-		x := v_0
-		if !(buildcfg.GOAMD64 >= 3) {
+		a := v_0
+		if a.Op != OpAMD64ADDQconstflags {
 			break
 		}
-		v.reset(OpAMD64TZCNTL)
+		c := auxIntToInt32(a.AuxInt)
+		x := a.Args[0]
+		if !(a.Uses == 1) {
+			break
+		}
+		v.reset(OpAMD64ADDQconst)
+		v.AuxInt = int32ToAuxInt(c)
 		v.AddArg(x)
 		return true
 	}
-	// match: (Ctz16NonZero x)
-	// cond: buildcfg.GOAMD64 < 3
-	// result: (BSFL x)
+	// match: (Select0 a:(ADDLconstflags [c] x))
+	// cond: a.Uses == 1
+	// result: (ADDLconst [c] x)
 	for {
-		x := v_0
-		if !(buildcfg.GOAMD64 < 3) {
+		a := v_0
+		if a.Op != OpAMD64ADDLconstflags {
 			break
 		}
-		v.reset(OpAMD64BSFL)
+		c := auxIntToInt32(a.AuxInt)
+		x := a.Args[0]
+		if !(a.Uses == 1) {
+			break
+		}
+		v.reset(OpAMD64ADDLconst)
+		v.AuxInt = int32ToAuxInt(c)
 		v.AddArg(x)
 		return true
 	}
 	return false
 }
-func rewriteValueAMD64_OpCtz32(v *Value) bool {
+func rewriteValueAMD64_OpSelect1(v *Value) bool {
 	v_0 := v.Args[0]
 	b := v.Block
 	typ := &b.Func.Config.Types
-	// match: (Ctz32 x)
-	// cond: buildcfg.GOAMD64 >= 3
-	// result: (TZCNTL x)
+	// match: (Select1 (Mul64uover x y))
+	// result: (SETO (Select1 <types.TypeFlags> (MULQU x y)))
 	for {
-		x := v_0
-		if !(buildcfg.GOAMD64 >= 3) {
+		if v_0.Op != OpMul64uover {
 			break
 		}
-		v.reset(OpAMD64TZCNTL)
-		v.AddArg(x)
+		y := v_0.Args[1]
+		x := v_0.Args[0]
+		v.reset(OpAMD64SETO)
+		v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
+		v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags))
+		v1.AddArg2(x, y)
+		v0.AddArg(v1)
+		v.AddArg(v0)
 		return true
 	}
-	// match: (Ctz32 x)
-	// cond: buildcfg.GOAMD64 < 3
-	// result: (Select0 (BSFQ (BTSQconst <typ.UInt64> [32] x)))
+	// match: (Select1 (Mul32uover x y))
+	// result: (SETO (Select1 <types.TypeFlags> (MULLU x y)))
 	for {
-		x := v_0
-		if !(buildcfg.GOAMD64 < 3) {
+		if v_0.Op != OpMul32uover {
 			break
 		}
-		v.reset(OpSelect0)
-		v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
-		v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64)
-		v1.AuxInt = int8ToAuxInt(32)
-		v1.AddArg(x)
+		y := v_0.Args[1]
+		x := v_0.Args[0]
+		v.reset(OpAMD64SETO)
+		v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
+		v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags))
+		v1.AddArg2(x, y)
 		v0.AddArg(v1)
 		v.AddArg(v0)
 		return true
 	}
-	return false
-}
-func rewriteValueAMD64_OpCtz32NonZero(v *Value) bool {
-	v_0 := v.Args[0]
-	// match: (Ctz32NonZero x)
-	// cond: buildcfg.GOAMD64 >= 3
-	// result: (TZCNTL x)
+	// match: (Select1 (Add64carry x y c))
+	// result: (NEGQ <typ.UInt64> (SBBQcarrymask <typ.UInt64> (Select1 <types.TypeFlags> (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
 	for {
-		x := v_0
-		if !(buildcfg.GOAMD64 >= 3) {
+		if v_0.Op != OpAdd64carry {
 			break
 		}
-		v.reset(OpAMD64TZCNTL)
-		v.AddArg(x)
+		c := v_0.Args[2]
+		x := v_0.Args[0]
+		y := v_0.Args[1]
+		v.reset(OpAMD64NEGQ)
+		v.Type = typ.UInt64
+		v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64)
+		v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
+		v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags))
+		v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
+		v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
+		v4.AddArg(c)
+		v3.AddArg(v4)
+		v2.AddArg3(x, y, v3)
+		v1.AddArg(v2)
+		v0.AddArg(v1)
+		v.AddArg(v0)
 		return true
 	}
-	// match: (Ctz32NonZero x)
-	// cond: buildcfg.GOAMD64 < 3
-	// result: (BSFL x)
+	// match: (Select1 (Sub64borrow x y c))
+	// result: (NEGQ <typ.UInt64> (SBBQcarrymask <typ.UInt64> (Select1 <types.TypeFlags> (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
 	for {
-		x := v_0
-		if !(buildcfg.GOAMD64 < 3) {
+		if v_0.Op != OpSub64borrow {
 			break
 		}
-		v.reset(OpAMD64BSFL)
-		v.AddArg(x)
+		c := v_0.Args[2]
+		x := v_0.Args[0]
+		y := v_0.Args[1]
+		v.reset(OpAMD64NEGQ)
+		v.Type = typ.UInt64
+		v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64)
+		v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
+		v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags))
+		v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
+		v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
+		v4.AddArg(c)
+		v3.AddArg(v4)
+		v2.AddArg3(x, y, v3)
+		v1.AddArg(v2)
+		v0.AddArg(v1)
+		v.AddArg(v0)
 		return true
 	}
-	return false
-}
-func rewriteValueAMD64_OpCtz64(v *Value) bool {
-	v_0 := v.Args[0]
-	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Ctz64 x)
-	// cond: buildcfg.GOAMD64 >= 3
-	// result: (TZCNTQ x)
+	// match: (Select1 (NEGLflags (MOVQconst [0])))
+	// result: (FlagEQ)
 	for {
-		x := v_0
-		if !(buildcfg.GOAMD64 >= 3) {
+		if v_0.Op != OpAMD64NEGLflags {
 			break
 		}
-		v.reset(OpAMD64TZCNTQ)
-		v.AddArg(x)
+		v_0_0 := v_0.Args[0]
+		if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 0 {
+			break
+		}
+		v.reset(OpAMD64FlagEQ)
 		return true
 	}
-	// match: (Ctz64 <t> x)
-	// cond: buildcfg.GOAMD64 < 3
-	// result: (CMOVQEQ (Select0 <t> (BSFQ x)) (MOVQconst <t> [64]) (Select1 <types.TypeFlags> (BSFQ x)))
+	// match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x))))
+	// result: x
 	for {
-		t := v.Type
-		x := v_0
-		if !(buildcfg.GOAMD64 < 3) {
+		if v_0.Op != OpAMD64NEGLflags {
+			break
+		}
+		v_0_0 := v_0.Args[0]
+		if v_0_0.Op != OpAMD64NEGQ {
+			break
+		}
+		v_0_0_0 := v_0_0.Args[0]
+		if v_0_0_0.Op != OpAMD64SBBQcarrymask {
+			break
+		}
+		x := v_0_0_0.Args[0]
+		v.copyOf(x)
+		return true
+	}
+	// match: (Select1 (AddTupleFirst32 _ tuple))
+	// result: (Select1 tuple)
+	for {
+		if v_0.Op != OpAMD64AddTupleFirst32 {
+			break
+		}
+		tuple := v_0.Args[1]
+		v.reset(OpSelect1)
+		v.AddArg(tuple)
+		return true
+	}
+	// match: (Select1 (AddTupleFirst64 _ tuple))
+	// result: (Select1 tuple)
+	for {
+		if v_0.Op != OpAMD64AddTupleFirst64 {
+			break
+		}
+		tuple := v_0.Args[1]
+		v.reset(OpSelect1)
+		v.AddArg(tuple)
+		return true
+	}
+	// match: (Select1 a:(LoweredAtomicAnd64 ptr val mem))
+	// cond: a.Uses == 1 && clobber(a)
+	// result: (ANDQlock ptr val mem)
+	for {
+		a := v_0
+		if a.Op != OpAMD64LoweredAtomicAnd64 {
+			break
+		}
+		mem := a.Args[2]
+		ptr := a.Args[0]
+		val := a.Args[1]
+		if !(a.Uses == 1 && clobber(a)) {
+			break
+		}
+		v.reset(OpAMD64ANDQlock)
+		v.AddArg3(ptr, val, mem)
+		return true
+	}
+	// match: (Select1 a:(LoweredAtomicAnd32 ptr val mem))
+	// cond: a.Uses == 1 && clobber(a)
+	// result: (ANDLlock ptr val mem)
+	for {
+		a := v_0
+		if a.Op != OpAMD64LoweredAtomicAnd32 {
 			break
 		}
-		v.reset(OpAMD64CMOVQEQ)
-		v0 := b.NewValue0(v.Pos, OpSelect0, t)
-		v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
-		v1.AddArg(x)
-		v0.AddArg(v1)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t)
-		v2.AuxInt = int64ToAuxInt(64)
-		v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
-		v3.AddArg(v1)
-		v.AddArg3(v0, v2, v3)
+		mem := a.Args[2]
+		ptr := a.Args[0]
+		val := a.Args[1]
+		if !(a.Uses == 1 && clobber(a)) {
+			break
+		}
+		v.reset(OpAMD64ANDLlock)
+		v.AddArg3(ptr, val, mem)
 		return true
 	}
-	return false
-}
-func rewriteValueAMD64_OpCtz64NonZero(v *Value) bool {
-	v_0 := v.Args[0]
-	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Ctz64NonZero x)
-	// cond: buildcfg.GOAMD64 >= 3
-	// result: (TZCNTQ x)
+	// match: (Select1 a:(LoweredAtomicOr64 ptr val mem))
+	// cond: a.Uses == 1 && clobber(a)
+	// result: (ORQlock ptr val mem)
 	for {
-		x := v_0
-		if !(buildcfg.GOAMD64 >= 3) {
+		a := v_0
+		if a.Op != OpAMD64LoweredAtomicOr64 {
 			break
 		}
-		v.reset(OpAMD64TZCNTQ)
-		v.AddArg(x)
+		mem := a.Args[2]
+		ptr := a.Args[0]
+		val := a.Args[1]
+		if !(a.Uses == 1 && clobber(a)) {
+			break
+		}
+		v.reset(OpAMD64ORQlock)
+		v.AddArg3(ptr, val, mem)
 		return true
 	}
-	// match: (Ctz64NonZero x)
-	// cond: buildcfg.GOAMD64 < 3
-	// result: (Select0 (BSFQ x))
+	// match: (Select1 a:(LoweredAtomicOr32 ptr val mem))
+	// cond: a.Uses == 1 && clobber(a)
+	// result: (ORLlock ptr val mem)
 	for {
-		x := v_0
-		if !(buildcfg.GOAMD64 < 3) {
+		a := v_0
+		if a.Op != OpAMD64LoweredAtomicOr32 {
 			break
 		}
-		v.reset(OpSelect0)
-		v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
-		v0.AddArg(x)
-		v.AddArg(v0)
+		mem := a.Args[2]
+		ptr := a.Args[0]
+		val := a.Args[1]
+		if !(a.Uses == 1 && clobber(a)) {
+			break
+		}
+		v.reset(OpAMD64ORLlock)
+		v.AddArg3(ptr, val, mem)
 		return true
 	}
 	return false
 }
-func rewriteValueAMD64_OpCtz8(v *Value) bool {
+func rewriteValueAMD64_OpSelectN(v *Value) bool {
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Ctz8 x)
-	// result: (BSFL (ORLconst <typ.UInt32> [1<<8 ] x))
-	for {
-		x := v_0
-		v.reset(OpAMD64BSFL)
-		v0 := b.NewValue0(v.Pos, OpAMD64ORLconst, typ.UInt32)
-		v0.AuxInt = int32ToAuxInt(1 << 8)
-		v0.AddArg(x)
-		v.AddArg(v0)
-		return true
-	}
-}
-func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool {
-	v_0 := v.Args[0]
-	// match: (Ctz8NonZero x)
-	// cond: buildcfg.GOAMD64 >= 3
-	// result: (TZCNTL x)
+	config := b.Func.Config
+	// match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem)))))
+	// cond: sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)
+	// result: (Move [sc.Val64()] dst src mem)
 	for {
-		x := v_0
-		if !(buildcfg.GOAMD64 >= 3) {
+		if auxIntToInt64(v.AuxInt) != 0 {
 			break
 		}
-		v.reset(OpAMD64TZCNTL)
-		v.AddArg(x)
+		call := v_0
+		if call.Op != OpAMD64CALLstatic || len(call.Args) != 1 {
+			break
+		}
+		sym := auxToCall(call.Aux)
+		s1 := call.Args[0]
+		if s1.Op != OpAMD64MOVQstoreconst {
+			break
+		}
+		sc := auxIntToValAndOff(s1.AuxInt)
+		_ = s1.Args[1]
+		s2 := s1.Args[1]
+		if s2.Op != OpAMD64MOVQstore {
+			break
+		}
+		_ = s2.Args[2]
+		src := s2.Args[1]
+		s3 := s2.Args[2]
+		if s3.Op != OpAMD64MOVQstore {
+			break
+		}
+		mem := s3.Args[2]
+		dst := s3.Args[1]
+		if !(sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)) {
+			break
+		}
+		v.reset(OpMove)
+		v.AuxInt = int64ToAuxInt(sc.Val64())
+		v.AddArg3(dst, src, mem)
 		return true
 	}
-	// match: (Ctz8NonZero x)
-	// cond: buildcfg.GOAMD64 < 3
-	// result: (BSFL x)
+	// match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem))
+	// cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)
+	// result: (Move [sz] dst src mem)
 	for {
-		x := v_0
-		if !(buildcfg.GOAMD64 < 3) {
+		if auxIntToInt64(v.AuxInt) != 0 {
 			break
 		}
-		v.reset(OpAMD64BSFL)
-		v.AddArg(x)
+		call := v_0
+		if call.Op != OpAMD64CALLstatic || len(call.Args) != 4 {
+			break
+		}
+		sym := auxToCall(call.Aux)
+		mem := call.Args[3]
+		dst := call.Args[0]
+		src := call.Args[1]
+		call_2 := call.Args[2]
+		if call_2.Op != OpAMD64MOVQconst {
+			break
+		}
+		sz := auxIntToInt64(call_2.AuxInt)
+		if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) {
+			break
+		}
+		v.reset(OpMove)
+		v.AuxInt = int64ToAuxInt(sz)
+		v.AddArg3(dst, src, mem)
 		return true
 	}
 	return false
 }
-func rewriteValueAMD64_OpDiv16(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Div16 [a] x y)
-	// result: (Select0 (DIVW [a] x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedInt16x16 [a] x y mask)
+	// result: (VPSHLDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		a := auxIntToBool(v.AuxInt)
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpSelect0)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
-		v0.AuxInt = boolToAuxInt(a)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDWMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpDiv16u(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Div16u x y)
-	// result: (Select0 (DIVWU x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedInt16x32 [a] x y mask)
+	// result: (VPSHLDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpSelect0)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDWMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpDiv32(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Div32 [a] x y)
-	// result: (Select0 (DIVL [a] x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedInt16x8 [a] x y mask)
+	// result: (VPSHLDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
-		a := auxIntToBool(v.AuxInt)
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpSelect0)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32))
-		v0.AuxInt = boolToAuxInt(a)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDWMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpDiv32u(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Div32u x y)
-	// result: (Select0 (DIVLU x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedInt32x16 [a] x y mask)
+	// result: (VPSHLDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpSelect0)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32))
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDDMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpDiv64(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Div64 [a] x y)
-	// result: (Select0 (DIVQ [a] x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedInt32x4 [a] x y mask)
+	// result: (VPSHLDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		a := auxIntToBool(v.AuxInt)
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpSelect0)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64))
-		v0.AuxInt = boolToAuxInt(a)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDDMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpDiv64u(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Div64u x y)
-	// result: (Select0 (DIVQU x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedInt32x8 [a] x y mask)
+	// result: (VPSHLDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpSelect0)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64))
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDDMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpDiv8(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Div8 x y)
-	// result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedInt64x2 [a] x y mask)
+	// result: (VPSHLDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpSelect0)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
-		v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
-		v1.AddArg(x)
-		v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
-		v2.AddArg(y)
-		v0.AddArg2(v1, v2)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDQMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpDiv8u(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Div8u x y)
-	// result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedInt64x4 [a] x y mask)
+	// result: (VPSHLDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpSelect0)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
-		v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
-		v1.AddArg(x)
-		v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
-		v2.AddArg(y)
-		v0.AddArg2(v1, v2)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDQMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpEq16(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Eq16 x y)
-	// result: (SETEQ (CMPW x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedInt64x8 [a] x y mask)
+	// result: (VPSHLDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETEQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDQMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpEq32(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Eq32 x y)
-	// result: (SETEQ (CMPL x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedUint16x16 [a] x y mask)
+	// result: (VPSHLDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETEQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDWMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpEq32F(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Eq32F x y)
-	// result: (SETEQF (UCOMISS x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedUint16x32 [a] x y mask)
+	// result: (VPSHLDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETEQF)
-		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDWMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpEq64(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Eq64 x y)
-	// result: (SETEQ (CMPQ x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedUint16x8 [a] x y mask)
+	// result: (VPSHLDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETEQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDWMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpEq64F(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Eq64F x y)
-	// result: (SETEQF (UCOMISD x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedUint32x16 [a] x y mask)
+	// result: (VPSHLDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETEQF)
-		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDDMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpEq8(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Eq8 x y)
-	// result: (SETEQ (CMPB x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedUint32x4 [a] x y mask)
+	// result: (VPSHLDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETEQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDDMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpEqB(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (EqB x y)
-	// result: (SETEQ (CMPB x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedUint32x8 [a] x y mask)
+	// result: (VPSHLDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETEQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDDMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpEqPtr(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (EqPtr x y)
-	// result: (SETEQ (CMPQ x y))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedUint64x2 [a] x y mask)
+	// result: (VPSHLDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETEQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDQMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpFMA(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint64x4(v *Value) bool {
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (FMA x y z)
-	// result: (VFMADD231SD z x y)
+	b := v.Block
+	// match: (ShiftAllLeftAndFillUpperFromMaskedUint64x4 [a] x y mask)
+	// result: (VPSHLDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		z := v_2
-		v.reset(OpAMD64VFMADD231SD)
-		v.AddArg3(z, x, y)
-		return true
-	}
-}
-func rewriteValueAMD64_OpFloor(v *Value) bool {
-	v_0 := v.Args[0]
-	// match: (Floor x)
-	// result: (ROUNDSD [1] x)
-	for {
-		x := v_0
-		v.reset(OpAMD64ROUNDSD)
-		v.AuxInt = int8ToAuxInt(1)
-		v.AddArg(x)
+		mask := v_2
+		v.reset(OpAMD64VPSHLDQMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpGetG(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (GetG mem)
-	// cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal
-	// result: (LoweredGetG mem)
-	for {
-		mem := v_0
-		if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) {
-			break
-		}
-		v.reset(OpAMD64LoweredGetG)
-		v.AddArg(mem)
-		return true
-	}
-	return false
-}
-func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool {
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (HasCPUFeature {s})
-	// result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s})))
+	// match: (ShiftAllLeftAndFillUpperFromMaskedUint64x8 [a] x y mask)
+	// result: (VPSHLDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		s := auxToSym(v.Aux)
-		v.reset(OpAMD64SETNE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
-		v0.AuxInt = int32ToAuxInt(0)
-		v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64)
-		v1.Aux = symToAux(s)
-		v0.AddArg(v1)
-		v.AddArg(v0)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSHLDQMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpIsInBounds(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (IsInBounds idx len)
-	// result: (SETB (CMPQ idx len))
+	// match: (ShiftAllLeftMaskedInt16x16 x y mask)
+	// result: (VPSLLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		idx := v_0
-		len := v_1
-		v.reset(OpAMD64SETB)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
-		v0.AddArg2(idx, len)
-		v.AddArg(v0)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpIsNonNil(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (IsNonNil p)
-	// result: (SETNE (TESTQ p p))
+	// match: (ShiftAllLeftMaskedInt16x32 x y mask)
+	// result: (VPSLLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
-		p := v_0
-		v.reset(OpAMD64SETNE)
-		v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags)
-		v0.AddArg2(p, p)
-		v.AddArg(v0)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (IsSliceInBounds idx len)
-	// result: (SETBE (CMPQ idx len))
+	// match: (ShiftAllLeftMaskedInt16x8 x y mask)
+	// result: (VPSLLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
-		idx := v_0
-		len := v_1
-		v.reset(OpAMD64SETBE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
-		v0.AddArg2(idx, len)
-		v.AddArg(v0)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLeq16(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Leq16 x y)
-	// result: (SETLE (CMPW x y))
+	// match: (ShiftAllLeftMaskedInt32x16 x y mask)
+	// result: (VPSLLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETLE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLeq16U(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Leq16U x y)
-	// result: (SETBE (CMPW x y))
+	// match: (ShiftAllLeftMaskedInt32x4 x y mask)
+	// result: (VPSLLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETBE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLeq32(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Leq32 x y)
-	// result: (SETLE (CMPL x y))
+	// match: (ShiftAllLeftMaskedInt32x8 x y mask)
+	// result: (VPSLLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETLE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLeq32F(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Leq32F x y)
-	// result: (SETGEF (UCOMISS y x))
+	// match: (ShiftAllLeftMaskedInt64x2 x y mask)
+	// result: (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETGEF)
-		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
-		v0.AddArg2(y, x)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLeq32U(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Leq32U x y)
-	// result: (SETBE (CMPL x y))
+	// match: (ShiftAllLeftMaskedInt64x4 x y mask)
+	// result: (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETBE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLeq64(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Leq64 x y)
-	// result: (SETLE (CMPQ x y))
+	// match: (ShiftAllLeftMaskedInt64x8 x y mask)
+	// result: (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETLE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLeq64F(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Leq64F x y)
-	// result: (SETGEF (UCOMISD y x))
+	// match: (ShiftAllLeftMaskedUint16x16 x y mask)
+	// result: (VPSLLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETGEF)
-		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
-		v0.AddArg2(y, x)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLeq64U(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Leq64U x y)
-	// result: (SETBE (CMPQ x y))
+	// match: (ShiftAllLeftMaskedUint16x32 x y mask)
+	// result: (VPSLLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETBE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLeq8(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Leq8 x y)
-	// result: (SETLE (CMPB x y))
+	// match: (ShiftAllLeftMaskedUint16x8 x y mask)
+	// result: (VPSLLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETLE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLeq8U(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Leq8U x y)
-	// result: (SETBE (CMPB x y))
+	// match: (ShiftAllLeftMaskedUint32x16 x y mask)
+	// result: (VPSLLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETBE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLess16(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Less16 x y)
-	// result: (SETL (CMPW x y))
+	// match: (ShiftAllLeftMaskedUint32x4 x y mask)
+	// result: (VPSLLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		y := v_1
-		v.reset(OpAMD64SETL)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLess16U(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Less16U x y)
-	// result: (SETB (CMPW x y))
+	// match: (ShiftAllLeftMaskedUint32x8 x y mask)
+	// result: (VPSLLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETB)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLess32(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Less32 x y)
-	// result: (SETL (CMPL x y))
+	// match: (ShiftAllLeftMaskedUint64x2 x y mask)
+	// result: (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETL)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLess32F(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Less32F x y)
-	// result: (SETGF (UCOMISS y x))
+	// match: (ShiftAllLeftMaskedUint64x4 x y mask)
+	// result: (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETGF)
-		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
-		v0.AddArg2(y, x)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLess32U(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllLeftMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Less32U x y)
-	// result: (SETB (CMPL x y))
+	// match: (ShiftAllLeftMaskedUint64x8 x y mask)
+	// result: (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETB)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSLLQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLess64(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Less64 x y)
-	// result: (SETL (CMPQ x y))
+	// match: (ShiftAllRightAndFillUpperFromMaskedInt16x16 [a] x y mask)
+	// result: (VPSHRDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETL)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDWMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLess64F(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Less64F x y)
-	// result: (SETGF (UCOMISD y x))
+	// match: (ShiftAllRightAndFillUpperFromMaskedInt16x32 [a] x y mask)
+	// result: (VPSHRDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETGF)
-		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
-		v0.AddArg2(y, x)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDWMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLess64U(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Less64U x y)
-	// result: (SETB (CMPQ x y))
+	// match: (ShiftAllRightAndFillUpperFromMaskedInt16x8 [a] x y mask)
+	// result: (VPSHRDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETB)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDWMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLess8(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Less8 x y)
-	// result: (SETL (CMPB x y))
+	// match: (ShiftAllRightAndFillUpperFromMaskedInt32x16 [a] x y mask)
+	// result: (VPSHRDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETL)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDDMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLess8U(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Less8U x y)
-	// result: (SETB (CMPB x y))
+	// match: (ShiftAllRightAndFillUpperFromMaskedInt32x4 [a] x y mask)
+	// result: (VPSHRDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETB)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDDMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpLoad(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (Load <t> ptr mem)
-	// cond: (is64BitInt(t) || isPtr(t))
-	// result: (MOVQload ptr mem)
-	for {
-		t := v.Type
-		ptr := v_0
-		mem := v_1
-		if !(is64BitInt(t) || isPtr(t)) {
-			break
-		}
-		v.reset(OpAMD64MOVQload)
-		v.AddArg2(ptr, mem)
-		return true
-	}
-	// match: (Load <t> ptr mem)
-	// cond: is32BitInt(t)
-	// result: (MOVLload ptr mem)
-	for {
-		t := v.Type
-		ptr := v_0
-		mem := v_1
-		if !(is32BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64MOVLload)
-		v.AddArg2(ptr, mem)
-		return true
-	}
-	// match: (Load <t> ptr mem)
-	// cond: is16BitInt(t)
-	// result: (MOVWload ptr mem)
-	for {
-		t := v.Type
-		ptr := v_0
-		mem := v_1
-		if !(is16BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64MOVWload)
-		v.AddArg2(ptr, mem)
-		return true
-	}
-	// match: (Load <t> ptr mem)
-	// cond: (t.IsBoolean() || is8BitInt(t))
-	// result: (MOVBload ptr mem)
-	for {
-		t := v.Type
-		ptr := v_0
-		mem := v_1
-		if !(t.IsBoolean() || is8BitInt(t)) {
-			break
-		}
-		v.reset(OpAMD64MOVBload)
-		v.AddArg2(ptr, mem)
-		return true
-	}
-	// match: (Load <t> ptr mem)
-	// cond: is32BitFloat(t)
-	// result: (MOVSSload ptr mem)
-	for {
-		t := v.Type
-		ptr := v_0
-		mem := v_1
-		if !(is32BitFloat(t)) {
-			break
-		}
-		v.reset(OpAMD64MOVSSload)
-		v.AddArg2(ptr, mem)
-		return true
-	}
-	// match: (Load <t> ptr mem)
-	// cond: is64BitFloat(t)
-	// result: (MOVSDload ptr mem)
+	b := v.Block
+	// match: (ShiftAllRightAndFillUpperFromMaskedInt32x8 [a] x y mask)
+	// result: (VPSHRDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
-		ptr := v_0
-		mem := v_1
-		if !(is64BitFloat(t)) {
-			break
-		}
-		v.reset(OpAMD64MOVSDload)
-		v.AddArg2(ptr, mem)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSHRDDMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLocalAddr(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (LocalAddr <t> {sym} base mem)
-	// cond: t.Elem().HasPointers()
-	// result: (LEAQ {sym} (SPanchored base mem))
-	for {
-		t := v.Type
-		sym := auxToSym(v.Aux)
-		base := v_0
-		mem := v_1
-		if !(t.Elem().HasPointers()) {
-			break
-		}
-		v.reset(OpAMD64LEAQ)
-		v.Aux = symToAux(sym)
-		v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr)
-		v0.AddArg2(base, mem)
-		v.AddArg(v0)
-		return true
-	}
-	// match: (LocalAddr <t> {sym} base _)
-	// cond: !t.Elem().HasPointers()
-	// result: (LEAQ {sym} base)
+	// match: (ShiftAllRightAndFillUpperFromMaskedInt64x2 [a] x y mask)
+	// result: (VPSHRDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
-		sym := auxToSym(v.Aux)
-		base := v_0
-		if !(!t.Elem().HasPointers()) {
-			break
-		}
-		v.reset(OpAMD64LEAQ)
-		v.Aux = symToAux(sym)
-		v.AddArg(base)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSHRDQMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh16x16(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh16x16 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
+	// match: (ShiftAllRightAndFillUpperFromMaskedInt64x4 [a] x y mask)
+	// result: (VPSHRDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
-		v2.AuxInt = int16ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDQMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh16x16 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLL x y)
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightAndFillUpperFromMaskedInt64x8 [a] x y mask)
+	// result: (VPSHRDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLL)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDQMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh16x32(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh16x32 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
+	// match: (ShiftAllRightAndFillUpperFromMaskedUint16x16 [a] x y mask)
+	// result: (VPSHRDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDWMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh16x32 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLL x y)
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightAndFillUpperFromMaskedUint16x32 [a] x y mask)
+	// result: (VPSHRDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLL)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDWMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh16x64(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh16x64 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
+	// match: (ShiftAllRightAndFillUpperFromMaskedUint16x8 [a] x y mask)
+	// result: (VPSHRDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDWMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh16x64 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLL x y)
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightAndFillUpperFromMaskedUint32x16 [a] x y mask)
+	// result: (VPSHRDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLL)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDDMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh16x8(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh16x8 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
+	// match: (ShiftAllRightAndFillUpperFromMaskedUint32x4 [a] x y mask)
+	// result: (VPSHRDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
-		v2.AuxInt = int8ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDDMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh16x8 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLL x y)
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightAndFillUpperFromMaskedUint32x8 [a] x y mask)
+	// result: (VPSHRDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLL)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDDMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh32x16(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh32x16 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
+	// match: (ShiftAllRightAndFillUpperFromMaskedUint64x2 [a] x y mask)
+	// result: (VPSHRDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
-		v2.AuxInt = int16ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDQMasked128)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh32x16 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLL x y)
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightAndFillUpperFromMaskedUint64x4 [a] x y mask)
+	// result: (VPSHRDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLL)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDQMasked256)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh32x32(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh32x32 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
+	// match: (ShiftAllRightAndFillUpperFromMaskedUint64x8 [a] x y mask)
+	// result: (VPSHRDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
+		a := auxIntToInt8(v.AuxInt)
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSHRDQMasked512)
+		v.AuxInt = int8ToAuxInt(a)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh32x32 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLL x y)
+}
+func rewriteValueAMD64_OpShiftAllRightMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightMaskedInt16x16 x y mask)
+	// result: (VPSRAWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLL)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRAWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh32x64(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh32x64 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
+	// match: (ShiftAllRightMaskedInt16x32 x y mask)
+	// result: (VPSRAWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRAWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh32x64 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLL x y)
+}
+func rewriteValueAMD64_OpShiftAllRightMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightMaskedInt16x8 x y mask)
+	// result: (VPSRAWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLL)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRAWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh32x8(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh32x8 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
+	// match: (ShiftAllRightMaskedInt32x16 x y mask)
+	// result: (VPSRADMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
-		v2.AuxInt = int8ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRADMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh32x8 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLL x y)
+}
+func rewriteValueAMD64_OpShiftAllRightMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightMaskedInt32x4 x y mask)
+	// result: (VPSRADMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLL)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRADMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh64x16(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh64x16 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64])))
+	// match: (ShiftAllRightMaskedInt32x8 x y mask)
+	// result: (VPSRADMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
-		v2.AuxInt = int16ToAuxInt(64)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRADMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh64x16 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLQ x y)
+}
+func rewriteValueAMD64_OpShiftAllRightMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightMaskedInt64x2 x y mask)
+	// result: (VPSRAQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLQ)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRAQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh64x32(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh64x32 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64])))
+	// match: (ShiftAllRightMaskedInt64x4 x y mask)
+	// result: (VPSRAQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(64)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRAQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh64x32 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLQ x y)
+}
+func rewriteValueAMD64_OpShiftAllRightMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightMaskedInt64x8 x y mask)
+	// result: (VPSRAQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLQ)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRAQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh64x64(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh64x64 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64])))
+	// match: (ShiftAllRightMaskedUint16x16 x y mask)
+	// result: (VPSRLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(64)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRLWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh64x64 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLQ x y)
+}
+func rewriteValueAMD64_OpShiftAllRightMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightMaskedUint16x32 x y mask)
+	// result: (VPSRLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLQ)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRLWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh64x8(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh64x8 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64])))
+	// match: (ShiftAllRightMaskedUint16x8 x y mask)
+	// result: (VPSRLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
-		v2.AuxInt = int8ToAuxInt(64)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRLWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh64x8 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLQ x y)
+}
+func rewriteValueAMD64_OpShiftAllRightMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightMaskedUint32x16 x y mask)
+	// result: (VPSRLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLQ)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRLDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh8x16(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh8x16 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
+	// match: (ShiftAllRightMaskedUint32x4 x y mask)
+	// result: (VPSRLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
-		v2.AuxInt = int16ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRLDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh8x16 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLL x y)
+}
+func rewriteValueAMD64_OpShiftAllRightMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightMaskedUint32x8 x y mask)
+	// result: (VPSRLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLL)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRLDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh8x32(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh8x32 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
+	// match: (ShiftAllRightMaskedUint64x2 x y mask)
+	// result: (VPSRLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRLQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh8x32 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLL x y)
+}
+func rewriteValueAMD64_OpShiftAllRightMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftAllRightMaskedUint64x4 x y mask)
+	// result: (VPSRLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLL)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRLQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh8x64(v *Value) bool {
+func rewriteValueAMD64_OpShiftAllRightMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh8x64 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
+	// match: (ShiftAllRightMaskedUint64x8 x y mask)
+	// result: (VPSRLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRLQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Lsh8x64 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLL x y)
+}
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt16x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftAndFillUpperFromMaskedInt16x16 x y z mask)
+	// result: (VPSHLDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLL)
-		v.AddArg2(x, y)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpLsh8x8(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt16x32(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Lsh8x8 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
+	// match: (ShiftLeftAndFillUpperFromMaskedInt16x32 x y z mask)
+	// result: (VPSHLDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
-		v2.AuxInt = int8ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	// match: (Lsh8x8 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHLL x y)
+}
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt16x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftAndFillUpperFromMaskedInt16x8 x y z mask)
+	// result: (VPSHLDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHLL)
-		v.AddArg2(x, y)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpMax32F(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Max32F <t> x y)
-	// result: (Neg32F <t> (Min32F <t> (Neg32F <t> x) (Neg32F <t> y)))
+	// match: (ShiftLeftAndFillUpperFromMaskedInt32x16 x y z mask)
+	// result: (VPSHLDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		v.reset(OpNeg32F)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpMin32F, t)
-		v1 := b.NewValue0(v.Pos, OpNeg32F, t)
-		v1.AddArg(x)
-		v2 := b.NewValue0(v.Pos, OpNeg32F, t)
-		v2.AddArg(y)
-		v0.AddArg2(v1, v2)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpMax64F(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt32x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Max64F <t> x y)
-	// result: (Neg64F <t> (Min64F <t> (Neg64F <t> x) (Neg64F <t> y)))
+	// match: (ShiftLeftAndFillUpperFromMaskedInt32x4 x y z mask)
+	// result: (VPSHLDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		v.reset(OpNeg64F)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpMin64F, t)
-		v1 := b.NewValue0(v.Pos, OpNeg64F, t)
-		v1.AddArg(x)
-		v2 := b.NewValue0(v.Pos, OpNeg64F, t)
-		v2.AddArg(y)
-		v0.AddArg2(v1, v2)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpMin32F(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Min32F <t> x y)
-	// result: (POR (MINSS <t> (MINSS <t> x y) x) (MINSS <t> x y))
+	// match: (ShiftLeftAndFillUpperFromMaskedInt32x8 x y z mask)
+	// result: (VPSHLDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64POR)
-		v0 := b.NewValue0(v.Pos, OpAMD64MINSS, t)
-		v1 := b.NewValue0(v.Pos, OpAMD64MINSS, t)
-		v1.AddArg2(x, y)
-		v0.AddArg2(v1, x)
-		v.AddArg2(v0, v1)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpMin64F(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt64x2(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Min64F <t> x y)
-	// result: (POR (MINSD <t> (MINSD <t> x y) x) (MINSD <t> x y))
+	// match: (ShiftLeftAndFillUpperFromMaskedInt64x2 x y z mask)
+	// result: (VPSHLDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64POR)
-		v0 := b.NewValue0(v.Pos, OpAMD64MINSD, t)
-		v1 := b.NewValue0(v.Pos, OpAMD64MINSD, t)
-		v1.AddArg2(x, y)
-		v0.AddArg2(v1, x)
-		v.AddArg2(v0, v1)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpMod16(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt64x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Mod16 [a] x y)
-	// result: (Select1 (DIVW [a] x y))
+	// match: (ShiftLeftAndFillUpperFromMaskedInt64x4 x y z mask)
+	// result: (VPSHLDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		a := auxIntToBool(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpSelect1)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
-		v0.AuxInt = boolToAuxInt(a)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpMod16u(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedInt64x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Mod16u x y)
-	// result: (Select1 (DIVWU x y))
+	// match: (ShiftLeftAndFillUpperFromMaskedInt64x8 x y z mask)
+	// result: (VPSHLDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpSelect1)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpMod32(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint16x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Mod32 [a] x y)
-	// result: (Select1 (DIVL [a] x y))
+	// match: (ShiftLeftAndFillUpperFromMaskedUint16x16 x y z mask)
+	// result: (VPSHLDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		a := auxIntToBool(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpSelect1)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32))
-		v0.AuxInt = boolToAuxInt(a)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpMod32u(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint16x32(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Mod32u x y)
-	// result: (Select1 (DIVLU x y))
+	// match: (ShiftLeftAndFillUpperFromMaskedUint16x32 x y z mask)
+	// result: (VPSHLDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpSelect1)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32))
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpMod64(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint16x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Mod64 [a] x y)
-	// result: (Select1 (DIVQ [a] x y))
+	// match: (ShiftLeftAndFillUpperFromMaskedUint16x8 x y z mask)
+	// result: (VPSHLDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
-		a := auxIntToBool(v.AuxInt)
 		x := v_0
 		y := v_1
-		v.reset(OpSelect1)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64))
-		v0.AuxInt = boolToAuxInt(a)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpMod64u(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Mod64u x y)
-	// result: (Select1 (DIVQU x y))
+	// match: (ShiftLeftAndFillUpperFromMaskedUint32x16 x y z mask)
+	// result: (VPSHLDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpSelect1)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64))
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpMod8(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint32x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Mod8 x y)
-	// result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
+	// match: (ShiftLeftAndFillUpperFromMaskedUint32x4 x y z mask)
+	// result: (VPSHLDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpSelect1)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
-		v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
-		v1.AddArg(x)
-		v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
-		v2.AddArg(y)
-		v0.AddArg2(v1, v2)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpMod8u(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Mod8u x y)
-	// result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
+	// match: (ShiftLeftAndFillUpperFromMaskedUint32x8 x y z mask)
+	// result: (VPSHLDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpSelect1)
-		v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
-		v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
-		v1.AddArg(x)
-		v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
-		v2.AddArg(y)
-		v0.AddArg2(v1, v2)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpMove(v *Value) bool {
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint64x2(v *Value) bool {
+	v_3 := v.Args[3]
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Move [0] _ _ mem)
-	// result: mem
+	// match: (ShiftLeftAndFillUpperFromMaskedUint64x2 x y z mask)
+	// result: (VPSHLDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 0 {
-			break
-		}
-		mem := v_2
-		v.copyOf(mem)
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	// match: (Move [1] dst src mem)
-	// result: (MOVBstore dst (MOVBload src mem) mem)
+}
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint64x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftAndFillUpperFromMaskedUint64x4 x y z mask)
+	// result: (VPSHLDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 1 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpAMD64MOVBstore)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
-		v0.AddArg2(src, mem)
-		v.AddArg3(dst, v0, mem)
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	// match: (Move [2] dst src mem)
-	// result: (MOVWstore dst (MOVWload src mem) mem)
+}
+func rewriteValueAMD64_OpShiftLeftAndFillUpperFromMaskedUint64x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftAndFillUpperFromMaskedUint64x8 x y z mask)
+	// result: (VPSHLDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 2 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpAMD64MOVWstore)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
-		v0.AddArg2(src, mem)
-		v.AddArg3(dst, v0, mem)
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHLDVQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	// match: (Move [4] dst src mem)
-	// result: (MOVLstore dst (MOVLload src mem) mem)
+}
+func rewriteValueAMD64_OpShiftLeftMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedInt16x16 x y mask)
+	// result: (VPSLLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 4 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpAMD64MOVLstore)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
-		v0.AddArg2(src, mem)
-		v.AddArg3(dst, v0, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [8] dst src mem)
-	// result: (MOVQstore dst (MOVQload src mem) mem)
+}
+func rewriteValueAMD64_OpShiftLeftMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedInt16x32 x y mask)
+	// result: (VPSLLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 8 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpAMD64MOVQstore)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
-		v0.AddArg2(src, mem)
-		v.AddArg3(dst, v0, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [16] dst src mem)
-	// result: (MOVOstore dst (MOVOload src mem) mem)
-	for {
-		if auxIntToInt64(v.AuxInt) != 16 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpAMD64MOVOstore)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128)
-		v0.AddArg2(src, mem)
-		v.AddArg3(dst, v0, mem)
+}
+func rewriteValueAMD64_OpShiftLeftMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedInt16x8 x y mask)
+	// result: (VPSLLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+	for {
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [32] dst src mem)
-	// result: (Move [16] (OffPtr <dst.Type> dst [16]) (OffPtr <src.Type> src [16]) (Move [16] dst src mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedInt32x16 x y mask)
+	// result: (VPSLLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 32 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpMove)
-		v.AuxInt = int64ToAuxInt(16)
-		v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
-		v0.AuxInt = int64ToAuxInt(16)
-		v0.AddArg(dst)
-		v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
-		v1.AuxInt = int64ToAuxInt(16)
-		v1.AddArg(src)
-		v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem)
-		v2.AuxInt = int64ToAuxInt(16)
-		v2.AddArg3(dst, src, mem)
-		v.AddArg3(v0, v1, v2)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [48] dst src mem)
-	// result: (Move [32] (OffPtr <dst.Type> dst [16]) (OffPtr <src.Type> src [16]) (Move [16] dst src mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedInt32x4 x y mask)
+	// result: (VPSLLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 48 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpMove)
-		v.AuxInt = int64ToAuxInt(32)
-		v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
-		v0.AuxInt = int64ToAuxInt(16)
-		v0.AddArg(dst)
-		v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
-		v1.AuxInt = int64ToAuxInt(16)
-		v1.AddArg(src)
-		v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem)
-		v2.AuxInt = int64ToAuxInt(16)
-		v2.AddArg3(dst, src, mem)
-		v.AddArg3(v0, v1, v2)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [64] dst src mem)
-	// result: (Move [32] (OffPtr <dst.Type> dst [32]) (OffPtr <src.Type> src [32]) (Move [32] dst src mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedInt32x8 x y mask)
+	// result: (VPSLLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 64 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpMove)
-		v.AuxInt = int64ToAuxInt(32)
-		v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
-		v0.AuxInt = int64ToAuxInt(32)
-		v0.AddArg(dst)
-		v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
-		v1.AuxInt = int64ToAuxInt(32)
-		v1.AddArg(src)
-		v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem)
-		v2.AuxInt = int64ToAuxInt(32)
-		v2.AddArg3(dst, src, mem)
-		v.AddArg3(v0, v1, v2)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [3] dst src mem)
-	// result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedInt64x2 x y mask)
+	// result: (VPSLLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 3 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpAMD64MOVBstore)
-		v.AuxInt = int32ToAuxInt(2)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
-		v0.AuxInt = int32ToAuxInt(2)
-		v0.AddArg2(src, mem)
-		v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
-		v2.AddArg2(src, mem)
-		v1.AddArg3(dst, v2, mem)
-		v.AddArg3(dst, v0, v1)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [5] dst src mem)
-	// result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedInt64x4 x y mask)
+	// result: (VPSLLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 5 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpAMD64MOVBstore)
-		v.AuxInt = int32ToAuxInt(4)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
-		v0.AuxInt = int32ToAuxInt(4)
-		v0.AddArg2(src, mem)
-		v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
-		v2.AddArg2(src, mem)
-		v1.AddArg3(dst, v2, mem)
-		v.AddArg3(dst, v0, v1)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [6] dst src mem)
-	// result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedInt64x8 x y mask)
+	// result: (VPSLLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 6 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpAMD64MOVWstore)
-		v.AuxInt = int32ToAuxInt(4)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
-		v0.AuxInt = int32ToAuxInt(4)
-		v0.AddArg2(src, mem)
-		v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
-		v2.AddArg2(src, mem)
-		v1.AddArg3(dst, v2, mem)
-		v.AddArg3(dst, v0, v1)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [7] dst src mem)
-	// result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedUint16x16 x y mask)
+	// result: (VPSLLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 7 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpAMD64MOVLstore)
-		v.AuxInt = int32ToAuxInt(3)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
-		v0.AuxInt = int32ToAuxInt(3)
-		v0.AddArg2(src, mem)
-		v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
-		v2.AddArg2(src, mem)
-		v1.AddArg3(dst, v2, mem)
-		v.AddArg3(dst, v0, v1)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [9] dst src mem)
-	// result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedUint16x32 x y mask)
+	// result: (VPSLLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 9 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpAMD64MOVBstore)
-		v.AuxInt = int32ToAuxInt(8)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
-		v0.AuxInt = int32ToAuxInt(8)
-		v0.AddArg2(src, mem)
-		v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
-		v2.AddArg2(src, mem)
-		v1.AddArg3(dst, v2, mem)
-		v.AddArg3(dst, v0, v1)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [10] dst src mem)
-	// result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedUint16x8 x y mask)
+	// result: (VPSLLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 10 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpAMD64MOVWstore)
-		v.AuxInt = int32ToAuxInt(8)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
-		v0.AuxInt = int32ToAuxInt(8)
-		v0.AddArg2(src, mem)
-		v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
-		v2.AddArg2(src, mem)
-		v1.AddArg3(dst, v2, mem)
-		v.AddArg3(dst, v0, v1)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [11] dst src mem)
-	// result: (MOVLstore [7] dst (MOVLload [7] src mem) (MOVQstore dst (MOVQload src mem) mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedUint32x16 x y mask)
+	// result: (VPSLLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 11 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpAMD64MOVLstore)
-		v.AuxInt = int32ToAuxInt(7)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
-		v0.AuxInt = int32ToAuxInt(7)
-		v0.AddArg2(src, mem)
-		v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
-		v2.AddArg2(src, mem)
-		v1.AddArg3(dst, v2, mem)
-		v.AddArg3(dst, v0, v1)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [12] dst src mem)
-	// result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedUint32x4 x y mask)
+	// result: (VPSLLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 12 {
-			break
-		}
-		dst := v_0
-		src := v_1
-		mem := v_2
-		v.reset(OpAMD64MOVLstore)
-		v.AuxInt = int32ToAuxInt(8)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
-		v0.AuxInt = int32ToAuxInt(8)
-		v0.AddArg2(src, mem)
-		v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
-		v2.AddArg2(src, mem)
-		v1.AddArg3(dst, v2, mem)
-		v.AddArg3(dst, v0, v1)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [s] dst src mem)
-	// cond: s >= 13 && s <= 15
-	// result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedUint32x8 x y mask)
+	// result: (VPSLLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		s := auxIntToInt64(v.AuxInt)
-		dst := v_0
-		src := v_1
-		mem := v_2
-		if !(s >= 13 && s <= 15) {
-			break
-		}
-		v.reset(OpAMD64MOVQstore)
-		v.AuxInt = int32ToAuxInt(int32(s - 8))
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
-		v0.AuxInt = int32ToAuxInt(int32(s - 8))
-		v0.AddArg2(src, mem)
-		v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
-		v2.AddArg2(src, mem)
-		v1.AddArg3(dst, v2, mem)
-		v.AddArg3(dst, v0, v1)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [s] dst src mem)
-	// cond: s > 16 && s%16 != 0 && s%16 <= 8
-	// result: (Move [s-s%16] (OffPtr <dst.Type> dst [s%16]) (OffPtr <src.Type> src [s%16]) (MOVQstore dst (MOVQload src mem) mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedUint64x2 x y mask)
+	// result: (VPSLLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		s := auxIntToInt64(v.AuxInt)
-		dst := v_0
-		src := v_1
-		mem := v_2
-		if !(s > 16 && s%16 != 0 && s%16 <= 8) {
-			break
-		}
-		v.reset(OpMove)
-		v.AuxInt = int64ToAuxInt(s - s%16)
-		v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
-		v0.AuxInt = int64ToAuxInt(s % 16)
-		v0.AddArg(dst)
-		v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
-		v1.AuxInt = int64ToAuxInt(s % 16)
-		v1.AddArg(src)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
-		v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
-		v3.AddArg2(src, mem)
-		v2.AddArg3(dst, v3, mem)
-		v.AddArg3(v0, v1, v2)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [s] dst src mem)
-	// cond: s > 16 && s%16 != 0 && s%16 > 8
-	// result: (Move [s-s%16] (OffPtr <dst.Type> dst [s%16]) (OffPtr <src.Type> src [s%16]) (MOVOstore dst (MOVOload src mem) mem))
+}
+func rewriteValueAMD64_OpShiftLeftMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedUint64x4 x y mask)
+	// result: (VPSLLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		s := auxIntToInt64(v.AuxInt)
-		dst := v_0
-		src := v_1
-		mem := v_2
-		if !(s > 16 && s%16 != 0 && s%16 > 8) {
-			break
-		}
-		v.reset(OpMove)
-		v.AuxInt = int64ToAuxInt(s - s%16)
-		v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
-		v0.AuxInt = int64ToAuxInt(s % 16)
-		v0.AddArg(dst)
-		v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
-		v1.AuxInt = int64ToAuxInt(s % 16)
-		v1.AddArg(src)
-		v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem)
-		v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128)
-		v3.AddArg2(src, mem)
-		v2.AddArg3(dst, v3, mem)
-		v.AddArg3(v0, v1, v2)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [s] dst src mem)
-	// cond: s > 64 && s <= 16*64 && s%16 == 0 && logLargeCopy(v, s)
-	// result: (DUFFCOPY [s] dst src mem)
+}
+func rewriteValueAMD64_OpShiftLeftMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftLeftMaskedUint64x8 x y mask)
+	// result: (VPSLLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		s := auxIntToInt64(v.AuxInt)
-		dst := v_0
-		src := v_1
-		mem := v_2
-		if !(s > 64 && s <= 16*64 && s%16 == 0 && logLargeCopy(v, s)) {
-			break
-		}
-		v.reset(OpAMD64DUFFCOPY)
-		v.AuxInt = int64ToAuxInt(s)
-		v.AddArg3(dst, src, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSLLVQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Move [s] dst src mem)
-	// cond: s > 16*64 && s%8 == 0 && logLargeCopy(v, s)
-	// result: (REPMOVSQ dst src (MOVQconst [s/8]) mem)
+}
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt16x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftRightAndFillUpperFromMaskedInt16x16 x y z mask)
+	// result: (VPSHRDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		s := auxIntToInt64(v.AuxInt)
-		dst := v_0
-		src := v_1
-		mem := v_2
-		if !(s > 16*64 && s%8 == 0 && logLargeCopy(v, s)) {
-			break
-		}
-		v.reset(OpAMD64REPMOVSQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
-		v0.AuxInt = int64ToAuxInt(s / 8)
-		v.AddArg4(dst, src, v0, mem)
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpNeg32F(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt16x32(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Neg32F x)
-	// result: (PXOR x (MOVSSconst <typ.Float32> [float32(math.Copysign(0, -1))]))
+	// match: (ShiftRightAndFillUpperFromMaskedInt16x32 x y z mask)
+	// result: (VPSHRDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		v.reset(OpAMD64PXOR)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32)
-		v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1)))
-		v.AddArg2(x, v0)
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpNeg64F(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt16x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Neg64F x)
-	// result: (PXOR x (MOVSDconst <typ.Float64> [math.Copysign(0, -1)]))
+	// match: (ShiftRightAndFillUpperFromMaskedInt16x8 x y z mask)
+	// result: (VPSHRDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		v.reset(OpAMD64PXOR)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64)
-		v0.AuxInt = float64ToAuxInt(math.Copysign(0, -1))
-		v.AddArg2(x, v0)
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpNeq16(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Neq16 x y)
-	// result: (SETNE (CMPW x y))
+	// match: (ShiftRightAndFillUpperFromMaskedInt32x16 x y z mask)
+	// result: (VPSHRDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETNE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpNeq32(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt32x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Neq32 x y)
-	// result: (SETNE (CMPL x y))
+	// match: (ShiftRightAndFillUpperFromMaskedInt32x4 x y z mask)
+	// result: (VPSHRDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETNE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpNeq32F(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Neq32F x y)
-	// result: (SETNEF (UCOMISS x y))
+	// match: (ShiftRightAndFillUpperFromMaskedInt32x8 x y z mask)
+	// result: (VPSHRDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETNEF)
-		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpNeq64(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt64x2(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Neq64 x y)
-	// result: (SETNE (CMPQ x y))
+	// match: (ShiftRightAndFillUpperFromMaskedInt64x2 x y z mask)
+	// result: (VPSHRDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETNE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpNeq64F(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt64x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Neq64F x y)
-	// result: (SETNEF (UCOMISD x y))
+	// match: (ShiftRightAndFillUpperFromMaskedInt64x4 x y z mask)
+	// result: (VPSHRDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETNEF)
-		v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpNeq8(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedInt64x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Neq8 x y)
-	// result: (SETNE (CMPB x y))
+	// match: (ShiftRightAndFillUpperFromMaskedInt64x8 x y z mask)
+	// result: (VPSHRDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETNE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpNeqB(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint16x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (NeqB x y)
-	// result: (SETNE (CMPB x y))
+	// match: (ShiftRightAndFillUpperFromMaskedUint16x16 x y z mask)
+	// result: (VPSHRDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETNE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpNeqPtr(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint16x32(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (NeqPtr x y)
-	// result: (SETNE (CMPQ x y))
+	// match: (ShiftRightAndFillUpperFromMaskedUint16x32 x y z mask)
+	// result: (VPSHRDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64SETNE)
-		v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpNot(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint16x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (Not x)
-	// result: (XORLconst [1] x)
+	b := v.Block
+	// match: (ShiftRightAndFillUpperFromMaskedUint16x8 x y z mask)
+	// result: (VPSHRDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		v.reset(OpAMD64XORLconst)
-		v.AuxInt = int32ToAuxInt(1)
-		v.AddArg(x)
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpOffPtr(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (OffPtr [off] ptr)
-	// cond: is32Bit(off)
-	// result: (ADDQconst [int32(off)] ptr)
-	for {
-		off := auxIntToInt64(v.AuxInt)
-		ptr := v_0
-		if !(is32Bit(off)) {
-			break
-		}
-		v.reset(OpAMD64ADDQconst)
-		v.AuxInt = int32ToAuxInt(int32(off))
-		v.AddArg(ptr)
-		return true
-	}
-	// match: (OffPtr [off] ptr)
-	// result: (ADDQ (MOVQconst [off]) ptr)
+	// match: (ShiftRightAndFillUpperFromMaskedUint32x16 x y z mask)
+	// result: (VPSHRDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		off := auxIntToInt64(v.AuxInt)
-		ptr := v_0
-		v.reset(OpAMD64ADDQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
-		v0.AuxInt = int64ToAuxInt(off)
-		v.AddArg2(v0, ptr)
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpPanicBounds(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint32x4(v *Value) bool {
+	v_3 := v.Args[3]
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (PanicBounds [kind] x y mem)
-	// cond: boundsABI(kind) == 0
-	// result: (LoweredPanicBoundsA [kind] x y mem)
+	b := v.Block
+	// match: (ShiftRightAndFillUpperFromMaskedUint32x4 x y z mask)
+	// result: (VPSHRDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		kind := auxIntToInt64(v.AuxInt)
 		x := v_0
 		y := v_1
-		mem := v_2
-		if !(boundsABI(kind) == 0) {
-			break
-		}
-		v.reset(OpAMD64LoweredPanicBoundsA)
-		v.AuxInt = int64ToAuxInt(kind)
-		v.AddArg3(x, y, mem)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	// match: (PanicBounds [kind] x y mem)
-	// cond: boundsABI(kind) == 1
-	// result: (LoweredPanicBoundsB [kind] x y mem)
+}
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftRightAndFillUpperFromMaskedUint32x8 x y z mask)
+	// result: (VPSHRDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		kind := auxIntToInt64(v.AuxInt)
 		x := v_0
 		y := v_1
-		mem := v_2
-		if !(boundsABI(kind) == 1) {
-			break
-		}
-		v.reset(OpAMD64LoweredPanicBoundsB)
-		v.AuxInt = int64ToAuxInt(kind)
-		v.AddArg3(x, y, mem)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	// match: (PanicBounds [kind] x y mem)
-	// cond: boundsABI(kind) == 2
-	// result: (LoweredPanicBoundsC [kind] x y mem)
+}
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint64x2(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftRightAndFillUpperFromMaskedUint64x2 x y z mask)
+	// result: (VPSHRDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		kind := auxIntToInt64(v.AuxInt)
 		x := v_0
 		y := v_1
-		mem := v_2
-		if !(boundsABI(kind) == 2) {
-			break
-		}
-		v.reset(OpAMD64LoweredPanicBoundsC)
-		v.AuxInt = int64ToAuxInt(kind)
-		v.AddArg3(x, y, mem)
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpPopCount16(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint64x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (PopCount16 x)
-	// result: (POPCNTL (MOVWQZX <typ.UInt32> x))
+	// match: (ShiftRightAndFillUpperFromMaskedUint64x4 x y z mask)
+	// result: (VPSHRDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		v.reset(OpAMD64POPCNTL)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32)
-		v0.AddArg(x)
-		v.AddArg(v0)
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpPopCount8(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightAndFillUpperFromMaskedUint64x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (PopCount8 x)
-	// result: (POPCNTL (MOVBQZX <typ.UInt32> x))
+	// match: (ShiftRightAndFillUpperFromMaskedUint64x8 x y z mask)
+	// result: (VPSHRDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		v.reset(OpAMD64POPCNTL)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32)
-		v0.AddArg(x)
-		v.AddArg(v0)
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPSHRDVQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpRoundToEven(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (RoundToEven x)
-	// result: (ROUNDSD [0] x)
+	b := v.Block
+	// match: (ShiftRightMaskedInt16x16 x y mask)
+	// result: (VPSRAVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		v.reset(OpAMD64ROUNDSD)
-		v.AuxInt = int8ToAuxInt(0)
-		v.AddArg(x)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSRAVWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh16Ux16 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPWconst y [16])))
+	// match: (ShiftRightMaskedInt16x32 x y mask)
+	// result: (VPSRAVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
-		v2.AuxInt = int16ToAuxInt(16)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRAVWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh16Ux16 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRW x y)
+}
+func rewriteValueAMD64_OpShiftRightMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftRightMaskedInt16x8 x y mask)
+	// result: (VPSRAVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRW)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRAVWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh16Ux32(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh16Ux32 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPLconst y [16])))
+	// match: (ShiftRightMaskedInt32x16 x y mask)
+	// result: (VPSRAVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(16)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRAVDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh16Ux32 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRW x y)
+}
+func rewriteValueAMD64_OpShiftRightMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftRightMaskedInt32x4 x y mask)
+	// result: (VPSRAVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRW)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRAVDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh16Ux64(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh16Ux64 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPQconst y [16])))
+	// match: (ShiftRightMaskedInt32x8 x y mask)
+	// result: (VPSRAVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(16)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRAVDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh16Ux64 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRW x y)
+}
+func rewriteValueAMD64_OpShiftRightMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftRightMaskedInt64x2 x y mask)
+	// result: (VPSRAVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRW)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRAVQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh16Ux8(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh16Ux8 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPBconst y [16])))
+	// match: (ShiftRightMaskedInt64x4 x y mask)
+	// result: (VPSRAVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
-		v2.AuxInt = int8ToAuxInt(16)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRAVQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh16Ux8 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRW x y)
+}
+func rewriteValueAMD64_OpShiftRightMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftRightMaskedInt64x8 x y mask)
+	// result: (VPSRAVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRW)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRAVQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh16x16(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh16x16 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [16])))))
+	// match: (ShiftRightMaskedUint16x16 x y mask)
+	// result: (VPSRLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARW)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
-		v3.AuxInt = int16ToAuxInt(16)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		mask := v_2
+		v.reset(OpAMD64VPSRLVWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh16x16 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARW x y)
+}
+func rewriteValueAMD64_OpShiftRightMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftRightMaskedUint16x32 x y mask)
+	// result: (VPSRLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARW)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRLVWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh16x32(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh16x32 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [16])))))
+	// match: (ShiftRightMaskedUint16x8 x y mask)
+	// result: (VPSRLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARW)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
-		v3.AuxInt = int32ToAuxInt(16)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		mask := v_2
+		v.reset(OpAMD64VPSRLVWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh16x32 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARW x y)
+}
+func rewriteValueAMD64_OpShiftRightMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftRightMaskedUint32x16 x y mask)
+	// result: (VPSRLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARW)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRLVDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh16x64(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh16x64 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARW <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [16])))))
+	// match: (ShiftRightMaskedUint32x4 x y mask)
+	// result: (VPSRLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARW)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v3.AuxInt = int32ToAuxInt(16)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		mask := v_2
+		v.reset(OpAMD64VPSRLVDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh16x64 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARW x y)
+}
+func rewriteValueAMD64_OpShiftRightMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftRightMaskedUint32x8 x y mask)
+	// result: (VPSRLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARW)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRLVDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh16x8(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh16x8 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [16])))))
+	// match: (ShiftRightMaskedUint64x2 x y mask)
+	// result: (VPSRLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARW)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
-		v3.AuxInt = int8ToAuxInt(16)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		mask := v_2
+		v.reset(OpAMD64VPSRLVQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh16x8 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARW x y)
+}
+func rewriteValueAMD64_OpShiftRightMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (ShiftRightMaskedUint64x4 x y mask)
+	// result: (VPSRLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARW)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSRLVQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh32Ux16(v *Value) bool {
+func rewriteValueAMD64_OpShiftRightMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh32Ux16 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
+	// match: (ShiftRightMaskedUint64x8 x y mask)
+	// result: (VPSRLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
-		v2.AuxInt = int16ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSRLVQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh32Ux16 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRL x y)
+}
+func rewriteValueAMD64_OpSlicemask(v *Value) bool {
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (Slicemask <t> x)
+	// result: (SARQconst (NEGQ <t> x) [63])
 	for {
+		t := v.Type
 		x := v_0
-		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRL)
-		v.AddArg2(x, y)
+		v.reset(OpAMD64SARQconst)
+		v.AuxInt = int8ToAuxInt(63)
+		v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
+		v0.AddArg(x)
+		v.AddArg(v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh32Ux32(v *Value) bool {
+func rewriteValueAMD64_OpSpectreIndex(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh32Ux32 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
+	typ := &b.Func.Config.Types
+	// match: (SpectreIndex <t> x y)
+	// result: (CMOVQCC x (MOVQconst [0]) (CMPQ x y))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		v.reset(OpAMD64CMOVQCC)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
+		v0.AuxInt = int64ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
+		v1.AddArg2(x, y)
+		v.AddArg3(x, v0, v1)
 		return true
 	}
-	// match: (Rsh32Ux32 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRL x y)
+}
+func rewriteValueAMD64_OpSpectreSliceIndex(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	typ := &b.Func.Config.Types
+	// match: (SpectreSliceIndex <t> x y)
+	// result: (CMOVQHI x (MOVQconst [0]) (CMPQ x y))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRL)
-		v.AddArg2(x, y)
+		v.reset(OpAMD64CMOVQHI)
+		v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
+		v0.AuxInt = int64ToAuxInt(0)
+		v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
+		v1.AddArg2(x, y)
+		v.AddArg3(x, v0, v1)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh32Ux64(v *Value) bool {
+func rewriteValueAMD64_OpSqrtMaskedFloat32x16(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh32Ux64 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
+	// match: (SqrtMaskedFloat32x16 x mask)
+	// result: (VSQRTPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
-		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_1
+		v.reset(OpAMD64VSQRTPSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
-	// match: (Rsh32Ux64 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRL x y)
+}
+func rewriteValueAMD64_OpSqrtMaskedFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SqrtMaskedFloat32x4 x mask)
+	// result: (VSQRTPSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRL)
-		v.AddArg2(x, y)
+		mask := v_1
+		v.reset(OpAMD64VSQRTPSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh32Ux8(v *Value) bool {
+func rewriteValueAMD64_OpSqrtMaskedFloat32x8(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh32Ux8 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
+	// match: (SqrtMaskedFloat32x8 x mask)
+	// result: (VSQRTPSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
-		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
-		v2.AuxInt = int8ToAuxInt(32)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_1
+		v.reset(OpAMD64VSQRTPSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
-	// match: (Rsh32Ux8 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRL x y)
+}
+func rewriteValueAMD64_OpSqrtMaskedFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SqrtMaskedFloat64x2 x mask)
+	// result: (VSQRTPDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRL)
-		v.AddArg2(x, y)
+		mask := v_1
+		v.reset(OpAMD64VSQRTPDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh32x16(v *Value) bool {
+func rewriteValueAMD64_OpSqrtMaskedFloat64x4(v *Value) bool {
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh32x16 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [32])))))
+	// match: (SqrtMaskedFloat64x4 x mask)
+	// result: (VSQRTPDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
-		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARL)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
-		v3.AuxInt = int16ToAuxInt(32)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
+		mask := v_1
+		v.reset(OpAMD64VSQRTPDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
 		v.AddArg2(x, v0)
 		return true
 	}
-	// match: (Rsh32x16 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARL x y)
+}
+func rewriteValueAMD64_OpSqrtMaskedFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SqrtMaskedFloat64x8 x mask)
+	// result: (VSQRTPDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARL)
-		v.AddArg2(x, y)
+		mask := v_1
+		v.reset(OpAMD64VSQRTPDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh32x32(v *Value) bool {
+func rewriteValueAMD64_OpStore(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	b := v.Block
-	// match: (Rsh32x32 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [32])))))
+	// match: (Store {t} ptr val mem)
+	// cond: t.Size() == 8 && t.IsFloat()
+	// result: (MOVSDstore ptr val mem)
 	for {
-		t := v.Type
-		x := v_0
-		y := v_1
-		if !(!shiftIsBounded(v)) {
+		t := auxToType(v.Aux)
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		if !(t.Size() == 8 && t.IsFloat()) {
 			break
 		}
-		v.reset(OpAMD64SARL)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
-		v3.AuxInt = int32ToAuxInt(32)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		v.reset(OpAMD64MOVSDstore)
+		v.AddArg3(ptr, val, mem)
 		return true
 	}
-	// match: (Rsh32x32 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARL x y)
+	// match: (Store {t} ptr val mem)
+	// cond: t.Size() == 4 && t.IsFloat()
+	// result: (MOVSSstore ptr val mem)
 	for {
-		x := v_0
-		y := v_1
-		if !(shiftIsBounded(v)) {
+		t := auxToType(v.Aux)
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		if !(t.Size() == 4 && t.IsFloat()) {
 			break
 		}
-		v.reset(OpAMD64SARL)
-		v.AddArg2(x, y)
+		v.reset(OpAMD64MOVSSstore)
+		v.AddArg3(ptr, val, mem)
 		return true
 	}
-	return false
-}
-func rewriteValueAMD64_OpRsh32x64(v *Value) bool {
-	v_1 := v.Args[1]
-	v_0 := v.Args[0]
-	b := v.Block
-	// match: (Rsh32x64 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARL <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [32])))))
+	// match: (Store {t} ptr val mem)
+	// cond: t.Size() == 8 && !t.IsFloat()
+	// result: (MOVQstore ptr val mem)
 	for {
-		t := v.Type
-		x := v_0
-		y := v_1
-		if !(!shiftIsBounded(v)) {
+		t := auxToType(v.Aux)
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		if !(t.Size() == 8 && !t.IsFloat()) {
 			break
 		}
-		v.reset(OpAMD64SARL)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v3.AuxInt = int32ToAuxInt(32)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		v.reset(OpAMD64MOVQstore)
+		v.AddArg3(ptr, val, mem)
 		return true
 	}
-	// match: (Rsh32x64 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARL x y)
+	// match: (Store {t} ptr val mem)
+	// cond: t.Size() == 4 && !t.IsFloat()
+	// result: (MOVLstore ptr val mem)
 	for {
-		x := v_0
-		y := v_1
-		if !(shiftIsBounded(v)) {
+		t := auxToType(v.Aux)
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		if !(t.Size() == 4 && !t.IsFloat()) {
 			break
 		}
-		v.reset(OpAMD64SARL)
-		v.AddArg2(x, y)
+		v.reset(OpAMD64MOVLstore)
+		v.AddArg3(ptr, val, mem)
 		return true
 	}
-	return false
-}
-func rewriteValueAMD64_OpRsh32x8(v *Value) bool {
-	v_1 := v.Args[1]
-	v_0 := v.Args[0]
-	b := v.Block
-	// match: (Rsh32x8 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [32])))))
+	// match: (Store {t} ptr val mem)
+	// cond: t.Size() == 2
+	// result: (MOVWstore ptr val mem)
 	for {
-		t := v.Type
-		x := v_0
-		y := v_1
-		if !(!shiftIsBounded(v)) {
+		t := auxToType(v.Aux)
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		if !(t.Size() == 2) {
 			break
 		}
-		v.reset(OpAMD64SARL)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
-		v3.AuxInt = int8ToAuxInt(32)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		v.reset(OpAMD64MOVWstore)
+		v.AddArg3(ptr, val, mem)
 		return true
 	}
-	// match: (Rsh32x8 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARL x y)
+	// match: (Store {t} ptr val mem)
+	// cond: t.Size() == 1
+	// result: (MOVBstore ptr val mem)
 	for {
-		x := v_0
-		y := v_1
-		if !(shiftIsBounded(v)) {
+		t := auxToType(v.Aux)
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		if !(t.Size() == 1) {
 			break
 		}
-		v.reset(OpAMD64SARL)
-		v.AddArg2(x, y)
+		v.reset(OpAMD64MOVBstore)
+		v.AddArg3(ptr, val, mem)
 		return true
 	}
-	return false
-}
-func rewriteValueAMD64_OpRsh64Ux16(v *Value) bool {
-	v_1 := v.Args[1]
-	v_0 := v.Args[0]
-	b := v.Block
-	// match: (Rsh64Ux16 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64])))
+	// match: (Store {t} ptr val mem)
+	// cond: t.Size() == 16
+	// result: (VMOVDQUstore128 ptr val mem)
 	for {
-		t := v.Type
-		x := v_0
-		y := v_1
-		if !(!shiftIsBounded(v)) {
+		t := auxToType(v.Aux)
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		if !(t.Size() == 16) {
 			break
 		}
-		v.reset(OpAMD64ANDQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
-		v2.AuxInt = int16ToAuxInt(64)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		v.reset(OpAMD64VMOVDQUstore128)
+		v.AddArg3(ptr, val, mem)
 		return true
 	}
-	// match: (Rsh64Ux16 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRQ x y)
+	// match: (Store {t} ptr val mem)
+	// cond: t.Size() == 32
+	// result: (VMOVDQUstore256 ptr val mem)
 	for {
-		x := v_0
-		y := v_1
-		if !(shiftIsBounded(v)) {
+		t := auxToType(v.Aux)
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		if !(t.Size() == 32) {
 			break
 		}
-		v.reset(OpAMD64SHRQ)
-		v.AddArg2(x, y)
+		v.reset(OpAMD64VMOVDQUstore256)
+		v.AddArg3(ptr, val, mem)
+		return true
+	}
+	// match: (Store {t} ptr val mem)
+	// cond: t.Size() == 64
+	// result: (VMOVDQUstore512 ptr val mem)
+	for {
+		t := auxToType(v.Aux)
+		ptr := v_0
+		val := v_1
+		mem := v_2
+		if !(t.Size() == 64) {
+			break
+		}
+		v.reset(OpAMD64VMOVDQUstore512)
+		v.AddArg3(ptr, val, mem)
 		return true
 	}
 	return false
 }
-func rewriteValueAMD64_OpRsh64Ux32(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedFloat32x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh64Ux32 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64])))
+	// match: (SubMaskedFloat32x16 x y mask)
+	// result: (VSUBPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(64)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VSUBPSMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh64Ux32 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRQ x y)
+}
+func rewriteValueAMD64_OpSubMaskedFloat32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedFloat32x4 x y mask)
+	// result: (VSUBPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRQ)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VSUBPSMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh64Ux64(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedFloat32x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh64Ux64 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64])))
+	// match: (SubMaskedFloat32x8 x y mask)
+	// result: (VSUBPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(64)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VSUBPSMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh64Ux64 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRQ x y)
+}
+func rewriteValueAMD64_OpSubMaskedFloat64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedFloat64x2 x y mask)
+	// result: (VSUBPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRQ)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VSUBPDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh64Ux8(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedFloat64x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh64Ux8 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64])))
+	// match: (SubMaskedFloat64x4 x y mask)
+	// result: (VSUBPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDQ)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
-		v2.AuxInt = int8ToAuxInt(64)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VSUBPDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh64Ux8 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRQ x y)
+}
+func rewriteValueAMD64_OpSubMaskedFloat64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedFloat64x8 x y mask)
+	// result: (VSUBPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRQ)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VSUBPDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh64x16(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedInt16x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh64x16 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [64])))))
+	// match: (SubMaskedInt16x16 x y mask)
+	// result: (VPSUBWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARQ)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
-		v3.AuxInt = int16ToAuxInt(64)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		mask := v_2
+		v.reset(OpAMD64VPSUBWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh64x16 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARQ x y)
+}
+func rewriteValueAMD64_OpSubMaskedInt16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedInt16x32 x y mask)
+	// result: (VPSUBWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARQ)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSUBWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh64x32(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedInt16x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh64x32 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [64])))))
+	// match: (SubMaskedInt16x8 x y mask)
+	// result: (VPSUBWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARQ)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
-		v3.AuxInt = int32ToAuxInt(64)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		mask := v_2
+		v.reset(OpAMD64VPSUBWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh64x32 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARQ x y)
+}
+func rewriteValueAMD64_OpSubMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedInt32x16 x y mask)
+	// result: (VPSUBDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		x := v_0
-		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARQ)
-		v.AddArg2(x, y)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPSUBDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh64x64(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh64x64 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARQ <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [64])))))
+	// match: (SubMaskedInt32x4 x y mask)
+	// result: (VPSUBDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARQ)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v3.AuxInt = int32ToAuxInt(64)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		mask := v_2
+		v.reset(OpAMD64VPSUBDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh64x64 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARQ x y)
+}
+func rewriteValueAMD64_OpSubMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedInt32x8 x y mask)
+	// result: (VPSUBDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARQ)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSUBDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh64x8(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh64x8 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [64])))))
+	// match: (SubMaskedInt64x2 x y mask)
+	// result: (VPSUBQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARQ)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
-		v3.AuxInt = int8ToAuxInt(64)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		mask := v_2
+		v.reset(OpAMD64VPSUBQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh64x8 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARQ x y)
+}
+func rewriteValueAMD64_OpSubMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedInt64x4 x y mask)
+	// result: (VPSUBQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARQ)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSUBQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh8Ux16(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedInt64x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh8Ux16 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPWconst y [8])))
+	// match: (SubMaskedInt64x8 x y mask)
+	// result: (VPSUBQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
-		v2.AuxInt = int16ToAuxInt(8)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSUBQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh8Ux16 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRB x y)
+}
+func rewriteValueAMD64_OpSubMaskedInt8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedInt8x16 x y mask)
+	// result: (VPSUBBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRB)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSUBBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh8Ux32(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedInt8x32(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh8Ux32 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPLconst y [8])))
+	// match: (SubMaskedInt8x32 x y mask)
+	// result: (VPSUBBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(8)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSUBBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh8Ux32 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRB x y)
+}
+func rewriteValueAMD64_OpSubMaskedInt8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedInt8x64 x y mask)
+	// result: (VPSUBBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRB)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSUBBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh8Ux64(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedUint16x16(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh8Ux64 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPQconst y [8])))
+	// match: (SubMaskedUint16x16 x y mask)
+	// result: (VPSUBWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v2.AuxInt = int32ToAuxInt(8)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSUBWMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh8Ux64 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRB x y)
+}
+func rewriteValueAMD64_OpSubMaskedUint16x32(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedUint16x32 x y mask)
+	// result: (VPSUBWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRB)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSUBWMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh8Ux8(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedUint16x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh8Ux8 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPBconst y [8])))
+	// match: (SubMaskedUint16x8 x y mask)
+	// result: (VPSUBWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64ANDL)
-		v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
-		v0.AddArg2(x, y)
-		v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
-		v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
-		v2.AuxInt = int8ToAuxInt(8)
-		v2.AddArg(y)
-		v1.AddArg(v2)
-		v.AddArg2(v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPSUBWMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh8Ux8 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SHRB x y)
+}
+func rewriteValueAMD64_OpSubMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedUint32x16 x y mask)
+	// result: (VPSUBDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SHRB)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSUBDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh8x16(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh8x16 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [8])))))
+	// match: (SubMaskedUint32x4 x y mask)
+	// result: (VPSUBDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARB)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
-		v3.AuxInt = int16ToAuxInt(8)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		mask := v_2
+		v.reset(OpAMD64VPSUBDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh8x16 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARB x y)
+}
+func rewriteValueAMD64_OpSubMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedUint32x8 x y mask)
+	// result: (VPSUBDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARB)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSUBDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh8x32(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh8x32 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [8])))))
+	// match: (SubMaskedUint64x2 x y mask)
+	// result: (VPSUBQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARB)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
-		v3.AuxInt = int32ToAuxInt(8)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		mask := v_2
+		v.reset(OpAMD64VPSUBQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh8x32 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARB x y)
+}
+func rewriteValueAMD64_OpSubMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedUint64x4 x y mask)
+	// result: (VPSUBQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARB)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSUBQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh8x64(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh8x64 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARB <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [8])))))
+	// match: (SubMaskedUint64x8 x y mask)
+	// result: (VPSUBQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARB)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
-		v3.AuxInt = int32ToAuxInt(8)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		mask := v_2
+		v.reset(OpAMD64VPSUBQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh8x64 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARB x y)
+}
+func rewriteValueAMD64_OpSubMaskedUint8x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedUint8x16 x y mask)
+	// result: (VPSUBBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARB)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSUBBMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpRsh8x8(v *Value) bool {
+func rewriteValueAMD64_OpSubMaskedUint8x32(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Rsh8x8 <t> x y)
-	// cond: !shiftIsBounded(v)
-	// result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [8])))))
+	// match: (SubMaskedUint8x32 x y mask)
+	// result: (VPSUBBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
 		y := v_1
-		if !(!shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARB)
-		v.Type = t
-		v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
-		v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
-		v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
-		v3.AuxInt = int8ToAuxInt(8)
-		v3.AddArg(y)
-		v2.AddArg(v3)
-		v1.AddArg(v2)
-		v0.AddArg2(y, v1)
-		v.AddArg2(x, v0)
+		mask := v_2
+		v.reset(OpAMD64VPSUBBMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Rsh8x8 x y)
-	// cond: shiftIsBounded(v)
-	// result: (SARB x y)
+}
+func rewriteValueAMD64_OpSubMaskedUint8x64(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (SubMaskedUint8x64 x y mask)
+	// result: (VPSUBBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		if !(shiftIsBounded(v)) {
-			break
-		}
-		v.reset(OpAMD64SARB)
-		v.AddArg2(x, y)
+		mask := v_2
+		v.reset(OpAMD64VPSUBBMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpSelect0(v *Value) bool {
+func rewriteValueAMD64_OpTrunc(v *Value) bool {
 	v_0 := v.Args[0]
-	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Select0 (Mul64uover x y))
-	// result: (Select0 <typ.UInt64> (MULQU x y))
+	// match: (Trunc x)
+	// result: (ROUNDSD [3] x)
 	for {
-		if v_0.Op != OpMul64uover {
-			break
-		}
-		y := v_0.Args[1]
-		x := v_0.Args[0]
-		v.reset(OpSelect0)
-		v.Type = typ.UInt64
-		v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags))
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		x := v_0
+		v.reset(OpAMD64ROUNDSD)
+		v.AuxInt = int8ToAuxInt(3)
+		v.AddArg(x)
 		return true
 	}
-	// match: (Select0 (Mul32uover x y))
-	// result: (Select0 <typ.UInt32> (MULLU x y))
+}
+func rewriteValueAMD64_OpTruncFloat32x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (TruncFloat32x4 x)
+	// result: (VROUNDPS128 [3] x)
 	for {
-		if v_0.Op != OpMul32uover {
-			break
-		}
-		y := v_0.Args[1]
-		x := v_0.Args[0]
-		v.reset(OpSelect0)
-		v.Type = typ.UInt32
-		v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags))
-		v0.AddArg2(x, y)
-		v.AddArg(v0)
+		x := v_0
+		v.reset(OpAMD64VROUNDPS128)
+		v.AuxInt = int8ToAuxInt(3)
+		v.AddArg(x)
 		return true
 	}
-	// match: (Select0 (Add64carry x y c))
-	// result: (Select0 <typ.UInt64> (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
+}
+func rewriteValueAMD64_OpTruncFloat32x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (TruncFloat32x8 x)
+	// result: (VROUNDPS256 [3] x)
 	for {
-		if v_0.Op != OpAdd64carry {
-			break
-		}
-		c := v_0.Args[2]
-		x := v_0.Args[0]
-		y := v_0.Args[1]
-		v.reset(OpSelect0)
-		v.Type = typ.UInt64
-		v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags))
-		v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
-		v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
-		v2.AddArg(c)
-		v1.AddArg(v2)
-		v0.AddArg3(x, y, v1)
-		v.AddArg(v0)
+		x := v_0
+		v.reset(OpAMD64VROUNDPS256)
+		v.AuxInt = int8ToAuxInt(3)
+		v.AddArg(x)
 		return true
 	}
-	// match: (Select0 (Sub64borrow x y c))
-	// result: (Select0 <typ.UInt64> (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
+}
+func rewriteValueAMD64_OpTruncFloat64x2(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (TruncFloat64x2 x)
+	// result: (VROUNDPD128 [3] x)
 	for {
-		if v_0.Op != OpSub64borrow {
-			break
-		}
-		c := v_0.Args[2]
-		x := v_0.Args[0]
-		y := v_0.Args[1]
-		v.reset(OpSelect0)
-		v.Type = typ.UInt64
-		v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags))
-		v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
-		v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
-		v2.AddArg(c)
-		v1.AddArg(v2)
-		v0.AddArg3(x, y, v1)
-		v.AddArg(v0)
+		x := v_0
+		v.reset(OpAMD64VROUNDPD128)
+		v.AuxInt = int8ToAuxInt(3)
+		v.AddArg(x)
 		return true
 	}
-	// match: (Select0 <t> (AddTupleFirst32 val tuple))
-	// result: (ADDL val (Select0 <t> tuple))
+}
+func rewriteValueAMD64_OpTruncFloat64x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (TruncFloat64x4 x)
+	// result: (VROUNDPD256 [3] x)
 	for {
-		t := v.Type
-		if v_0.Op != OpAMD64AddTupleFirst32 {
-			break
-		}
-		tuple := v_0.Args[1]
-		val := v_0.Args[0]
-		v.reset(OpAMD64ADDL)
-		v0 := b.NewValue0(v.Pos, OpSelect0, t)
-		v0.AddArg(tuple)
-		v.AddArg2(val, v0)
+		x := v_0
+		v.reset(OpAMD64VROUNDPD256)
+		v.AuxInt = int8ToAuxInt(3)
+		v.AddArg(x)
 		return true
 	}
-	// match: (Select0 <t> (AddTupleFirst64 val tuple))
-	// result: (ADDQ val (Select0 <t> tuple))
+}
+func rewriteValueAMD64_OpTruncWithPrecisionFloat32x16(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (TruncWithPrecisionFloat32x16 [a] x)
+	// result: (VRNDSCALEPS512 [a+3] x)
 	for {
-		t := v.Type
-		if v_0.Op != OpAMD64AddTupleFirst64 {
-			break
-		}
-		tuple := v_0.Args[1]
-		val := v_0.Args[0]
-		v.reset(OpAMD64ADDQ)
-		v0 := b.NewValue0(v.Pos, OpSelect0, t)
-		v0.AddArg(tuple)
-		v.AddArg2(val, v0)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPS512)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v.AddArg(x)
 		return true
 	}
-	// match: (Select0 a:(ADDQconstflags [c] x))
-	// cond: a.Uses == 1
-	// result: (ADDQconst [c] x)
+}
+func rewriteValueAMD64_OpTruncWithPrecisionFloat32x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (TruncWithPrecisionFloat32x4 [a] x)
+	// result: (VRNDSCALEPS128 [a+3] x)
 	for {
-		a := v_0
-		if a.Op != OpAMD64ADDQconstflags {
-			break
-		}
-		c := auxIntToInt32(a.AuxInt)
-		x := a.Args[0]
-		if !(a.Uses == 1) {
-			break
-		}
-		v.reset(OpAMD64ADDQconst)
-		v.AuxInt = int32ToAuxInt(c)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPS128)
+		v.AuxInt = int8ToAuxInt(a + 3)
 		v.AddArg(x)
 		return true
 	}
-	// match: (Select0 a:(ADDLconstflags [c] x))
-	// cond: a.Uses == 1
-	// result: (ADDLconst [c] x)
+}
+func rewriteValueAMD64_OpTruncWithPrecisionFloat32x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (TruncWithPrecisionFloat32x8 [a] x)
+	// result: (VRNDSCALEPS256 [a+3] x)
 	for {
-		a := v_0
-		if a.Op != OpAMD64ADDLconstflags {
-			break
-		}
-		c := auxIntToInt32(a.AuxInt)
-		x := a.Args[0]
-		if !(a.Uses == 1) {
-			break
-		}
-		v.reset(OpAMD64ADDLconst)
-		v.AuxInt = int32ToAuxInt(c)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPS256)
+		v.AuxInt = int8ToAuxInt(a + 3)
 		v.AddArg(x)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpSelect1(v *Value) bool {
+func rewriteValueAMD64_OpTruncWithPrecisionFloat64x2(v *Value) bool {
 	v_0 := v.Args[0]
-	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (Select1 (Mul64uover x y))
-	// result: (SETO (Select1 <types.TypeFlags> (MULQU x y)))
+	// match: (TruncWithPrecisionFloat64x2 [a] x)
+	// result: (VRNDSCALEPD128 [a+3] x)
 	for {
-		if v_0.Op != OpMul64uover {
-			break
-		}
-		y := v_0.Args[1]
-		x := v_0.Args[0]
-		v.reset(OpAMD64SETO)
-		v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
-		v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags))
-		v1.AddArg2(x, y)
-		v0.AddArg(v1)
-		v.AddArg(v0)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPD128)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v.AddArg(x)
 		return true
 	}
-	// match: (Select1 (Mul32uover x y))
-	// result: (SETO (Select1 <types.TypeFlags> (MULLU x y)))
+}
+func rewriteValueAMD64_OpTruncWithPrecisionFloat64x4(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (TruncWithPrecisionFloat64x4 [a] x)
+	// result: (VRNDSCALEPD256 [a+3] x)
 	for {
-		if v_0.Op != OpMul32uover {
-			break
-		}
-		y := v_0.Args[1]
-		x := v_0.Args[0]
-		v.reset(OpAMD64SETO)
-		v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
-		v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags))
-		v1.AddArg2(x, y)
-		v0.AddArg(v1)
-		v.AddArg(v0)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPD256)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v.AddArg(x)
 		return true
 	}
-	// match: (Select1 (Add64carry x y c))
-	// result: (NEGQ <typ.UInt64> (SBBQcarrymask <typ.UInt64> (Select1 <types.TypeFlags> (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
+}
+func rewriteValueAMD64_OpTruncWithPrecisionFloat64x8(v *Value) bool {
+	v_0 := v.Args[0]
+	// match: (TruncWithPrecisionFloat64x8 [a] x)
+	// result: (VRNDSCALEPD512 [a+3] x)
 	for {
-		if v_0.Op != OpAdd64carry {
-			break
-		}
-		c := v_0.Args[2]
-		x := v_0.Args[0]
-		y := v_0.Args[1]
-		v.reset(OpAMD64NEGQ)
-		v.Type = typ.UInt64
-		v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64)
-		v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
-		v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags))
-		v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
-		v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
-		v4.AddArg(c)
-		v3.AddArg(v4)
-		v2.AddArg3(x, y, v3)
-		v1.AddArg(v2)
-		v0.AddArg(v1)
-		v.AddArg(v0)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		v.reset(OpAMD64VRNDSCALEPD512)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v.AddArg(x)
 		return true
 	}
-	// match: (Select1 (Sub64borrow x y c))
-	// result: (NEGQ <typ.UInt64> (SBBQcarrymask <typ.UInt64> (Select1 <types.TypeFlags> (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
+}
+func rewriteValueAMD64_OpTruncWithPrecisionMaskedFloat32x16(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (TruncWithPrecisionMaskedFloat32x16 [a] x mask)
+	// result: (VRNDSCALEPSMasked512 [a+3] x (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		if v_0.Op != OpSub64borrow {
-			break
-		}
-		c := v_0.Args[2]
-		x := v_0.Args[0]
-		y := v_0.Args[1]
-		v.reset(OpAMD64NEGQ)
-		v.Type = typ.UInt64
-		v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64)
-		v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
-		v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags))
-		v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
-		v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
-		v4.AddArg(c)
-		v3.AddArg(v4)
-		v2.AddArg3(x, y, v3)
-		v1.AddArg(v2)
-		v0.AddArg(v1)
-		v.AddArg(v0)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPSMasked512)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
-	// match: (Select1 (NEGLflags (MOVQconst [0])))
-	// result: (FlagEQ)
+}
+func rewriteValueAMD64_OpTruncWithPrecisionMaskedFloat32x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (TruncWithPrecisionMaskedFloat32x4 [a] x mask)
+	// result: (VRNDSCALEPSMasked128 [a+3] x (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		if v_0.Op != OpAMD64NEGLflags {
-			break
-		}
-		v_0_0 := v_0.Args[0]
-		if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 0 {
-			break
-		}
-		v.reset(OpAMD64FlagEQ)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPSMasked128)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
-	// match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x))))
-	// result: x
+}
+func rewriteValueAMD64_OpTruncWithPrecisionMaskedFloat32x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (TruncWithPrecisionMaskedFloat32x8 [a] x mask)
+	// result: (VRNDSCALEPSMasked256 [a+3] x (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		if v_0.Op != OpAMD64NEGLflags {
-			break
-		}
-		v_0_0 := v_0.Args[0]
-		if v_0_0.Op != OpAMD64NEGQ {
-			break
-		}
-		v_0_0_0 := v_0_0.Args[0]
-		if v_0_0_0.Op != OpAMD64SBBQcarrymask {
-			break
-		}
-		x := v_0_0_0.Args[0]
-		v.copyOf(x)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPSMasked256)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
-	// match: (Select1 (AddTupleFirst32 _ tuple))
-	// result: (Select1 tuple)
+}
+func rewriteValueAMD64_OpTruncWithPrecisionMaskedFloat64x2(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (TruncWithPrecisionMaskedFloat64x2 [a] x mask)
+	// result: (VRNDSCALEPDMasked128 [a+3] x (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		if v_0.Op != OpAMD64AddTupleFirst32 {
-			break
-		}
-		tuple := v_0.Args[1]
-		v.reset(OpSelect1)
-		v.AddArg(tuple)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPDMasked128)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
-	// match: (Select1 (AddTupleFirst64 _ tuple))
-	// result: (Select1 tuple)
+}
+func rewriteValueAMD64_OpTruncWithPrecisionMaskedFloat64x4(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (TruncWithPrecisionMaskedFloat64x4 [a] x mask)
+	// result: (VRNDSCALEPDMasked256 [a+3] x (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		if v_0.Op != OpAMD64AddTupleFirst64 {
-			break
-		}
-		tuple := v_0.Args[1]
-		v.reset(OpSelect1)
-		v.AddArg(tuple)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPDMasked256)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
-	// match: (Select1 a:(LoweredAtomicAnd64 ptr val mem))
-	// cond: a.Uses == 1 && clobber(a)
-	// result: (ANDQlock ptr val mem)
+}
+func rewriteValueAMD64_OpTruncWithPrecisionMaskedFloat64x8(v *Value) bool {
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (TruncWithPrecisionMaskedFloat64x8 [a] x mask)
+	// result: (VRNDSCALEPDMasked512 [a+3] x (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		a := v_0
-		if a.Op != OpAMD64LoweredAtomicAnd64 {
-			break
-		}
-		mem := a.Args[2]
-		ptr := a.Args[0]
-		val := a.Args[1]
-		if !(a.Uses == 1 && clobber(a)) {
-			break
-		}
-		v.reset(OpAMD64ANDQlock)
-		v.AddArg3(ptr, val, mem)
+		a := auxIntToInt8(v.AuxInt)
+		x := v_0
+		mask := v_1
+		v.reset(OpAMD64VRNDSCALEPDMasked512)
+		v.AuxInt = int8ToAuxInt(a + 3)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg2(x, v0)
 		return true
 	}
-	// match: (Select1 a:(LoweredAtomicAnd32 ptr val mem))
-	// cond: a.Uses == 1 && clobber(a)
-	// result: (ANDLlock ptr val mem)
+}
+func rewriteValueAMD64_OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x16(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (UnsignedSignedQuadDotProdAccumulateMaskedInt32x16 x y z mask)
+	// result: (VPDPBUSDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		a := v_0
-		if a.Op != OpAMD64LoweredAtomicAnd32 {
-			break
-		}
-		mem := a.Args[2]
-		ptr := a.Args[0]
-		val := a.Args[1]
-		if !(a.Uses == 1 && clobber(a)) {
-			break
-		}
-		v.reset(OpAMD64ANDLlock)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPDPBUSDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	// match: (Select1 a:(LoweredAtomicOr64 ptr val mem))
-	// cond: a.Uses == 1 && clobber(a)
-	// result: (ORQlock ptr val mem)
+}
+func rewriteValueAMD64_OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x4(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (UnsignedSignedQuadDotProdAccumulateMaskedInt32x4 x y z mask)
+	// result: (VPDPBUSDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		a := v_0
-		if a.Op != OpAMD64LoweredAtomicOr64 {
-			break
-		}
-		mem := a.Args[2]
-		ptr := a.Args[0]
-		val := a.Args[1]
-		if !(a.Uses == 1 && clobber(a)) {
-			break
-		}
-		v.reset(OpAMD64ORQlock)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPDPBUSDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	// match: (Select1 a:(LoweredAtomicOr32 ptr val mem))
-	// cond: a.Uses == 1 && clobber(a)
-	// result: (ORLlock ptr val mem)
+}
+func rewriteValueAMD64_OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x8(v *Value) bool {
+	v_3 := v.Args[3]
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (UnsignedSignedQuadDotProdAccumulateMaskedInt32x8 x y z mask)
+	// result: (VPDPBUSDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		a := v_0
-		if a.Op != OpAMD64LoweredAtomicOr32 {
-			break
-		}
-		mem := a.Args[2]
-		ptr := a.Args[0]
-		val := a.Args[1]
-		if !(a.Uses == 1 && clobber(a)) {
-			break
-		}
-		v.reset(OpAMD64ORLlock)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		y := v_1
+		z := v_2
+		mask := v_3
+		v.reset(OpAMD64VPDPBUSDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg4(x, y, z, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpSelectN(v *Value) bool {
+func rewriteValueAMD64_OpXorMaskedInt32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	config := b.Func.Config
-	// match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem)))))
-	// cond: sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)
-	// result: (Move [sc.Val64()] dst src mem)
+	// match: (XorMaskedInt32x16 x y mask)
+	// result: (VPXORDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 0 {
-			break
-		}
-		call := v_0
-		if call.Op != OpAMD64CALLstatic || len(call.Args) != 1 {
-			break
-		}
-		sym := auxToCall(call.Aux)
-		s1 := call.Args[0]
-		if s1.Op != OpAMD64MOVQstoreconst {
-			break
-		}
-		sc := auxIntToValAndOff(s1.AuxInt)
-		_ = s1.Args[1]
-		s2 := s1.Args[1]
-		if s2.Op != OpAMD64MOVQstore {
-			break
-		}
-		_ = s2.Args[2]
-		src := s2.Args[1]
-		s3 := s2.Args[2]
-		if s3.Op != OpAMD64MOVQstore {
-			break
-		}
-		mem := s3.Args[2]
-		dst := s3.Args[1]
-		if !(sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)) {
-			break
-		}
-		v.reset(OpMove)
-		v.AuxInt = int64ToAuxInt(sc.Val64())
-		v.AddArg3(dst, src, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPXORDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem))
-	// cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)
-	// result: (Move [sz] dst src mem)
+}
+func rewriteValueAMD64_OpXorMaskedInt32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (XorMaskedInt32x4 x y mask)
+	// result: (VPXORDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		if auxIntToInt64(v.AuxInt) != 0 {
-			break
-		}
-		call := v_0
-		if call.Op != OpAMD64CALLstatic || len(call.Args) != 4 {
-			break
-		}
-		sym := auxToCall(call.Aux)
-		mem := call.Args[3]
-		dst := call.Args[0]
-		src := call.Args[1]
-		call_2 := call.Args[2]
-		if call_2.Op != OpAMD64MOVQconst {
-			break
-		}
-		sz := auxIntToInt64(call_2.AuxInt)
-		if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) {
-			break
-		}
-		v.reset(OpMove)
-		v.AuxInt = int64ToAuxInt(sz)
-		v.AddArg3(dst, src, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPXORDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpSlicemask(v *Value) bool {
+func rewriteValueAMD64_OpXorMaskedInt32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	// match: (Slicemask <t> x)
-	// result: (SARQconst (NEGQ <t> x) [63])
+	// match: (XorMaskedInt32x8 x y mask)
+	// result: (VPXORDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		t := v.Type
 		x := v_0
-		v.reset(OpAMD64SARQconst)
-		v.AuxInt = int8ToAuxInt(63)
-		v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
-		v0.AddArg(x)
-		v.AddArg(v0)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPXORDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpSpectreIndex(v *Value) bool {
+func rewriteValueAMD64_OpXorMaskedInt64x2(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (SpectreIndex <t> x y)
-	// result: (CMOVQCC x (MOVQconst [0]) (CMPQ x y))
+	// match: (XorMaskedInt64x2 x y mask)
+	// result: (VPXORQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64CMOVQCC)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
-		v0.AuxInt = int64ToAuxInt(0)
-		v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
-		v1.AddArg2(x, y)
-		v.AddArg3(x, v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPXORQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpSpectreSliceIndex(v *Value) bool {
+func rewriteValueAMD64_OpXorMaskedInt64x4(v *Value) bool {
+	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
 	b := v.Block
-	typ := &b.Func.Config.Types
-	// match: (SpectreSliceIndex <t> x y)
-	// result: (CMOVQHI x (MOVQconst [0]) (CMPQ x y))
+	// match: (XorMaskedInt64x4 x y mask)
+	// result: (VPXORQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
 		x := v_0
 		y := v_1
-		v.reset(OpAMD64CMOVQHI)
-		v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
-		v0.AuxInt = int64ToAuxInt(0)
-		v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
-		v1.AddArg2(x, y)
-		v.AddArg3(x, v0, v1)
+		mask := v_2
+		v.reset(OpAMD64VPXORQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
-func rewriteValueAMD64_OpStore(v *Value) bool {
+func rewriteValueAMD64_OpXorMaskedInt64x8(v *Value) bool {
 	v_2 := v.Args[2]
 	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (Store {t} ptr val mem)
-	// cond: t.Size() == 8 && t.IsFloat()
-	// result: (MOVSDstore ptr val mem)
+	b := v.Block
+	// match: (XorMaskedInt64x8 x y mask)
+	// result: (VPXORQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
-		t := auxToType(v.Aux)
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		if !(t.Size() == 8 && t.IsFloat()) {
-			break
-		}
-		v.reset(OpAMD64MOVSDstore)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPXORQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Store {t} ptr val mem)
-	// cond: t.Size() == 4 && t.IsFloat()
-	// result: (MOVSSstore ptr val mem)
+}
+func rewriteValueAMD64_OpXorMaskedUint32x16(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (XorMaskedUint32x16 x y mask)
+	// result: (VPXORDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 	for {
-		t := auxToType(v.Aux)
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		if !(t.Size() == 4 && t.IsFloat()) {
-			break
-		}
-		v.reset(OpAMD64MOVSSstore)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPXORDMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Store {t} ptr val mem)
-	// cond: t.Size() == 8 && !t.IsFloat()
-	// result: (MOVQstore ptr val mem)
+}
+func rewriteValueAMD64_OpXorMaskedUint32x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (XorMaskedUint32x4 x y mask)
+	// result: (VPXORDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 	for {
-		t := auxToType(v.Aux)
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		if !(t.Size() == 8 && !t.IsFloat()) {
-			break
-		}
-		v.reset(OpAMD64MOVQstore)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPXORDMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Store {t} ptr val mem)
-	// cond: t.Size() == 4 && !t.IsFloat()
-	// result: (MOVLstore ptr val mem)
+}
+func rewriteValueAMD64_OpXorMaskedUint32x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (XorMaskedUint32x8 x y mask)
+	// result: (VPXORDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 	for {
-		t := auxToType(v.Aux)
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		if !(t.Size() == 4 && !t.IsFloat()) {
-			break
-		}
-		v.reset(OpAMD64MOVLstore)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPXORDMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Store {t} ptr val mem)
-	// cond: t.Size() == 2
-	// result: (MOVWstore ptr val mem)
+}
+func rewriteValueAMD64_OpXorMaskedUint64x2(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (XorMaskedUint64x2 x y mask)
+	// result: (VPXORQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 	for {
-		t := auxToType(v.Aux)
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		if !(t.Size() == 2) {
-			break
-		}
-		v.reset(OpAMD64MOVWstore)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPXORQMasked128)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	// match: (Store {t} ptr val mem)
-	// cond: t.Size() == 1
-	// result: (MOVBstore ptr val mem)
+}
+func rewriteValueAMD64_OpXorMaskedUint64x4(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
+	v_0 := v.Args[0]
+	b := v.Block
+	// match: (XorMaskedUint64x4 x y mask)
+	// result: (VPXORQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 	for {
-		t := auxToType(v.Aux)
-		ptr := v_0
-		val := v_1
-		mem := v_2
-		if !(t.Size() == 1) {
-			break
-		}
-		v.reset(OpAMD64MOVBstore)
-		v.AddArg3(ptr, val, mem)
+		x := v_0
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPXORQMasked256)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
-	return false
 }
-func rewriteValueAMD64_OpTrunc(v *Value) bool {
+func rewriteValueAMD64_OpXorMaskedUint64x8(v *Value) bool {
+	v_2 := v.Args[2]
+	v_1 := v.Args[1]
 	v_0 := v.Args[0]
-	// match: (Trunc x)
-	// result: (ROUNDSD [3] x)
+	b := v.Block
+	// match: (XorMaskedUint64x8 x y mask)
+	// result: (VPXORQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 	for {
 		x := v_0
-		v.reset(OpAMD64ROUNDSD)
-		v.AuxInt = int8ToAuxInt(3)
-		v.AddArg(x)
+		y := v_1
+		mask := v_2
+		v.reset(OpAMD64VPXORQMasked512)
+		v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+		v0.AddArg(mask)
+		v.AddArg3(x, y, v0)
 		return true
 	}
 }
@@ -30117,6 +54438,45 @@ func rewriteValueAMD64_OpZero(v *Value) bool {
 	}
 	return false
 }
+func rewriteValueAMD64_OpZeroSIMD(v *Value) bool {
+	// match: (ZeroSIMD <t>)
+	// cond: t.Size() == 16
+	// result: (Zero128 <t>)
+	for {
+		t := v.Type
+		if !(t.Size() == 16) {
+			break
+		}
+		v.reset(OpAMD64Zero128)
+		v.Type = t
+		return true
+	}
+	// match: (ZeroSIMD <t>)
+	// cond: t.Size() == 32
+	// result: (Zero256 <t>)
+	for {
+		t := v.Type
+		if !(t.Size() == 32) {
+			break
+		}
+		v.reset(OpAMD64Zero256)
+		v.Type = t
+		return true
+	}
+	// match: (ZeroSIMD <t>)
+	// cond: t.Size() == 64
+	// result: (Zero512 <t>)
+	for {
+		t := v.Type
+		if !(t.Size() == 64) {
+			break
+		}
+		v.reset(OpAMD64Zero512)
+		v.Type = t
+		return true
+	}
+	return false
+}
 func rewriteBlockAMD64(b *Block) bool {
 	typ := &b.Func.Config.Types
 	switch b.Kind {
diff --git a/src/cmd/compile/internal/ssa/rewritegeneric.go b/src/cmd/compile/internal/ssa/rewritegeneric.go
index bfbd3c8522ed24..b7a4ff95d1af63 100644
--- a/src/cmd/compile/internal/ssa/rewritegeneric.go
+++ b/src/cmd/compile/internal/ssa/rewritegeneric.go
@@ -14149,11 +14149,11 @@ func rewriteValuegeneric_OpLoad(v *Value) bool {
 		return true
 	}
 	// match: (Load <t> _ _)
-	// cond: t.IsStruct() && CanSSA(t)
+	// cond: t.IsStruct() && CanSSA(t) && !t.IsSIMD()
 	// result: rewriteStructLoad(v)
 	for {
 		t := v.Type
-		if !(t.IsStruct() && CanSSA(t)) {
+		if !(t.IsStruct() && CanSSA(t) && !t.IsSIMD()) {
 			break
 		}
 		v.copyOf(rewriteStructLoad(v))
diff --git a/src/cmd/compile/internal/ssa/value.go b/src/cmd/compile/internal/ssa/value.go
index e80b712ddba764..8f921a80037a77 100644
--- a/src/cmd/compile/internal/ssa/value.go
+++ b/src/cmd/compile/internal/ssa/value.go
@@ -596,6 +596,9 @@ func AutoVar(v *Value) (*ir.Name, int64) {
 // CanSSA reports whether values of type t can be represented as a Value.
 func CanSSA(t *types.Type) bool {
 	types.CalcSize(t)
+	if t.IsSIMD() {
+		return true
+	}
 	if t.Size() > int64(4*types.PtrSize) {
 		// 4*Widthptr is an arbitrary constant. We want it
 		// to be at least 3*Widthptr so slices can be registerized.
diff --git a/src/cmd/compile/internal/ssagen/abi.go b/src/cmd/compile/internal/ssagen/abi.go
index 3d50155cf36d10..0e8dbd944540e0 100644
--- a/src/cmd/compile/internal/ssagen/abi.go
+++ b/src/cmd/compile/internal/ssagen/abi.go
@@ -99,6 +99,18 @@ func (s *SymABIs) ReadSymABIs(file string) {
 	}
 }
 
+// HasDef returns whether the given symbol has an assembly definition.
+func (s *SymABIs) HasDef(sym *types.Sym) bool {
+	symName := sym.Linkname
+	if symName == "" {
+		symName = sym.Pkg.Prefix + "." + sym.Name
+	}
+	symName = s.canonicalize(symName)
+
+	_, hasDefABI := s.defs[symName]
+	return hasDefABI
+}
+
 // GenABIWrappers applies ABI information to Funcs and generates ABI
 // wrapper functions where necessary.
 func (s *SymABIs) GenABIWrappers() {
diff --git a/src/cmd/compile/internal/ssagen/intrinsics.go b/src/cmd/compile/internal/ssagen/intrinsics.go
index 6b58e7e5914538..337f0b86e61136 100644
--- a/src/cmd/compile/internal/ssagen/intrinsics.go
+++ b/src/cmd/compile/internal/ssagen/intrinsics.go
@@ -12,6 +12,7 @@ import (
 	"cmd/compile/internal/base"
 	"cmd/compile/internal/ir"
 	"cmd/compile/internal/ssa"
+	"cmd/compile/internal/typecheck"
 	"cmd/compile/internal/types"
 	"cmd/internal/sys"
 )
@@ -1602,6 +1603,176 @@ func initIntrinsics(cfg *intrinsicBuildConfig) {
 			return s.newValue1(ssa.OpZeroExt8to64, types.Types[types.TUINT64], out)
 		},
 		sys.AMD64)
+
+	if buildcfg.Experiment.SIMD {
+		// Only enable intrinsics, if SIMD experiment.
+		simdIntrinsics(addF)
+	}
+}
+
+func opLen1(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		return s.newValue1(op, t, args[0])
+	}
+}
+
+func opLen2(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		return s.newValue2(op, t, args[0], args[1])
+	}
+}
+
+func opLen2_21(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		return s.newValue2(op, t, args[1], args[0])
+	}
+}
+
+func opLen3(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		return s.newValue3(op, t, args[0], args[1], args[2])
+	}
+}
+
+func opLen3_31(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		return s.newValue3(op, t, args[2], args[1], args[0])
+	}
+}
+
+func opLen3_21(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		return s.newValue3(op, t, args[1], args[0], args[2])
+	}
+}
+
+func opLen3_231(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		return s.newValue3(op, t, args[2], args[0], args[1])
+	}
+}
+
+func opLen4(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		return s.newValue4(op, t, args[0], args[1], args[2], args[3])
+	}
+}
+
+func opLen4_231(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		return s.newValue4(op, t, args[2], args[0], args[1], args[3])
+	}
+}
+
+func opLen4_31(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		return s.newValue4(op, t, args[2], args[1], args[0], args[3])
+	}
+}
+
+func plainPanicSimdImm(s *state) {
+	cmp := s.newValue0(ssa.OpConstBool, types.Types[types.TBOOL])
+	cmp.AuxInt = 0
+	// TODO: make this a standalone panic instead of reusing the overflow panic.
+	// Or maybe after we implement the switch table this will be obsolete anyway.
+	s.check(cmp, ir.Syms.Panicoverflow)
+}
+
+func opLen1Imm8(op ssa.Op, t *types.Type, offset int) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		if args[1].Op == ssa.OpConst8 {
+			return s.newValue1I(op, t, args[1].AuxInt<<int64(offset), args[0])
+		}
+		plainPanicSimdImm(s)
+		// Even though this default call is unreachable semantically,
+		// it has to return something, otherwise the compiler will try to generate
+		// default codes which might lead to a FwdRef being put at the entry block
+		// triggering a compiler panic.
+		return s.newValue1I(op, t, 0, args[0])
+	}
+}
+
+func opLen2Imm8(op ssa.Op, t *types.Type, offset int) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		if args[1].Op == ssa.OpConst8 {
+			return s.newValue2I(op, t, args[1].AuxInt<<int64(offset), args[0], args[2])
+		}
+		plainPanicSimdImm(s)
+		// Even though this default call is unreachable semantically,
+		// it has to return something, otherwise the compiler will try to generate
+		// default codes which might lead to a FwdRef being put at the entry block
+		// triggering a compiler panic.
+		return s.newValue2I(op, t, 0, args[0], args[2])
+	}
+}
+
+func opLen3Imm8(op ssa.Op, t *types.Type, offset int) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		if args[1].Op == ssa.OpConst8 {
+			return s.newValue3I(op, t, args[1].AuxInt<<int64(offset), args[0], args[2], args[3])
+		}
+		plainPanicSimdImm(s)
+		// Even though this default call is unreachable semantically,
+		// it has to return something, otherwise the compiler will try to generate
+		// default codes which might lead to a FwdRef being put at the entry block
+		// triggering a compiler panic.
+		return s.newValue3I(op, t, 0, args[0], args[2], args[3])
+	}
+}
+
+func opLen2Imm8_2I(op ssa.Op, t *types.Type, offset int) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		if args[1].Op == ssa.OpConst8 {
+			return s.newValue2I(op, t, args[2].AuxInt<<int64(offset), args[0], args[1])
+		}
+		plainPanicSimdImm(s)
+		// Even though this default call is unreachable semantically,
+		// it has to return something, otherwise the compiler will try to generate
+		// default codes which might lead to a FwdRef being put at the entry block
+		// triggering a compiler panic.
+		return s.newValue2I(op, t, 0, args[0], args[1])
+	}
+}
+
+func opLen3Imm8_2I(op ssa.Op, t *types.Type, offset int) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		if args[1].Op == ssa.OpConst8 {
+			return s.newValue3I(op, t, args[2].AuxInt<<int64(offset), args[0], args[1], args[3])
+		}
+		plainPanicSimdImm(s)
+		// Even though this default call is unreachable semantically,
+		// it has to return something, otherwise the compiler will try to generate
+		// default codes which might lead to a FwdRef being put at the entry block
+		// triggering a compiler panic.
+		return s.newValue3I(op, t, 0, args[0], args[1], args[3])
+	}
+}
+
+func opLen4Imm8(op ssa.Op, t *types.Type, offset int) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		if args[1].Op == ssa.OpConst8 {
+			return s.newValue4I(op, t, args[1].AuxInt<<int64(offset), args[0], args[2], args[3], args[4])
+		}
+		plainPanicSimdImm(s)
+		// Even though this default call is unreachable semantically,
+		// it has to return something, otherwise the compiler will try to generate
+		// default codes which might lead to a FwdRef being put at the entry block
+		// triggering a compiler panic.
+		return s.newValue4I(op, t, 0, args[0], args[2], args[3], args[4])
+	}
+}
+
+func simdLoad() func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		return s.newValue2(ssa.OpLoad, n.Type(), args[0], s.mem())
+	}
+}
+
+func simdStore() func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+	return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
+		s.store(args[0].Type, args[1], args[0])
+		return nil
+	}
 }
 
 // findIntrinsic returns a function which builds the SSA equivalent of the
@@ -1627,7 +1798,8 @@ func findIntrinsic(sym *types.Sym) intrinsicBuilder {
 
 	fn := sym.Name
 	if ssa.IntrinsicsDisable {
-		if pkg == "internal/runtime/sys" && (fn == "GetCallerPC" || fn == "GrtCallerSP" || fn == "GetClosurePtr") {
+		if pkg == "internal/runtime/sys" && (fn == "GetCallerPC" || fn == "GrtCallerSP" || fn == "GetClosurePtr") ||
+			pkg == "internal/simd" || pkg == "simd" { // TODO after simd has been moved to package simd, remove internal/simd
 			// These runtime functions don't have definitions, must be intrinsics.
 		} else {
 			return nil
@@ -1644,5 +1816,65 @@ func IsIntrinsicCall(n *ir.CallExpr) bool {
 	if !ok {
 		return false
 	}
-	return findIntrinsic(name.Sym()) != nil
+	return IsIntrinsicSym(name.Sym())
+}
+
+func IsIntrinsicSym(sym *types.Sym) bool {
+	return findIntrinsic(sym) != nil
+}
+
+// GenIntrinsicBody generates the function body for a bodyless intrinsic.
+// This is used when the intrinsic is used in a non-call context, e.g.
+// as a function pointer, or (for a method) being referenced from the type
+// descriptor.
+//
+// The compiler already recognizes a call to fn as an intrinsic and can
+// directly generate code for it. So we just fill in the body with a call
+// to fn.
+func GenIntrinsicBody(fn *ir.Func) {
+	if ir.CurFunc != nil {
+		base.FatalfAt(fn.Pos(), "enqueueFunc %v inside %v", fn, ir.CurFunc)
+	}
+
+	if base.Flag.LowerR != 0 {
+		fmt.Println("generate intrinsic for", ir.FuncName(fn))
+	}
+
+	pos := fn.Pos()
+	ft := fn.Type()
+	var ret ir.Node
+
+	// For a method, it usually starts with an ODOTMETH (pre-typecheck) or
+	// OMETHEXPR (post-typecheck) referencing the method symbol without the
+	// receiver type, and Walk rewrites it to a call directly to the
+	// type-qualified method symbol, moving the receiver to an argument.
+	// Here fn has already the type-qualified method symbol, and it is hard
+	// to get the unqualified symbol. So we just generate the post-Walk form
+	// and mark it typechecked and Walked.
+	call := ir.NewCallExpr(pos, ir.OCALLFUNC, fn.Nname, nil)
+	call.Args = ir.RecvParamNames(ft)
+	call.IsDDD = ft.IsVariadic()
+	typecheck.Exprs(call.Args)
+	call.SetTypecheck(1)
+	call.SetWalked(true)
+	ret = call
+	if ft.NumResults() > 0 {
+		if ft.NumResults() == 1 {
+			call.SetType(ft.Result(0).Type)
+		} else {
+			call.SetType(ft.ResultsTuple())
+		}
+		n := ir.NewReturnStmt(base.Pos, nil)
+		n.Results = []ir.Node{call}
+		ret = n
+	}
+	fn.Body.Append(ret)
+
+	if base.Flag.LowerR != 0 {
+		ir.DumpList("generate intrinsic body", fn.Body)
+	}
+
+	ir.CurFunc = fn
+	typecheck.Stmts(fn.Body)
+	ir.CurFunc = nil // we know CurFunc is nil at entry
 }
diff --git a/src/cmd/compile/internal/ssagen/intrinsics_test.go b/src/cmd/compile/internal/ssagen/intrinsics_test.go
index 0623c5f2098c4e..7a212f1c3ae06c 100644
--- a/src/cmd/compile/internal/ssagen/intrinsics_test.go
+++ b/src/cmd/compile/internal/ssagen/intrinsics_test.go
@@ -16,6 +16,9 @@ import (
 
 var updateIntrinsics = flag.Bool("update", false, "Print an updated intrinsics table")
 
+// TODO turn on after SIMD is stable.  The time burned keeping this test happy during SIMD development has already well exceeded any plausible benefit.
+var simd = flag.Bool("simd", false, "Also check SIMD intrinsics; for now, it is noisy and not helpful")
+
 type testIntrinsicKey struct {
 	archName string
 	pkg      string
@@ -1375,13 +1378,13 @@ func TestIntrinsics(t *testing.T) {
 		gotIntrinsics[testIntrinsicKey{ik.arch.Name, ik.pkg, ik.fn}] = struct{}{}
 	}
 	for ik, _ := range gotIntrinsics {
-		if _, found := wantIntrinsics[ik]; !found {
+		if _, found := wantIntrinsics[ik]; !found && (ik.pkg != "simd" || *simd) {
 			t.Errorf("Got unwanted intrinsic %v %v.%v", ik.archName, ik.pkg, ik.fn)
 		}
 	}
 
 	for ik, _ := range wantIntrinsics {
-		if _, found := gotIntrinsics[ik]; !found {
+		if _, found := gotIntrinsics[ik]; !found && (ik.pkg != "simd" || *simd) {
 			t.Errorf("Want missing intrinsic %v %v.%v", ik.archName, ik.pkg, ik.fn)
 		}
 	}
diff --git a/src/cmd/compile/internal/ssagen/simdintrinsics.go b/src/cmd/compile/internal/ssagen/simdintrinsics.go
new file mode 100644
index 00000000000000..3d9294990853e6
--- /dev/null
+++ b/src/cmd/compile/internal/ssagen/simdintrinsics.go
@@ -0,0 +1,2207 @@
+// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT.
+package ssagen
+
+import (
+	"cmd/compile/internal/ir"
+	"cmd/compile/internal/ssa"
+	"cmd/compile/internal/types"
+	"cmd/internal/sys"
+)
+
+const simdPackage = "simd"
+
+func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies ...sys.ArchFamily)) {
+	addF(simdPackage, "Int8x16.Absolute", opLen1(ssa.OpAbsoluteInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Absolute", opLen1(ssa.OpAbsoluteInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.Absolute", opLen1(ssa.OpAbsoluteInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.Absolute", opLen1(ssa.OpAbsoluteInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Absolute", opLen1(ssa.OpAbsoluteInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.Absolute", opLen1(ssa.OpAbsoluteInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.Absolute", opLen1(ssa.OpAbsoluteInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.Absolute", opLen1(ssa.OpAbsoluteInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.Absolute", opLen1(ssa.OpAbsoluteInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.Absolute", opLen1(ssa.OpAbsoluteInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.Absolute", opLen1(ssa.OpAbsoluteInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.Absolute", opLen1(ssa.OpAbsoluteInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.AbsoluteMasked", opLen2(ssa.OpAbsoluteMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.AbsoluteMasked", opLen2(ssa.OpAbsoluteMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.AbsoluteMasked", opLen2(ssa.OpAbsoluteMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.AbsoluteMasked", opLen2(ssa.OpAbsoluteMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.AbsoluteMasked", opLen2(ssa.OpAbsoluteMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.AbsoluteMasked", opLen2(ssa.OpAbsoluteMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.AbsoluteMasked", opLen2(ssa.OpAbsoluteMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.AbsoluteMasked", opLen2(ssa.OpAbsoluteMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.AbsoluteMasked", opLen2(ssa.OpAbsoluteMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.AbsoluteMasked", opLen2(ssa.OpAbsoluteMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.AbsoluteMasked", opLen2(ssa.OpAbsoluteMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.AbsoluteMasked", opLen2(ssa.OpAbsoluteMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.Add", opLen2(ssa.OpAddFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Add", opLen2(ssa.OpAddFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Add", opLen2(ssa.OpAddFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.Add", opLen2(ssa.OpAddFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Add", opLen2(ssa.OpAddFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Add", opLen2(ssa.OpAddFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.Add", opLen2(ssa.OpAddInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Add", opLen2(ssa.OpAddInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.Add", opLen2(ssa.OpAddInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.Add", opLen2(ssa.OpAddInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Add", opLen2(ssa.OpAddInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.Add", opLen2(ssa.OpAddInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.Add", opLen2(ssa.OpAddInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.Add", opLen2(ssa.OpAddInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.Add", opLen2(ssa.OpAddInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.Add", opLen2(ssa.OpAddInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.Add", opLen2(ssa.OpAddInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.Add", opLen2(ssa.OpAddInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Add", opLen2(ssa.OpAddUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Add", opLen2(ssa.OpAddUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.Add", opLen2(ssa.OpAddUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Add", opLen2(ssa.OpAddUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Add", opLen2(ssa.OpAddUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.Add", opLen2(ssa.OpAddUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.Add", opLen2(ssa.OpAddUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Add", opLen2(ssa.OpAddUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Add", opLen2(ssa.OpAddUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.Add", opLen2(ssa.OpAddUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Add", opLen2(ssa.OpAddUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Add", opLen2(ssa.OpAddUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.AddMasked", opLen3(ssa.OpAddMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.AddMasked", opLen3(ssa.OpAddMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.AddMasked", opLen3(ssa.OpAddMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.AddMasked", opLen3(ssa.OpAddMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.AddMasked", opLen3(ssa.OpAddMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.AddMasked", opLen3(ssa.OpAddMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.AddMasked", opLen3(ssa.OpAddMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.AddMasked", opLen3(ssa.OpAddMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.AddMasked", opLen3(ssa.OpAddMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.AddMasked", opLen3(ssa.OpAddMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.AddMasked", opLen3(ssa.OpAddMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.AddMasked", opLen3(ssa.OpAddMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.AddMasked", opLen3(ssa.OpAddMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.AddMasked", opLen3(ssa.OpAddMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.AddMasked", opLen3(ssa.OpAddMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.AddMasked", opLen3(ssa.OpAddMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.AddMasked", opLen3(ssa.OpAddMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.AddMasked", opLen3(ssa.OpAddMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.AddMasked", opLen3(ssa.OpAddMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.AddMasked", opLen3(ssa.OpAddMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.AddMasked", opLen3(ssa.OpAddMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.AddMasked", opLen3(ssa.OpAddMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.AddMasked", opLen3(ssa.OpAddMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.AddMasked", opLen3(ssa.OpAddMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.AddMasked", opLen3(ssa.OpAddMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.AddMasked", opLen3(ssa.OpAddMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.AddMasked", opLen3(ssa.OpAddMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.AddMasked", opLen3(ssa.OpAddMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.AddMasked", opLen3(ssa.OpAddMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.AddMasked", opLen3(ssa.OpAddMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.AddSub", opLen2(ssa.OpAddSubFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.AddSub", opLen2(ssa.OpAddSubFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x2.AddSub", opLen2(ssa.OpAddSubFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.AddSub", opLen2(ssa.OpAddSubFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x16.And", opLen2(ssa.OpAndInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.And", opLen2(ssa.OpAndInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x8.And", opLen2(ssa.OpAndInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.And", opLen2(ssa.OpAndInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x4.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.And", opLen2(ssa.OpAndInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.And", opLen2(ssa.OpAndInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.And", opLen2(ssa.OpAndInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.And", opLen2(ssa.OpAndInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.And", opLen2(ssa.OpAndInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.And", opLen2(ssa.OpAndUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.And", opLen2(ssa.OpAndUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x8.And", opLen2(ssa.OpAndUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.And", opLen2(ssa.OpAndUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x4.And", opLen2(ssa.OpAndUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.And", opLen2(ssa.OpAndUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.And", opLen2(ssa.OpAndUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.And", opLen2(ssa.OpAndUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.And", opLen2(ssa.OpAndUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.And", opLen2(ssa.OpAndUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.AndMasked", opLen3(ssa.OpAndMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.AndMasked", opLen3(ssa.OpAndMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.AndMasked", opLen3(ssa.OpAndMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.AndMasked", opLen3(ssa.OpAndMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.AndMasked", opLen3(ssa.OpAndMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.AndMasked", opLen3(ssa.OpAndMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.AndMasked", opLen3(ssa.OpAndMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.AndMasked", opLen3(ssa.OpAndMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.AndMasked", opLen3(ssa.OpAndMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.AndMasked", opLen3(ssa.OpAndMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.AndMasked", opLen3(ssa.OpAndMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.AndMasked", opLen3(ssa.OpAndMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.AndNot", opLen2_21(ssa.OpAndNotInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.AndNot", opLen2_21(ssa.OpAndNotInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x8.AndNot", opLen2_21(ssa.OpAndNotInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.AndNot", opLen2_21(ssa.OpAndNotInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x4.AndNot", opLen2_21(ssa.OpAndNotInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.AndNot", opLen2_21(ssa.OpAndNotInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.AndNot", opLen2_21(ssa.OpAndNotInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.AndNot", opLen2_21(ssa.OpAndNotInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.AndNot", opLen2_21(ssa.OpAndNotInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.AndNot", opLen2_21(ssa.OpAndNotInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.AndNot", opLen2_21(ssa.OpAndNotUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.AndNot", opLen2_21(ssa.OpAndNotUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x8.AndNot", opLen2_21(ssa.OpAndNotUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.AndNot", opLen2_21(ssa.OpAndNotUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x4.AndNot", opLen2_21(ssa.OpAndNotUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.AndNot", opLen2_21(ssa.OpAndNotUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.AndNot", opLen2_21(ssa.OpAndNotUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.AndNot", opLen2_21(ssa.OpAndNotUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.AndNot", opLen2_21(ssa.OpAndNotUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.AndNot", opLen2_21(ssa.OpAndNotUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.AndNotMasked", opLen3_21(ssa.OpAndNotMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.AndNotMasked", opLen3_21(ssa.OpAndNotMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.AndNotMasked", opLen3_21(ssa.OpAndNotMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.AndNotMasked", opLen3_21(ssa.OpAndNotMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.AndNotMasked", opLen3_21(ssa.OpAndNotMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.AndNotMasked", opLen3_21(ssa.OpAndNotMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.AndNotMasked", opLen3_21(ssa.OpAndNotMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.AndNotMasked", opLen3_21(ssa.OpAndNotMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.AndNotMasked", opLen3_21(ssa.OpAndNotMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.AndNotMasked", opLen3_21(ssa.OpAndNotMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.AndNotMasked", opLen3_21(ssa.OpAndNotMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.AndNotMasked", opLen3_21(ssa.OpAndNotMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.ApproximateReciprocal", opLen1(ssa.OpApproximateReciprocalFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.ApproximateReciprocal", opLen1(ssa.OpApproximateReciprocalFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.ApproximateReciprocal", opLen1(ssa.OpApproximateReciprocalFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.ApproximateReciprocal", opLen1(ssa.OpApproximateReciprocalFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.ApproximateReciprocal", opLen1(ssa.OpApproximateReciprocalFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.ApproximateReciprocal", opLen1(ssa.OpApproximateReciprocalFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.ApproximateReciprocalMasked", opLen2(ssa.OpApproximateReciprocalMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.ApproximateReciprocalMasked", opLen2(ssa.OpApproximateReciprocalMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.ApproximateReciprocalMasked", opLen2(ssa.OpApproximateReciprocalMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.ApproximateReciprocalMasked", opLen2(ssa.OpApproximateReciprocalMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.ApproximateReciprocalMasked", opLen2(ssa.OpApproximateReciprocalMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.ApproximateReciprocalMasked", opLen2(ssa.OpApproximateReciprocalMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.ApproximateReciprocalOfSqrt", opLen1(ssa.OpApproximateReciprocalOfSqrtFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.ApproximateReciprocalOfSqrt", opLen1(ssa.OpApproximateReciprocalOfSqrtFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.ApproximateReciprocalOfSqrt", opLen1(ssa.OpApproximateReciprocalOfSqrtFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.ApproximateReciprocalOfSqrt", opLen1(ssa.OpApproximateReciprocalOfSqrtFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.ApproximateReciprocalOfSqrt", opLen1(ssa.OpApproximateReciprocalOfSqrtFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.ApproximateReciprocalOfSqrt", opLen1(ssa.OpApproximateReciprocalOfSqrtFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.ApproximateReciprocalOfSqrtMasked", opLen2(ssa.OpApproximateReciprocalOfSqrtMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.ApproximateReciprocalOfSqrtMasked", opLen2(ssa.OpApproximateReciprocalOfSqrtMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.ApproximateReciprocalOfSqrtMasked", opLen2(ssa.OpApproximateReciprocalOfSqrtMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.ApproximateReciprocalOfSqrtMasked", opLen2(ssa.OpApproximateReciprocalOfSqrtMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.ApproximateReciprocalOfSqrtMasked", opLen2(ssa.OpApproximateReciprocalOfSqrtMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.ApproximateReciprocalOfSqrtMasked", opLen2(ssa.OpApproximateReciprocalOfSqrtMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Average", opLen2(ssa.OpAverageUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Average", opLen2(ssa.OpAverageUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.Average", opLen2(ssa.OpAverageUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Average", opLen2(ssa.OpAverageUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Average", opLen2(ssa.OpAverageUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.Average", opLen2(ssa.OpAverageUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.AverageMasked", opLen3(ssa.OpAverageMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.AverageMasked", opLen3(ssa.OpAverageMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.AverageMasked", opLen3(ssa.OpAverageMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.AverageMasked", opLen3(ssa.OpAverageMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.AverageMasked", opLen3(ssa.OpAverageMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.AverageMasked", opLen3(ssa.OpAverageMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.Ceil", opLen1(ssa.OpCeilFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Ceil", opLen1(ssa.OpCeilFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x2.Ceil", opLen1(ssa.OpCeilFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Ceil", opLen1(ssa.OpCeilFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x4.CeilWithPrecision", opLen1Imm8(ssa.OpCeilWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.CeilWithPrecision", opLen1Imm8(ssa.OpCeilWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.CeilWithPrecision", opLen1Imm8(ssa.OpCeilWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.CeilWithPrecision", opLen1Imm8(ssa.OpCeilWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.CeilWithPrecision", opLen1Imm8(ssa.OpCeilWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.CeilWithPrecision", opLen1Imm8(ssa.OpCeilWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.CeilWithPrecisionMasked", opLen2Imm8(ssa.OpCeilWithPrecisionMaskedFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.CeilWithPrecisionMasked", opLen2Imm8(ssa.OpCeilWithPrecisionMaskedFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.CeilWithPrecisionMasked", opLen2Imm8(ssa.OpCeilWithPrecisionMaskedFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.CeilWithPrecisionMasked", opLen2Imm8(ssa.OpCeilWithPrecisionMaskedFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.CeilWithPrecisionMasked", opLen2Imm8(ssa.OpCeilWithPrecisionMaskedFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.CeilWithPrecisionMasked", opLen2Imm8(ssa.OpCeilWithPrecisionMaskedFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.Compress", opLen2(ssa.OpCompressFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Compress", opLen2(ssa.OpCompressFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Compress", opLen2(ssa.OpCompressFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.Compress", opLen2(ssa.OpCompressFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Compress", opLen2(ssa.OpCompressFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Compress", opLen2(ssa.OpCompressFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.Compress", opLen2(ssa.OpCompressInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Compress", opLen2(ssa.OpCompressInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.Compress", opLen2(ssa.OpCompressInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.Compress", opLen2(ssa.OpCompressInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Compress", opLen2(ssa.OpCompressInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.Compress", opLen2(ssa.OpCompressInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.Compress", opLen2(ssa.OpCompressInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.Compress", opLen2(ssa.OpCompressInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.Compress", opLen2(ssa.OpCompressInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.Compress", opLen2(ssa.OpCompressInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.Compress", opLen2(ssa.OpCompressInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.Compress", opLen2(ssa.OpCompressInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Compress", opLen2(ssa.OpCompressUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Compress", opLen2(ssa.OpCompressUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.Compress", opLen2(ssa.OpCompressUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Compress", opLen2(ssa.OpCompressUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Compress", opLen2(ssa.OpCompressUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.Compress", opLen2(ssa.OpCompressUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.Compress", opLen2(ssa.OpCompressUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Compress", opLen2(ssa.OpCompressUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Compress", opLen2(ssa.OpCompressUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.Compress", opLen2(ssa.OpCompressUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Compress", opLen2(ssa.OpCompressUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Compress", opLen2(ssa.OpCompressUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.DiffWithCeilWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.DiffWithCeilWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.DiffWithCeilWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.DiffWithCeilWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.DiffWithCeilWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.DiffWithCeilWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.DiffWithCeilWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithCeilWithPrecisionMaskedFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.DiffWithCeilWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithCeilWithPrecisionMaskedFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.DiffWithCeilWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithCeilWithPrecisionMaskedFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.DiffWithCeilWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithCeilWithPrecisionMaskedFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.DiffWithCeilWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithCeilWithPrecisionMaskedFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.DiffWithCeilWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithCeilWithPrecisionMaskedFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.DiffWithFloorWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.DiffWithFloorWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.DiffWithFloorWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.DiffWithFloorWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.DiffWithFloorWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.DiffWithFloorWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.DiffWithFloorWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithFloorWithPrecisionMaskedFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.DiffWithFloorWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithFloorWithPrecisionMaskedFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.DiffWithFloorWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithFloorWithPrecisionMaskedFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.DiffWithFloorWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithFloorWithPrecisionMaskedFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.DiffWithFloorWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithFloorWithPrecisionMaskedFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.DiffWithFloorWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithFloorWithPrecisionMaskedFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.DiffWithRoundWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.DiffWithRoundWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.DiffWithRoundWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.DiffWithRoundWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.DiffWithRoundWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.DiffWithRoundWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.DiffWithRoundWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithRoundWithPrecisionMaskedFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.DiffWithRoundWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithRoundWithPrecisionMaskedFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.DiffWithRoundWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithRoundWithPrecisionMaskedFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.DiffWithRoundWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithRoundWithPrecisionMaskedFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.DiffWithRoundWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithRoundWithPrecisionMaskedFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.DiffWithRoundWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithRoundWithPrecisionMaskedFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.DiffWithTruncWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.DiffWithTruncWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.DiffWithTruncWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.DiffWithTruncWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.DiffWithTruncWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.DiffWithTruncWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.DiffWithTruncWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithTruncWithPrecisionMaskedFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.DiffWithTruncWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithTruncWithPrecisionMaskedFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.DiffWithTruncWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithTruncWithPrecisionMaskedFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.DiffWithTruncWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithTruncWithPrecisionMaskedFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.DiffWithTruncWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithTruncWithPrecisionMaskedFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.DiffWithTruncWithPrecisionMasked", opLen2Imm8(ssa.OpDiffWithTruncWithPrecisionMaskedFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.Div", opLen2(ssa.OpDivFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Div", opLen2(ssa.OpDivFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Div", opLen2(ssa.OpDivFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.Div", opLen2(ssa.OpDivFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Div", opLen2(ssa.OpDivFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Div", opLen2(ssa.OpDivFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.DivMasked", opLen3(ssa.OpDivMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.DivMasked", opLen3(ssa.OpDivMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.DivMasked", opLen3(ssa.OpDivMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.DivMasked", opLen3(ssa.OpDivMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.DivMasked", opLen3(ssa.OpDivMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.DivMasked", opLen3(ssa.OpDivMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.DotProdBroadcast", opLen2(ssa.OpDotProdBroadcastFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.DotProdBroadcast", opLen2(ssa.OpDotProdBroadcastFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x2.DotProdBroadcast", opLen2(ssa.OpDotProdBroadcastFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x16.Equal", opLen2(ssa.OpEqualInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Equal", opLen2(ssa.OpEqualInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x8.Equal", opLen2(ssa.OpEqualInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Equal", opLen2(ssa.OpEqualInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x4.Equal", opLen2(ssa.OpEqualInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.Equal", opLen2(ssa.OpEqualInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x2.Equal", opLen2(ssa.OpEqualInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.Equal", opLen2(ssa.OpEqualInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Equal", opLen2(ssa.OpEqualUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Equal", opLen2(ssa.OpEqualUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Equal", opLen2(ssa.OpEqualUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Equal", opLen2(ssa.OpEqualUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x4.Equal", opLen2(ssa.OpEqualUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Equal", opLen2(ssa.OpEqualUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x2.Equal", opLen2(ssa.OpEqualUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Equal", opLen2(ssa.OpEqualUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x4.Equal", opLen2(ssa.OpEqualFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Equal", opLen2(ssa.OpEqualFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Equal", opLen2(ssa.OpEqualFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.Equal", opLen2(ssa.OpEqualFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Equal", opLen2(ssa.OpEqualFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Equal", opLen2(ssa.OpEqualFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x64.Equal", opLen2(ssa.OpEqualInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x32.Equal", opLen2(ssa.OpEqualInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x16.Equal", opLen2(ssa.OpEqualInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x8.Equal", opLen2(ssa.OpEqualInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x64.Equal", opLen2(ssa.OpEqualUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x32.Equal", opLen2(ssa.OpEqualUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Equal", opLen2(ssa.OpEqualUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Equal", opLen2(ssa.OpEqualUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.EqualMasked", opLen3(ssa.OpEqualMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.EqualMasked", opLen3(ssa.OpEqualMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.EqualMasked", opLen3(ssa.OpEqualMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.EqualMasked", opLen3(ssa.OpEqualMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.EqualMasked", opLen3(ssa.OpEqualMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.EqualMasked", opLen3(ssa.OpEqualMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.EqualMasked", opLen3(ssa.OpEqualMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.EqualMasked", opLen3(ssa.OpEqualMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.EqualMasked", opLen3(ssa.OpEqualMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.EqualMasked", opLen3(ssa.OpEqualMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.EqualMasked", opLen3(ssa.OpEqualMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.EqualMasked", opLen3(ssa.OpEqualMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.EqualMasked", opLen3(ssa.OpEqualMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.EqualMasked", opLen3(ssa.OpEqualMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.EqualMasked", opLen3(ssa.OpEqualMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.EqualMasked", opLen3(ssa.OpEqualMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.EqualMasked", opLen3(ssa.OpEqualMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.EqualMasked", opLen3(ssa.OpEqualMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.EqualMasked", opLen3(ssa.OpEqualMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.EqualMasked", opLen3(ssa.OpEqualMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.EqualMasked", opLen3(ssa.OpEqualMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.EqualMasked", opLen3(ssa.OpEqualMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.EqualMasked", opLen3(ssa.OpEqualMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.EqualMasked", opLen3(ssa.OpEqualMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.EqualMasked", opLen3(ssa.OpEqualMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.EqualMasked", opLen3(ssa.OpEqualMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.EqualMasked", opLen3(ssa.OpEqualMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.EqualMasked", opLen3(ssa.OpEqualMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.EqualMasked", opLen3(ssa.OpEqualMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.EqualMasked", opLen3(ssa.OpEqualMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.Floor", opLen1(ssa.OpFloorFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Floor", opLen1(ssa.OpFloorFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x2.Floor", opLen1(ssa.OpFloorFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Floor", opLen1(ssa.OpFloorFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x4.FloorWithPrecision", opLen1Imm8(ssa.OpFloorWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.FloorWithPrecision", opLen1Imm8(ssa.OpFloorWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.FloorWithPrecision", opLen1Imm8(ssa.OpFloorWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.FloorWithPrecision", opLen1Imm8(ssa.OpFloorWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.FloorWithPrecision", opLen1Imm8(ssa.OpFloorWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.FloorWithPrecision", opLen1Imm8(ssa.OpFloorWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.FloorWithPrecisionMasked", opLen2Imm8(ssa.OpFloorWithPrecisionMaskedFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.FloorWithPrecisionMasked", opLen2Imm8(ssa.OpFloorWithPrecisionMaskedFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.FloorWithPrecisionMasked", opLen2Imm8(ssa.OpFloorWithPrecisionMaskedFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.FloorWithPrecisionMasked", opLen2Imm8(ssa.OpFloorWithPrecisionMaskedFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.FloorWithPrecisionMasked", opLen2Imm8(ssa.OpFloorWithPrecisionMaskedFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.FloorWithPrecisionMasked", opLen2Imm8(ssa.OpFloorWithPrecisionMaskedFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.FusedMultiplyAdd", opLen3(ssa.OpFusedMultiplyAddFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.FusedMultiplyAdd", opLen3(ssa.OpFusedMultiplyAddFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.FusedMultiplyAdd", opLen3(ssa.OpFusedMultiplyAddFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.FusedMultiplyAdd", opLen3(ssa.OpFusedMultiplyAddFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.FusedMultiplyAdd", opLen3(ssa.OpFusedMultiplyAddFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.FusedMultiplyAdd", opLen3(ssa.OpFusedMultiplyAddFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.FusedMultiplyAddMasked", opLen4(ssa.OpFusedMultiplyAddMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.FusedMultiplyAddMasked", opLen4(ssa.OpFusedMultiplyAddMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.FusedMultiplyAddMasked", opLen4(ssa.OpFusedMultiplyAddMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.FusedMultiplyAddMasked", opLen4(ssa.OpFusedMultiplyAddMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.FusedMultiplyAddMasked", opLen4(ssa.OpFusedMultiplyAddMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.FusedMultiplyAddMasked", opLen4(ssa.OpFusedMultiplyAddMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.FusedMultiplyAddSub", opLen3(ssa.OpFusedMultiplyAddSubFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.FusedMultiplyAddSub", opLen3(ssa.OpFusedMultiplyAddSubFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.FusedMultiplyAddSub", opLen3(ssa.OpFusedMultiplyAddSubFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.FusedMultiplyAddSub", opLen3(ssa.OpFusedMultiplyAddSubFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.FusedMultiplyAddSub", opLen3(ssa.OpFusedMultiplyAddSubFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.FusedMultiplyAddSub", opLen3(ssa.OpFusedMultiplyAddSubFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.FusedMultiplyAddSubMasked", opLen4(ssa.OpFusedMultiplyAddSubMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.FusedMultiplyAddSubMasked", opLen4(ssa.OpFusedMultiplyAddSubMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.FusedMultiplyAddSubMasked", opLen4(ssa.OpFusedMultiplyAddSubMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.FusedMultiplyAddSubMasked", opLen4(ssa.OpFusedMultiplyAddSubMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.FusedMultiplyAddSubMasked", opLen4(ssa.OpFusedMultiplyAddSubMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.FusedMultiplyAddSubMasked", opLen4(ssa.OpFusedMultiplyAddSubMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.FusedMultiplySubAdd", opLen3(ssa.OpFusedMultiplySubAddFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.FusedMultiplySubAdd", opLen3(ssa.OpFusedMultiplySubAddFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.FusedMultiplySubAdd", opLen3(ssa.OpFusedMultiplySubAddFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.FusedMultiplySubAdd", opLen3(ssa.OpFusedMultiplySubAddFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.FusedMultiplySubAdd", opLen3(ssa.OpFusedMultiplySubAddFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.FusedMultiplySubAdd", opLen3(ssa.OpFusedMultiplySubAddFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.FusedMultiplySubAddMasked", opLen4(ssa.OpFusedMultiplySubAddMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.FusedMultiplySubAddMasked", opLen4(ssa.OpFusedMultiplySubAddMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.FusedMultiplySubAddMasked", opLen4(ssa.OpFusedMultiplySubAddMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.FusedMultiplySubAddMasked", opLen4(ssa.OpFusedMultiplySubAddMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.FusedMultiplySubAddMasked", opLen4(ssa.OpFusedMultiplySubAddMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.FusedMultiplySubAddMasked", opLen4(ssa.OpFusedMultiplySubAddMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.GaloisFieldAffineTransform", opLen2Imm8_2I(ssa.OpGaloisFieldAffineTransformUint8x16, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x32.GaloisFieldAffineTransform", opLen2Imm8_2I(ssa.OpGaloisFieldAffineTransformUint8x32, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x64.GaloisFieldAffineTransform", opLen2Imm8_2I(ssa.OpGaloisFieldAffineTransformUint8x64, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x16.GaloisFieldAffineTransformInverse", opLen2Imm8_2I(ssa.OpGaloisFieldAffineTransformInverseUint8x16, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x32.GaloisFieldAffineTransformInverse", opLen2Imm8_2I(ssa.OpGaloisFieldAffineTransformInverseUint8x32, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x64.GaloisFieldAffineTransformInverse", opLen2Imm8_2I(ssa.OpGaloisFieldAffineTransformInverseUint8x64, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x16.GaloisFieldAffineTransformInverseMasked", opLen3Imm8_2I(ssa.OpGaloisFieldAffineTransformInverseMaskedUint8x16, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x32.GaloisFieldAffineTransformInverseMasked", opLen3Imm8_2I(ssa.OpGaloisFieldAffineTransformInverseMaskedUint8x32, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x64.GaloisFieldAffineTransformInverseMasked", opLen3Imm8_2I(ssa.OpGaloisFieldAffineTransformInverseMaskedUint8x64, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x16.GaloisFieldAffineTransformMasked", opLen3Imm8_2I(ssa.OpGaloisFieldAffineTransformMaskedUint8x16, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x32.GaloisFieldAffineTransformMasked", opLen3Imm8_2I(ssa.OpGaloisFieldAffineTransformMaskedUint8x32, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x64.GaloisFieldAffineTransformMasked", opLen3Imm8_2I(ssa.OpGaloisFieldAffineTransformMaskedUint8x64, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x16.GaloisFieldMul", opLen2(ssa.OpGaloisFieldMulUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.GaloisFieldMul", opLen2(ssa.OpGaloisFieldMulUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.GaloisFieldMul", opLen2(ssa.OpGaloisFieldMulUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.GaloisFieldMulMasked", opLen3(ssa.OpGaloisFieldMulMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.GaloisFieldMulMasked", opLen3(ssa.OpGaloisFieldMulMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.GaloisFieldMulMasked", opLen3(ssa.OpGaloisFieldMulMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x8.Get128", opLen1Imm8(ssa.OpGet128Float32x8, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Float64x4.Get128", opLen1Imm8(ssa.OpGet128Float64x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int8x32.Get128", opLen1Imm8(ssa.OpGet128Int8x32, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int16x16.Get128", opLen1Imm8(ssa.OpGet128Int16x16, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int32x8.Get128", opLen1Imm8(ssa.OpGet128Int32x8, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int64x4.Get128", opLen1Imm8(ssa.OpGet128Int64x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Get128", opLen1Imm8(ssa.OpGet128Uint8x32, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Get128", opLen1Imm8(ssa.OpGet128Uint16x16, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Get128", opLen1Imm8(ssa.OpGet128Uint32x8, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Get128", opLen1Imm8(ssa.OpGet128Uint64x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int8x16.GetElem", opLen1Imm8(ssa.OpGetElemInt8x16, types.Types[types.TINT8], 0), sys.AMD64)
+	addF(simdPackage, "Int16x8.GetElem", opLen1Imm8(ssa.OpGetElemInt16x8, types.Types[types.TINT16], 0), sys.AMD64)
+	addF(simdPackage, "Int32x4.GetElem", opLen1Imm8(ssa.OpGetElemInt32x4, types.Types[types.TINT32], 0), sys.AMD64)
+	addF(simdPackage, "Int64x2.GetElem", opLen1Imm8(ssa.OpGetElemInt64x2, types.Types[types.TINT64], 0), sys.AMD64)
+	addF(simdPackage, "Uint8x16.GetElem", opLen1Imm8(ssa.OpGetElemUint8x16, types.Types[types.TUINT8], 0), sys.AMD64)
+	addF(simdPackage, "Uint16x8.GetElem", opLen1Imm8(ssa.OpGetElemUint16x8, types.Types[types.TUINT16], 0), sys.AMD64)
+	addF(simdPackage, "Uint32x4.GetElem", opLen1Imm8(ssa.OpGetElemUint32x4, types.Types[types.TUINT32], 0), sys.AMD64)
+	addF(simdPackage, "Uint64x2.GetElem", opLen1Imm8(ssa.OpGetElemUint64x2, types.Types[types.TUINT64], 0), sys.AMD64)
+	addF(simdPackage, "Int8x16.Greater", opLen2(ssa.OpGreaterInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Greater", opLen2(ssa.OpGreaterInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x8.Greater", opLen2(ssa.OpGreaterInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Greater", opLen2(ssa.OpGreaterInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x4.Greater", opLen2(ssa.OpGreaterInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.Greater", opLen2(ssa.OpGreaterInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x2.Greater", opLen2(ssa.OpGreaterInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.Greater", opLen2(ssa.OpGreaterInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x4.Greater", opLen2(ssa.OpGreaterFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Greater", opLen2(ssa.OpGreaterFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Greater", opLen2(ssa.OpGreaterFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.Greater", opLen2(ssa.OpGreaterFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Greater", opLen2(ssa.OpGreaterFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Greater", opLen2(ssa.OpGreaterFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x64.Greater", opLen2(ssa.OpGreaterInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x32.Greater", opLen2(ssa.OpGreaterInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x16.Greater", opLen2(ssa.OpGreaterInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x8.Greater", opLen2(ssa.OpGreaterInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Greater", opLen2(ssa.OpGreaterUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Greater", opLen2(ssa.OpGreaterUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.Greater", opLen2(ssa.OpGreaterUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Greater", opLen2(ssa.OpGreaterUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Greater", opLen2(ssa.OpGreaterUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.Greater", opLen2(ssa.OpGreaterUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.Greater", opLen2(ssa.OpGreaterUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Greater", opLen2(ssa.OpGreaterUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Greater", opLen2(ssa.OpGreaterUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.Greater", opLen2(ssa.OpGreaterUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Greater", opLen2(ssa.OpGreaterUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Greater", opLen2(ssa.OpGreaterUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.GreaterEqual", opLen2(ssa.OpGreaterEqualFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.GreaterEqual", opLen2(ssa.OpGreaterEqualInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.GreaterEqual", opLen2(ssa.OpGreaterEqualInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.GreaterEqual", opLen2(ssa.OpGreaterEqualInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.GreaterEqual", opLen2(ssa.OpGreaterEqualInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.GreaterEqual", opLen2(ssa.OpGreaterEqualInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.GreaterEqual", opLen2(ssa.OpGreaterEqualInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.GreaterEqual", opLen2(ssa.OpGreaterEqualInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.GreaterEqual", opLen2(ssa.OpGreaterEqualInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.GreaterEqual", opLen2(ssa.OpGreaterEqualInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.GreaterEqual", opLen2(ssa.OpGreaterEqualInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.GreaterEqual", opLen2(ssa.OpGreaterEqualInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.GreaterEqual", opLen2(ssa.OpGreaterEqualInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.GreaterEqual", opLen2(ssa.OpGreaterEqualUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.GreaterEqual", opLen2(ssa.OpGreaterEqualUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.GreaterEqual", opLen2(ssa.OpGreaterEqualUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.GreaterEqual", opLen2(ssa.OpGreaterEqualUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.GreaterEqual", opLen2(ssa.OpGreaterEqualUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.GreaterEqual", opLen2(ssa.OpGreaterEqualUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.GreaterEqual", opLen2(ssa.OpGreaterEqualUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.GreaterEqual", opLen2(ssa.OpGreaterEqualUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.GreaterEqual", opLen2(ssa.OpGreaterEqualUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.GreaterEqual", opLen2(ssa.OpGreaterEqualUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.GreaterEqual", opLen2(ssa.OpGreaterEqualUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.GreaterEqual", opLen2(ssa.OpGreaterEqualUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.GreaterEqualMasked", opLen3(ssa.OpGreaterEqualMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.GreaterMasked", opLen3(ssa.OpGreaterMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.GreaterMasked", opLen3(ssa.OpGreaterMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.GreaterMasked", opLen3(ssa.OpGreaterMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.GreaterMasked", opLen3(ssa.OpGreaterMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.GreaterMasked", opLen3(ssa.OpGreaterMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.GreaterMasked", opLen3(ssa.OpGreaterMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.GreaterMasked", opLen3(ssa.OpGreaterMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.GreaterMasked", opLen3(ssa.OpGreaterMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.GreaterMasked", opLen3(ssa.OpGreaterMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.GreaterMasked", opLen3(ssa.OpGreaterMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.GreaterMasked", opLen3(ssa.OpGreaterMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.GreaterMasked", opLen3(ssa.OpGreaterMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.GreaterMasked", opLen3(ssa.OpGreaterMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.GreaterMasked", opLen3(ssa.OpGreaterMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.GreaterMasked", opLen3(ssa.OpGreaterMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.GreaterMasked", opLen3(ssa.OpGreaterMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.GreaterMasked", opLen3(ssa.OpGreaterMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.GreaterMasked", opLen3(ssa.OpGreaterMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.GreaterMasked", opLen3(ssa.OpGreaterMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.GreaterMasked", opLen3(ssa.OpGreaterMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.GreaterMasked", opLen3(ssa.OpGreaterMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.GreaterMasked", opLen3(ssa.OpGreaterMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.GreaterMasked", opLen3(ssa.OpGreaterMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.GreaterMasked", opLen3(ssa.OpGreaterMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.GreaterMasked", opLen3(ssa.OpGreaterMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.GreaterMasked", opLen3(ssa.OpGreaterMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.GreaterMasked", opLen3(ssa.OpGreaterMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.GreaterMasked", opLen3(ssa.OpGreaterMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.GreaterMasked", opLen3(ssa.OpGreaterMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.GreaterMasked", opLen3(ssa.OpGreaterMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.IsNan", opLen2(ssa.OpIsNanFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.IsNan", opLen2(ssa.OpIsNanFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.IsNan", opLen2(ssa.OpIsNanFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.IsNan", opLen2(ssa.OpIsNanFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.IsNan", opLen2(ssa.OpIsNanFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.IsNan", opLen2(ssa.OpIsNanFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.IsNanMasked", opLen3(ssa.OpIsNanMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.IsNanMasked", opLen3(ssa.OpIsNanMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.IsNanMasked", opLen3(ssa.OpIsNanMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.IsNanMasked", opLen3(ssa.OpIsNanMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.IsNanMasked", opLen3(ssa.OpIsNanMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.IsNanMasked", opLen3(ssa.OpIsNanMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.Less", opLen2(ssa.OpLessFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Less", opLen2(ssa.OpLessFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Less", opLen2(ssa.OpLessFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.Less", opLen2(ssa.OpLessFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Less", opLen2(ssa.OpLessFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Less", opLen2(ssa.OpLessFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.Less", opLen2(ssa.OpLessInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Less", opLen2(ssa.OpLessInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.Less", opLen2(ssa.OpLessInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.Less", opLen2(ssa.OpLessInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Less", opLen2(ssa.OpLessInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.Less", opLen2(ssa.OpLessInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.Less", opLen2(ssa.OpLessInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.Less", opLen2(ssa.OpLessInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.Less", opLen2(ssa.OpLessInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.Less", opLen2(ssa.OpLessInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.Less", opLen2(ssa.OpLessInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.Less", opLen2(ssa.OpLessInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Less", opLen2(ssa.OpLessUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Less", opLen2(ssa.OpLessUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.Less", opLen2(ssa.OpLessUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Less", opLen2(ssa.OpLessUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Less", opLen2(ssa.OpLessUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.Less", opLen2(ssa.OpLessUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.Less", opLen2(ssa.OpLessUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Less", opLen2(ssa.OpLessUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Less", opLen2(ssa.OpLessUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.Less", opLen2(ssa.OpLessUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Less", opLen2(ssa.OpLessUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Less", opLen2(ssa.OpLessUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.LessEqual", opLen2(ssa.OpLessEqualFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.LessEqual", opLen2(ssa.OpLessEqualFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.LessEqual", opLen2(ssa.OpLessEqualFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.LessEqual", opLen2(ssa.OpLessEqualFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.LessEqual", opLen2(ssa.OpLessEqualFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.LessEqual", opLen2(ssa.OpLessEqualFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.LessEqual", opLen2(ssa.OpLessEqualInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.LessEqual", opLen2(ssa.OpLessEqualInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.LessEqual", opLen2(ssa.OpLessEqualInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.LessEqual", opLen2(ssa.OpLessEqualInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.LessEqual", opLen2(ssa.OpLessEqualInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.LessEqual", opLen2(ssa.OpLessEqualInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.LessEqual", opLen2(ssa.OpLessEqualInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.LessEqual", opLen2(ssa.OpLessEqualInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.LessEqual", opLen2(ssa.OpLessEqualInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.LessEqual", opLen2(ssa.OpLessEqualInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.LessEqual", opLen2(ssa.OpLessEqualInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.LessEqual", opLen2(ssa.OpLessEqualInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.LessEqual", opLen2(ssa.OpLessEqualUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.LessEqual", opLen2(ssa.OpLessEqualUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.LessEqual", opLen2(ssa.OpLessEqualUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.LessEqual", opLen2(ssa.OpLessEqualUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.LessEqual", opLen2(ssa.OpLessEqualUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.LessEqual", opLen2(ssa.OpLessEqualUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.LessEqual", opLen2(ssa.OpLessEqualUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.LessEqual", opLen2(ssa.OpLessEqualUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.LessEqual", opLen2(ssa.OpLessEqualUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.LessEqual", opLen2(ssa.OpLessEqualUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.LessEqual", opLen2(ssa.OpLessEqualUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.LessEqual", opLen2(ssa.OpLessEqualUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.LessEqualMasked", opLen3(ssa.OpLessEqualMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.LessMasked", opLen3(ssa.OpLessMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.LessMasked", opLen3(ssa.OpLessMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.LessMasked", opLen3(ssa.OpLessMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.LessMasked", opLen3(ssa.OpLessMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.LessMasked", opLen3(ssa.OpLessMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.LessMasked", opLen3(ssa.OpLessMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.LessMasked", opLen3(ssa.OpLessMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.LessMasked", opLen3(ssa.OpLessMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.LessMasked", opLen3(ssa.OpLessMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.LessMasked", opLen3(ssa.OpLessMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.LessMasked", opLen3(ssa.OpLessMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.LessMasked", opLen3(ssa.OpLessMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.LessMasked", opLen3(ssa.OpLessMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.LessMasked", opLen3(ssa.OpLessMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.LessMasked", opLen3(ssa.OpLessMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.LessMasked", opLen3(ssa.OpLessMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.LessMasked", opLen3(ssa.OpLessMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.LessMasked", opLen3(ssa.OpLessMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.LessMasked", opLen3(ssa.OpLessMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.LessMasked", opLen3(ssa.OpLessMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.LessMasked", opLen3(ssa.OpLessMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.LessMasked", opLen3(ssa.OpLessMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.LessMasked", opLen3(ssa.OpLessMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.LessMasked", opLen3(ssa.OpLessMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.LessMasked", opLen3(ssa.OpLessMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.LessMasked", opLen3(ssa.OpLessMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.LessMasked", opLen3(ssa.OpLessMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.LessMasked", opLen3(ssa.OpLessMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.LessMasked", opLen3(ssa.OpLessMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.LessMasked", opLen3(ssa.OpLessMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.Max", opLen2(ssa.OpMaxFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Max", opLen2(ssa.OpMaxFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Max", opLen2(ssa.OpMaxFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.Max", opLen2(ssa.OpMaxFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Max", opLen2(ssa.OpMaxFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Max", opLen2(ssa.OpMaxFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.Max", opLen2(ssa.OpMaxInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Max", opLen2(ssa.OpMaxInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.Max", opLen2(ssa.OpMaxInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.Max", opLen2(ssa.OpMaxInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Max", opLen2(ssa.OpMaxInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.Max", opLen2(ssa.OpMaxInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.Max", opLen2(ssa.OpMaxInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.Max", opLen2(ssa.OpMaxInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.Max", opLen2(ssa.OpMaxInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.Max", opLen2(ssa.OpMaxInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.Max", opLen2(ssa.OpMaxInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.Max", opLen2(ssa.OpMaxInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Max", opLen2(ssa.OpMaxUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Max", opLen2(ssa.OpMaxUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.Max", opLen2(ssa.OpMaxUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Max", opLen2(ssa.OpMaxUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Max", opLen2(ssa.OpMaxUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.Max", opLen2(ssa.OpMaxUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.Max", opLen2(ssa.OpMaxUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Max", opLen2(ssa.OpMaxUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Max", opLen2(ssa.OpMaxUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.Max", opLen2(ssa.OpMaxUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Max", opLen2(ssa.OpMaxUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Max", opLen2(ssa.OpMaxUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.MaxMasked", opLen3(ssa.OpMaxMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.MaxMasked", opLen3(ssa.OpMaxMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.MaxMasked", opLen3(ssa.OpMaxMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.MaxMasked", opLen3(ssa.OpMaxMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.MaxMasked", opLen3(ssa.OpMaxMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.MaxMasked", opLen3(ssa.OpMaxMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.MaxMasked", opLen3(ssa.OpMaxMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.MaxMasked", opLen3(ssa.OpMaxMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.MaxMasked", opLen3(ssa.OpMaxMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.MaxMasked", opLen3(ssa.OpMaxMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.MaxMasked", opLen3(ssa.OpMaxMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.MaxMasked", opLen3(ssa.OpMaxMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.MaxMasked", opLen3(ssa.OpMaxMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.MaxMasked", opLen3(ssa.OpMaxMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.MaxMasked", opLen3(ssa.OpMaxMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.MaxMasked", opLen3(ssa.OpMaxMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.MaxMasked", opLen3(ssa.OpMaxMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.MaxMasked", opLen3(ssa.OpMaxMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.MaxMasked", opLen3(ssa.OpMaxMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.MaxMasked", opLen3(ssa.OpMaxMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.MaxMasked", opLen3(ssa.OpMaxMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.MaxMasked", opLen3(ssa.OpMaxMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.MaxMasked", opLen3(ssa.OpMaxMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.MaxMasked", opLen3(ssa.OpMaxMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.MaxMasked", opLen3(ssa.OpMaxMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.MaxMasked", opLen3(ssa.OpMaxMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.MaxMasked", opLen3(ssa.OpMaxMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.MaxMasked", opLen3(ssa.OpMaxMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.MaxMasked", opLen3(ssa.OpMaxMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.MaxMasked", opLen3(ssa.OpMaxMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.Min", opLen2(ssa.OpMinFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Min", opLen2(ssa.OpMinFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Min", opLen2(ssa.OpMinFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.Min", opLen2(ssa.OpMinFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Min", opLen2(ssa.OpMinFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Min", opLen2(ssa.OpMinFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.Min", opLen2(ssa.OpMinInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Min", opLen2(ssa.OpMinInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.Min", opLen2(ssa.OpMinInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.Min", opLen2(ssa.OpMinInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Min", opLen2(ssa.OpMinInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.Min", opLen2(ssa.OpMinInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.Min", opLen2(ssa.OpMinInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.Min", opLen2(ssa.OpMinInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.Min", opLen2(ssa.OpMinInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.Min", opLen2(ssa.OpMinInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.Min", opLen2(ssa.OpMinInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.Min", opLen2(ssa.OpMinInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Min", opLen2(ssa.OpMinUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Min", opLen2(ssa.OpMinUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.Min", opLen2(ssa.OpMinUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Min", opLen2(ssa.OpMinUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Min", opLen2(ssa.OpMinUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.Min", opLen2(ssa.OpMinUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.Min", opLen2(ssa.OpMinUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Min", opLen2(ssa.OpMinUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Min", opLen2(ssa.OpMinUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.Min", opLen2(ssa.OpMinUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Min", opLen2(ssa.OpMinUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Min", opLen2(ssa.OpMinUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.MinMasked", opLen3(ssa.OpMinMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.MinMasked", opLen3(ssa.OpMinMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.MinMasked", opLen3(ssa.OpMinMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.MinMasked", opLen3(ssa.OpMinMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.MinMasked", opLen3(ssa.OpMinMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.MinMasked", opLen3(ssa.OpMinMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.MinMasked", opLen3(ssa.OpMinMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.MinMasked", opLen3(ssa.OpMinMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.MinMasked", opLen3(ssa.OpMinMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.MinMasked", opLen3(ssa.OpMinMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.MinMasked", opLen3(ssa.OpMinMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.MinMasked", opLen3(ssa.OpMinMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.MinMasked", opLen3(ssa.OpMinMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.MinMasked", opLen3(ssa.OpMinMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.MinMasked", opLen3(ssa.OpMinMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.MinMasked", opLen3(ssa.OpMinMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.MinMasked", opLen3(ssa.OpMinMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.MinMasked", opLen3(ssa.OpMinMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.MinMasked", opLen3(ssa.OpMinMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.MinMasked", opLen3(ssa.OpMinMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.MinMasked", opLen3(ssa.OpMinMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.MinMasked", opLen3(ssa.OpMinMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.MinMasked", opLen3(ssa.OpMinMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.MinMasked", opLen3(ssa.OpMinMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.MinMasked", opLen3(ssa.OpMinMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.MinMasked", opLen3(ssa.OpMinMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.MinMasked", opLen3(ssa.OpMinMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.MinMasked", opLen3(ssa.OpMinMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.MinMasked", opLen3(ssa.OpMinMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.MinMasked", opLen3(ssa.OpMinMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.Mul", opLen2(ssa.OpMulFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Mul", opLen2(ssa.OpMulFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Mul", opLen2(ssa.OpMulFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.Mul", opLen2(ssa.OpMulFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Mul", opLen2(ssa.OpMulFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Mul", opLen2(ssa.OpMulFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.MulByPowOf2", opLen2(ssa.OpMulByPowOf2Float32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.MulByPowOf2", opLen2(ssa.OpMulByPowOf2Float32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.MulByPowOf2", opLen2(ssa.OpMulByPowOf2Float32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.MulByPowOf2", opLen2(ssa.OpMulByPowOf2Float64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.MulByPowOf2", opLen2(ssa.OpMulByPowOf2Float64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.MulByPowOf2", opLen2(ssa.OpMulByPowOf2Float64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.MulByPowOf2Masked", opLen3(ssa.OpMulByPowOf2MaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.MulByPowOf2Masked", opLen3(ssa.OpMulByPowOf2MaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.MulByPowOf2Masked", opLen3(ssa.OpMulByPowOf2MaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.MulByPowOf2Masked", opLen3(ssa.OpMulByPowOf2MaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.MulByPowOf2Masked", opLen3(ssa.OpMulByPowOf2MaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.MulByPowOf2Masked", opLen3(ssa.OpMulByPowOf2MaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.MulEvenWiden", opLen2(ssa.OpMulEvenWidenInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.MulEvenWiden", opLen2(ssa.OpMulEvenWidenInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x2.MulEvenWiden", opLen2(ssa.OpMulEvenWidenInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.MulEvenWiden", opLen2(ssa.OpMulEvenWidenInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.MulEvenWiden", opLen2(ssa.OpMulEvenWidenInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.MulEvenWiden", opLen2(ssa.OpMulEvenWidenUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.MulEvenWiden", opLen2(ssa.OpMulEvenWidenUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x2.MulEvenWiden", opLen2(ssa.OpMulEvenWidenUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.MulEvenWiden", opLen2(ssa.OpMulEvenWidenUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.MulEvenWiden", opLen2(ssa.OpMulEvenWidenUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.MulEvenWidenMasked", opLen3(ssa.OpMulEvenWidenMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.MulEvenWidenMasked", opLen3(ssa.OpMulEvenWidenMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.MulEvenWidenMasked", opLen3(ssa.OpMulEvenWidenMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.MulEvenWidenMasked", opLen3(ssa.OpMulEvenWidenMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.MulEvenWidenMasked", opLen3(ssa.OpMulEvenWidenMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.MulEvenWidenMasked", opLen3(ssa.OpMulEvenWidenMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.MulHigh", opLen2(ssa.OpMulHighInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.MulHigh", opLen2(ssa.OpMulHighInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.MulHigh", opLen2(ssa.OpMulHighInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.MulHigh", opLen2(ssa.OpMulHighUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.MulHigh", opLen2(ssa.OpMulHighUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.MulHigh", opLen2(ssa.OpMulHighUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.MulHighMasked", opLen3(ssa.OpMulHighMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.MulHighMasked", opLen3(ssa.OpMulHighMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.MulHighMasked", opLen3(ssa.OpMulHighMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.MulHighMasked", opLen3(ssa.OpMulHighMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.MulHighMasked", opLen3(ssa.OpMulHighMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.MulHighMasked", opLen3(ssa.OpMulHighMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.MulLow", opLen2(ssa.OpMulLowInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.MulLow", opLen2(ssa.OpMulLowInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.MulLow", opLen2(ssa.OpMulLowInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.MulLow", opLen2(ssa.OpMulLowInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.MulLow", opLen2(ssa.OpMulLowInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.MulLow", opLen2(ssa.OpMulLowInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.MulLow", opLen2(ssa.OpMulLowInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.MulLow", opLen2(ssa.OpMulLowInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.MulLow", opLen2(ssa.OpMulLowInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.MulLowMasked", opLen3(ssa.OpMulLowMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.MulLowMasked", opLen3(ssa.OpMulLowMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.MulLowMasked", opLen3(ssa.OpMulLowMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.MulLowMasked", opLen3(ssa.OpMulLowMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.MulLowMasked", opLen3(ssa.OpMulLowMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.MulLowMasked", opLen3(ssa.OpMulLowMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.MulLowMasked", opLen3(ssa.OpMulLowMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.MulLowMasked", opLen3(ssa.OpMulLowMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.MulLowMasked", opLen3(ssa.OpMulLowMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.MulMasked", opLen3(ssa.OpMulMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.MulMasked", opLen3(ssa.OpMulMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.MulMasked", opLen3(ssa.OpMulMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.MulMasked", opLen3(ssa.OpMulMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.MulMasked", opLen3(ssa.OpMulMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.MulMasked", opLen3(ssa.OpMulMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.NotEqual", opLen2(ssa.OpNotEqualFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.NotEqual", opLen2(ssa.OpNotEqualFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.NotEqual", opLen2(ssa.OpNotEqualFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.NotEqual", opLen2(ssa.OpNotEqualFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.NotEqual", opLen2(ssa.OpNotEqualFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.NotEqual", opLen2(ssa.OpNotEqualFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.NotEqual", opLen2(ssa.OpNotEqualInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.NotEqual", opLen2(ssa.OpNotEqualInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.NotEqual", opLen2(ssa.OpNotEqualInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.NotEqual", opLen2(ssa.OpNotEqualInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.NotEqual", opLen2(ssa.OpNotEqualInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.NotEqual", opLen2(ssa.OpNotEqualInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.NotEqual", opLen2(ssa.OpNotEqualInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.NotEqual", opLen2(ssa.OpNotEqualInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.NotEqual", opLen2(ssa.OpNotEqualInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.NotEqual", opLen2(ssa.OpNotEqualInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.NotEqual", opLen2(ssa.OpNotEqualInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.NotEqual", opLen2(ssa.OpNotEqualInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.NotEqual", opLen2(ssa.OpNotEqualUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.NotEqual", opLen2(ssa.OpNotEqualUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.NotEqual", opLen2(ssa.OpNotEqualUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.NotEqual", opLen2(ssa.OpNotEqualUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.NotEqual", opLen2(ssa.OpNotEqualUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.NotEqual", opLen2(ssa.OpNotEqualUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.NotEqual", opLen2(ssa.OpNotEqualUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.NotEqual", opLen2(ssa.OpNotEqualUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.NotEqual", opLen2(ssa.OpNotEqualUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.NotEqual", opLen2(ssa.OpNotEqualUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.NotEqual", opLen2(ssa.OpNotEqualUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.NotEqual", opLen2(ssa.OpNotEqualUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.NotEqualMasked", opLen3(ssa.OpNotEqualMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.Or", opLen2(ssa.OpOrInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Or", opLen2(ssa.OpOrInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x8.Or", opLen2(ssa.OpOrInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Or", opLen2(ssa.OpOrInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x4.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.Or", opLen2(ssa.OpOrInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.Or", opLen2(ssa.OpOrInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.Or", opLen2(ssa.OpOrInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.Or", opLen2(ssa.OpOrInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.Or", opLen2(ssa.OpOrInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Or", opLen2(ssa.OpOrUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Or", opLen2(ssa.OpOrUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Or", opLen2(ssa.OpOrUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Or", opLen2(ssa.OpOrUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x4.Or", opLen2(ssa.OpOrUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Or", opLen2(ssa.OpOrUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Or", opLen2(ssa.OpOrUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.Or", opLen2(ssa.OpOrUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Or", opLen2(ssa.OpOrUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Or", opLen2(ssa.OpOrUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.OrMasked", opLen3(ssa.OpOrMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.OrMasked", opLen3(ssa.OpOrMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.OrMasked", opLen3(ssa.OpOrMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.OrMasked", opLen3(ssa.OpOrMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.OrMasked", opLen3(ssa.OpOrMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.OrMasked", opLen3(ssa.OpOrMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.OrMasked", opLen3(ssa.OpOrMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.OrMasked", opLen3(ssa.OpOrMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.OrMasked", opLen3(ssa.OpOrMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.OrMasked", opLen3(ssa.OpOrMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.OrMasked", opLen3(ssa.OpOrMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.OrMasked", opLen3(ssa.OpOrMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.PairDotProd", opLen2(ssa.OpPairDotProdInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.PairDotProd", opLen2(ssa.OpPairDotProdInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.PairDotProd", opLen2(ssa.OpPairDotProdInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.PairDotProdAccumulate", opLen3_31(ssa.OpPairDotProdAccumulateInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.PairDotProdAccumulate", opLen3_31(ssa.OpPairDotProdAccumulateInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.PairDotProdAccumulate", opLen3_31(ssa.OpPairDotProdAccumulateInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.PairDotProdAccumulateMasked", opLen4_31(ssa.OpPairDotProdAccumulateMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.PairDotProdAccumulateMasked", opLen4_31(ssa.OpPairDotProdAccumulateMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.PairDotProdAccumulateMasked", opLen4_31(ssa.OpPairDotProdAccumulateMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.PairDotProdMasked", opLen3(ssa.OpPairDotProdMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.PairDotProdMasked", opLen3(ssa.OpPairDotProdMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.PairDotProdMasked", opLen3(ssa.OpPairDotProdMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.PairwiseAdd", opLen2(ssa.OpPairwiseAddFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.PairwiseAdd", opLen2(ssa.OpPairwiseAddFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x2.PairwiseAdd", opLen2(ssa.OpPairwiseAddFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.PairwiseAdd", opLen2(ssa.OpPairwiseAddFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x8.PairwiseAdd", opLen2(ssa.OpPairwiseAddInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.PairwiseAdd", opLen2(ssa.OpPairwiseAddInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x4.PairwiseAdd", opLen2(ssa.OpPairwiseAddInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.PairwiseAdd", opLen2(ssa.OpPairwiseAddInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x8.PairwiseAdd", opLen2(ssa.OpPairwiseAddUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.PairwiseAdd", opLen2(ssa.OpPairwiseAddUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x4.PairwiseAdd", opLen2(ssa.OpPairwiseAddUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.PairwiseAdd", opLen2(ssa.OpPairwiseAddUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x4.PairwiseSub", opLen2(ssa.OpPairwiseSubFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.PairwiseSub", opLen2(ssa.OpPairwiseSubFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x2.PairwiseSub", opLen2(ssa.OpPairwiseSubFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.PairwiseSub", opLen2(ssa.OpPairwiseSubFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x8.PairwiseSub", opLen2(ssa.OpPairwiseSubInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.PairwiseSub", opLen2(ssa.OpPairwiseSubInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x4.PairwiseSub", opLen2(ssa.OpPairwiseSubInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.PairwiseSub", opLen2(ssa.OpPairwiseSubInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x8.PairwiseSub", opLen2(ssa.OpPairwiseSubUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.PairwiseSub", opLen2(ssa.OpPairwiseSubUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x4.PairwiseSub", opLen2(ssa.OpPairwiseSubUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.PairwiseSub", opLen2(ssa.OpPairwiseSubUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x16.Permute", opLen2_21(ssa.OpPermuteInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Permute", opLen2_21(ssa.OpPermuteUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Permute", opLen2_21(ssa.OpPermuteInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Permute", opLen2_21(ssa.OpPermuteUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.Permute", opLen2_21(ssa.OpPermuteInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x64.Permute", opLen2_21(ssa.OpPermuteUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.Permute", opLen2_21(ssa.OpPermuteInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Permute", opLen2_21(ssa.OpPermuteUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Permute", opLen2_21(ssa.OpPermuteInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Permute", opLen2_21(ssa.OpPermuteUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.Permute", opLen2_21(ssa.OpPermuteInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x32.Permute", opLen2_21(ssa.OpPermuteUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x8.Permute", opLen2_21(ssa.OpPermuteFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x8.Permute", opLen2_21(ssa.OpPermuteInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Permute", opLen2_21(ssa.OpPermuteUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Permute", opLen2_21(ssa.OpPermuteFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x16.Permute", opLen2_21(ssa.OpPermuteInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Permute", opLen2_21(ssa.OpPermuteUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x4.Permute", opLen2_21(ssa.OpPermuteFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x4.Permute", opLen2_21(ssa.OpPermuteInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Permute", opLen2_21(ssa.OpPermuteUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Permute", opLen2_21(ssa.OpPermuteFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x8.Permute", opLen2_21(ssa.OpPermuteInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Permute", opLen2_21(ssa.OpPermuteUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.Permute2", opLen3_231(ssa.OpPermute2Int8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Permute2", opLen3_231(ssa.OpPermute2Uint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Permute2", opLen3_231(ssa.OpPermute2Int8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Permute2", opLen3_231(ssa.OpPermute2Uint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.Permute2", opLen3_231(ssa.OpPermute2Int8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x64.Permute2", opLen3_231(ssa.OpPermute2Uint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.Permute2", opLen3_231(ssa.OpPermute2Int16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Permute2", opLen3_231(ssa.OpPermute2Uint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Permute2", opLen3_231(ssa.OpPermute2Int16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Permute2", opLen3_231(ssa.OpPermute2Uint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.Permute2", opLen3_231(ssa.OpPermute2Int16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x32.Permute2", opLen3_231(ssa.OpPermute2Uint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.Permute2", opLen3_231(ssa.OpPermute2Float32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x4.Permute2", opLen3_231(ssa.OpPermute2Int32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x4.Permute2", opLen3_231(ssa.OpPermute2Uint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Permute2", opLen3_231(ssa.OpPermute2Float32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x8.Permute2", opLen3_231(ssa.OpPermute2Int32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Permute2", opLen3_231(ssa.OpPermute2Uint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Permute2", opLen3_231(ssa.OpPermute2Float32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x16.Permute2", opLen3_231(ssa.OpPermute2Int32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Permute2", opLen3_231(ssa.OpPermute2Uint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.Permute2", opLen3_231(ssa.OpPermute2Float64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x2.Permute2", opLen3_231(ssa.OpPermute2Int64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x2.Permute2", opLen3_231(ssa.OpPermute2Uint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Permute2", opLen3_231(ssa.OpPermute2Float64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x4.Permute2", opLen3_231(ssa.OpPermute2Int64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Permute2", opLen3_231(ssa.OpPermute2Uint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Permute2", opLen3_231(ssa.OpPermute2Float64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x8.Permute2", opLen3_231(ssa.OpPermute2Int64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Permute2", opLen3_231(ssa.OpPermute2Uint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x64.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x32.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x4.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x4.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x8.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x16.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x2.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x2.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x4.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x8.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Permute2Masked", opLen4_231(ssa.OpPermute2MaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x16.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x32.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x64.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x8.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x16.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x32.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x8.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x8.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x8.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x16.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x16.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x4.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x4.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x4.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x8.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x8.PermuteMasked", opLen3_21(ssa.OpPermuteMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.PopCount", opLen1(ssa.OpPopCountInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.PopCount", opLen1(ssa.OpPopCountInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.PopCount", opLen1(ssa.OpPopCountInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.PopCount", opLen1(ssa.OpPopCountInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.PopCount", opLen1(ssa.OpPopCountInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.PopCount", opLen1(ssa.OpPopCountInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.PopCount", opLen1(ssa.OpPopCountInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.PopCount", opLen1(ssa.OpPopCountInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.PopCount", opLen1(ssa.OpPopCountInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.PopCount", opLen1(ssa.OpPopCountInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.PopCount", opLen1(ssa.OpPopCountInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.PopCount", opLen1(ssa.OpPopCountInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.PopCount", opLen1(ssa.OpPopCountUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.PopCount", opLen1(ssa.OpPopCountUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.PopCount", opLen1(ssa.OpPopCountUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.PopCount", opLen1(ssa.OpPopCountUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.PopCount", opLen1(ssa.OpPopCountUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.PopCount", opLen1(ssa.OpPopCountUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.PopCount", opLen1(ssa.OpPopCountUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.PopCount", opLen1(ssa.OpPopCountUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.PopCount", opLen1(ssa.OpPopCountUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.PopCount", opLen1(ssa.OpPopCountUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.PopCount", opLen1(ssa.OpPopCountUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.PopCount", opLen1(ssa.OpPopCountUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.PopCountMasked", opLen2(ssa.OpPopCountMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.PopCountMasked", opLen2(ssa.OpPopCountMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.PopCountMasked", opLen2(ssa.OpPopCountMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.PopCountMasked", opLen2(ssa.OpPopCountMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.PopCountMasked", opLen2(ssa.OpPopCountMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.PopCountMasked", opLen2(ssa.OpPopCountMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.PopCountMasked", opLen2(ssa.OpPopCountMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.PopCountMasked", opLen2(ssa.OpPopCountMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.PopCountMasked", opLen2(ssa.OpPopCountMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.PopCountMasked", opLen2(ssa.OpPopCountMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.PopCountMasked", opLen2(ssa.OpPopCountMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.PopCountMasked", opLen2(ssa.OpPopCountMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.PopCountMasked", opLen2(ssa.OpPopCountMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.PopCountMasked", opLen2(ssa.OpPopCountMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.PopCountMasked", opLen2(ssa.OpPopCountMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.PopCountMasked", opLen2(ssa.OpPopCountMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.PopCountMasked", opLen2(ssa.OpPopCountMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.PopCountMasked", opLen2(ssa.OpPopCountMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.PopCountMasked", opLen2(ssa.OpPopCountMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.PopCountMasked", opLen2(ssa.OpPopCountMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.PopCountMasked", opLen2(ssa.OpPopCountMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.PopCountMasked", opLen2(ssa.OpPopCountMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.PopCountMasked", opLen2(ssa.OpPopCountMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.PopCountMasked", opLen2(ssa.OpPopCountMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int32x8.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int32x16.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int64x2.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int64x4.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int64x8.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x4.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x8.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x16.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x2.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x4.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x8.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int32x4.RotateAllLeftMasked", opLen2Imm8(ssa.OpRotateAllLeftMaskedInt32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int32x8.RotateAllLeftMasked", opLen2Imm8(ssa.OpRotateAllLeftMaskedInt32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int32x16.RotateAllLeftMasked", opLen2Imm8(ssa.OpRotateAllLeftMaskedInt32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int64x2.RotateAllLeftMasked", opLen2Imm8(ssa.OpRotateAllLeftMaskedInt64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int64x4.RotateAllLeftMasked", opLen2Imm8(ssa.OpRotateAllLeftMaskedInt64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int64x8.RotateAllLeftMasked", opLen2Imm8(ssa.OpRotateAllLeftMaskedInt64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x4.RotateAllLeftMasked", opLen2Imm8(ssa.OpRotateAllLeftMaskedUint32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x8.RotateAllLeftMasked", opLen2Imm8(ssa.OpRotateAllLeftMaskedUint32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x16.RotateAllLeftMasked", opLen2Imm8(ssa.OpRotateAllLeftMaskedUint32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x2.RotateAllLeftMasked", opLen2Imm8(ssa.OpRotateAllLeftMaskedUint64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x4.RotateAllLeftMasked", opLen2Imm8(ssa.OpRotateAllLeftMaskedUint64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x8.RotateAllLeftMasked", opLen2Imm8(ssa.OpRotateAllLeftMaskedUint64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int32x4.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int32x8.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int32x16.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int64x2.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int64x4.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int64x8.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x4.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x8.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x16.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x2.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x4.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x8.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int32x4.RotateAllRightMasked", opLen2Imm8(ssa.OpRotateAllRightMaskedInt32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int32x8.RotateAllRightMasked", opLen2Imm8(ssa.OpRotateAllRightMaskedInt32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int32x16.RotateAllRightMasked", opLen2Imm8(ssa.OpRotateAllRightMaskedInt32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int64x2.RotateAllRightMasked", opLen2Imm8(ssa.OpRotateAllRightMaskedInt64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int64x4.RotateAllRightMasked", opLen2Imm8(ssa.OpRotateAllRightMaskedInt64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int64x8.RotateAllRightMasked", opLen2Imm8(ssa.OpRotateAllRightMaskedInt64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x4.RotateAllRightMasked", opLen2Imm8(ssa.OpRotateAllRightMaskedUint32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x8.RotateAllRightMasked", opLen2Imm8(ssa.OpRotateAllRightMaskedUint32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x16.RotateAllRightMasked", opLen2Imm8(ssa.OpRotateAllRightMaskedUint32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x2.RotateAllRightMasked", opLen2Imm8(ssa.OpRotateAllRightMaskedUint64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x4.RotateAllRightMasked", opLen2Imm8(ssa.OpRotateAllRightMaskedUint64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x8.RotateAllRightMasked", opLen2Imm8(ssa.OpRotateAllRightMaskedUint64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int32x4.RotateLeft", opLen2(ssa.OpRotateLeftInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.RotateLeft", opLen2(ssa.OpRotateLeftInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.RotateLeft", opLen2(ssa.OpRotateLeftInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.RotateLeft", opLen2(ssa.OpRotateLeftInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.RotateLeft", opLen2(ssa.OpRotateLeftInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.RotateLeft", opLen2(ssa.OpRotateLeftInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.RotateLeft", opLen2(ssa.OpRotateLeftUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.RotateLeft", opLen2(ssa.OpRotateLeftUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.RotateLeft", opLen2(ssa.OpRotateLeftUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.RotateLeft", opLen2(ssa.OpRotateLeftUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.RotateLeft", opLen2(ssa.OpRotateLeftUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.RotateLeft", opLen2(ssa.OpRotateLeftUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.RotateLeftMasked", opLen3(ssa.OpRotateLeftMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.RotateLeftMasked", opLen3(ssa.OpRotateLeftMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.RotateLeftMasked", opLen3(ssa.OpRotateLeftMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.RotateLeftMasked", opLen3(ssa.OpRotateLeftMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.RotateLeftMasked", opLen3(ssa.OpRotateLeftMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.RotateLeftMasked", opLen3(ssa.OpRotateLeftMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.RotateLeftMasked", opLen3(ssa.OpRotateLeftMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.RotateLeftMasked", opLen3(ssa.OpRotateLeftMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.RotateLeftMasked", opLen3(ssa.OpRotateLeftMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.RotateLeftMasked", opLen3(ssa.OpRotateLeftMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.RotateLeftMasked", opLen3(ssa.OpRotateLeftMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.RotateLeftMasked", opLen3(ssa.OpRotateLeftMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.RotateRight", opLen2(ssa.OpRotateRightInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.RotateRight", opLen2(ssa.OpRotateRightInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.RotateRight", opLen2(ssa.OpRotateRightInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.RotateRight", opLen2(ssa.OpRotateRightInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.RotateRight", opLen2(ssa.OpRotateRightInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.RotateRight", opLen2(ssa.OpRotateRightInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.RotateRight", opLen2(ssa.OpRotateRightUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.RotateRight", opLen2(ssa.OpRotateRightUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.RotateRight", opLen2(ssa.OpRotateRightUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.RotateRight", opLen2(ssa.OpRotateRightUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.RotateRight", opLen2(ssa.OpRotateRightUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.RotateRight", opLen2(ssa.OpRotateRightUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.RotateRightMasked", opLen3(ssa.OpRotateRightMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.RotateRightMasked", opLen3(ssa.OpRotateRightMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.RotateRightMasked", opLen3(ssa.OpRotateRightMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.RotateRightMasked", opLen3(ssa.OpRotateRightMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.RotateRightMasked", opLen3(ssa.OpRotateRightMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.RotateRightMasked", opLen3(ssa.OpRotateRightMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.RotateRightMasked", opLen3(ssa.OpRotateRightMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.RotateRightMasked", opLen3(ssa.OpRotateRightMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.RotateRightMasked", opLen3(ssa.OpRotateRightMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.RotateRightMasked", opLen3(ssa.OpRotateRightMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.RotateRightMasked", opLen3(ssa.OpRotateRightMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.RotateRightMasked", opLen3(ssa.OpRotateRightMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.Round", opLen1(ssa.OpRoundFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Round", opLen1(ssa.OpRoundFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x2.Round", opLen1(ssa.OpRoundFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Round", opLen1(ssa.OpRoundFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x4.RoundWithPrecision", opLen1Imm8(ssa.OpRoundWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.RoundWithPrecision", opLen1Imm8(ssa.OpRoundWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.RoundWithPrecision", opLen1Imm8(ssa.OpRoundWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.RoundWithPrecision", opLen1Imm8(ssa.OpRoundWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.RoundWithPrecision", opLen1Imm8(ssa.OpRoundWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.RoundWithPrecision", opLen1Imm8(ssa.OpRoundWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.RoundWithPrecisionMasked", opLen2Imm8(ssa.OpRoundWithPrecisionMaskedFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.RoundWithPrecisionMasked", opLen2Imm8(ssa.OpRoundWithPrecisionMaskedFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.RoundWithPrecisionMasked", opLen2Imm8(ssa.OpRoundWithPrecisionMaskedFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.RoundWithPrecisionMasked", opLen2Imm8(ssa.OpRoundWithPrecisionMaskedFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.RoundWithPrecisionMasked", opLen2Imm8(ssa.OpRoundWithPrecisionMaskedFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.RoundWithPrecisionMasked", opLen2Imm8(ssa.OpRoundWithPrecisionMaskedFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Int8x16.SaturatedAdd", opLen2(ssa.OpSaturatedAddInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.SaturatedAdd", opLen2(ssa.OpSaturatedAddInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.SaturatedAdd", opLen2(ssa.OpSaturatedAddInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.SaturatedAdd", opLen2(ssa.OpSaturatedAddInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.SaturatedAdd", opLen2(ssa.OpSaturatedAddInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.SaturatedAdd", opLen2(ssa.OpSaturatedAddInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.SaturatedAdd", opLen2(ssa.OpSaturatedAddUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.SaturatedAdd", opLen2(ssa.OpSaturatedAddUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.SaturatedAdd", opLen2(ssa.OpSaturatedAddUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.SaturatedAdd", opLen2(ssa.OpSaturatedAddUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.SaturatedAdd", opLen2(ssa.OpSaturatedAddUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.SaturatedAdd", opLen2(ssa.OpSaturatedAddUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.SaturatedAddMasked", opLen3(ssa.OpSaturatedAddMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.SaturatedAddMasked", opLen3(ssa.OpSaturatedAddMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.SaturatedAddMasked", opLen3(ssa.OpSaturatedAddMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.SaturatedAddMasked", opLen3(ssa.OpSaturatedAddMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.SaturatedAddMasked", opLen3(ssa.OpSaturatedAddMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.SaturatedAddMasked", opLen3(ssa.OpSaturatedAddMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.SaturatedAddMasked", opLen3(ssa.OpSaturatedAddMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.SaturatedAddMasked", opLen3(ssa.OpSaturatedAddMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.SaturatedAddMasked", opLen3(ssa.OpSaturatedAddMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.SaturatedAddMasked", opLen3(ssa.OpSaturatedAddMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.SaturatedAddMasked", opLen3(ssa.OpSaturatedAddMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.SaturatedAddMasked", opLen3(ssa.OpSaturatedAddMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.SaturatedPairDotProdAccumulate", opLen3_31(ssa.OpSaturatedPairDotProdAccumulateInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.SaturatedPairDotProdAccumulate", opLen3_31(ssa.OpSaturatedPairDotProdAccumulateInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.SaturatedPairDotProdAccumulate", opLen3_31(ssa.OpSaturatedPairDotProdAccumulateInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.SaturatedPairDotProdAccumulateMasked", opLen4_31(ssa.OpSaturatedPairDotProdAccumulateMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.SaturatedPairDotProdAccumulateMasked", opLen4_31(ssa.OpSaturatedPairDotProdAccumulateMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.SaturatedPairDotProdAccumulateMasked", opLen4_31(ssa.OpSaturatedPairDotProdAccumulateMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.SaturatedPairwiseAdd", opLen2(ssa.OpSaturatedPairwiseAddInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.SaturatedPairwiseAdd", opLen2(ssa.OpSaturatedPairwiseAddInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x8.SaturatedPairwiseSub", opLen2(ssa.OpSaturatedPairwiseSubInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.SaturatedPairwiseSub", opLen2(ssa.OpSaturatedPairwiseSubInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x16.SaturatedSub", opLen2(ssa.OpSaturatedSubInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.SaturatedSub", opLen2(ssa.OpSaturatedSubInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.SaturatedSub", opLen2(ssa.OpSaturatedSubInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.SaturatedSub", opLen2(ssa.OpSaturatedSubInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.SaturatedSub", opLen2(ssa.OpSaturatedSubInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.SaturatedSub", opLen2(ssa.OpSaturatedSubInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.SaturatedSub", opLen2(ssa.OpSaturatedSubUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.SaturatedSub", opLen2(ssa.OpSaturatedSubUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.SaturatedSub", opLen2(ssa.OpSaturatedSubUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.SaturatedSub", opLen2(ssa.OpSaturatedSubUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.SaturatedSub", opLen2(ssa.OpSaturatedSubUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.SaturatedSub", opLen2(ssa.OpSaturatedSubUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.SaturatedSubMasked", opLen3(ssa.OpSaturatedSubMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.SaturatedSubMasked", opLen3(ssa.OpSaturatedSubMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.SaturatedSubMasked", opLen3(ssa.OpSaturatedSubMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.SaturatedSubMasked", opLen3(ssa.OpSaturatedSubMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.SaturatedSubMasked", opLen3(ssa.OpSaturatedSubMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.SaturatedSubMasked", opLen3(ssa.OpSaturatedSubMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.SaturatedSubMasked", opLen3(ssa.OpSaturatedSubMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.SaturatedSubMasked", opLen3(ssa.OpSaturatedSubMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.SaturatedSubMasked", opLen3(ssa.OpSaturatedSubMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.SaturatedSubMasked", opLen3(ssa.OpSaturatedSubMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.SaturatedSubMasked", opLen3(ssa.OpSaturatedSubMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.SaturatedSubMasked", opLen3(ssa.OpSaturatedSubMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.SaturatedUnsignedSignedPairDotProd", opLen2(ssa.OpSaturatedUnsignedSignedPairDotProdUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.SaturatedUnsignedSignedPairDotProd", opLen2(ssa.OpSaturatedUnsignedSignedPairDotProdUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.SaturatedUnsignedSignedPairDotProd", opLen2(ssa.OpSaturatedUnsignedSignedPairDotProdUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.SaturatedUnsignedSignedPairDotProdMasked", opLen3(ssa.OpSaturatedUnsignedSignedPairDotProdMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.SaturatedUnsignedSignedPairDotProdMasked", opLen3(ssa.OpSaturatedUnsignedSignedPairDotProdMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.SaturatedUnsignedSignedPairDotProdMasked", opLen3(ssa.OpSaturatedUnsignedSignedPairDotProdMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.SaturatedUnsignedSignedQuadDotProdAccumulate", opLen3_31(ssa.OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.SaturatedUnsignedSignedQuadDotProdAccumulate", opLen3_31(ssa.OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.SaturatedUnsignedSignedQuadDotProdAccumulate", opLen3_31(ssa.OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.SaturatedUnsignedSignedQuadDotProdAccumulateMasked", opLen4_31(ssa.OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.SaturatedUnsignedSignedQuadDotProdAccumulateMasked", opLen4_31(ssa.OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.SaturatedUnsignedSignedQuadDotProdAccumulateMasked", opLen4_31(ssa.OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x8.Set128", opLen2Imm8(ssa.OpSet128Float32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Float64x4.Set128", opLen2Imm8(ssa.OpSet128Float64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int8x32.Set128", opLen2Imm8(ssa.OpSet128Int8x32, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int16x16.Set128", opLen2Imm8(ssa.OpSet128Int16x16, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int32x8.Set128", opLen2Imm8(ssa.OpSet128Int32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int64x4.Set128", opLen2Imm8(ssa.OpSet128Int64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Set128", opLen2Imm8(ssa.OpSet128Uint8x32, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Set128", opLen2Imm8(ssa.OpSet128Uint16x16, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Set128", opLen2Imm8(ssa.OpSet128Uint32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Set128", opLen2Imm8(ssa.OpSet128Uint64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int8x16.SetElem", opLen2Imm8(ssa.OpSetElemInt8x16, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int16x8.SetElem", opLen2Imm8(ssa.OpSetElemInt16x8, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int32x4.SetElem", opLen2Imm8(ssa.OpSetElemInt32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int64x2.SetElem", opLen2Imm8(ssa.OpSetElemInt64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint8x16.SetElem", opLen2Imm8(ssa.OpSetElemUint8x16, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x8.SetElem", opLen2Imm8(ssa.OpSetElemUint16x8, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x4.SetElem", opLen2Imm8(ssa.OpSetElemUint32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x2.SetElem", opLen2Imm8(ssa.OpSetElemUint64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt16x8, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt16x16, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt16x32, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint16x8, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint16x16, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint16x32, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedInt16x8, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedInt16x16, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedInt16x32, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedInt32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedInt32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedInt32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedInt64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedInt64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedInt64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedUint16x8, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedUint16x16, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedUint16x32, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedUint32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedUint32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedUint32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedUint64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedUint64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftAllLeftAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllLeftAndFillUpperFromMaskedUint64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftAllLeftMasked", opLen3(ssa.OpShiftAllLeftMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt16x8, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt16x16, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt16x32, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint16x8, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint16x16, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint16x32, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedInt16x8, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedInt16x16, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedInt16x32, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedInt32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedInt32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedInt32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedInt64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedInt64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedInt64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedUint16x8, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedUint16x16, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedUint16x32, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedUint32x4, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedUint32x8, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedUint32x16, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedUint64x2, types.TypeVec128, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedUint64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftAllRightAndFillUpperFromMasked", opLen3Imm8(ssa.OpShiftAllRightAndFillUpperFromMaskedUint64x8, types.TypeVec512, 0), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftAllRightMasked", opLen3(ssa.OpShiftAllRightMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftLeft", opLen2(ssa.OpShiftLeftInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftLeft", opLen2(ssa.OpShiftLeftInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftLeft", opLen2(ssa.OpShiftLeftInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftLeft", opLen2(ssa.OpShiftLeftInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftLeft", opLen2(ssa.OpShiftLeftInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftLeft", opLen2(ssa.OpShiftLeftInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftLeft", opLen2(ssa.OpShiftLeftInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftLeft", opLen2(ssa.OpShiftLeftInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftLeft", opLen2(ssa.OpShiftLeftInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftLeft", opLen2(ssa.OpShiftLeftUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftLeft", opLen2(ssa.OpShiftLeftUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftLeft", opLen2(ssa.OpShiftLeftUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftLeft", opLen2(ssa.OpShiftLeftUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftLeft", opLen2(ssa.OpShiftLeftUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftLeft", opLen2(ssa.OpShiftLeftUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftLeft", opLen2(ssa.OpShiftLeftUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftLeft", opLen2(ssa.OpShiftLeftUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftLeft", opLen2(ssa.OpShiftLeftUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftLeftAndFillUpperFromMasked", opLen4(ssa.OpShiftLeftAndFillUpperFromMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftLeftMasked", opLen3(ssa.OpShiftLeftMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftRight", opLen2(ssa.OpShiftRightInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftRight", opLen2(ssa.OpShiftRightInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftRight", opLen2(ssa.OpShiftRightInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftRight", opLen2(ssa.OpShiftRightInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftRight", opLen2(ssa.OpShiftRightInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftRight", opLen2(ssa.OpShiftRightInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftRight", opLen2(ssa.OpShiftRightInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftRight", opLen2(ssa.OpShiftRightInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftRight", opLen2(ssa.OpShiftRightInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftRight", opLen2(ssa.OpShiftRightUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftRight", opLen2(ssa.OpShiftRightUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftRight", opLen2(ssa.OpShiftRightUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftRight", opLen2(ssa.OpShiftRightUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftRight", opLen2(ssa.OpShiftRightUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftRight", opLen2(ssa.OpShiftRightUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftRight", opLen2(ssa.OpShiftRightUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftRight", opLen2(ssa.OpShiftRightUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftRight", opLen2(ssa.OpShiftRightUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftRightAndFillUpperFromMasked", opLen4(ssa.OpShiftRightAndFillUpperFromMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.ShiftRightMasked", opLen3(ssa.OpShiftRightMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.Sign", opLen2(ssa.OpSignInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Sign", opLen2(ssa.OpSignInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x8.Sign", opLen2(ssa.OpSignInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Sign", opLen2(ssa.OpSignInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x4.Sign", opLen2(ssa.OpSignInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.Sign", opLen2(ssa.OpSignInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x4.Sqrt", opLen1(ssa.OpSqrtFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Sqrt", opLen1(ssa.OpSqrtFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Sqrt", opLen1(ssa.OpSqrtFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.Sqrt", opLen1(ssa.OpSqrtFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Sqrt", opLen1(ssa.OpSqrtFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Sqrt", opLen1(ssa.OpSqrtFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.SqrtMasked", opLen2(ssa.OpSqrtMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.SqrtMasked", opLen2(ssa.OpSqrtMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.SqrtMasked", opLen2(ssa.OpSqrtMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.SqrtMasked", opLen2(ssa.OpSqrtMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.SqrtMasked", opLen2(ssa.OpSqrtMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.SqrtMasked", opLen2(ssa.OpSqrtMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.Sub", opLen2(ssa.OpSubFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Sub", opLen2(ssa.OpSubFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.Sub", opLen2(ssa.OpSubFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.Sub", opLen2(ssa.OpSubFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Sub", opLen2(ssa.OpSubFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.Sub", opLen2(ssa.OpSubFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.Sub", opLen2(ssa.OpSubInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Sub", opLen2(ssa.OpSubInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.Sub", opLen2(ssa.OpSubInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.Sub", opLen2(ssa.OpSubInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Sub", opLen2(ssa.OpSubInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.Sub", opLen2(ssa.OpSubInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.Sub", opLen2(ssa.OpSubInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.Sub", opLen2(ssa.OpSubInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.Sub", opLen2(ssa.OpSubInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.Sub", opLen2(ssa.OpSubInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.Sub", opLen2(ssa.OpSubInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.Sub", opLen2(ssa.OpSubInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Sub", opLen2(ssa.OpSubUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Sub", opLen2(ssa.OpSubUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.Sub", opLen2(ssa.OpSubUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Sub", opLen2(ssa.OpSubUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Sub", opLen2(ssa.OpSubUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.Sub", opLen2(ssa.OpSubUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.Sub", opLen2(ssa.OpSubUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Sub", opLen2(ssa.OpSubUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Sub", opLen2(ssa.OpSubUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.Sub", opLen2(ssa.OpSubUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Sub", opLen2(ssa.OpSubUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Sub", opLen2(ssa.OpSubUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.SubMasked", opLen3(ssa.OpSubMaskedFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.SubMasked", opLen3(ssa.OpSubMaskedFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x16.SubMasked", opLen3(ssa.OpSubMaskedFloat32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float64x2.SubMasked", opLen3(ssa.OpSubMaskedFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.SubMasked", opLen3(ssa.OpSubMaskedFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x8.SubMasked", opLen3(ssa.OpSubMaskedFloat64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.SubMasked", opLen3(ssa.OpSubMaskedInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.SubMasked", opLen3(ssa.OpSubMaskedInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.SubMasked", opLen3(ssa.OpSubMaskedInt8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int16x8.SubMasked", opLen3(ssa.OpSubMaskedInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.SubMasked", opLen3(ssa.OpSubMaskedInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x32.SubMasked", opLen3(ssa.OpSubMaskedInt16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.SubMasked", opLen3(ssa.OpSubMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.SubMasked", opLen3(ssa.OpSubMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.SubMasked", opLen3(ssa.OpSubMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.SubMasked", opLen3(ssa.OpSubMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.SubMasked", opLen3(ssa.OpSubMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.SubMasked", opLen3(ssa.OpSubMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.SubMasked", opLen3(ssa.OpSubMaskedUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.SubMasked", opLen3(ssa.OpSubMaskedUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint8x64.SubMasked", opLen3(ssa.OpSubMaskedUint8x64, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint16x8.SubMasked", opLen3(ssa.OpSubMaskedUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.SubMasked", opLen3(ssa.OpSubMaskedUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x32.SubMasked", opLen3(ssa.OpSubMaskedUint16x32, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.SubMasked", opLen3(ssa.OpSubMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.SubMasked", opLen3(ssa.OpSubMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.SubMasked", opLen3(ssa.OpSubMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.SubMasked", opLen3(ssa.OpSubMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.SubMasked", opLen3(ssa.OpSubMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.SubMasked", opLen3(ssa.OpSubMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.Trunc", opLen1(ssa.OpTruncFloat32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float32x8.Trunc", opLen1(ssa.OpTruncFloat32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float64x2.Trunc", opLen1(ssa.OpTruncFloat64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Float64x4.Trunc", opLen1(ssa.OpTruncFloat64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Float32x4.TruncWithPrecision", opLen1Imm8(ssa.OpTruncWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.TruncWithPrecision", opLen1Imm8(ssa.OpTruncWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.TruncWithPrecision", opLen1Imm8(ssa.OpTruncWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.TruncWithPrecision", opLen1Imm8(ssa.OpTruncWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.TruncWithPrecision", opLen1Imm8(ssa.OpTruncWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.TruncWithPrecision", opLen1Imm8(ssa.OpTruncWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float32x4.TruncWithPrecisionMasked", opLen2Imm8(ssa.OpTruncWithPrecisionMaskedFloat32x4, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float32x8.TruncWithPrecisionMasked", opLen2Imm8(ssa.OpTruncWithPrecisionMaskedFloat32x8, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float32x16.TruncWithPrecisionMasked", opLen2Imm8(ssa.OpTruncWithPrecisionMaskedFloat32x16, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Float64x2.TruncWithPrecisionMasked", opLen2Imm8(ssa.OpTruncWithPrecisionMaskedFloat64x2, types.TypeVec128, 4), sys.AMD64)
+	addF(simdPackage, "Float64x4.TruncWithPrecisionMasked", opLen2Imm8(ssa.OpTruncWithPrecisionMaskedFloat64x4, types.TypeVec256, 4), sys.AMD64)
+	addF(simdPackage, "Float64x8.TruncWithPrecisionMasked", opLen2Imm8(ssa.OpTruncWithPrecisionMaskedFloat64x8, types.TypeVec512, 4), sys.AMD64)
+	addF(simdPackage, "Int8x16.UnsignedSignedQuadDotProdAccumulate", opLen3_31(ssa.OpUnsignedSignedQuadDotProdAccumulateInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.UnsignedSignedQuadDotProdAccumulate", opLen3_31(ssa.OpUnsignedSignedQuadDotProdAccumulateInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.UnsignedSignedQuadDotProdAccumulate", opLen3_31(ssa.OpUnsignedSignedQuadDotProdAccumulateInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.UnsignedSignedQuadDotProdAccumulateMasked", opLen4_31(ssa.OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.UnsignedSignedQuadDotProdAccumulateMasked", opLen4_31(ssa.OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int8x64.UnsignedSignedQuadDotProdAccumulateMasked", opLen4_31(ssa.OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int8x16.Xor", opLen2(ssa.OpXorInt8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int8x32.Xor", opLen2(ssa.OpXorInt8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int16x8.Xor", opLen2(ssa.OpXorInt16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int16x16.Xor", opLen2(ssa.OpXorInt16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x4.Xor", opLen2(ssa.OpXorInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.Xor", opLen2(ssa.OpXorInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.Xor", opLen2(ssa.OpXorInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.Xor", opLen2(ssa.OpXorInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.Xor", opLen2(ssa.OpXorInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.Xor", opLen2(ssa.OpXorInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Xor", opLen2(ssa.OpXorUint8x16, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Xor", opLen2(ssa.OpXorUint8x32, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Xor", opLen2(ssa.OpXorUint16x8, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Xor", opLen2(ssa.OpXorUint16x16, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x4.Xor", opLen2(ssa.OpXorUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Xor", opLen2(ssa.OpXorUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Xor", opLen2(ssa.OpXorUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.Xor", opLen2(ssa.OpXorUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Xor", opLen2(ssa.OpXorUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Xor", opLen2(ssa.OpXorUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.XorMasked", opLen3(ssa.OpXorMaskedInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.XorMasked", opLen3(ssa.OpXorMaskedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.XorMasked", opLen3(ssa.OpXorMaskedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int64x2.XorMasked", opLen3(ssa.OpXorMaskedInt64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int64x4.XorMasked", opLen3(ssa.OpXorMaskedInt64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int64x8.XorMasked", opLen3(ssa.OpXorMaskedInt64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint32x4.XorMasked", opLen3(ssa.OpXorMaskedUint32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint32x8.XorMasked", opLen3(ssa.OpXorMaskedUint32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint32x16.XorMasked", opLen3(ssa.OpXorMaskedUint32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Uint64x2.XorMasked", opLen3(ssa.OpXorMaskedUint64x2, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Uint64x4.XorMasked", opLen3(ssa.OpXorMaskedUint64x4, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Uint64x8.XorMasked", opLen3(ssa.OpXorMaskedUint64x8, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Float32x4.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x4.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x4.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x4.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x4.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x4.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x4.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x4.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x4.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x8.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x8.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x8.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x8.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x8.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x8.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x8.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x8.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x8.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x16.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x16.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x16.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x16.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x16.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x16.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x16.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x16.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float32x16.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x2.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x2.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x2.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x2.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x2.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x2.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x2.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x2.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x2.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x4.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x4.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x4.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x4.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x4.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x4.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x4.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x4.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x4.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x8.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x8.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x8.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x8.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x8.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x8.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x8.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x8.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Float64x8.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x16.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x16.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x16.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x16.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x16.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x16.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x16.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x16.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x16.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x32.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x32.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x32.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x32.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x32.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x32.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x32.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x32.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x32.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x64.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x64.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x64.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x64.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x64.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x64.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x64.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x64.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x64.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x8.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x8.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x8.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x8.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x8.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x8.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x8.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x8.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x8.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x16.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x16.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x16.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x16.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x16.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x16.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x16.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x16.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x16.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x32.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x32.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x32.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x32.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x32.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x32.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x32.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x32.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x32.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x4.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x4.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x4.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x4.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x4.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x4.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x4.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x4.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x4.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x8.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x8.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x8.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x8.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x8.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x8.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x8.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x8.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x8.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x16.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x16.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x16.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x16.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x16.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x16.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x16.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x16.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x16.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x2.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x2.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x2.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x2.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x2.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x2.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x2.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x2.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x2.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x4.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x4.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x4.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x4.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x4.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x4.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x4.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x4.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x4.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x8.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x8.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x8.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x8.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x8.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x8.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x8.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x8.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x8.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x16.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x16.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x16.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x16.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x16.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x16.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x16.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x16.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x16.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x32.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x32.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x32.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x32.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x32.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x32.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x32.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x32.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x32.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x64.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x64.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x64.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x64.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x64.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x64.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x64.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x64.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint8x64.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x8.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x8.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x8.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x8.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x8.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x8.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x8.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x8.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x8.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x16.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x16.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x16.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x16.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x16.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x16.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x16.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x16.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x16.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x32.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x32.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x32.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x32.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x32.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x32.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x32.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x32.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint16x32.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x4.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x4.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x4.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x4.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x4.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x4.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x4.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x4.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x4.AsUint64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x8.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x8.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x8.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x8.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x8.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x8.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x8.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x8.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x8.AsUint64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x16.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x16.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x16.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x16.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x16.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x16.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x16.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x16.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint32x16.AsUint64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x2.AsFloat32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x2.AsFloat64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x2.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x2.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x2.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x2.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x2.AsUint8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x2.AsUint16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x2.AsUint32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x4.AsFloat32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x4.AsFloat64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x4.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x4.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x4.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x4.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x4.AsUint8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x4.AsUint16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x4.AsUint32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x8.AsFloat32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x8.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x8.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x8.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x8.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x8.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x8.AsUint8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x8.AsUint16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Uint64x8.AsUint32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "LoadFloat32x4", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Float32x4.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadFloat32x8", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Float32x8.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadFloat32x16", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Float32x16.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadFloat64x2", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Float64x2.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadFloat64x4", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Float64x4.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadFloat64x8", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Float64x8.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadInt8x16", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Int8x16.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadInt8x32", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Int8x32.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadInt8x64", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Int8x64.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadInt16x8", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Int16x8.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadInt16x16", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Int16x16.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadInt16x32", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Int16x32.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadInt32x4", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Int32x4.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadInt32x8", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Int32x8.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadInt32x16", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Int32x16.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadInt64x2", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Int64x2.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadInt64x4", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Int64x4.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadInt64x8", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Int64x8.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadUint8x16", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Uint8x16.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadUint8x32", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Uint8x32.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadUint8x64", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Uint8x64.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadUint16x8", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Uint16x8.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadUint16x16", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Uint16x16.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadUint16x32", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Uint16x32.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadUint32x4", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Uint32x4.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadUint32x8", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Uint32x8.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadUint32x16", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Uint32x16.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadUint64x2", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Uint64x2.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadUint64x4", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Uint64x4.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadUint64x8", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Uint64x8.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadMask8x16", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Mask8x16.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadMask8x32", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Mask8x32.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadMask8x64", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Mask8x64.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadMask16x8", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Mask16x8.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadMask16x16", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Mask16x16.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadMask16x32", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Mask16x32.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadMask32x4", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Mask32x4.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadMask32x8", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Mask32x8.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadMask32x16", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Mask32x16.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadMask64x2", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Mask64x2.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadMask64x4", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Mask64x4.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "LoadMask64x8", simdLoad(), sys.AMD64)
+	addF(simdPackage, "Mask64x8.Store", simdStore(), sys.AMD64)
+	addF(simdPackage, "Mask8x16.AsInt8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x16.AsMask8x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Mask8x16.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Mask8x16.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Mask8x32.AsInt8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x32.AsMask8x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Mask8x32.And", opLen2(ssa.OpAndInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Mask8x32.Or", opLen2(ssa.OpOrInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Mask8x64.AsInt8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int8x64.AsMask8x64", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Mask8x64.And", opLen2(ssa.OpAndInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Mask8x64.Or", opLen2(ssa.OpOrInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Mask16x8.AsInt16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x8.AsMask16x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Mask16x8.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Mask16x8.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Mask16x16.AsInt16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x16.AsMask16x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Mask16x16.And", opLen2(ssa.OpAndInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Mask16x16.Or", opLen2(ssa.OpOrInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Mask16x32.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int16x32.AsMask16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Mask16x32.And", opLen2(ssa.OpAndInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Mask16x32.Or", opLen2(ssa.OpOrInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Mask32x4.AsInt32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x4.AsMask32x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Mask32x4.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Mask32x4.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Mask32x8.AsInt32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x8.AsMask32x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Mask32x8.And", opLen2(ssa.OpAndInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Mask32x8.Or", opLen2(ssa.OpOrInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Mask32x16.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int32x16.AsMask32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Mask32x16.And", opLen2(ssa.OpAndInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Mask32x16.Or", opLen2(ssa.OpOrInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Mask64x2.AsInt64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x2.AsMask64x2", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Mask64x2.And", opLen2(ssa.OpAndInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Mask64x2.Or", opLen2(ssa.OpOrInt32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Mask64x4.AsInt64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x4.AsMask64x4", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Mask64x4.And", opLen2(ssa.OpAndInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Mask64x4.Or", opLen2(ssa.OpOrInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Mask64x8.AsInt64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Int64x8.AsMask64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
+	addF(simdPackage, "Mask64x8.And", opLen2(ssa.OpAndInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Mask64x8.Or", opLen2(ssa.OpOrInt32x16, types.TypeVec512), sys.AMD64)
+}
diff --git a/src/cmd/compile/internal/ssagen/ssa.go b/src/cmd/compile/internal/ssagen/ssa.go
index e241e9b9bc0f4f..e9121c9ee23358 100644
--- a/src/cmd/compile/internal/ssagen/ssa.go
+++ b/src/cmd/compile/internal/ssagen/ssa.go
@@ -623,6 +623,9 @@ func buildssa(fn *ir.Func, worker int, isPgoHot bool) *ssa.Func {
 	// TODO figure out exactly what's unused, don't spill it. Make liveness fine-grained, also.
 	for _, p := range params.InParams() {
 		typs, offs := p.RegisterTypesAndOffsets()
+		if len(offs) < len(typs) {
+			s.Fatalf("len(offs)=%d < len(typs)=%d, params=\n%s", len(offs), len(typs), params)
+		}
 		for i, t := range typs {
 			o := offs[i]                // offset within parameter
 			fo := p.FrameOffset(params) // offset of parameter in frame
@@ -1399,7 +1402,7 @@ func (s *state) instrument(t *types.Type, addr *ssa.Value, kind instrumentKind)
 // If it is instrumenting for MSAN or ASAN and t is a struct type, it instruments
 // operation for each field, instead of for the whole struct.
 func (s *state) instrumentFields(t *types.Type, addr *ssa.Value, kind instrumentKind) {
-	if !(base.Flag.MSan || base.Flag.ASan) || !t.IsStruct() {
+	if !(base.Flag.MSan || base.Flag.ASan) || !isStructNotSIMD(t) {
 		s.instrument(t, addr, kind)
 		return
 	}
@@ -4335,7 +4338,7 @@ func (s *state) zeroVal(t *types.Type) *ssa.Value {
 		return s.constInterface(t)
 	case t.IsSlice():
 		return s.constSlice(t)
-	case t.IsStruct():
+	case isStructNotSIMD(t):
 		n := t.NumFields()
 		v := s.entryNewValue0(ssa.OpStructMake, t)
 		for i := 0; i < n; i++ {
@@ -4349,6 +4352,8 @@ func (s *state) zeroVal(t *types.Type) *ssa.Value {
 		case 1:
 			return s.entryNewValue1(ssa.OpArrayMake1, t, s.zeroVal(t.Elem()))
 		}
+	case t.IsSIMD():
+		return s.newValue0(ssa.OpZeroSIMD, t)
 	}
 	s.Fatalf("zero for type %v not implemented", t)
 	return nil
@@ -5328,7 +5333,7 @@ func (s *state) storeType(t *types.Type, left, right *ssa.Value, skip skipMask,
 // do *left = right for all scalar (non-pointer) parts of t.
 func (s *state) storeTypeScalars(t *types.Type, left, right *ssa.Value, skip skipMask) {
 	switch {
-	case t.IsBoolean() || t.IsInteger() || t.IsFloat() || t.IsComplex():
+	case t.IsBoolean() || t.IsInteger() || t.IsFloat() || t.IsComplex() || t.IsSIMD():
 		s.store(t, left, right)
 	case t.IsPtrShaped():
 		if t.IsPtr() && t.Elem().NotInHeap() {
@@ -5357,7 +5362,7 @@ func (s *state) storeTypeScalars(t *types.Type, left, right *ssa.Value, skip ski
 		// itab field doesn't need a write barrier (even though it is a pointer).
 		itab := s.newValue1(ssa.OpITab, s.f.Config.Types.BytePtr, right)
 		s.store(types.Types[types.TUINTPTR], left, itab)
-	case t.IsStruct():
+	case isStructNotSIMD(t):
 		n := t.NumFields()
 		for i := 0; i < n; i++ {
 			ft := t.FieldType(i)
@@ -5394,7 +5399,7 @@ func (s *state) storeTypePtrs(t *types.Type, left, right *ssa.Value) {
 		idata := s.newValue1(ssa.OpIData, s.f.Config.Types.BytePtr, right)
 		idataAddr := s.newValue1I(ssa.OpOffPtr, s.f.Config.Types.BytePtrPtr, s.config.PtrSize, left)
 		s.store(s.f.Config.Types.BytePtr, idataAddr, idata)
-	case t.IsStruct():
+	case isStructNotSIMD(t):
 		n := t.NumFields()
 		for i := 0; i < n; i++ {
 			ft := t.FieldType(i)
@@ -6477,7 +6482,7 @@ func EmitArgInfo(f *ir.Func, abiInfo *abi.ABIParamResultInfo) *obj.LSym {
 	uintptrTyp := types.Types[types.TUINTPTR]
 
 	isAggregate := func(t *types.Type) bool {
-		return t.IsStruct() || t.IsArray() || t.IsComplex() || t.IsInterface() || t.IsString() || t.IsSlice()
+		return isStructNotSIMD(t) || t.IsArray() || t.IsComplex() || t.IsInterface() || t.IsString() || t.IsSlice()
 	}
 
 	wOff := 0
@@ -6537,7 +6542,7 @@ func EmitArgInfo(f *ir.Func, abiInfo *abi.ABIParamResultInfo) *obj.LSym {
 				}
 				baseOffset += t.Elem().Size()
 			}
-		case t.IsStruct():
+		case isStructNotSIMD(t):
 			if t.NumFields() == 0 {
 				n++ // {} counts as a component
 				break
@@ -7554,7 +7559,7 @@ func (s *State) UseArgs(n int64) {
 // fieldIdx finds the index of the field referred to by the ODOT node n.
 func fieldIdx(n *ir.SelectorExpr) int {
 	t := n.X.Type()
-	if !t.IsStruct() {
+	if !isStructNotSIMD(t) {
 		panic("ODOT's LHS is not a struct")
 	}
 
@@ -7762,6 +7767,10 @@ func SpillSlotAddr(spill ssa.Spill, baseReg int16, extraOffset int64) obj.Addr {
 	}
 }
 
+func isStructNotSIMD(t *types.Type) bool {
+	return t.IsStruct() && !t.IsSIMD()
+}
+
 var (
 	BoundsCheckFunc [ssa.BoundsKindCount]*obj.LSym
 	ExtendCheckFunc [ssa.BoundsKindCount]*obj.LSym
diff --git a/src/cmd/compile/internal/types/size.go b/src/cmd/compile/internal/types/size.go
index 72ec4052a808e4..2aa437b56ffe7e 100644
--- a/src/cmd/compile/internal/types/size.go
+++ b/src/cmd/compile/internal/types/size.go
@@ -10,6 +10,7 @@ import (
 
 	"cmd/compile/internal/base"
 	"cmd/internal/src"
+	"internal/buildcfg"
 	"internal/types/errors"
 )
 
@@ -410,6 +411,10 @@ func CalcSize(t *Type) {
 		}
 		CalcStructSize(t)
 		w = t.width
+		if t.IsSIMD() { // XXX
+			t.intRegs = 0
+			t.floatRegs = 1
+		}
 
 	// make fake type to check later to
 	// trigger function argument computation.
@@ -452,6 +457,31 @@ func CalcSize(t *Type) {
 	ResumeCheckSize()
 }
 
+// simdify marks as type as "SIMD", either as a tag field,
+// or having the SIMD attribute.  The tag field is a marker
+// type used to identify a struct that is not really a struct.
+// A SIMD type is allocated to a vector register (on amd64,
+// xmm, ymm, or zmm).  The fields of a SIMD type are ignored
+// by the compiler except for the space that they reserve.
+func simdify(st *Type, isTag bool) {
+	st.align = 8
+	st.alg = AMEM
+	st.intRegs = 0
+	st.isSIMD = true
+	if isTag {
+		st.width = 0
+		st.isSIMDTag = true
+		st.floatRegs = 0
+	} else {
+		st.floatRegs = 1
+	}
+	// if st.Sym() != nil {
+	// 	base.Warn("Simdify %s, %v, %d", st.Sym().Name, isTag, st.width)
+	// } else {
+	// 	base.Warn("Simdify %v, %v, %d", st, isTag, st.width)
+	// }
+}
+
 // CalcStructSize calculates the size of t,
 // filling in t.width, t.align, t.intRegs, and t.floatRegs,
 // even if size calculation is otherwise disabled.
@@ -464,10 +494,27 @@ func CalcStructSize(t *Type) {
 		switch {
 		case sym.Name == "align64" && isAtomicStdPkg(sym.Pkg):
 			maxAlign = 8
+
+		case buildcfg.Experiment.SIMD && (sym.Pkg.Path == "internal/simd" || sym.Pkg.Path == "simd") && len(t.Fields()) >= 1:
+			// This gates the experiment -- without it, no user-visible types can be "simd".
+			// The SSA-visible SIMD types remain.
+			// TODO after simd has been moved to package simd, remove internal/simd.
+			switch sym.Name {
+			case "v128":
+				simdify(t, true)
+				return
+			case "v256":
+				simdify(t, true)
+				return
+			case "v512":
+				simdify(t, true)
+				return
+			}
 		}
 	}
 
 	fields := t.Fields()
+
 	size := calcStructOffset(t, fields, 0)
 
 	// For non-zero-sized structs which end in a zero-sized field, we
@@ -540,6 +587,11 @@ func CalcStructSize(t *Type) {
 			break
 		}
 	}
+
+	if len(t.Fields()) >= 1 && t.Fields()[0].Type.isSIMDTag {
+		// this catches `type Foo simd.Whatever` -- Foo is also SIMD.
+		simdify(t, false)
+	}
 }
 
 // CalcArraySize calculates the size of t,
diff --git a/src/cmd/compile/internal/types/type.go b/src/cmd/compile/internal/types/type.go
index c4080ed0b526ae..f7b9b0f3f75940 100644
--- a/src/cmd/compile/internal/types/type.go
+++ b/src/cmd/compile/internal/types/type.go
@@ -201,8 +201,9 @@ type Type struct {
 
 	intRegs, floatRegs uint8 // registers needed for ABIInternal
 
-	flags bitset8
-	alg   AlgKind // valid if Align > 0
+	flags             bitset8
+	alg               AlgKind // valid if Align > 0
+	isSIMDTag, isSIMD bool    // tag is the marker type, isSIMD means has marker type
 
 	// size of prefix of object that contains all pointers. valid if Align > 0.
 	// Note that for pointers, this is always PtrSize even if the element type
@@ -605,6 +606,12 @@ func newSSA(name string) *Type {
 	return t
 }
 
+func newSIMD(name string) *Type {
+	t := newSSA(name)
+	t.isSIMD = true
+	return t
+}
+
 // NewMap returns a new map Type with key type k and element (aka value) type v.
 func NewMap(k, v *Type) *Type {
 	t := newType(TMAP)
@@ -995,10 +1002,7 @@ func (t *Type) ArgWidth() int64 {
 
 func (t *Type) Size() int64 {
 	if t.kind == TSSA {
-		if t == TypeInt128 {
-			return 16
-		}
-		return 0
+		return t.width
 	}
 	CalcSize(t)
 	return t.width
@@ -1626,12 +1630,26 @@ var (
 	TypeFlags     = newSSA("flags")
 	TypeVoid      = newSSA("void")
 	TypeInt128    = newSSA("int128")
+	TypeVec128    = newSIMD("vec128")
+	TypeVec256    = newSIMD("vec256")
+	TypeVec512    = newSIMD("vec512")
+	TypeMask      = newSIMD("mask") // not a vector, not 100% sure what this should be.
 	TypeResultMem = newResults([]*Type{TypeMem})
 )
 
 func init() {
 	TypeInt128.width = 16
 	TypeInt128.align = 8
+
+	TypeVec128.width = 16
+	TypeVec128.align = 8
+	TypeVec256.width = 32
+	TypeVec256.align = 8
+	TypeVec512.width = 64
+	TypeVec512.align = 8
+
+	TypeMask.width = 8 // This will depend on the architecture; spilling will be "interesting".
+	TypeMask.align = 8
 }
 
 // NewNamed returns a new named type for the given type name. obj should be an
@@ -2017,3 +2035,7 @@ var SimType [NTYPE]Kind
 
 // Fake package for shape types (see typecheck.Shapify()).
 var ShapePkg = NewPkg("go.shape", "go.shape")
+
+func (t *Type) IsSIMD() bool {
+	return t.isSIMD
+}
diff --git a/src/cmd/compile/internal/walk/walk.go b/src/cmd/compile/internal/walk/walk.go
index 2fa51f12809362..8b4381980d58eb 100644
--- a/src/cmd/compile/internal/walk/walk.go
+++ b/src/cmd/compile/internal/walk/walk.go
@@ -311,6 +311,15 @@ func backingArrayPtrLen(n ir.Node) (ptr, length ir.Node) {
 // function calls, which could clobber function call arguments/results
 // currently on the stack.
 func mayCall(n ir.Node) bool {
+	// This is intended to avoid putting constants
+	// into temporaries with the race detector (or other
+	// instrumentation) which interferes with simple
+	// "this is a constant" tests in ssagen.
+	// Also, it will generally lead to better code.
+	if n.Op() == ir.OLITERAL {
+		return false
+	}
+
 	// When instrumenting, any expression might require function calls.
 	if base.Flag.Cfg.Instrumenting {
 		return true
diff --git a/src/cmd/dist/test.go b/src/cmd/dist/test.go
index aa09d1eba34be8..b731ea51e5a1f0 100644
--- a/src/cmd/dist/test.go
+++ b/src/cmd/dist/test.go
@@ -955,7 +955,9 @@ func (t *tester) registerTests() {
 	// which is darwin,linux,windows/amd64 and darwin/arm64.
 	//
 	// The same logic applies to the release notes that correspond to each api/next file.
-	if goos == "darwin" || ((goos == "linux" || goos == "windows") && goarch == "amd64") {
+	//
+	// TODO: remove the exclusion of goexperiment simd right before dev.simd branch is merged to master.
+	if goos == "darwin" || ((goos == "linux" || goos == "windows") && (goarch == "amd64" && !strings.Contains(goexperiment, "simd"))) {
 		t.registerTest("API release note check", &goTest{variant: "check", pkg: "cmd/relnote", testFlags: []string{"-check"}})
 		t.registerTest("API check", &goTest{variant: "check", pkg: "cmd/api", timeout: 5 * time.Minute, testFlags: []string{"-check"}})
 	}
diff --git a/src/go/build/deps_test.go b/src/go/build/deps_test.go
index 6d92542e31b652..d62f177b1a024a 100644
--- a/src/go/build/deps_test.go
+++ b/src/go/build/deps_test.go
@@ -70,6 +70,8 @@ var depsRules = `
 	internal/goarch < internal/abi;
 	internal/byteorder, internal/cpu, internal/goarch < internal/chacha8rand;
 
+	internal/cpu < simd;
+
 	# RUNTIME is the core runtime group of packages, all of them very light-weight.
 	internal/abi,
 	internal/chacha8rand,
diff --git a/src/go/doc/comment/std.go b/src/go/doc/comment/std.go
index 191e1f129107de..73cf9627a02b58 100644
--- a/src/go/doc/comment/std.go
+++ b/src/go/doc/comment/std.go
@@ -35,6 +35,7 @@ var stdPkgs = []string{
 	"reflect",
 	"regexp",
 	"runtime",
+	"simd",
 	"slices",
 	"sort",
 	"strconv",
diff --git a/src/internal/buildcfg/exp.go b/src/internal/buildcfg/exp.go
index 689ca8ce58a6f2..4c30ff10458a78 100644
--- a/src/internal/buildcfg/exp.go
+++ b/src/internal/buildcfg/exp.go
@@ -84,6 +84,7 @@ func ParseGOEXPERIMENT(goos, goarch, goexp string) (*ExperimentFlags, error) {
 		AliasTypeParams: true,
 		SwissMap:        true,
 		SyncHashTrieMap: true,
+		SIMD:            goarch == "amd64", // TODO remove this (default to false) when dev.simd is merged
 		Dwarf5:          dwarf5Supported,
 	}
 
diff --git a/src/internal/cpu/cpu.go b/src/internal/cpu/cpu.go
index 760dc0b469d83d..1eeb580711439e 100644
--- a/src/internal/cpu/cpu.go
+++ b/src/internal/cpu/cpu.go
@@ -26,29 +26,34 @@ var CacheLineSize uintptr = CacheLinePadSize
 // in addition to the cpuid feature bit being set.
 // The struct is padded to avoid false sharing.
 var X86 struct {
-	_            CacheLinePad
-	HasAES       bool
-	HasADX       bool
-	HasAVX       bool
-	HasAVX2      bool
-	HasAVX512F   bool
-	HasAVX512BW  bool
-	HasAVX512VL  bool
-	HasBMI1      bool
-	HasBMI2      bool
-	HasERMS      bool
-	HasFSRM      bool
-	HasFMA       bool
-	HasOSXSAVE   bool
-	HasPCLMULQDQ bool
-	HasPOPCNT    bool
-	HasRDTSCP    bool
-	HasSHA       bool
-	HasSSE3      bool
-	HasSSSE3     bool
-	HasSSE41     bool
-	HasSSE42     bool
-	_            CacheLinePad
+	_             CacheLinePad
+	HasAES        bool
+	HasADX        bool
+	HasAVX        bool
+	HasAVX2       bool
+	HasAVX512GFNI bool // Virtual feature: F+CD+BW+DQ+VL+GFNI
+	HasAVX512     bool // Virtual feature: F+CD+BW+DQ+VL
+	HasAVX512F    bool
+	HasAVX512CD   bool
+	HasAVX512BW   bool
+	HasAVX512DQ   bool
+	HasAVX512VL   bool
+	HasBMI1       bool
+	HasBMI2       bool
+	HasERMS       bool
+	HasFSRM       bool
+	HasFMA        bool
+	HasGFNI       bool
+	HasOSXSAVE    bool
+	HasPCLMULQDQ  bool
+	HasPOPCNT     bool
+	HasRDTSCP     bool
+	HasSHA        bool
+	HasSSE3       bool
+	HasSSSE3      bool
+	HasSSE41      bool
+	HasSSE42      bool
+	_             CacheLinePad
 }
 
 // The booleans in ARM contain the correspondingly named cpu feature bit.
@@ -160,6 +165,10 @@ var RISCV64 struct {
 //go:linkname S390X
 //go:linkname RISCV64
 
+// doDerived, if non-nil, is called after processing GODEBUG to set "derived"
+// feature flags.
+var doDerived func()
+
 // Initialize examines the processor and sets the relevant variables above.
 // This is called by the runtime package early in program initialization,
 // before normal init functions are run. env is set by runtime if the OS supports
@@ -167,6 +176,9 @@ var RISCV64 struct {
 func Initialize(env string) {
 	doinit()
 	processOptions(env)
+	if doDerived != nil {
+		doDerived()
+	}
 }
 
 // options contains the cpu debug options that can be used in GODEBUG.
diff --git a/src/internal/cpu/cpu_x86.go b/src/internal/cpu/cpu_x86.go
index ee812076e96c49..152a08cdbfd11a 100644
--- a/src/internal/cpu/cpu_x86.go
+++ b/src/internal/cpu/cpu_x86.go
@@ -22,6 +22,7 @@ const (
 	cpuid_SSE3      = 1 << 0
 	cpuid_PCLMULQDQ = 1 << 1
 	cpuid_SSSE3     = 1 << 9
+	cpuid_GFNI      = 1 << 8
 	cpuid_FMA       = 1 << 12
 	cpuid_SSE41     = 1 << 19
 	cpuid_SSE42     = 1 << 20
@@ -36,7 +37,9 @@ const (
 	cpuid_BMI2     = 1 << 8
 	cpuid_ERMS     = 1 << 9
 	cpuid_AVX512F  = 1 << 16
+	cpuid_AVX512DQ = 1 << 17
 	cpuid_ADX      = 1 << 19
+	cpuid_AVX512CD = 1 << 28
 	cpuid_SHA      = 1 << 29
 	cpuid_AVX512BW = 1 << 30
 	cpuid_AVX512VL = 1 << 31
@@ -84,7 +87,9 @@ func doinit() {
 		// they can be turned off.
 		options = append(options,
 			option{Name: "avx512f", Feature: &X86.HasAVX512F},
+			option{Name: "avx512cd", Feature: &X86.HasAVX512CD},
 			option{Name: "avx512bw", Feature: &X86.HasAVX512BW},
+			option{Name: "avx512dq", Feature: &X86.HasAVX512DQ},
 			option{Name: "avx512vl", Feature: &X86.HasAVX512VL},
 		)
 	}
@@ -139,7 +144,7 @@ func doinit() {
 		return
 	}
 
-	_, ebx7, _, edx7 := cpuid(7, 0)
+	_, ebx7, ecx7, edx7 := cpuid(7, 0)
 	X86.HasBMI1 = isSet(ebx7, cpuid_BMI1)
 	X86.HasAVX2 = isSet(ebx7, cpuid_AVX2) && osSupportsAVX
 	X86.HasBMI2 = isSet(ebx7, cpuid_BMI2)
@@ -149,11 +154,14 @@ func doinit() {
 
 	X86.HasAVX512F = isSet(ebx7, cpuid_AVX512F) && osSupportsAVX512
 	if X86.HasAVX512F {
+		X86.HasAVX512CD = isSet(ebx7, cpuid_AVX512CD)
 		X86.HasAVX512BW = isSet(ebx7, cpuid_AVX512BW)
+		X86.HasAVX512DQ = isSet(ebx7, cpuid_AVX512DQ)
 		X86.HasAVX512VL = isSet(ebx7, cpuid_AVX512VL)
 	}
 
 	X86.HasFSRM = isSet(edx7, cpuid_FSRM)
+	X86.HasGFNI = isSet(ecx7, cpuid_GFNI)
 
 	var maxExtendedInformation uint32
 	maxExtendedInformation, _, _, _ = cpuid(0x80000000, 0)
@@ -164,6 +172,18 @@ func doinit() {
 
 	_, _, _, edxExt1 := cpuid(0x80000001, 0)
 	X86.HasRDTSCP = isSet(edxExt1, cpuid_RDTSCP)
+
+	doDerived = func() {
+		// Rather than carefully gating on fundamental AVX-512 features, we have
+		// a virtual "AVX512" feature that captures F+CD+BW+DQ+VL. BW, DQ, and
+		// VL have a huge effect on which AVX-512 instructions are available,
+		// and these have all been supported on everything except the earliest
+		// Phi chips with AVX-512. No CPU has had CD without F, so we include
+		// it. GOAMD64=v4 also implies exactly this set, and these are all
+		// included in AVX10.1.
+		X86.HasAVX512 = X86.HasAVX512F && X86.HasAVX512CD && X86.HasAVX512BW && X86.HasAVX512DQ && X86.HasAVX512VL
+		X86.HasAVX512GFNI = X86.HasAVX512 && X86.HasGFNI
+	}
 }
 
 func isSet(hwc uint32, value uint32) bool {
diff --git a/src/internal/goexperiment/exp_simd_off.go b/src/internal/goexperiment/exp_simd_off.go
new file mode 100644
index 00000000000000..ebc40b308e384d
--- /dev/null
+++ b/src/internal/goexperiment/exp_simd_off.go
@@ -0,0 +1,8 @@
+// Code generated by mkconsts.go. DO NOT EDIT.
+
+//go:build !goexperiment.simd
+
+package goexperiment
+
+const SIMD = false
+const SIMDInt = 0
diff --git a/src/internal/goexperiment/exp_simd_on.go b/src/internal/goexperiment/exp_simd_on.go
new file mode 100644
index 00000000000000..137d1dd1ba3fba
--- /dev/null
+++ b/src/internal/goexperiment/exp_simd_on.go
@@ -0,0 +1,8 @@
+// Code generated by mkconsts.go. DO NOT EDIT.
+
+//go:build goexperiment.simd
+
+package goexperiment
+
+const SIMD = true
+const SIMDInt = 1
diff --git a/src/internal/goexperiment/flags.go b/src/internal/goexperiment/flags.go
index 63a338883991e0..09349357a74e66 100644
--- a/src/internal/goexperiment/flags.go
+++ b/src/internal/goexperiment/flags.go
@@ -129,4 +129,8 @@ type Flags struct {
 
 	// GreenTeaGC enables the Green Tea GC implementation.
 	GreenTeaGC bool
+
+	// SIMD enables the simd package and the compiler's handling
+	// of SIMD intrinsics.
+	SIMD bool
 }
diff --git a/src/runtime/cpuflags.go b/src/runtime/cpuflags.go
index bd1cb328d37b87..6452364b68ec32 100644
--- a/src/runtime/cpuflags.go
+++ b/src/runtime/cpuflags.go
@@ -13,6 +13,7 @@ import (
 const (
 	offsetX86HasAVX    = unsafe.Offsetof(cpu.X86.HasAVX)
 	offsetX86HasAVX2   = unsafe.Offsetof(cpu.X86.HasAVX2)
+	offsetX86HasAVX512 = unsafe.Offsetof(cpu.X86.HasAVX512) // F+CD+BW+DQ+VL
 	offsetX86HasERMS   = unsafe.Offsetof(cpu.X86.HasERMS)
 	offsetX86HasRDTSCP = unsafe.Offsetof(cpu.X86.HasRDTSCP)
 
diff --git a/src/runtime/export_test.go b/src/runtime/export_test.go
index 9a4611e26e52a2..81542deb595b89 100644
--- a/src/runtime/export_test.go
+++ b/src/runtime/export_test.go
@@ -555,6 +555,8 @@ type G = g
 
 type Sudog = sudog
 
+type XRegPerG = xRegPerG
+
 func Getg() *G {
 	return getg()
 }
diff --git a/src/runtime/lockrank.go b/src/runtime/lockrank.go
index 44015ce862d077..9821e499989951 100644
--- a/src/runtime/lockrank.go
+++ b/src/runtime/lockrank.go
@@ -70,6 +70,7 @@ const (
 	lockRankHchanLeaf
 	// WB
 	lockRankWbufSpans
+	lockRankXRegAlloc
 	lockRankMheap
 	lockRankMheapSpecial
 	lockRankGlobalAlloc
@@ -143,6 +144,7 @@ var lockNames = []string{
 	lockRankStackLarge:          "stackLarge",
 	lockRankHchanLeaf:           "hchanLeaf",
 	lockRankWbufSpans:           "wbufSpans",
+	lockRankXRegAlloc:           "xRegAlloc",
 	lockRankMheap:               "mheap",
 	lockRankMheapSpecial:        "mheapSpecial",
 	lockRankGlobalAlloc:         "globalAlloc",
@@ -228,9 +230,10 @@ var lockPartialOrder [][]lockRank = [][]lockRank{
 	lockRankStackLarge:          {lockRankSysmon, lockRankScavenge, lockRankForcegc, lockRankComputeMaxProcs, lockRankUpdateMaxProcsG, lockRankSweepWaiters, lockRankAssistQueue, lockRankStrongFromWeakQueue, lockRankCleanupQueue, lockRankSweep, lockRankTestR, lockRankVgetrandom, lockRankTimerSend, lockRankExecW, lockRankCpuprof, lockRankPollDesc, lockRankWakeableSleep, lockRankHchan, lockRankAllocmR, lockRankExecR, lockRankSched, lockRankAllg, lockRankAllp, lockRankNotifyList, lockRankTimers, lockRankTimer, lockRankNetpollInit, lockRankRoot, lockRankItab, lockRankReflectOffs, lockRankSynctest, lockRankUserArenaState, lockRankTraceBuf, lockRankTraceStrings, lockRankFin, lockRankSpanSetSpine, lockRankMspanSpecial, lockRankGcBitsArenas, lockRankProfInsert, lockRankProfBlock, lockRankProfMemActive, lockRankProfMemFuture, lockRankGscan},
 	lockRankHchanLeaf:           {lockRankSysmon, lockRankScavenge, lockRankForcegc, lockRankComputeMaxProcs, lockRankUpdateMaxProcsG, lockRankSweepWaiters, lockRankAssistQueue, lockRankStrongFromWeakQueue, lockRankCleanupQueue, lockRankSweep, lockRankTestR, lockRankVgetrandom, lockRankTimerSend, lockRankExecW, lockRankCpuprof, lockRankPollDesc, lockRankWakeableSleep, lockRankHchan, lockRankAllocmR, lockRankExecR, lockRankSched, lockRankAllg, lockRankAllp, lockRankNotifyList, lockRankTimers, lockRankTimer, lockRankNetpollInit, lockRankRoot, lockRankItab, lockRankReflectOffs, lockRankSynctest, lockRankUserArenaState, lockRankTraceBuf, lockRankTraceStrings, lockRankFin, lockRankSpanSetSpine, lockRankMspanSpecial, lockRankGcBitsArenas, lockRankProfInsert, lockRankProfBlock, lockRankProfMemActive, lockRankProfMemFuture, lockRankGscan, lockRankHchanLeaf},
 	lockRankWbufSpans:           {lockRankSysmon, lockRankScavenge, lockRankForcegc, lockRankComputeMaxProcs, lockRankUpdateMaxProcsG, lockRankDefer, lockRankSweepWaiters, lockRankAssistQueue, lockRankStrongFromWeakQueue, lockRankCleanupQueue, lockRankSweep, lockRankTestR, lockRankVgetrandom, lockRankTimerSend, lockRankExecW, lockRankCpuprof, lockRankPollCache, lockRankPollDesc, lockRankWakeableSleep, lockRankHchan, lockRankAllocmR, lockRankExecR, lockRankSched, lockRankAllg, lockRankAllp, lockRankNotifyList, lockRankSudog, lockRankTimers, lockRankTimer, lockRankNetpollInit, lockRankRoot, lockRankItab, lockRankReflectOffs, lockRankSynctest, lockRankUserArenaState, lockRankTraceBuf, lockRankTraceStrings, lockRankFin, lockRankSpanSetSpine, lockRankMspanSpecial, lockRankGcBitsArenas, lockRankProfInsert, lockRankProfBlock, lockRankProfMemActive, lockRankProfMemFuture, lockRankGscan},
+	lockRankXRegAlloc:           {lockRankSysmon, lockRankScavenge, lockRankForcegc, lockRankComputeMaxProcs, lockRankUpdateMaxProcsG, lockRankSweepWaiters, lockRankAssistQueue, lockRankStrongFromWeakQueue, lockRankCleanupQueue, lockRankSweep, lockRankTestR, lockRankTimerSend, lockRankCpuprof, lockRankPollDesc, lockRankWakeableSleep, lockRankHchan, lockRankAllocmR, lockRankExecR, lockRankSched},
 	lockRankMheap:               {lockRankSysmon, lockRankScavenge, lockRankForcegc, lockRankComputeMaxProcs, lockRankUpdateMaxProcsG, lockRankDefer, lockRankSweepWaiters, lockRankAssistQueue, lockRankStrongFromWeakQueue, lockRankCleanupQueue, lockRankSweep, lockRankTestR, lockRankVgetrandom, lockRankTimerSend, lockRankExecW, lockRankCpuprof, lockRankPollCache, lockRankPollDesc, lockRankWakeableSleep, lockRankHchan, lockRankAllocmR, lockRankExecR, lockRankSched, lockRankAllg, lockRankAllp, lockRankNotifyList, lockRankSudog, lockRankTimers, lockRankTimer, lockRankNetpollInit, lockRankRoot, lockRankItab, lockRankReflectOffs, lockRankSynctest, lockRankUserArenaState, lockRankTraceBuf, lockRankTraceStrings, lockRankFin, lockRankSpanSetSpine, lockRankMspanSpecial, lockRankGcBitsArenas, lockRankProfInsert, lockRankProfBlock, lockRankProfMemActive, lockRankProfMemFuture, lockRankGscan, lockRankStackpool, lockRankStackLarge, lockRankWbufSpans},
 	lockRankMheapSpecial:        {lockRankSysmon, lockRankScavenge, lockRankForcegc, lockRankComputeMaxProcs, lockRankUpdateMaxProcsG, lockRankDefer, lockRankSweepWaiters, lockRankAssistQueue, lockRankStrongFromWeakQueue, lockRankCleanupQueue, lockRankSweep, lockRankTestR, lockRankVgetrandom, lockRankTimerSend, lockRankExecW, lockRankCpuprof, lockRankPollCache, lockRankPollDesc, lockRankWakeableSleep, lockRankHchan, lockRankAllocmR, lockRankExecR, lockRankSched, lockRankAllg, lockRankAllp, lockRankNotifyList, lockRankSudog, lockRankTimers, lockRankTimer, lockRankNetpollInit, lockRankRoot, lockRankItab, lockRankReflectOffs, lockRankSynctest, lockRankUserArenaState, lockRankTraceBuf, lockRankTraceStrings, lockRankFin, lockRankSpanSetSpine, lockRankMspanSpecial, lockRankGcBitsArenas, lockRankProfInsert, lockRankProfBlock, lockRankProfMemActive, lockRankProfMemFuture, lockRankGscan, lockRankStackpool, lockRankStackLarge, lockRankWbufSpans, lockRankMheap},
-	lockRankGlobalAlloc:         {lockRankSysmon, lockRankScavenge, lockRankForcegc, lockRankComputeMaxProcs, lockRankUpdateMaxProcsG, lockRankDefer, lockRankSweepWaiters, lockRankAssistQueue, lockRankStrongFromWeakQueue, lockRankCleanupQueue, lockRankSweep, lockRankTestR, lockRankVgetrandom, lockRankTimerSend, lockRankExecW, lockRankCpuprof, lockRankPollCache, lockRankPollDesc, lockRankWakeableSleep, lockRankHchan, lockRankAllocmR, lockRankExecR, lockRankSched, lockRankAllg, lockRankAllp, lockRankNotifyList, lockRankSudog, lockRankTimers, lockRankTimer, lockRankNetpollInit, lockRankRoot, lockRankItab, lockRankReflectOffs, lockRankSynctest, lockRankUserArenaState, lockRankTraceBuf, lockRankTraceStrings, lockRankFin, lockRankSpanSetSpine, lockRankMspanSpecial, lockRankGcBitsArenas, lockRankProfInsert, lockRankProfBlock, lockRankProfMemActive, lockRankProfMemFuture, lockRankGscan, lockRankStackpool, lockRankStackLarge, lockRankWbufSpans, lockRankMheap, lockRankMheapSpecial},
+	lockRankGlobalAlloc:         {lockRankSysmon, lockRankScavenge, lockRankForcegc, lockRankComputeMaxProcs, lockRankUpdateMaxProcsG, lockRankDefer, lockRankSweepWaiters, lockRankAssistQueue, lockRankStrongFromWeakQueue, lockRankCleanupQueue, lockRankSweep, lockRankTestR, lockRankVgetrandom, lockRankTimerSend, lockRankExecW, lockRankCpuprof, lockRankPollCache, lockRankPollDesc, lockRankWakeableSleep, lockRankHchan, lockRankAllocmR, lockRankExecR, lockRankSched, lockRankAllg, lockRankAllp, lockRankNotifyList, lockRankSudog, lockRankTimers, lockRankTimer, lockRankNetpollInit, lockRankRoot, lockRankItab, lockRankReflectOffs, lockRankSynctest, lockRankUserArenaState, lockRankTraceBuf, lockRankTraceStrings, lockRankFin, lockRankSpanSetSpine, lockRankMspanSpecial, lockRankGcBitsArenas, lockRankProfInsert, lockRankProfBlock, lockRankProfMemActive, lockRankProfMemFuture, lockRankGscan, lockRankStackpool, lockRankStackLarge, lockRankWbufSpans, lockRankXRegAlloc, lockRankMheap, lockRankMheapSpecial},
 	lockRankTrace:               {lockRankSysmon, lockRankScavenge, lockRankForcegc, lockRankComputeMaxProcs, lockRankUpdateMaxProcsG, lockRankDefer, lockRankSweepWaiters, lockRankAssistQueue, lockRankStrongFromWeakQueue, lockRankCleanupQueue, lockRankSweep, lockRankTestR, lockRankVgetrandom, lockRankTimerSend, lockRankExecW, lockRankCpuprof, lockRankPollCache, lockRankPollDesc, lockRankWakeableSleep, lockRankHchan, lockRankAllocmR, lockRankExecR, lockRankSched, lockRankAllg, lockRankAllp, lockRankNotifyList, lockRankSudog, lockRankTimers, lockRankTimer, lockRankNetpollInit, lockRankRoot, lockRankItab, lockRankReflectOffs, lockRankSynctest, lockRankUserArenaState, lockRankTraceBuf, lockRankTraceStrings, lockRankFin, lockRankSpanSetSpine, lockRankMspanSpecial, lockRankGcBitsArenas, lockRankProfInsert, lockRankProfBlock, lockRankProfMemActive, lockRankProfMemFuture, lockRankGscan, lockRankStackpool, lockRankStackLarge, lockRankWbufSpans, lockRankMheap},
 	lockRankTraceStackTab:       {lockRankSysmon, lockRankScavenge, lockRankForcegc, lockRankComputeMaxProcs, lockRankUpdateMaxProcsG, lockRankDefer, lockRankSweepWaiters, lockRankAssistQueue, lockRankStrongFromWeakQueue, lockRankCleanupQueue, lockRankSweep, lockRankTestR, lockRankVgetrandom, lockRankTimerSend, lockRankExecW, lockRankCpuprof, lockRankPollCache, lockRankPollDesc, lockRankWakeableSleep, lockRankHchan, lockRankAllocmR, lockRankExecR, lockRankSched, lockRankAllg, lockRankAllp, lockRankNotifyList, lockRankSudog, lockRankTimers, lockRankTimer, lockRankNetpollInit, lockRankRoot, lockRankItab, lockRankReflectOffs, lockRankSynctest, lockRankUserArenaState, lockRankTraceBuf, lockRankTraceStrings, lockRankFin, lockRankSpanSetSpine, lockRankMspanSpecial, lockRankGcBitsArenas, lockRankProfInsert, lockRankProfBlock, lockRankProfMemActive, lockRankProfMemFuture, lockRankGscan, lockRankStackpool, lockRankStackLarge, lockRankWbufSpans, lockRankMheap, lockRankTrace},
 	lockRankPanic:               {},
diff --git a/src/runtime/mheap.go b/src/runtime/mheap.go
index f25dbb429d7f78..358de2f376dd7f 100644
--- a/src/runtime/mheap.go
+++ b/src/runtime/mheap.go
@@ -821,6 +821,8 @@ func (h *mheap) init() {
 	}
 
 	h.pages.init(&h.lock, &memstats.gcMiscSys, false)
+
+	xRegInitAlloc()
 }
 
 // reclaim sweeps and reclaims at least npage pages into the heap.
diff --git a/src/runtime/mklockrank.go b/src/runtime/mklockrank.go
index 46a063fdce569c..9c503369a35841 100644
--- a/src/runtime/mklockrank.go
+++ b/src/runtime/mklockrank.go
@@ -193,6 +193,9 @@ defer,
 # Below WB is the write barrier implementation.
 < wbufSpans;
 
+# xRegState allocator
+sched < xRegAlloc;
+
 # Span allocator
 stackLarge,
   stackpool,
@@ -205,7 +208,8 @@ stackLarge,
 # an mspanSpecial lock, and they're part of the malloc implementation.
 # Pinner bits might be freed by the span allocator.
 mheap, mspanSpecial < mheapSpecial;
-mheap, mheapSpecial < globalAlloc;
+# Fixallocs
+mheap, mheapSpecial, xRegAlloc < globalAlloc;
 
 # Execution tracer events (with a P)
 hchan,
diff --git a/src/runtime/mkpreempt.go b/src/runtime/mkpreempt.go
index 6a9cf77a43fcf0..7786f342b501d0 100644
--- a/src/runtime/mkpreempt.go
+++ b/src/runtime/mkpreempt.go
@@ -9,8 +9,10 @@
 package main
 
 import (
+	"bytes"
 	"flag"
 	"fmt"
+	"go/format"
 	"io"
 	"log"
 	"os"
@@ -73,16 +75,14 @@ var regNamesAMD64 = []string{
 	"X15",
 }
 
-var out io.Writer
-
-var arches = map[string]func(){
+var arches = map[string]func(g *gen){
 	"386":     gen386,
 	"amd64":   genAMD64,
 	"arm":     genARM,
 	"arm64":   genARM64,
 	"loong64": genLoong64,
-	"mips64x": func() { genMIPS(true) },
-	"mipsx":   func() { genMIPS(false) },
+	"mips64x": func(g *gen) { genMIPS(g, true) },
+	"mipsx":   func(g *gen) { genMIPS(g, false) },
 	"ppc64x":  genPPC64,
 	"riscv64": genRISCV64,
 	"s390x":   genS390X,
@@ -93,53 +93,100 @@ var beLe = map[string]bool{"mips64x": true, "mipsx": true, "ppc64x": true}
 func main() {
 	flag.Parse()
 	if flag.NArg() > 0 {
-		out = os.Stdout
 		for _, arch := range flag.Args() {
-			gen, ok := arches[arch]
+			genFn, ok := arches[arch]
 			if !ok {
 				log.Fatalf("unknown arch %s", arch)
 			}
-			header(arch)
-			gen()
+			g := gen{os.Stdout, arch}
+			g.asmHeader()
+			genFn(&g)
 		}
 		return
 	}
 
-	for arch, gen := range arches {
+	for arch, genFn := range arches {
 		f, err := os.Create(fmt.Sprintf("preempt_%s.s", arch))
 		if err != nil {
 			log.Fatal(err)
 		}
-		out = f
-		header(arch)
-		gen()
+		g := gen{f, arch}
+		g.asmHeader()
+		genFn(&g)
 		if err := f.Close(); err != nil {
 			log.Fatal(err)
 		}
 	}
 }
 
-func header(arch string) {
-	fmt.Fprintf(out, "// Code generated by mkpreempt.go; DO NOT EDIT.\n\n")
-	if beLe[arch] {
-		base := arch[:len(arch)-1]
-		fmt.Fprintf(out, "//go:build %s || %sle\n\n", base, base)
+type gen struct {
+	w      io.Writer
+	goarch string
+}
+
+func (g *gen) commonHeader() {
+	fmt.Fprintf(g.w, "// Code generated by mkpreempt.go; DO NOT EDIT.\n\n")
+	if beLe[g.goarch] {
+		base := g.goarch[:len(g.goarch)-1]
+		fmt.Fprintf(g.w, "//go:build %s || %sle\n\n", base, base)
 	}
-	fmt.Fprintf(out, "#include \"go_asm.h\"\n")
-	if arch == "amd64" {
-		fmt.Fprintf(out, "#include \"asm_amd64.h\"\n")
+}
+
+func (g *gen) asmHeader() {
+	g.commonHeader()
+	fmt.Fprintf(g.w, "#include \"go_asm.h\"\n")
+	if g.goarch == "amd64" {
+		fmt.Fprintf(g.w, "#include \"go_tls.h\"\n")
+		fmt.Fprintf(g.w, "#include \"asm_amd64.h\"\n")
 	}
-	fmt.Fprintf(out, "#include \"textflag.h\"\n\n")
-	fmt.Fprintf(out, "TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0\n")
+	fmt.Fprintf(g.w, "#include \"textflag.h\"\n\n")
+	fmt.Fprintf(g.w, "TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0\n")
 }
 
-func p(f string, args ...any) {
+func (g *gen) p(f string, args ...any) {
 	fmted := fmt.Sprintf(f, args...)
-	fmt.Fprintf(out, "\t%s\n", strings.ReplaceAll(fmted, "\n", "\n\t"))
+	fmt.Fprintf(g.w, "\t%s\n", strings.ReplaceAll(fmted, "\n", "\n\t"))
 }
 
-func label(l string) {
-	fmt.Fprintf(out, "%s\n", l)
+func (g *gen) label(l string) {
+	fmt.Fprintf(g.w, "%s\n", l)
+}
+
+// writeXRegs writes an architecture xregs file.
+func writeXRegs(arch string, l *layout) {
+	var code bytes.Buffer
+	g := gen{&code, arch}
+	g.commonHeader()
+	fmt.Fprintf(g.w, `
+package runtime
+
+type xRegs struct {
+`)
+	pos := 0
+	for _, reg := range l.regs {
+		if reg.pos != pos {
+			log.Fatalf("padding not implemented")
+		}
+		typ := fmt.Sprintf("[%d]byte", reg.size)
+		switch {
+		case reg.size == 4 && reg.pos%4 == 0:
+			typ = "uint32"
+		case reg.size == 8 && reg.pos%8 == 0:
+			typ = "uint64"
+		}
+		fmt.Fprintf(g.w, "\t%s %s\n", reg.reg, typ)
+		pos += reg.size
+	}
+	fmt.Fprintf(g.w, "}\n")
+
+	path := fmt.Sprintf("preempt_%s.go", arch)
+	b, err := format.Source(code.Bytes())
+	if err != nil {
+		log.Fatalf("formatting %s: %s", path, err)
+	}
+	if err := os.WriteFile(path, b, 0666); err != nil {
+		log.Fatal(err)
+	}
 }
 
 type layout struct {
@@ -149,7 +196,7 @@ type layout struct {
 }
 
 type regPos struct {
-	pos int
+	pos, size int
 
 	saveOp    string
 	restoreOp string
@@ -162,42 +209,44 @@ type regPos struct {
 }
 
 func (l *layout) add(op, reg string, size int) {
-	l.regs = append(l.regs, regPos{saveOp: op, restoreOp: op, reg: reg, pos: l.stack})
+	l.regs = append(l.regs, regPos{saveOp: op, restoreOp: op, reg: reg, pos: l.stack, size: size})
 	l.stack += size
 }
 
 func (l *layout) add2(sop, rop, reg string, size int) {
-	l.regs = append(l.regs, regPos{saveOp: sop, restoreOp: rop, reg: reg, pos: l.stack})
+	l.regs = append(l.regs, regPos{saveOp: sop, restoreOp: rop, reg: reg, pos: l.stack, size: size})
 	l.stack += size
 }
 
 func (l *layout) addSpecial(save, restore string, size int) {
-	l.regs = append(l.regs, regPos{save: save, restore: restore, pos: l.stack})
+	l.regs = append(l.regs, regPos{save: save, restore: restore, pos: l.stack, size: size})
 	l.stack += size
 }
 
-func (l *layout) save() {
+func (l *layout) save(g *gen) {
 	for _, reg := range l.regs {
 		if reg.save != "" {
-			p(reg.save, reg.pos)
+			g.p(reg.save, reg.pos)
 		} else {
-			p("%s %s, %d(%s)", reg.saveOp, reg.reg, reg.pos, l.sp)
+			g.p("%s %s, %d(%s)", reg.saveOp, reg.reg, reg.pos, l.sp)
 		}
 	}
 }
 
-func (l *layout) restore() {
+func (l *layout) restore(g *gen) {
 	for i := len(l.regs) - 1; i >= 0; i-- {
 		reg := l.regs[i]
 		if reg.restore != "" {
-			p(reg.restore, reg.pos)
+			g.p(reg.restore, reg.pos)
 		} else {
-			p("%s %d(%s), %s", reg.restoreOp, reg.pos, l.sp, reg.reg)
+			g.p("%s %d(%s), %s", reg.restoreOp, reg.pos, l.sp, reg.reg)
 		}
 	}
 }
 
-func gen386() {
+func gen386(g *gen) {
+	p := g.p
+
 	p("PUSHFL")
 	// Save general purpose registers.
 	var l = layout{sp: "SP"}
@@ -218,22 +267,26 @@ func gen386() {
 
 	p("ADJSP $%d", lSSE.stack)
 	p("NOP SP")
-	l.save()
+	l.save(g)
 	p("#ifndef %s", softfloat)
-	lSSE.save()
+	lSSE.save(g)
 	p("#endif")
 	p("CALL ·asyncPreempt2(SB)")
 	p("#ifndef %s", softfloat)
-	lSSE.restore()
+	lSSE.restore(g)
 	p("#endif")
-	l.restore()
+	l.restore(g)
 	p("ADJSP $%d", -lSSE.stack)
 
 	p("POPFL")
 	p("RET")
 }
 
-func genAMD64() {
+func genAMD64(g *gen) {
+	const xReg = "AX" // *xRegState
+
+	p, label := g.p, g.label
+
 	// Assign stack offsets.
 	var l = layout{sp: "SP"}
 	for _, reg := range regNamesAMD64 {
@@ -244,37 +297,121 @@ func genAMD64() {
 			l.add("MOVQ", reg, 8)
 		}
 	}
-	lSSE := layout{stack: l.stack, sp: "SP"}
-	for _, reg := range regNamesAMD64 {
-		if strings.HasPrefix(reg, "X") {
-			lSSE.add("MOVUPS", reg, 16)
+	// Create layouts for X, Y, and Z registers.
+	const (
+		numXRegs = 16
+		numZRegs = 32
+		numKRegs = 8
+	)
+	lZRegs := layout{sp: xReg} // Non-GP registers
+	lXRegs, lYRegs := lZRegs, lZRegs
+	for i := range numZRegs {
+		lZRegs.add("VMOVDQU64", fmt.Sprintf("Z%d", i), 512/8)
+		if i < numXRegs {
+			// Use SSE-only instructions for X registers.
+			lXRegs.add("MOVUPS", fmt.Sprintf("X%d", i), 128/8)
+			lYRegs.add("VMOVDQU", fmt.Sprintf("Y%d", i), 256/8)
 		}
 	}
-
-	// TODO: MXCSR register?
+	for i := range numKRegs {
+		lZRegs.add("KMOVQ", fmt.Sprintf("K%d", i), 8)
+	}
+	// The Z layout is the most general, so we line up the others with that one.
+	// We don't have to do this, but it results in a nice Go type. If we split
+	// this into multiple types, we probably should stop doing this.
+	for i := range lXRegs.regs {
+		lXRegs.regs[i].pos = lZRegs.regs[i].pos
+		lYRegs.regs[i].pos = lZRegs.regs[i].pos
+	}
+	writeXRegs(g.goarch, &lZRegs)
 
 	p("PUSHQ BP")
 	p("MOVQ SP, BP")
 	p("// Save flags before clobbering them")
 	p("PUSHFQ")
 	p("// obj doesn't understand ADD/SUB on SP, but does understand ADJSP")
-	p("ADJSP $%d", lSSE.stack)
+	p("ADJSP $%d", l.stack)
 	p("// But vet doesn't know ADJSP, so suppress vet stack checking")
 	p("NOP SP")
 
-	l.save()
+	p("// Save GPs")
+	l.save(g)
+
+	// In general, the limitations on asynchronous preemption mean we only
+	// preempt in ABIInternal code. However, there's at least one exception to
+	// this: when we're in an open-coded transition between an ABIInternal
+	// function and an ABI0 call. We could more carefully arrange unsafe points
+	// to avoid ever landing in ABI0, but it's easy to just make this code not
+	// sensitive to the ABI we're preempting. The CALL to asyncPreempt2 will
+	// ensure we're in ABIInternal register state.
+	p("// Save extended register state to p.xRegs.scratch")
+	p("// Don't make assumptions about ABI register state. See mkpreempt.go")
+	p("get_tls(CX)")
+	p("MOVQ g(CX), R14")
+	p("MOVQ g_m(R14), %s", xReg)
+	p("MOVQ m_p(%s), %s", xReg, xReg)
+	p("LEAQ (p_xRegs+xRegPerP_scratch)(%s), %s", xReg, xReg)
+
+	// Which registers do we need to save?
+	p("#ifdef GOEXPERIMENT_simd")
+	p("CMPB internal∕cpu·X86+const_offsetX86HasAVX512(SB), $1")
+	p("JE saveAVX512")
+	p("CMPB internal∕cpu·X86+const_offsetX86HasAVX2(SB), $1")
+	p("JE saveAVX2")
+	p("#endif")
+
+	// No features. Assume only SSE.
+	label("saveSSE:")
+	lXRegs.save(g)
+	p("JMP preempt")
+
+	label("saveAVX2:")
+	lYRegs.save(g)
+	p("JMP preempt")
 
-	lSSE.save()
+	label("saveAVX512:")
+	lZRegs.save(g)
+	p("JMP preempt")
+
+	label("preempt:")
 	p("CALL ·asyncPreempt2(SB)")
-	lSSE.restore()
-	l.restore()
-	p("ADJSP $%d", -lSSE.stack)
+
+	p("// Restore non-GPs from *p.xRegs.cache")
+	p("MOVQ g_m(R14), %s", xReg)
+	p("MOVQ m_p(%s), %s", xReg, xReg)
+	p("MOVQ (p_xRegs+xRegPerP_cache)(%s), %s", xReg, xReg)
+
+	p("#ifdef GOEXPERIMENT_simd")
+	p("CMPB internal∕cpu·X86+const_offsetX86HasAVX512(SB), $1")
+	p("JE restoreAVX512")
+	p("CMPB internal∕cpu·X86+const_offsetX86HasAVX2(SB), $1")
+	p("JE restoreAVX2")
+	p("#endif")
+
+	label("restoreSSE:")
+	lXRegs.restore(g)
+	p("JMP restoreGPs")
+
+	label("restoreAVX2:")
+	lYRegs.restore(g)
+	p("JMP restoreGPs")
+
+	label("restoreAVX512:")
+	lZRegs.restore(g)
+	p("JMP restoreGPs")
+
+	label("restoreGPs:")
+	p("// Restore GPs")
+	l.restore(g)
+	p("ADJSP $%d", -l.stack)
 	p("POPFQ")
 	p("POPQ BP")
 	p("RET")
 }
 
-func genARM() {
+func genARM(g *gen) {
+	p := g.p
+
 	// Add integer registers R0-R12.
 	// R13 (SP), R14 (LR), R15 (PC) are special and not saved here.
 	var l = layout{sp: "R13", stack: 4} // add LR slot
@@ -303,22 +440,23 @@ func genARM() {
 	}
 
 	p("MOVW.W R14, -%d(R13)", lfp.stack) // allocate frame, save LR
-	l.save()
+	l.save(g)
 	p("MOVB ·goarmsoftfp(SB), R0\nCMP $0, R0\nBNE nofp") // test goarmsoftfp, and skip FP registers if goarmsoftfp!=0.
-	lfp.save()
-	label("nofp:")
+	lfp.save(g)
+	g.label("nofp:")
 	p("CALL ·asyncPreempt2(SB)")
 	p("MOVB ·goarmsoftfp(SB), R0\nCMP $0, R0\nBNE nofp2") // test goarmsoftfp, and skip FP registers if goarmsoftfp!=0.
-	lfp.restore()
-	label("nofp2:")
-	l.restore()
+	lfp.restore(g)
+	g.label("nofp2:")
+	l.restore(g)
 
 	p("MOVW %d(R13), R14", lfp.stack)     // sigctxt.pushCall pushes LR on stack, restore it
 	p("MOVW.P %d(R13), R15", lfp.stack+4) // load PC, pop frame (including the space pushed by sigctxt.pushCall)
 	p("UNDEF")                            // shouldn't get here
 }
 
-func genARM64() {
+func genARM64(g *gen) {
+	p := g.p
 	// Add integer registers R0-R26
 	// R27 (REGTMP), R28 (g), R29 (FP), R30 (LR), R31 (SP) are special
 	// and not saved here.
@@ -362,9 +500,9 @@ func genARM64() {
 	p("MOVD R30, (RSP)")
 	p("#endif")
 
-	l.save()
+	l.save(g)
 	p("CALL ·asyncPreempt2(SB)")
-	l.restore()
+	l.restore(g)
 
 	p("MOVD %d(RSP), R30", l.stack) // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
 	p("MOVD -8(RSP), R29")          // restore frame pointer
@@ -373,7 +511,9 @@ func genARM64() {
 	p("RET (R27)")
 }
 
-func genMIPS(_64bit bool) {
+func genMIPS(g *gen, _64bit bool) {
+	p := g.p
+
 	mov := "MOVW"
 	movf := "MOVF"
 	add := "ADD"
@@ -428,15 +568,15 @@ func genMIPS(_64bit bool) {
 	p(mov+" R31, -%d(R29)", lfp.stack)
 	p(sub+" $%d, R29", lfp.stack)
 
-	l.save()
+	l.save(g)
 	p("#ifndef %s", softfloat)
-	lfp.save()
+	lfp.save(g)
 	p("#endif")
 	p("CALL ·asyncPreempt2(SB)")
 	p("#ifndef %s", softfloat)
-	lfp.restore()
+	lfp.restore(g)
 	p("#endif")
-	l.restore()
+	l.restore(g)
 
 	p(mov+" %d(R29), R31", lfp.stack)     // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
 	p(mov + " (R29), R23")                // load PC to REGTMP
@@ -444,7 +584,9 @@ func genMIPS(_64bit bool) {
 	p("JMP (R23)")
 }
 
-func genLoong64() {
+func genLoong64(g *gen) {
+	p := g.p
+
 	mov := "MOVV"
 	movf := "MOVD"
 	add := "ADDV"
@@ -478,9 +620,9 @@ func genLoong64() {
 	p(mov+" R1, -%d(R3)", l.stack)
 	p(sub+" $%d, R3", l.stack)
 
-	l.save()
+	l.save(g)
 	p("CALL ·asyncPreempt2(SB)")
-	l.restore()
+	l.restore(g)
 
 	p(mov+" %d(R3), R1", l.stack)      // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
 	p(mov + " (R3), R30")              // load PC to REGTMP
@@ -488,7 +630,9 @@ func genLoong64() {
 	p("JMP (R30)")
 }
 
-func genPPC64() {
+func genPPC64(g *gen) {
+	p := g.p
+
 	// Add integer registers R3-R29
 	// R0 (zero), R1 (SP), R30 (g) are special and not saved here.
 	// R2 (TOC pointer in PIC mode), R12 (function entry address in PIC mode) have been saved in sigctxt.pushCall.
@@ -528,9 +672,9 @@ func genPPC64() {
 	p("MOVD LR, R31")
 	p("MOVDU R31, -%d(R1)", l.stack) // allocate frame, save PC of interrupted instruction (in LR)
 
-	l.save()
+	l.save(g)
 	p("CALL ·asyncPreempt2(SB)")
-	l.restore()
+	l.restore(g)
 
 	p("MOVD %d(R1), R31", l.stack) // sigctxt.pushCall has pushed LR, R2, R12 (at interrupt) on stack, restore them
 	p("MOVD R31, LR")
@@ -543,7 +687,9 @@ func genPPC64() {
 	p("JMP (CTR)")
 }
 
-func genRISCV64() {
+func genRISCV64(g *gen) {
+	p := g.p
+
 	// X0 (zero), X1 (LR), X2 (SP), X3 (GP), X4 (TP), X27 (g), X31 (TMP) are special.
 	var l = layout{sp: "X2", stack: 8}
 
@@ -564,16 +710,18 @@ func genRISCV64() {
 
 	p("MOV X1, -%d(X2)", l.stack)
 	p("SUB $%d, X2", l.stack)
-	l.save()
+	l.save(g)
 	p("CALL ·asyncPreempt2(SB)")
-	l.restore()
+	l.restore(g)
 	p("MOV %d(X2), X1", l.stack)
 	p("MOV (X2), X31")
 	p("ADD $%d, X2", l.stack+8)
 	p("JMP (X31)")
 }
 
-func genS390X() {
+func genS390X(g *gen) {
+	p := g.p
+
 	// Add integer registers R0-R12
 	// R13 (g), R14 (LR), R15 (SP) are special, and not saved here.
 	// Saving R10 (REGTMP) is not necessary, but it is saved anyway.
@@ -594,9 +742,9 @@ func genS390X() {
 	p("ADD $-%d, R15", l.stack)
 	p("MOVW R10, 8(R15)") // save flags
 
-	l.save()
+	l.save(g)
 	p("CALL ·asyncPreempt2(SB)")
-	l.restore()
+	l.restore(g)
 
 	p("MOVD %d(R15), R14", l.stack)    // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
 	p("ADD $%d, R15", l.stack+8)       // pop frame (including the space pushed by sigctxt.pushCall)
@@ -606,12 +754,14 @@ func genS390X() {
 	p("JMP (R10)")
 }
 
-func genWasm() {
+func genWasm(g *gen) {
+	p := g.p
 	p("// No async preemption on wasm")
 	p("UNDEF")
 }
 
-func notImplemented() {
+func notImplemented(g *gen) {
+	p := g.p
 	p("// Not implemented yet")
 	p("JMP ·abort(SB)")
 }
diff --git a/src/runtime/preempt.go b/src/runtime/preempt.go
index c41c3558359c0c..22727df74eead2 100644
--- a/src/runtime/preempt.go
+++ b/src/runtime/preempt.go
@@ -292,21 +292,52 @@ func canPreemptM(mp *m) bool {
 
 // asyncPreempt saves all user registers and calls asyncPreempt2.
 //
-// When stack scanning encounters an asyncPreempt frame, it scans that
+// It saves GP registers (anything that might contain a pointer) to the G stack.
+// Hence, when stack scanning encounters an asyncPreempt frame, it scans that
 // frame and its parent frame conservatively.
 //
+// On some platforms, it saves large additional scalar-only register state such
+// as vector registers to an "extended register state" on the P.
+//
 // asyncPreempt is implemented in assembly.
 func asyncPreempt()
 
+// asyncPreempt2 is the Go continuation of asyncPreempt.
+//
+// It must be deeply nosplit because there's untyped data on the stack from
+// asyncPreempt.
+//
+// It must not have any write barriers because we need to limit the amount of
+// stack it uses.
+//
 //go:nosplit
+//go:nowritebarrierrec
 func asyncPreempt2() {
+	// We can't grow the stack with untyped data from asyncPreempt, so switch to
+	// the system stack right away.
+	mcall(func(gp *g) {
+		gp.asyncSafePoint = true
+
+		// Move the extended register state from the P to the G. We do this now that
+		// we're on the system stack to avoid stack splits.
+		xRegSave(gp)
+
+		if gp.preemptStop {
+			preemptPark(gp)
+		} else {
+			gopreempt_m(gp)
+		}
+		// The above functions never return.
+	})
+
+	// Do not grow the stack below here!
+
 	gp := getg()
-	gp.asyncSafePoint = true
-	if gp.preemptStop {
-		mcall(preemptPark)
-	} else {
-		mcall(gopreempt_m)
-	}
+
+	// Put the extended register state back on the M so resumption can find it.
+	// We can't do this in asyncPreemptM because the park calls never return.
+	xRegRestore(gp)
+
 	gp.asyncSafePoint = false
 }
 
@@ -319,19 +350,13 @@ func init() {
 	total := funcMaxSPDelta(f)
 	f = findfunc(abi.FuncPCABIInternal(asyncPreempt2))
 	total += funcMaxSPDelta(f)
+	f = findfunc(abi.FuncPCABIInternal(xRegRestore))
+	total += funcMaxSPDelta(f)
 	// Add some overhead for return PCs, etc.
 	asyncPreemptStack = uintptr(total) + 8*goarch.PtrSize
 	if asyncPreemptStack > stackNosplit {
-		// We need more than the nosplit limit. This isn't
-		// unsafe, but it may limit asynchronous preemption.
-		//
-		// This may be a problem if we start using more
-		// registers. In that case, we should store registers
-		// in a context object. If we pre-allocate one per P,
-		// asyncPreempt can spill just a few registers to the
-		// stack, then grab its context object and spill into
-		// it. When it enters the runtime, it would allocate a
-		// new context for the P.
+		// We need more than the nosplit limit. This isn't unsafe, but it may
+		// limit asynchronous preemption. Consider moving state into xRegState.
 		print("runtime: asyncPreemptStack=", asyncPreemptStack, "\n")
 		throw("async stack too large")
 	}
diff --git a/src/runtime/preempt_amd64.go b/src/runtime/preempt_amd64.go
new file mode 100644
index 00000000000000..78dec40e1f1e94
--- /dev/null
+++ b/src/runtime/preempt_amd64.go
@@ -0,0 +1,46 @@
+// Code generated by mkpreempt.go; DO NOT EDIT.
+
+package runtime
+
+type xRegs struct {
+	Z0  [64]byte
+	Z1  [64]byte
+	Z2  [64]byte
+	Z3  [64]byte
+	Z4  [64]byte
+	Z5  [64]byte
+	Z6  [64]byte
+	Z7  [64]byte
+	Z8  [64]byte
+	Z9  [64]byte
+	Z10 [64]byte
+	Z11 [64]byte
+	Z12 [64]byte
+	Z13 [64]byte
+	Z14 [64]byte
+	Z15 [64]byte
+	Z16 [64]byte
+	Z17 [64]byte
+	Z18 [64]byte
+	Z19 [64]byte
+	Z20 [64]byte
+	Z21 [64]byte
+	Z22 [64]byte
+	Z23 [64]byte
+	Z24 [64]byte
+	Z25 [64]byte
+	Z26 [64]byte
+	Z27 [64]byte
+	Z28 [64]byte
+	Z29 [64]byte
+	Z30 [64]byte
+	Z31 [64]byte
+	K0  uint64
+	K1  uint64
+	K2  uint64
+	K3  uint64
+	K4  uint64
+	K5  uint64
+	K6  uint64
+	K7  uint64
+}
diff --git a/src/runtime/preempt_amd64.s b/src/runtime/preempt_amd64.s
index 8e3ed0d7c59dce..a5b949a242cf19 100644
--- a/src/runtime/preempt_amd64.s
+++ b/src/runtime/preempt_amd64.s
@@ -1,6 +1,7 @@
 // Code generated by mkpreempt.go; DO NOT EDIT.
 
 #include "go_asm.h"
+#include "go_tls.h"
 #include "asm_amd64.h"
 #include "textflag.h"
 
@@ -10,9 +11,10 @@ TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0
 	// Save flags before clobbering them
 	PUSHFQ
 	// obj doesn't understand ADD/SUB on SP, but does understand ADJSP
-	ADJSP $368
+	ADJSP $112
 	// But vet doesn't know ADJSP, so suppress vet stack checking
 	NOP SP
+	// Save GPs
 	MOVQ AX, 0(SP)
 	MOVQ CX, 8(SP)
 	MOVQ DX, 16(SP)
@@ -27,39 +29,189 @@ TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0
 	MOVQ R13, 88(SP)
 	MOVQ R14, 96(SP)
 	MOVQ R15, 104(SP)
-	MOVUPS X0, 112(SP)
-	MOVUPS X1, 128(SP)
-	MOVUPS X2, 144(SP)
-	MOVUPS X3, 160(SP)
-	MOVUPS X4, 176(SP)
-	MOVUPS X5, 192(SP)
-	MOVUPS X6, 208(SP)
-	MOVUPS X7, 224(SP)
-	MOVUPS X8, 240(SP)
-	MOVUPS X9, 256(SP)
-	MOVUPS X10, 272(SP)
-	MOVUPS X11, 288(SP)
-	MOVUPS X12, 304(SP)
-	MOVUPS X13, 320(SP)
-	MOVUPS X14, 336(SP)
-	MOVUPS X15, 352(SP)
+	// Save extended register state to p.xRegs.scratch
+	// Don't make assumptions about ABI register state. See mkpreempt.go
+	get_tls(CX)
+	MOVQ g(CX), R14
+	MOVQ g_m(R14), AX
+	MOVQ m_p(AX), AX
+	LEAQ (p_xRegs+xRegPerP_scratch)(AX), AX
+	#ifdef GOEXPERIMENT_simd
+	CMPB internal∕cpu·X86+const_offsetX86HasAVX512(SB), $1
+	JE saveAVX512
+	CMPB internal∕cpu·X86+const_offsetX86HasAVX2(SB), $1
+	JE saveAVX2
+	#endif
+saveSSE:
+	MOVUPS X0, 0(AX)
+	MOVUPS X1, 64(AX)
+	MOVUPS X2, 128(AX)
+	MOVUPS X3, 192(AX)
+	MOVUPS X4, 256(AX)
+	MOVUPS X5, 320(AX)
+	MOVUPS X6, 384(AX)
+	MOVUPS X7, 448(AX)
+	MOVUPS X8, 512(AX)
+	MOVUPS X9, 576(AX)
+	MOVUPS X10, 640(AX)
+	MOVUPS X11, 704(AX)
+	MOVUPS X12, 768(AX)
+	MOVUPS X13, 832(AX)
+	MOVUPS X14, 896(AX)
+	MOVUPS X15, 960(AX)
+	JMP preempt
+saveAVX2:
+	VMOVDQU Y0, 0(AX)
+	VMOVDQU Y1, 64(AX)
+	VMOVDQU Y2, 128(AX)
+	VMOVDQU Y3, 192(AX)
+	VMOVDQU Y4, 256(AX)
+	VMOVDQU Y5, 320(AX)
+	VMOVDQU Y6, 384(AX)
+	VMOVDQU Y7, 448(AX)
+	VMOVDQU Y8, 512(AX)
+	VMOVDQU Y9, 576(AX)
+	VMOVDQU Y10, 640(AX)
+	VMOVDQU Y11, 704(AX)
+	VMOVDQU Y12, 768(AX)
+	VMOVDQU Y13, 832(AX)
+	VMOVDQU Y14, 896(AX)
+	VMOVDQU Y15, 960(AX)
+	JMP preempt
+saveAVX512:
+	VMOVDQU64 Z0, 0(AX)
+	VMOVDQU64 Z1, 64(AX)
+	VMOVDQU64 Z2, 128(AX)
+	VMOVDQU64 Z3, 192(AX)
+	VMOVDQU64 Z4, 256(AX)
+	VMOVDQU64 Z5, 320(AX)
+	VMOVDQU64 Z6, 384(AX)
+	VMOVDQU64 Z7, 448(AX)
+	VMOVDQU64 Z8, 512(AX)
+	VMOVDQU64 Z9, 576(AX)
+	VMOVDQU64 Z10, 640(AX)
+	VMOVDQU64 Z11, 704(AX)
+	VMOVDQU64 Z12, 768(AX)
+	VMOVDQU64 Z13, 832(AX)
+	VMOVDQU64 Z14, 896(AX)
+	VMOVDQU64 Z15, 960(AX)
+	VMOVDQU64 Z16, 1024(AX)
+	VMOVDQU64 Z17, 1088(AX)
+	VMOVDQU64 Z18, 1152(AX)
+	VMOVDQU64 Z19, 1216(AX)
+	VMOVDQU64 Z20, 1280(AX)
+	VMOVDQU64 Z21, 1344(AX)
+	VMOVDQU64 Z22, 1408(AX)
+	VMOVDQU64 Z23, 1472(AX)
+	VMOVDQU64 Z24, 1536(AX)
+	VMOVDQU64 Z25, 1600(AX)
+	VMOVDQU64 Z26, 1664(AX)
+	VMOVDQU64 Z27, 1728(AX)
+	VMOVDQU64 Z28, 1792(AX)
+	VMOVDQU64 Z29, 1856(AX)
+	VMOVDQU64 Z30, 1920(AX)
+	VMOVDQU64 Z31, 1984(AX)
+	KMOVQ K0, 2048(AX)
+	KMOVQ K1, 2056(AX)
+	KMOVQ K2, 2064(AX)
+	KMOVQ K3, 2072(AX)
+	KMOVQ K4, 2080(AX)
+	KMOVQ K5, 2088(AX)
+	KMOVQ K6, 2096(AX)
+	KMOVQ K7, 2104(AX)
+	JMP preempt
+preempt:
 	CALL ·asyncPreempt2(SB)
-	MOVUPS 352(SP), X15
-	MOVUPS 336(SP), X14
-	MOVUPS 320(SP), X13
-	MOVUPS 304(SP), X12
-	MOVUPS 288(SP), X11
-	MOVUPS 272(SP), X10
-	MOVUPS 256(SP), X9
-	MOVUPS 240(SP), X8
-	MOVUPS 224(SP), X7
-	MOVUPS 208(SP), X6
-	MOVUPS 192(SP), X5
-	MOVUPS 176(SP), X4
-	MOVUPS 160(SP), X3
-	MOVUPS 144(SP), X2
-	MOVUPS 128(SP), X1
-	MOVUPS 112(SP), X0
+	// Restore non-GPs from *p.xRegs.cache
+	MOVQ g_m(R14), AX
+	MOVQ m_p(AX), AX
+	MOVQ (p_xRegs+xRegPerP_cache)(AX), AX
+	#ifdef GOEXPERIMENT_simd
+	CMPB internal∕cpu·X86+const_offsetX86HasAVX512(SB), $1
+	JE restoreAVX512
+	CMPB internal∕cpu·X86+const_offsetX86HasAVX2(SB), $1
+	JE restoreAVX2
+	#endif
+restoreSSE:
+	MOVUPS 960(AX), X15
+	MOVUPS 896(AX), X14
+	MOVUPS 832(AX), X13
+	MOVUPS 768(AX), X12
+	MOVUPS 704(AX), X11
+	MOVUPS 640(AX), X10
+	MOVUPS 576(AX), X9
+	MOVUPS 512(AX), X8
+	MOVUPS 448(AX), X7
+	MOVUPS 384(AX), X6
+	MOVUPS 320(AX), X5
+	MOVUPS 256(AX), X4
+	MOVUPS 192(AX), X3
+	MOVUPS 128(AX), X2
+	MOVUPS 64(AX), X1
+	MOVUPS 0(AX), X0
+	JMP restoreGPs
+restoreAVX2:
+	VMOVDQU 960(AX), Y15
+	VMOVDQU 896(AX), Y14
+	VMOVDQU 832(AX), Y13
+	VMOVDQU 768(AX), Y12
+	VMOVDQU 704(AX), Y11
+	VMOVDQU 640(AX), Y10
+	VMOVDQU 576(AX), Y9
+	VMOVDQU 512(AX), Y8
+	VMOVDQU 448(AX), Y7
+	VMOVDQU 384(AX), Y6
+	VMOVDQU 320(AX), Y5
+	VMOVDQU 256(AX), Y4
+	VMOVDQU 192(AX), Y3
+	VMOVDQU 128(AX), Y2
+	VMOVDQU 64(AX), Y1
+	VMOVDQU 0(AX), Y0
+	JMP restoreGPs
+restoreAVX512:
+	KMOVQ 2104(AX), K7
+	KMOVQ 2096(AX), K6
+	KMOVQ 2088(AX), K5
+	KMOVQ 2080(AX), K4
+	KMOVQ 2072(AX), K3
+	KMOVQ 2064(AX), K2
+	KMOVQ 2056(AX), K1
+	KMOVQ 2048(AX), K0
+	VMOVDQU64 1984(AX), Z31
+	VMOVDQU64 1920(AX), Z30
+	VMOVDQU64 1856(AX), Z29
+	VMOVDQU64 1792(AX), Z28
+	VMOVDQU64 1728(AX), Z27
+	VMOVDQU64 1664(AX), Z26
+	VMOVDQU64 1600(AX), Z25
+	VMOVDQU64 1536(AX), Z24
+	VMOVDQU64 1472(AX), Z23
+	VMOVDQU64 1408(AX), Z22
+	VMOVDQU64 1344(AX), Z21
+	VMOVDQU64 1280(AX), Z20
+	VMOVDQU64 1216(AX), Z19
+	VMOVDQU64 1152(AX), Z18
+	VMOVDQU64 1088(AX), Z17
+	VMOVDQU64 1024(AX), Z16
+	VMOVDQU64 960(AX), Z15
+	VMOVDQU64 896(AX), Z14
+	VMOVDQU64 832(AX), Z13
+	VMOVDQU64 768(AX), Z12
+	VMOVDQU64 704(AX), Z11
+	VMOVDQU64 640(AX), Z10
+	VMOVDQU64 576(AX), Z9
+	VMOVDQU64 512(AX), Z8
+	VMOVDQU64 448(AX), Z7
+	VMOVDQU64 384(AX), Z6
+	VMOVDQU64 320(AX), Z5
+	VMOVDQU64 256(AX), Z4
+	VMOVDQU64 192(AX), Z3
+	VMOVDQU64 128(AX), Z2
+	VMOVDQU64 64(AX), Z1
+	VMOVDQU64 0(AX), Z0
+	JMP restoreGPs
+restoreGPs:
+	// Restore GPs
 	MOVQ 104(SP), R15
 	MOVQ 96(SP), R14
 	MOVQ 88(SP), R13
@@ -74,7 +226,7 @@ TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0
 	MOVQ 16(SP), DX
 	MOVQ 8(SP), CX
 	MOVQ 0(SP), AX
-	ADJSP $-368
+	ADJSP $-112
 	POPFQ
 	POPQ BP
 	RET
diff --git a/src/runtime/preempt_noxreg.go b/src/runtime/preempt_noxreg.go
new file mode 100644
index 00000000000000..dfe46559b5b723
--- /dev/null
+++ b/src/runtime/preempt_noxreg.go
@@ -0,0 +1,27 @@
+// Copyright 2025 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+//go:build !amd64
+
+// This provides common support for architectures that DO NOT use extended
+// register state in asynchronous preemption.
+
+package runtime
+
+type xRegPerG struct{}
+
+type xRegPerP struct{}
+
+// xRegState is defined only so the build fails if we try to define a real
+// xRegState on a noxreg architecture.
+type xRegState struct{}
+
+func xRegInitAlloc() {}
+
+func xRegSave(gp *g) {}
+
+//go:nosplit
+func xRegRestore(gp *g) {}
+
+func (*xRegPerP) free() {}
diff --git a/src/runtime/preempt_xreg.go b/src/runtime/preempt_xreg.go
new file mode 100644
index 00000000000000..9e05455ddbb747
--- /dev/null
+++ b/src/runtime/preempt_xreg.go
@@ -0,0 +1,137 @@
+// Copyright 2025 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+//go:build amd64
+
+// This provides common support for architectures that use extended register
+// state in asynchronous preemption.
+//
+// While asynchronous preemption stores general-purpose (GP) registers on the
+// preempted goroutine's own stack, extended register state can be used to save
+// non-GP state off the stack. In particular, this is meant for large vector
+// register files. Currently, we assume this contains only scalar data, though
+// we could change this constraint by conservatively scanning this memory.
+//
+// For an architecture to support extended register state, it must provide a Go
+// definition of an xRegState type for storing the state, and its asyncPreempt
+// implementation must write this register state to p.xRegs.scratch.
+
+package runtime
+
+import (
+	"internal/runtime/sys"
+	"unsafe"
+)
+
+// xRegState is long-lived extended register state. It is allocated off-heap and
+// manually managed.
+type xRegState struct {
+	_    sys.NotInHeap // Allocated from xRegAlloc
+	regs xRegs
+}
+
+// xRegPerG stores extended register state while a goroutine is asynchronously
+// preempted. This is nil otherwise, so we can reuse a (likely small) pool of
+// xRegState objects.
+type xRegPerG struct {
+	state *xRegState
+}
+
+type xRegPerP struct {
+	// scratch temporary per-P space where [asyncPreempt] saves the register
+	// state before entering Go. It's quickly copied to per-G state.
+	scratch xRegs
+
+	// cache is a 1-element allocation cache of extended register state used by
+	// asynchronous preemption. On entry to preemption, this is used as a simple
+	// allocation cache. On exit from preemption, the G's xRegState is always
+	// stored here where it can be restored, and later either freed or reused
+	// for another preemption. On exit, this serves the dual purpose of
+	// delay-freeing the allocated xRegState until after we've definitely
+	// restored it.
+	cache *xRegState
+}
+
+// xRegAlloc allocates xRegState objects.
+var xRegAlloc struct {
+	lock  mutex
+	alloc fixalloc
+}
+
+func xRegInitAlloc() {
+	lockInit(&xRegAlloc.lock, lockRankXRegAlloc)
+	xRegAlloc.alloc.init(unsafe.Sizeof(xRegState{}), nil, nil, &memstats.other_sys)
+}
+
+// xRegSave saves the extended register state on this P to gp.
+//
+// This must run on the system stack because it assumes the P won't change.
+//
+//go:systemstack
+func xRegSave(gp *g) {
+	if gp.xRegs.state != nil {
+		// Double preempt?
+		throw("gp.xRegState.p != nil on async preempt")
+	}
+
+	// Get the place to save the register state.
+	var dest *xRegState
+	pp := gp.m.p.ptr()
+	if pp.xRegs.cache != nil {
+		// Use the cached allocation.
+		dest = pp.xRegs.cache
+		pp.xRegs.cache = nil
+	} else {
+		// Allocate a new save block.
+		lock(&xRegAlloc.lock)
+		dest = (*xRegState)(xRegAlloc.alloc.alloc())
+		unlock(&xRegAlloc.lock)
+	}
+
+	// Copy state saved in the scratchpad to dest.
+	//
+	// If we ever need to save less state (e.g., avoid saving vector registers
+	// that aren't in use), we could have multiple allocation pools for
+	// different size states and copy only the registers we need.
+	dest.regs = pp.xRegs.scratch
+
+	// Save on the G.
+	gp.xRegs.state = dest
+}
+
+// xRegRestore prepares the extended register state on gp to be restored.
+//
+// It moves the state to gp.m.p.xRegs.cache where [asyncPreempt] expects to find
+// it. This means nothing else may use the cache between this call and the
+// return to asyncPreempt. This is not quite symmetric with [xRegSave], which
+// uses gp.m.p.xRegs.scratch. By using cache instead, we save a block copy.
+//
+// This is called with asyncPreempt on the stack and thus must not grow the
+// stack.
+//
+//go:nosplit
+func xRegRestore(gp *g) {
+	if gp.xRegs.state == nil {
+		throw("gp.xRegState.p == nil on return from async preempt")
+	}
+	// If the P has a block cached on it, free that so we can replace it.
+	pp := gp.m.p.ptr()
+	if pp.xRegs.cache != nil {
+		// Don't grow the G stack.
+		systemstack(func() {
+			pp.xRegs.free()
+		})
+	}
+	pp.xRegs.cache = gp.xRegs.state
+	gp.xRegs.state = nil
+}
+
+func (xRegs *xRegPerP) free() {
+	if xRegs.cache != nil {
+		lock(&xRegAlloc.lock)
+		xRegAlloc.alloc.free(unsafe.Pointer(xRegs.cache))
+		xRegs.cache = nil
+		unlock(&xRegAlloc.lock)
+	}
+}
diff --git a/src/runtime/proc.go b/src/runtime/proc.go
index b41bbe93cf57c7..bee3b26c0e3d36 100644
--- a/src/runtime/proc.go
+++ b/src/runtime/proc.go
@@ -5838,6 +5838,7 @@ func (pp *p) destroy() {
 	pp.gcAssistTime = 0
 	gcCleanups.queued += pp.cleanupsQueued
 	pp.cleanupsQueued = 0
+	pp.xRegs.free()
 	pp.status = _Pdead
 }
 
diff --git a/src/runtime/runtime2.go b/src/runtime/runtime2.go
index 527611f96a29d9..1e2de52989f928 100644
--- a/src/runtime/runtime2.go
+++ b/src/runtime/runtime2.go
@@ -492,6 +492,10 @@ type g struct {
 	coroarg *coro // argument during coroutine transfers
 	bubble  *synctestBubble
 
+	// xRegs stores the extended register state if this G has been
+	// asynchronously preempted.
+	xRegs xRegPerG
+
 	// Per-G tracer state.
 	trace gTraceState
 
@@ -762,6 +766,11 @@ type p struct {
 	// gcStopTime is the nanotime timestamp that this P last entered _Pgcstop.
 	gcStopTime int64
 
+	// xRegs is the per-P extended register state used by asynchronous
+	// preemption. This is an empty struct on platforms that don't use extended
+	// register state.
+	xRegs xRegPerP
+
 	// Padding is no longer needed. False sharing is now not a worry because p is large enough
 	// that its size class is an integer multiple of the cache line size (for any of our architectures).
 }
diff --git a/src/runtime/sizeof_test.go b/src/runtime/sizeof_test.go
index a5dc8aed3443bc..de859866a5adb2 100644
--- a/src/runtime/sizeof_test.go
+++ b/src/runtime/sizeof_test.go
@@ -15,13 +15,18 @@ import (
 
 func TestSizeof(t *testing.T) {
 	const _64bit = unsafe.Sizeof(uintptr(0)) == 8
+	const xreg = unsafe.Sizeof(runtime.XRegPerG{}) // Varies per architecture
 	var tests = []struct {
 		val    any     // type as a value
 		_32bit uintptr // size on 32bit platforms
 		_64bit uintptr // size on 64bit platforms
 	}{
-		{runtime.G{}, 280, 440},   // g, but exported for testing
-		{runtime.Sudog{}, 56, 88}, // sudog, but exported for testing
+		{runtime.G{}, 280 + xreg, 440 + xreg}, // g, but exported for testing
+		{runtime.Sudog{}, 56, 88},             // sudog, but exported for testing
+	}
+
+	if xreg > runtime.PtrSize {
+		t.Errorf("unsafe.Sizeof(xRegPerG) = %d, want <= %d", xreg, runtime.PtrSize)
 	}
 
 	for _, tt := range tests {
diff --git a/src/simd/cpu.go b/src/simd/cpu.go
new file mode 100644
index 00000000000000..5ff47b8873488d
--- /dev/null
+++ b/src/simd/cpu.go
@@ -0,0 +1,22 @@
+// Copyright 2025 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+//go:build goexperiment.simd
+
+// The build condition == if the experiment is not on, cmd/api TestCheck will see this and complain
+// see also go/doc/comment, where "simd" is inserted to the package list of the experiment is not on.
+
+package simd
+
+import "internal/cpu"
+
+// HasAVX512GFNI checks AVX512 CPU feature F+CD+BW+DQ+VL+GFNI.
+func HasAVX512GFNI() bool {
+	return cpu.X86.HasAVX512GFNI
+}
+
+// HasAVX512 checks AVX512 CPU feature F+CD+BW+DQ+VL.
+func HasAVX512() bool {
+	return cpu.X86.HasAVX512
+}
diff --git a/src/simd/dummy.s b/src/simd/dummy.s
new file mode 100644
index 00000000000000..f78313afee7f7f
--- /dev/null
+++ b/src/simd/dummy.s
@@ -0,0 +1,7 @@
+// Copyright 2025 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+//go:build amd64
+
+// Empty file to allow bodyless functions.
diff --git a/src/simd/genslice.go b/src/simd/genslice.go
new file mode 100644
index 00000000000000..77b9b41c09754e
--- /dev/null
+++ b/src/simd/genslice.go
@@ -0,0 +1,117 @@
+// Copyright 2025 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+//go:build ignore
+
+package main
+
+// this generates all the code to load and store simd
+// vectors to/from slices.
+
+import (
+	"bytes"
+	"flag"
+	"fmt"
+	"go/format"
+	"io"
+	"os"
+	"strings"
+)
+
+// //go:noescape
+// func LoadUint8x16Slice(s []uint8) Uint8x16 {
+// 	return LoadUint8x16((*[16]uint8)(s[:16]))
+// }
+
+// //go:noescape
+// func (x Uint8x16) StoreSlice(s []uint8) {
+//    x.Store((*[16]uint8)(s[:16]))
+// }
+
+func slice(e string, w, c int, out io.Writer) {
+	b := w * c
+	if b < 128 || b > 512 {
+		return
+	}
+	E := strings.ToUpper(e[:1]) + e[1:]
+	t := fmt.Sprintf("%s%d", e, w)
+	v := fmt.Sprintf("%s%dx%d", E, w, c)
+	a := "a"
+	if strings.Contains("aeiou", e[:1]) {
+		a = "an"
+	}
+	fmt.Fprintf(out,
+		`
+// Load%sSlice loads %s %s from a slice of at least %d %ss
+func Load%sSlice(s []%s) %s {
+	return Load%s((*[%d]%s)(s))
+}
+`, v, a, v, c, t, v, t, v, v, c, t)
+
+	fmt.Fprintf(out,
+		`
+// StoreSlice stores x into a slice of at least %d %ss
+func (x %s) StoreSlice(s []%s) {
+   x.Store((*[%d]%s)(s))
+}
+`, c, t, v, t, c, t)
+
+}
+
+func prologue(s string, out io.Writer) {
+	fmt.Fprintf(out,
+		`// Code generated by '%s'; DO NOT EDIT.
+
+//go:build goexperiment.simd
+
+// The build condition == if the experiment is not on, cmd/api TestCheck will see this and complain
+// see also go/doc/comment, where "simd" is inserted to the package list of the experiment is not on.
+
+package simd
+
+`, s)
+}
+
+func main() {
+	filename := flag.String("o", "", "write generated code to this file")
+	flag.Parse()
+
+	ofile := os.Stdout
+
+	if *filename != "" {
+		var err error
+		ofile, err = os.Create(*filename)
+		if err != nil {
+			fmt.Fprintf(os.Stderr, "Could not create the output file for the generated code, %v", err)
+			os.Exit(1)
+		}
+	}
+
+	out := new(bytes.Buffer)
+
+	prologue("go run genslice.go -o slice_amd64.go", out)
+
+	vecs := []int{128, 256, 512}
+	ints := []int{8, 16, 32, 64}
+	floats := []int{32, 64}
+	for _, v := range vecs {
+		for _, w := range ints {
+			c := v / w
+			slice("int", w, c, out)
+			slice("uint", w, c, out)
+		}
+		for _, w := range floats {
+			c := v / w
+			slice("float", w, c, out)
+		}
+	}
+	b, err := format.Source(out.Bytes())
+	if err != nil {
+		fmt.Fprintf(os.Stderr, "There was a problem formatting the generated code, %v", err)
+		os.Exit(1)
+	} else {
+		ofile.Write(b)
+		ofile.Close()
+	}
+}
diff --git a/src/simd/no_tag.go b/src/simd/no_tag.go
new file mode 100644
index 00000000000000..c11fd51b2345d6
--- /dev/null
+++ b/src/simd/no_tag.go
@@ -0,0 +1,9 @@
+// Copyright 2025 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package simd
+
+// This file has no build tag, so that go generate can run without a build tag.
+
+//go:generate go run genslice.go -o slice_amd64.go
diff --git a/src/simd/ops_amd64.go b/src/simd/ops_amd64.go
new file mode 100644
index 00000000000000..a5c2f2d5c28187
--- /dev/null
+++ b/src/simd/ops_amd64.go
@@ -0,0 +1,12894 @@
+// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT.
+
+//go:build goexperiment.simd
+
+package simd
+
+/* Absolute */
+
+// Absolute computes the absolute value of each element.
+//
+// Asm: VPABSB, CPU Feature: AVX
+func (x Int8x16) Absolute() Int8x16
+
+// Absolute computes the absolute value of each element.
+//
+// Asm: VPABSB, CPU Feature: AVX2
+func (x Int8x32) Absolute() Int8x32
+
+// Absolute computes the absolute value of each element.
+//
+// Asm: VPABSB, CPU Feature: AVX512BW
+func (x Int8x64) Absolute() Int8x64
+
+// Absolute computes the absolute value of each element.
+//
+// Asm: VPABSW, CPU Feature: AVX
+func (x Int16x8) Absolute() Int16x8
+
+// Absolute computes the absolute value of each element.
+//
+// Asm: VPABSW, CPU Feature: AVX2
+func (x Int16x16) Absolute() Int16x16
+
+// Absolute computes the absolute value of each element.
+//
+// Asm: VPABSW, CPU Feature: AVX512BW
+func (x Int16x32) Absolute() Int16x32
+
+// Absolute computes the absolute value of each element.
+//
+// Asm: VPABSD, CPU Feature: AVX
+func (x Int32x4) Absolute() Int32x4
+
+// Absolute computes the absolute value of each element.
+//
+// Asm: VPABSD, CPU Feature: AVX2
+func (x Int32x8) Absolute() Int32x8
+
+// Absolute computes the absolute value of each element.
+//
+// Asm: VPABSD, CPU Feature: AVX512F
+func (x Int32x16) Absolute() Int32x16
+
+// Absolute computes the absolute value of each element.
+//
+// Asm: VPABSQ, CPU Feature: AVX512F
+func (x Int64x2) Absolute() Int64x2
+
+// Absolute computes the absolute value of each element.
+//
+// Asm: VPABSQ, CPU Feature: AVX512F
+func (x Int64x4) Absolute() Int64x4
+
+// Absolute computes the absolute value of each element.
+//
+// Asm: VPABSQ, CPU Feature: AVX512F
+func (x Int64x8) Absolute() Int64x8
+
+/* AbsoluteMasked */
+
+// AbsoluteMasked computes the absolute value of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPABSB, CPU Feature: AVX512BW
+func (x Int8x16) AbsoluteMasked(mask Mask8x16) Int8x16
+
+// AbsoluteMasked computes the absolute value of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPABSB, CPU Feature: AVX512BW
+func (x Int8x32) AbsoluteMasked(mask Mask8x32) Int8x32
+
+// AbsoluteMasked computes the absolute value of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPABSB, CPU Feature: AVX512BW
+func (x Int8x64) AbsoluteMasked(mask Mask8x64) Int8x64
+
+// AbsoluteMasked computes the absolute value of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPABSW, CPU Feature: AVX512BW
+func (x Int16x8) AbsoluteMasked(mask Mask16x8) Int16x8
+
+// AbsoluteMasked computes the absolute value of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPABSW, CPU Feature: AVX512BW
+func (x Int16x16) AbsoluteMasked(mask Mask16x16) Int16x16
+
+// AbsoluteMasked computes the absolute value of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPABSW, CPU Feature: AVX512BW
+func (x Int16x32) AbsoluteMasked(mask Mask16x32) Int16x32
+
+// AbsoluteMasked computes the absolute value of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPABSD, CPU Feature: AVX512F
+func (x Int32x4) AbsoluteMasked(mask Mask32x4) Int32x4
+
+// AbsoluteMasked computes the absolute value of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPABSD, CPU Feature: AVX512F
+func (x Int32x8) AbsoluteMasked(mask Mask32x8) Int32x8
+
+// AbsoluteMasked computes the absolute value of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPABSD, CPU Feature: AVX512F
+func (x Int32x16) AbsoluteMasked(mask Mask32x16) Int32x16
+
+// AbsoluteMasked computes the absolute value of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPABSQ, CPU Feature: AVX512F
+func (x Int64x2) AbsoluteMasked(mask Mask64x2) Int64x2
+
+// AbsoluteMasked computes the absolute value of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPABSQ, CPU Feature: AVX512F
+func (x Int64x4) AbsoluteMasked(mask Mask64x4) Int64x4
+
+// AbsoluteMasked computes the absolute value of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPABSQ, CPU Feature: AVX512F
+func (x Int64x8) AbsoluteMasked(mask Mask64x8) Int64x8
+
+/* Add */
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VADDPS, CPU Feature: AVX
+func (x Float32x4) Add(y Float32x4) Float32x4
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VADDPS, CPU Feature: AVX
+func (x Float32x8) Add(y Float32x8) Float32x8
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VADDPS, CPU Feature: AVX512F
+func (x Float32x16) Add(y Float32x16) Float32x16
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VADDPD, CPU Feature: AVX
+func (x Float64x2) Add(y Float64x2) Float64x2
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VADDPD, CPU Feature: AVX
+func (x Float64x4) Add(y Float64x4) Float64x4
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VADDPD, CPU Feature: AVX512F
+func (x Float64x8) Add(y Float64x8) Float64x8
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDB, CPU Feature: AVX
+func (x Int8x16) Add(y Int8x16) Int8x16
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDB, CPU Feature: AVX2
+func (x Int8x32) Add(y Int8x32) Int8x32
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDB, CPU Feature: AVX512BW
+func (x Int8x64) Add(y Int8x64) Int8x64
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDW, CPU Feature: AVX
+func (x Int16x8) Add(y Int16x8) Int16x8
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDW, CPU Feature: AVX2
+func (x Int16x16) Add(y Int16x16) Int16x16
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDW, CPU Feature: AVX512BW
+func (x Int16x32) Add(y Int16x32) Int16x32
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDD, CPU Feature: AVX
+func (x Int32x4) Add(y Int32x4) Int32x4
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDD, CPU Feature: AVX2
+func (x Int32x8) Add(y Int32x8) Int32x8
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDD, CPU Feature: AVX512F
+func (x Int32x16) Add(y Int32x16) Int32x16
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDQ, CPU Feature: AVX
+func (x Int64x2) Add(y Int64x2) Int64x2
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDQ, CPU Feature: AVX2
+func (x Int64x4) Add(y Int64x4) Int64x4
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDQ, CPU Feature: AVX512F
+func (x Int64x8) Add(y Int64x8) Int64x8
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDB, CPU Feature: AVX
+func (x Uint8x16) Add(y Uint8x16) Uint8x16
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDB, CPU Feature: AVX2
+func (x Uint8x32) Add(y Uint8x32) Uint8x32
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDB, CPU Feature: AVX512BW
+func (x Uint8x64) Add(y Uint8x64) Uint8x64
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDW, CPU Feature: AVX
+func (x Uint16x8) Add(y Uint16x8) Uint16x8
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDW, CPU Feature: AVX2
+func (x Uint16x16) Add(y Uint16x16) Uint16x16
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDW, CPU Feature: AVX512BW
+func (x Uint16x32) Add(y Uint16x32) Uint16x32
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDD, CPU Feature: AVX
+func (x Uint32x4) Add(y Uint32x4) Uint32x4
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDD, CPU Feature: AVX2
+func (x Uint32x8) Add(y Uint32x8) Uint32x8
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDD, CPU Feature: AVX512F
+func (x Uint32x16) Add(y Uint32x16) Uint32x16
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDQ, CPU Feature: AVX
+func (x Uint64x2) Add(y Uint64x2) Uint64x2
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDQ, CPU Feature: AVX2
+func (x Uint64x4) Add(y Uint64x4) Uint64x4
+
+// Add adds corresponding elements of two vectors.
+//
+// Asm: VPADDQ, CPU Feature: AVX512F
+func (x Uint64x8) Add(y Uint64x8) Uint64x8
+
+/* AddMasked */
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VADDPS, CPU Feature: AVX512F
+func (x Float32x4) AddMasked(y Float32x4, mask Mask32x4) Float32x4
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VADDPS, CPU Feature: AVX512F
+func (x Float32x8) AddMasked(y Float32x8, mask Mask32x8) Float32x8
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VADDPS, CPU Feature: AVX512F
+func (x Float32x16) AddMasked(y Float32x16, mask Mask32x16) Float32x16
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VADDPD, CPU Feature: AVX512F
+func (x Float64x2) AddMasked(y Float64x2, mask Mask64x2) Float64x2
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VADDPD, CPU Feature: AVX512F
+func (x Float64x4) AddMasked(y Float64x4, mask Mask64x4) Float64x4
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VADDPD, CPU Feature: AVX512F
+func (x Float64x8) AddMasked(y Float64x8, mask Mask64x8) Float64x8
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDB, CPU Feature: AVX512BW
+func (x Int8x16) AddMasked(y Int8x16, mask Mask8x16) Int8x16
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDB, CPU Feature: AVX512BW
+func (x Int8x32) AddMasked(y Int8x32, mask Mask8x32) Int8x32
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDB, CPU Feature: AVX512BW
+func (x Int8x64) AddMasked(y Int8x64, mask Mask8x64) Int8x64
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDW, CPU Feature: AVX512BW
+func (x Int16x8) AddMasked(y Int16x8, mask Mask16x8) Int16x8
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDW, CPU Feature: AVX512BW
+func (x Int16x16) AddMasked(y Int16x16, mask Mask16x16) Int16x16
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDW, CPU Feature: AVX512BW
+func (x Int16x32) AddMasked(y Int16x32, mask Mask16x32) Int16x32
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDD, CPU Feature: AVX512F
+func (x Int32x4) AddMasked(y Int32x4, mask Mask32x4) Int32x4
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDD, CPU Feature: AVX512F
+func (x Int32x8) AddMasked(y Int32x8, mask Mask32x8) Int32x8
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDD, CPU Feature: AVX512F
+func (x Int32x16) AddMasked(y Int32x16, mask Mask32x16) Int32x16
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDQ, CPU Feature: AVX512F
+func (x Int64x2) AddMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDQ, CPU Feature: AVX512F
+func (x Int64x4) AddMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDQ, CPU Feature: AVX512F
+func (x Int64x8) AddMasked(y Int64x8, mask Mask64x8) Int64x8
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDB, CPU Feature: AVX512BW
+func (x Uint8x16) AddMasked(y Uint8x16, mask Mask8x16) Uint8x16
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDB, CPU Feature: AVX512BW
+func (x Uint8x32) AddMasked(y Uint8x32, mask Mask8x32) Uint8x32
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDB, CPU Feature: AVX512BW
+func (x Uint8x64) AddMasked(y Uint8x64, mask Mask8x64) Uint8x64
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDW, CPU Feature: AVX512BW
+func (x Uint16x8) AddMasked(y Uint16x8, mask Mask16x8) Uint16x8
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDW, CPU Feature: AVX512BW
+func (x Uint16x16) AddMasked(y Uint16x16, mask Mask16x16) Uint16x16
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDW, CPU Feature: AVX512BW
+func (x Uint16x32) AddMasked(y Uint16x32, mask Mask16x32) Uint16x32
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDD, CPU Feature: AVX512F
+func (x Uint32x4) AddMasked(y Uint32x4, mask Mask32x4) Uint32x4
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDD, CPU Feature: AVX512F
+func (x Uint32x8) AddMasked(y Uint32x8, mask Mask32x8) Uint32x8
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDD, CPU Feature: AVX512F
+func (x Uint32x16) AddMasked(y Uint32x16, mask Mask32x16) Uint32x16
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDQ, CPU Feature: AVX512F
+func (x Uint64x2) AddMasked(y Uint64x2, mask Mask64x2) Uint64x2
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDQ, CPU Feature: AVX512F
+func (x Uint64x4) AddMasked(y Uint64x4, mask Mask64x4) Uint64x4
+
+// AddMasked adds corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDQ, CPU Feature: AVX512F
+func (x Uint64x8) AddMasked(y Uint64x8, mask Mask64x8) Uint64x8
+
+/* AddSub */
+
+// AddSub subtracts even elements and adds odd elements of two vectors.
+//
+// Asm: VADDSUBPS, CPU Feature: AVX
+func (x Float32x4) AddSub(y Float32x4) Float32x4
+
+// AddSub subtracts even elements and adds odd elements of two vectors.
+//
+// Asm: VADDSUBPS, CPU Feature: AVX
+func (x Float32x8) AddSub(y Float32x8) Float32x8
+
+// AddSub subtracts even elements and adds odd elements of two vectors.
+//
+// Asm: VADDSUBPD, CPU Feature: AVX
+func (x Float64x2) AddSub(y Float64x2) Float64x2
+
+// AddSub subtracts even elements and adds odd elements of two vectors.
+//
+// Asm: VADDSUBPD, CPU Feature: AVX
+func (x Float64x4) AddSub(y Float64x4) Float64x4
+
+/* And */
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX
+func (x Int8x16) And(y Int8x16) Int8x16
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX2
+func (x Int8x32) And(y Int8x32) Int8x32
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX
+func (x Int16x8) And(y Int16x8) Int16x8
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX2
+func (x Int16x16) And(y Int16x16) Int16x16
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX
+func (x Int32x4) And(y Int32x4) Int32x4
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX2
+func (x Int32x8) And(y Int32x8) Int32x8
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPANDD, CPU Feature: AVX512F
+func (x Int32x16) And(y Int32x16) Int32x16
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX
+func (x Int64x2) And(y Int64x2) Int64x2
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX2
+func (x Int64x4) And(y Int64x4) Int64x4
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPANDQ, CPU Feature: AVX512F
+func (x Int64x8) And(y Int64x8) Int64x8
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX
+func (x Uint8x16) And(y Uint8x16) Uint8x16
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX2
+func (x Uint8x32) And(y Uint8x32) Uint8x32
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX
+func (x Uint16x8) And(y Uint16x8) Uint16x8
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX2
+func (x Uint16x16) And(y Uint16x16) Uint16x16
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX
+func (x Uint32x4) And(y Uint32x4) Uint32x4
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX2
+func (x Uint32x8) And(y Uint32x8) Uint32x8
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPANDD, CPU Feature: AVX512F
+func (x Uint32x16) And(y Uint32x16) Uint32x16
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX
+func (x Uint64x2) And(y Uint64x2) Uint64x2
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPAND, CPU Feature: AVX2
+func (x Uint64x4) And(y Uint64x4) Uint64x4
+
+// And performs a bitwise AND operation between two vectors.
+//
+// Asm: VPANDQ, CPU Feature: AVX512F
+func (x Uint64x8) And(y Uint64x8) Uint64x8
+
+/* AndMasked */
+
+// AndMasked performs a bitwise AND operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDD, CPU Feature: AVX512F
+func (x Int32x4) AndMasked(y Int32x4, mask Mask32x4) Int32x4
+
+// AndMasked performs a bitwise AND operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDD, CPU Feature: AVX512F
+func (x Int32x8) AndMasked(y Int32x8, mask Mask32x8) Int32x8
+
+// AndMasked performs a bitwise AND operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDD, CPU Feature: AVX512F
+func (x Int32x16) AndMasked(y Int32x16, mask Mask32x16) Int32x16
+
+// AndMasked performs a bitwise AND operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDQ, CPU Feature: AVX512F
+func (x Int64x2) AndMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// AndMasked performs a bitwise AND operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDQ, CPU Feature: AVX512F
+func (x Int64x4) AndMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// AndMasked performs a bitwise AND operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDQ, CPU Feature: AVX512F
+func (x Int64x8) AndMasked(y Int64x8, mask Mask64x8) Int64x8
+
+// AndMasked performs a bitwise AND operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDD, CPU Feature: AVX512F
+func (x Uint32x4) AndMasked(y Uint32x4, mask Mask32x4) Uint32x4
+
+// AndMasked performs a bitwise AND operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDD, CPU Feature: AVX512F
+func (x Uint32x8) AndMasked(y Uint32x8, mask Mask32x8) Uint32x8
+
+// AndMasked performs a bitwise AND operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDD, CPU Feature: AVX512F
+func (x Uint32x16) AndMasked(y Uint32x16, mask Mask32x16) Uint32x16
+
+// AndMasked performs a bitwise AND operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDQ, CPU Feature: AVX512F
+func (x Uint64x2) AndMasked(y Uint64x2, mask Mask64x2) Uint64x2
+
+// AndMasked performs a bitwise AND operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDQ, CPU Feature: AVX512F
+func (x Uint64x4) AndMasked(y Uint64x4, mask Mask64x4) Uint64x4
+
+// AndMasked performs a bitwise AND operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDQ, CPU Feature: AVX512F
+func (x Uint64x8) AndMasked(y Uint64x8, mask Mask64x8) Uint64x8
+
+/* AndNot */
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX
+func (x Int8x16) AndNot(y Int8x16) Int8x16
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX2
+func (x Int8x32) AndNot(y Int8x32) Int8x32
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX
+func (x Int16x8) AndNot(y Int16x8) Int16x8
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX2
+func (x Int16x16) AndNot(y Int16x16) Int16x16
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX
+func (x Int32x4) AndNot(y Int32x4) Int32x4
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX2
+func (x Int32x8) AndNot(y Int32x8) Int32x8
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDND, CPU Feature: AVX512F
+func (x Int32x16) AndNot(y Int32x16) Int32x16
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX
+func (x Int64x2) AndNot(y Int64x2) Int64x2
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX2
+func (x Int64x4) AndNot(y Int64x4) Int64x4
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDNQ, CPU Feature: AVX512F
+func (x Int64x8) AndNot(y Int64x8) Int64x8
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX
+func (x Uint8x16) AndNot(y Uint8x16) Uint8x16
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX2
+func (x Uint8x32) AndNot(y Uint8x32) Uint8x32
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX
+func (x Uint16x8) AndNot(y Uint16x8) Uint16x8
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX2
+func (x Uint16x16) AndNot(y Uint16x16) Uint16x16
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX
+func (x Uint32x4) AndNot(y Uint32x4) Uint32x4
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX2
+func (x Uint32x8) AndNot(y Uint32x8) Uint32x8
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDND, CPU Feature: AVX512F
+func (x Uint32x16) AndNot(y Uint32x16) Uint32x16
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX
+func (x Uint64x2) AndNot(y Uint64x2) Uint64x2
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDN, CPU Feature: AVX2
+func (x Uint64x4) AndNot(y Uint64x4) Uint64x4
+
+// AndNot performs a bitwise x &^ y.
+//
+// Asm: VPANDNQ, CPU Feature: AVX512F
+func (x Uint64x8) AndNot(y Uint64x8) Uint64x8
+
+/* AndNotMasked */
+
+// AndNotMasked performs a bitwise x &^ y.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDND, CPU Feature: AVX512F
+func (x Int32x4) AndNotMasked(y Int32x4, mask Mask32x4) Int32x4
+
+// AndNotMasked performs a bitwise x &^ y.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDND, CPU Feature: AVX512F
+func (x Int32x8) AndNotMasked(y Int32x8, mask Mask32x8) Int32x8
+
+// AndNotMasked performs a bitwise x &^ y.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDND, CPU Feature: AVX512F
+func (x Int32x16) AndNotMasked(y Int32x16, mask Mask32x16) Int32x16
+
+// AndNotMasked performs a bitwise x &^ y.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDNQ, CPU Feature: AVX512F
+func (x Int64x2) AndNotMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// AndNotMasked performs a bitwise x &^ y.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDNQ, CPU Feature: AVX512F
+func (x Int64x4) AndNotMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// AndNotMasked performs a bitwise x &^ y.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDNQ, CPU Feature: AVX512F
+func (x Int64x8) AndNotMasked(y Int64x8, mask Mask64x8) Int64x8
+
+// AndNotMasked performs a bitwise x &^ y.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDND, CPU Feature: AVX512F
+func (x Uint32x4) AndNotMasked(y Uint32x4, mask Mask32x4) Uint32x4
+
+// AndNotMasked performs a bitwise x &^ y.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDND, CPU Feature: AVX512F
+func (x Uint32x8) AndNotMasked(y Uint32x8, mask Mask32x8) Uint32x8
+
+// AndNotMasked performs a bitwise x &^ y.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDND, CPU Feature: AVX512F
+func (x Uint32x16) AndNotMasked(y Uint32x16, mask Mask32x16) Uint32x16
+
+// AndNotMasked performs a bitwise x &^ y.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDNQ, CPU Feature: AVX512F
+func (x Uint64x2) AndNotMasked(y Uint64x2, mask Mask64x2) Uint64x2
+
+// AndNotMasked performs a bitwise x &^ y.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDNQ, CPU Feature: AVX512F
+func (x Uint64x4) AndNotMasked(y Uint64x4, mask Mask64x4) Uint64x4
+
+// AndNotMasked performs a bitwise x &^ y.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPANDNQ, CPU Feature: AVX512F
+func (x Uint64x8) AndNotMasked(y Uint64x8, mask Mask64x8) Uint64x8
+
+/* ApproximateReciprocal */
+
+// ApproximateReciprocal computes an approximate reciprocal of each element.
+//
+// Asm: VRCP14PS, CPU Feature: AVX512F
+func (x Float32x4) ApproximateReciprocal() Float32x4
+
+// ApproximateReciprocal computes an approximate reciprocal of each element.
+//
+// Asm: VRCP14PS, CPU Feature: AVX512F
+func (x Float32x8) ApproximateReciprocal() Float32x8
+
+// ApproximateReciprocal computes an approximate reciprocal of each element.
+//
+// Asm: VRCP14PS, CPU Feature: AVX512F
+func (x Float32x16) ApproximateReciprocal() Float32x16
+
+// ApproximateReciprocal computes an approximate reciprocal of each element.
+//
+// Asm: VRCP14PD, CPU Feature: AVX512F
+func (x Float64x2) ApproximateReciprocal() Float64x2
+
+// ApproximateReciprocal computes an approximate reciprocal of each element.
+//
+// Asm: VRCP14PD, CPU Feature: AVX512F
+func (x Float64x4) ApproximateReciprocal() Float64x4
+
+// ApproximateReciprocal computes an approximate reciprocal of each element.
+//
+// Asm: VRCP14PD, CPU Feature: AVX512F
+func (x Float64x8) ApproximateReciprocal() Float64x8
+
+/* ApproximateReciprocalMasked */
+
+// ApproximateReciprocalMasked computes an approximate reciprocal of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VRCP14PS, CPU Feature: AVX512F
+func (x Float32x4) ApproximateReciprocalMasked(mask Mask32x4) Float32x4
+
+// ApproximateReciprocalMasked computes an approximate reciprocal of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VRCP14PS, CPU Feature: AVX512F
+func (x Float32x8) ApproximateReciprocalMasked(mask Mask32x8) Float32x8
+
+// ApproximateReciprocalMasked computes an approximate reciprocal of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VRCP14PS, CPU Feature: AVX512F
+func (x Float32x16) ApproximateReciprocalMasked(mask Mask32x16) Float32x16
+
+// ApproximateReciprocalMasked computes an approximate reciprocal of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VRCP14PD, CPU Feature: AVX512F
+func (x Float64x2) ApproximateReciprocalMasked(mask Mask64x2) Float64x2
+
+// ApproximateReciprocalMasked computes an approximate reciprocal of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VRCP14PD, CPU Feature: AVX512F
+func (x Float64x4) ApproximateReciprocalMasked(mask Mask64x4) Float64x4
+
+// ApproximateReciprocalMasked computes an approximate reciprocal of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VRCP14PD, CPU Feature: AVX512F
+func (x Float64x8) ApproximateReciprocalMasked(mask Mask64x8) Float64x8
+
+/* ApproximateReciprocalOfSqrt */
+
+// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element.
+//
+// Asm: VRSQRTPS, CPU Feature: AVX
+func (x Float32x4) ApproximateReciprocalOfSqrt() Float32x4
+
+// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element.
+//
+// Asm: VRSQRTPS, CPU Feature: AVX
+func (x Float32x8) ApproximateReciprocalOfSqrt() Float32x8
+
+// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element.
+//
+// Asm: VRSQRT14PS, CPU Feature: AVX512F
+func (x Float32x16) ApproximateReciprocalOfSqrt() Float32x16
+
+// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element.
+//
+// Asm: VRSQRT14PD, CPU Feature: AVX512F
+func (x Float64x2) ApproximateReciprocalOfSqrt() Float64x2
+
+// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element.
+//
+// Asm: VRSQRT14PD, CPU Feature: AVX512F
+func (x Float64x4) ApproximateReciprocalOfSqrt() Float64x4
+
+// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element.
+//
+// Asm: VRSQRT14PD, CPU Feature: AVX512F
+func (x Float64x8) ApproximateReciprocalOfSqrt() Float64x8
+
+/* ApproximateReciprocalOfSqrtMasked */
+
+// ApproximateReciprocalOfSqrtMasked computes an approximate reciprocal of the square root of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VRSQRT14PS, CPU Feature: AVX512F
+func (x Float32x4) ApproximateReciprocalOfSqrtMasked(mask Mask32x4) Float32x4
+
+// ApproximateReciprocalOfSqrtMasked computes an approximate reciprocal of the square root of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VRSQRT14PS, CPU Feature: AVX512F
+func (x Float32x8) ApproximateReciprocalOfSqrtMasked(mask Mask32x8) Float32x8
+
+// ApproximateReciprocalOfSqrtMasked computes an approximate reciprocal of the square root of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VRSQRT14PS, CPU Feature: AVX512F
+func (x Float32x16) ApproximateReciprocalOfSqrtMasked(mask Mask32x16) Float32x16
+
+// ApproximateReciprocalOfSqrtMasked computes an approximate reciprocal of the square root of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VRSQRT14PD, CPU Feature: AVX512F
+func (x Float64x2) ApproximateReciprocalOfSqrtMasked(mask Mask64x2) Float64x2
+
+// ApproximateReciprocalOfSqrtMasked computes an approximate reciprocal of the square root of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VRSQRT14PD, CPU Feature: AVX512F
+func (x Float64x4) ApproximateReciprocalOfSqrtMasked(mask Mask64x4) Float64x4
+
+// ApproximateReciprocalOfSqrtMasked computes an approximate reciprocal of the square root of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VRSQRT14PD, CPU Feature: AVX512F
+func (x Float64x8) ApproximateReciprocalOfSqrtMasked(mask Mask64x8) Float64x8
+
+/* Average */
+
+// Average computes the rounded average of corresponding elements.
+//
+// Asm: VPAVGB, CPU Feature: AVX
+func (x Uint8x16) Average(y Uint8x16) Uint8x16
+
+// Average computes the rounded average of corresponding elements.
+//
+// Asm: VPAVGB, CPU Feature: AVX2
+func (x Uint8x32) Average(y Uint8x32) Uint8x32
+
+// Average computes the rounded average of corresponding elements.
+//
+// Asm: VPAVGB, CPU Feature: AVX512BW
+func (x Uint8x64) Average(y Uint8x64) Uint8x64
+
+// Average computes the rounded average of corresponding elements.
+//
+// Asm: VPAVGW, CPU Feature: AVX
+func (x Uint16x8) Average(y Uint16x8) Uint16x8
+
+// Average computes the rounded average of corresponding elements.
+//
+// Asm: VPAVGW, CPU Feature: AVX2
+func (x Uint16x16) Average(y Uint16x16) Uint16x16
+
+// Average computes the rounded average of corresponding elements.
+//
+// Asm: VPAVGW, CPU Feature: AVX512BW
+func (x Uint16x32) Average(y Uint16x32) Uint16x32
+
+/* AverageMasked */
+
+// AverageMasked computes the rounded average of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPAVGB, CPU Feature: AVX512BW
+func (x Uint8x16) AverageMasked(y Uint8x16, mask Mask8x16) Uint8x16
+
+// AverageMasked computes the rounded average of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPAVGB, CPU Feature: AVX512BW
+func (x Uint8x32) AverageMasked(y Uint8x32, mask Mask8x32) Uint8x32
+
+// AverageMasked computes the rounded average of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPAVGB, CPU Feature: AVX512BW
+func (x Uint8x64) AverageMasked(y Uint8x64, mask Mask8x64) Uint8x64
+
+// AverageMasked computes the rounded average of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPAVGW, CPU Feature: AVX512BW
+func (x Uint16x8) AverageMasked(y Uint16x8, mask Mask16x8) Uint16x8
+
+// AverageMasked computes the rounded average of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPAVGW, CPU Feature: AVX512BW
+func (x Uint16x16) AverageMasked(y Uint16x16, mask Mask16x16) Uint16x16
+
+// AverageMasked computes the rounded average of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPAVGW, CPU Feature: AVX512BW
+func (x Uint16x32) AverageMasked(y Uint16x32, mask Mask16x32) Uint16x32
+
+/* Ceil */
+
+// Ceil rounds elements up to the nearest integer.
+//
+// Asm: VROUNDPS, CPU Feature: AVX
+func (x Float32x4) Ceil() Float32x4
+
+// Ceil rounds elements up to the nearest integer.
+//
+// Asm: VROUNDPS, CPU Feature: AVX
+func (x Float32x8) Ceil() Float32x8
+
+// Ceil rounds elements up to the nearest integer.
+//
+// Asm: VROUNDPD, CPU Feature: AVX
+func (x Float64x2) Ceil() Float64x2
+
+// Ceil rounds elements up to the nearest integer.
+//
+// Asm: VROUNDPD, CPU Feature: AVX
+func (x Float64x4) Ceil() Float64x4
+
+/* CeilWithPrecision */
+
+// CeilWithPrecision rounds elements up with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x4) CeilWithPrecision(prec uint8) Float32x4
+
+// CeilWithPrecision rounds elements up with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x8) CeilWithPrecision(prec uint8) Float32x8
+
+// CeilWithPrecision rounds elements up with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x16) CeilWithPrecision(prec uint8) Float32x16
+
+// CeilWithPrecision rounds elements up with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x2) CeilWithPrecision(prec uint8) Float64x2
+
+// CeilWithPrecision rounds elements up with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x4) CeilWithPrecision(prec uint8) Float64x4
+
+// CeilWithPrecision rounds elements up with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x8) CeilWithPrecision(prec uint8) Float64x8
+
+/* CeilWithPrecisionMasked */
+
+// CeilWithPrecisionMasked rounds elements up with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x4) CeilWithPrecisionMasked(prec uint8, mask Mask32x4) Float32x4
+
+// CeilWithPrecisionMasked rounds elements up with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x8) CeilWithPrecisionMasked(prec uint8, mask Mask32x8) Float32x8
+
+// CeilWithPrecisionMasked rounds elements up with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x16) CeilWithPrecisionMasked(prec uint8, mask Mask32x16) Float32x16
+
+// CeilWithPrecisionMasked rounds elements up with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x2) CeilWithPrecisionMasked(prec uint8, mask Mask64x2) Float64x2
+
+// CeilWithPrecisionMasked rounds elements up with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x4) CeilWithPrecisionMasked(prec uint8, mask Mask64x4) Float64x4
+
+// CeilWithPrecisionMasked rounds elements up with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x8) CeilWithPrecisionMasked(prec uint8, mask Mask64x8) Float64x8
+
+/* Compress */
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VCOMPRESSPS, CPU Feature: AVX512F
+func (x Float32x4) Compress(mask Mask32x4) Float32x4
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VCOMPRESSPS, CPU Feature: AVX512F
+func (x Float32x8) Compress(mask Mask32x8) Float32x8
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VCOMPRESSPS, CPU Feature: AVX512F
+func (x Float32x16) Compress(mask Mask32x16) Float32x16
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VCOMPRESSPD, CPU Feature: AVX512F
+func (x Float64x2) Compress(mask Mask64x2) Float64x2
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VCOMPRESSPD, CPU Feature: AVX512F
+func (x Float64x4) Compress(mask Mask64x4) Float64x4
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VCOMPRESSPD, CPU Feature: AVX512F
+func (x Float64x8) Compress(mask Mask64x8) Float64x8
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSB, CPU Feature: AVX512VBMI2
+func (x Int8x16) Compress(mask Mask8x16) Int8x16
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSB, CPU Feature: AVX512VBMI2
+func (x Int8x32) Compress(mask Mask8x32) Int8x32
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSB, CPU Feature: AVX512VBMI2
+func (x Int8x64) Compress(mask Mask8x64) Int8x64
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSW, CPU Feature: AVX512VBMI2
+func (x Int16x8) Compress(mask Mask16x8) Int16x8
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSW, CPU Feature: AVX512VBMI2
+func (x Int16x16) Compress(mask Mask16x16) Int16x16
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSW, CPU Feature: AVX512VBMI2
+func (x Int16x32) Compress(mask Mask16x32) Int16x32
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSD, CPU Feature: AVX512F
+func (x Int32x4) Compress(mask Mask32x4) Int32x4
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSD, CPU Feature: AVX512F
+func (x Int32x8) Compress(mask Mask32x8) Int32x8
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSD, CPU Feature: AVX512F
+func (x Int32x16) Compress(mask Mask32x16) Int32x16
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSQ, CPU Feature: AVX512F
+func (x Int64x2) Compress(mask Mask64x2) Int64x2
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSQ, CPU Feature: AVX512F
+func (x Int64x4) Compress(mask Mask64x4) Int64x4
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSQ, CPU Feature: AVX512F
+func (x Int64x8) Compress(mask Mask64x8) Int64x8
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSB, CPU Feature: AVX512VBMI2
+func (x Uint8x16) Compress(mask Mask8x16) Uint8x16
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSB, CPU Feature: AVX512VBMI2
+func (x Uint8x32) Compress(mask Mask8x32) Uint8x32
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSB, CPU Feature: AVX512VBMI2
+func (x Uint8x64) Compress(mask Mask8x64) Uint8x64
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSW, CPU Feature: AVX512VBMI2
+func (x Uint16x8) Compress(mask Mask16x8) Uint16x8
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSW, CPU Feature: AVX512VBMI2
+func (x Uint16x16) Compress(mask Mask16x16) Uint16x16
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSW, CPU Feature: AVX512VBMI2
+func (x Uint16x32) Compress(mask Mask16x32) Uint16x32
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSD, CPU Feature: AVX512F
+func (x Uint32x4) Compress(mask Mask32x4) Uint32x4
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSD, CPU Feature: AVX512F
+func (x Uint32x8) Compress(mask Mask32x8) Uint32x8
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSD, CPU Feature: AVX512F
+func (x Uint32x16) Compress(mask Mask32x16) Uint32x16
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSQ, CPU Feature: AVX512F
+func (x Uint64x2) Compress(mask Mask64x2) Uint64x2
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSQ, CPU Feature: AVX512F
+func (x Uint64x4) Compress(mask Mask64x4) Uint64x4
+
+// Compress performs a compression on vector x using mask by
+// selecting elements as indicated by mask, and pack them to lower indexed elements.
+//
+// Asm: VPCOMPRESSQ, CPU Feature: AVX512F
+func (x Uint64x8) Compress(mask Mask64x8) Uint64x8
+
+/* DiffWithCeilWithPrecision */
+
+// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x4) DiffWithCeilWithPrecision(prec uint8) Float32x4
+
+// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x8) DiffWithCeilWithPrecision(prec uint8) Float32x8
+
+// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x16) DiffWithCeilWithPrecision(prec uint8) Float32x16
+
+// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x2) DiffWithCeilWithPrecision(prec uint8) Float64x2
+
+// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x4) DiffWithCeilWithPrecision(prec uint8) Float64x4
+
+// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x8) DiffWithCeilWithPrecision(prec uint8) Float64x8
+
+/* DiffWithCeilWithPrecisionMasked */
+
+// DiffWithCeilWithPrecisionMasked computes the difference after ceiling with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x4) DiffWithCeilWithPrecisionMasked(prec uint8, mask Mask32x4) Float32x4
+
+// DiffWithCeilWithPrecisionMasked computes the difference after ceiling with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x8) DiffWithCeilWithPrecisionMasked(prec uint8, mask Mask32x8) Float32x8
+
+// DiffWithCeilWithPrecisionMasked computes the difference after ceiling with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x16) DiffWithCeilWithPrecisionMasked(prec uint8, mask Mask32x16) Float32x16
+
+// DiffWithCeilWithPrecisionMasked computes the difference after ceiling with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x2) DiffWithCeilWithPrecisionMasked(prec uint8, mask Mask64x2) Float64x2
+
+// DiffWithCeilWithPrecisionMasked computes the difference after ceiling with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x4) DiffWithCeilWithPrecisionMasked(prec uint8, mask Mask64x4) Float64x4
+
+// DiffWithCeilWithPrecisionMasked computes the difference after ceiling with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x8) DiffWithCeilWithPrecisionMasked(prec uint8, mask Mask64x8) Float64x8
+
+/* DiffWithFloorWithPrecision */
+
+// DiffWithFloorWithPrecision computes the difference after flooring with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x4) DiffWithFloorWithPrecision(prec uint8) Float32x4
+
+// DiffWithFloorWithPrecision computes the difference after flooring with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x8) DiffWithFloorWithPrecision(prec uint8) Float32x8
+
+// DiffWithFloorWithPrecision computes the difference after flooring with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x16) DiffWithFloorWithPrecision(prec uint8) Float32x16
+
+// DiffWithFloorWithPrecision computes the difference after flooring with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x2) DiffWithFloorWithPrecision(prec uint8) Float64x2
+
+// DiffWithFloorWithPrecision computes the difference after flooring with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x4) DiffWithFloorWithPrecision(prec uint8) Float64x4
+
+// DiffWithFloorWithPrecision computes the difference after flooring with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x8) DiffWithFloorWithPrecision(prec uint8) Float64x8
+
+/* DiffWithFloorWithPrecisionMasked */
+
+// DiffWithFloorWithPrecisionMasked computes the difference after flooring with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x4) DiffWithFloorWithPrecisionMasked(prec uint8, mask Mask32x4) Float32x4
+
+// DiffWithFloorWithPrecisionMasked computes the difference after flooring with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x8) DiffWithFloorWithPrecisionMasked(prec uint8, mask Mask32x8) Float32x8
+
+// DiffWithFloorWithPrecisionMasked computes the difference after flooring with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x16) DiffWithFloorWithPrecisionMasked(prec uint8, mask Mask32x16) Float32x16
+
+// DiffWithFloorWithPrecisionMasked computes the difference after flooring with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x2) DiffWithFloorWithPrecisionMasked(prec uint8, mask Mask64x2) Float64x2
+
+// DiffWithFloorWithPrecisionMasked computes the difference after flooring with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x4) DiffWithFloorWithPrecisionMasked(prec uint8, mask Mask64x4) Float64x4
+
+// DiffWithFloorWithPrecisionMasked computes the difference after flooring with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x8) DiffWithFloorWithPrecisionMasked(prec uint8, mask Mask64x8) Float64x8
+
+/* DiffWithRoundWithPrecision */
+
+// DiffWithRoundWithPrecision computes the difference after rounding with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x4) DiffWithRoundWithPrecision(prec uint8) Float32x4
+
+// DiffWithRoundWithPrecision computes the difference after rounding with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x8) DiffWithRoundWithPrecision(prec uint8) Float32x8
+
+// DiffWithRoundWithPrecision computes the difference after rounding with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x16) DiffWithRoundWithPrecision(prec uint8) Float32x16
+
+// DiffWithRoundWithPrecision computes the difference after rounding with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x2) DiffWithRoundWithPrecision(prec uint8) Float64x2
+
+// DiffWithRoundWithPrecision computes the difference after rounding with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x4) DiffWithRoundWithPrecision(prec uint8) Float64x4
+
+// DiffWithRoundWithPrecision computes the difference after rounding with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x8) DiffWithRoundWithPrecision(prec uint8) Float64x8
+
+/* DiffWithRoundWithPrecisionMasked */
+
+// DiffWithRoundWithPrecisionMasked computes the difference after rounding with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x4) DiffWithRoundWithPrecisionMasked(prec uint8, mask Mask32x4) Float32x4
+
+// DiffWithRoundWithPrecisionMasked computes the difference after rounding with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x8) DiffWithRoundWithPrecisionMasked(prec uint8, mask Mask32x8) Float32x8
+
+// DiffWithRoundWithPrecisionMasked computes the difference after rounding with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x16) DiffWithRoundWithPrecisionMasked(prec uint8, mask Mask32x16) Float32x16
+
+// DiffWithRoundWithPrecisionMasked computes the difference after rounding with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x2) DiffWithRoundWithPrecisionMasked(prec uint8, mask Mask64x2) Float64x2
+
+// DiffWithRoundWithPrecisionMasked computes the difference after rounding with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x4) DiffWithRoundWithPrecisionMasked(prec uint8, mask Mask64x4) Float64x4
+
+// DiffWithRoundWithPrecisionMasked computes the difference after rounding with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x8) DiffWithRoundWithPrecisionMasked(prec uint8, mask Mask64x8) Float64x8
+
+/* DiffWithTruncWithPrecision */
+
+// DiffWithTruncWithPrecision computes the difference after truncating with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x4) DiffWithTruncWithPrecision(prec uint8) Float32x4
+
+// DiffWithTruncWithPrecision computes the difference after truncating with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x8) DiffWithTruncWithPrecision(prec uint8) Float32x8
+
+// DiffWithTruncWithPrecision computes the difference after truncating with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x16) DiffWithTruncWithPrecision(prec uint8) Float32x16
+
+// DiffWithTruncWithPrecision computes the difference after truncating with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x2) DiffWithTruncWithPrecision(prec uint8) Float64x2
+
+// DiffWithTruncWithPrecision computes the difference after truncating with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x4) DiffWithTruncWithPrecision(prec uint8) Float64x4
+
+// DiffWithTruncWithPrecision computes the difference after truncating with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x8) DiffWithTruncWithPrecision(prec uint8) Float64x8
+
+/* DiffWithTruncWithPrecisionMasked */
+
+// DiffWithTruncWithPrecisionMasked computes the difference after truncating with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x4) DiffWithTruncWithPrecisionMasked(prec uint8, mask Mask32x4) Float32x4
+
+// DiffWithTruncWithPrecisionMasked computes the difference after truncating with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x8) DiffWithTruncWithPrecisionMasked(prec uint8, mask Mask32x8) Float32x8
+
+// DiffWithTruncWithPrecisionMasked computes the difference after truncating with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPS, CPU Feature: AVX512DQ
+func (x Float32x16) DiffWithTruncWithPrecisionMasked(prec uint8, mask Mask32x16) Float32x16
+
+// DiffWithTruncWithPrecisionMasked computes the difference after truncating with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x2) DiffWithTruncWithPrecisionMasked(prec uint8, mask Mask64x2) Float64x2
+
+// DiffWithTruncWithPrecisionMasked computes the difference after truncating with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x4) DiffWithTruncWithPrecisionMasked(prec uint8, mask Mask64x4) Float64x4
+
+// DiffWithTruncWithPrecisionMasked computes the difference after truncating with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VREDUCEPD, CPU Feature: AVX512DQ
+func (x Float64x8) DiffWithTruncWithPrecisionMasked(prec uint8, mask Mask64x8) Float64x8
+
+/* Div */
+
+// Div divides elements of two vectors.
+//
+// Asm: VDIVPS, CPU Feature: AVX
+func (x Float32x4) Div(y Float32x4) Float32x4
+
+// Div divides elements of two vectors.
+//
+// Asm: VDIVPS, CPU Feature: AVX
+func (x Float32x8) Div(y Float32x8) Float32x8
+
+// Div divides elements of two vectors.
+//
+// Asm: VDIVPS, CPU Feature: AVX512F
+func (x Float32x16) Div(y Float32x16) Float32x16
+
+// Div divides elements of two vectors.
+//
+// Asm: VDIVPD, CPU Feature: AVX
+func (x Float64x2) Div(y Float64x2) Float64x2
+
+// Div divides elements of two vectors.
+//
+// Asm: VDIVPD, CPU Feature: AVX
+func (x Float64x4) Div(y Float64x4) Float64x4
+
+// Div divides elements of two vectors.
+//
+// Asm: VDIVPD, CPU Feature: AVX512F
+func (x Float64x8) Div(y Float64x8) Float64x8
+
+/* DivMasked */
+
+// DivMasked divides elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VDIVPS, CPU Feature: AVX512F
+func (x Float32x4) DivMasked(y Float32x4, mask Mask32x4) Float32x4
+
+// DivMasked divides elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VDIVPS, CPU Feature: AVX512F
+func (x Float32x8) DivMasked(y Float32x8, mask Mask32x8) Float32x8
+
+// DivMasked divides elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VDIVPS, CPU Feature: AVX512F
+func (x Float32x16) DivMasked(y Float32x16, mask Mask32x16) Float32x16
+
+// DivMasked divides elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VDIVPD, CPU Feature: AVX512F
+func (x Float64x2) DivMasked(y Float64x2, mask Mask64x2) Float64x2
+
+// DivMasked divides elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VDIVPD, CPU Feature: AVX512F
+func (x Float64x4) DivMasked(y Float64x4, mask Mask64x4) Float64x4
+
+// DivMasked divides elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VDIVPD, CPU Feature: AVX512F
+func (x Float64x8) DivMasked(y Float64x8, mask Mask64x8) Float64x8
+
+/* DotProdBroadcast */
+
+// DotProdBroadcast multiplies all elements and broadcasts the sum.
+//
+// Asm: VDPPS, CPU Feature: AVX
+func (x Float32x4) DotProdBroadcast(y Float32x4) Float32x4
+
+// DotProdBroadcast multiplies all elements and broadcasts the sum.
+//
+// Asm: VDPPS, CPU Feature: AVX
+func (x Float32x8) DotProdBroadcast(y Float32x8) Float32x8
+
+// DotProdBroadcast multiplies all elements and broadcasts the sum.
+//
+// Asm: VDPPD, CPU Feature: AVX
+func (x Float64x2) DotProdBroadcast(y Float64x2) Float64x2
+
+/* Equal */
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQB, CPU Feature: AVX
+func (x Int8x16) Equal(y Int8x16) Mask8x16
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQB, CPU Feature: AVX2
+func (x Int8x32) Equal(y Int8x32) Mask8x32
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQW, CPU Feature: AVX
+func (x Int16x8) Equal(y Int16x8) Mask16x8
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQW, CPU Feature: AVX2
+func (x Int16x16) Equal(y Int16x16) Mask16x16
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQD, CPU Feature: AVX
+func (x Int32x4) Equal(y Int32x4) Mask32x4
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQD, CPU Feature: AVX2
+func (x Int32x8) Equal(y Int32x8) Mask32x8
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQQ, CPU Feature: AVX
+func (x Int64x2) Equal(y Int64x2) Mask64x2
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQQ, CPU Feature: AVX2
+func (x Int64x4) Equal(y Int64x4) Mask64x4
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQB, CPU Feature: AVX
+func (x Uint8x16) Equal(y Uint8x16) Mask8x16
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQB, CPU Feature: AVX2
+func (x Uint8x32) Equal(y Uint8x32) Mask8x32
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQW, CPU Feature: AVX
+func (x Uint16x8) Equal(y Uint16x8) Mask16x8
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQW, CPU Feature: AVX2
+func (x Uint16x16) Equal(y Uint16x16) Mask16x16
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQD, CPU Feature: AVX
+func (x Uint32x4) Equal(y Uint32x4) Mask32x4
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQD, CPU Feature: AVX2
+func (x Uint32x8) Equal(y Uint32x8) Mask32x8
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQQ, CPU Feature: AVX
+func (x Uint64x2) Equal(y Uint64x2) Mask64x2
+
+// Equal compares for equality.
+//
+// Asm: VPCMPEQQ, CPU Feature: AVX2
+func (x Uint64x4) Equal(y Uint64x4) Mask64x4
+
+// Equal compares for equality.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x4) Equal(y Float32x4) Mask32x4
+
+// Equal compares for equality.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x8) Equal(y Float32x8) Mask32x8
+
+// Equal compares for equality.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) Equal(y Float32x16) Mask32x16
+
+// Equal compares for equality.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x2) Equal(y Float64x2) Mask64x2
+
+// Equal compares for equality.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x4) Equal(y Float64x4) Mask64x4
+
+// Equal compares for equality.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) Equal(y Float64x8) Mask64x8
+
+// Equal compares for equality.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x64) Equal(y Int8x64) Mask8x64
+
+// Equal compares for equality.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x32) Equal(y Int16x32) Mask16x32
+
+// Equal compares for equality.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x16) Equal(y Int32x16) Mask32x16
+
+// Equal compares for equality.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x8) Equal(y Int64x8) Mask64x8
+
+// Equal compares for equality.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x64) Equal(y Uint8x64) Mask8x64
+
+// Equal compares for equality.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x32) Equal(y Uint16x32) Mask16x32
+
+// Equal compares for equality.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x16) Equal(y Uint32x16) Mask32x16
+
+// Equal compares for equality.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x8) Equal(y Uint64x8) Mask64x8
+
+/* EqualMasked */
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x4) EqualMasked(y Float32x4, mask Mask32x4) Mask32x4
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x8) EqualMasked(y Float32x8, mask Mask32x8) Mask32x8
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) EqualMasked(y Float32x16, mask Mask32x16) Mask32x16
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x2) EqualMasked(y Float64x2, mask Mask64x2) Mask64x2
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x4) EqualMasked(y Float64x4, mask Mask64x4) Mask64x4
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) EqualMasked(y Float64x8, mask Mask64x8) Mask64x8
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x16) EqualMasked(y Int8x16, mask Mask8x16) Mask8x16
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x32) EqualMasked(y Int8x32, mask Mask8x32) Mask8x32
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x64) EqualMasked(y Int8x64, mask Mask8x64) Mask8x64
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x8) EqualMasked(y Int16x8, mask Mask16x8) Mask16x8
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x16) EqualMasked(y Int16x16, mask Mask16x16) Mask16x16
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x32) EqualMasked(y Int16x32, mask Mask16x32) Mask16x32
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x4) EqualMasked(y Int32x4, mask Mask32x4) Mask32x4
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x8) EqualMasked(y Int32x8, mask Mask32x8) Mask32x8
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x16) EqualMasked(y Int32x16, mask Mask32x16) Mask32x16
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x2) EqualMasked(y Int64x2, mask Mask64x2) Mask64x2
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x4) EqualMasked(y Int64x4, mask Mask64x4) Mask64x4
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x8) EqualMasked(y Int64x8, mask Mask64x8) Mask64x8
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x16) EqualMasked(y Uint8x16, mask Mask8x16) Mask8x16
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x32) EqualMasked(y Uint8x32, mask Mask8x32) Mask8x32
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x64) EqualMasked(y Uint8x64, mask Mask8x64) Mask8x64
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x8) EqualMasked(y Uint16x8, mask Mask16x8) Mask16x8
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x16) EqualMasked(y Uint16x16, mask Mask16x16) Mask16x16
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x32) EqualMasked(y Uint16x32, mask Mask16x32) Mask16x32
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x4) EqualMasked(y Uint32x4, mask Mask32x4) Mask32x4
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x8) EqualMasked(y Uint32x8, mask Mask32x8) Mask32x8
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x16) EqualMasked(y Uint32x16, mask Mask32x16) Mask32x16
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x2) EqualMasked(y Uint64x2, mask Mask64x2) Mask64x2
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x4) EqualMasked(y Uint64x4, mask Mask64x4) Mask64x4
+
+// EqualMasked compares for equality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x8) EqualMasked(y Uint64x8, mask Mask64x8) Mask64x8
+
+/* Floor */
+
+// Floor rounds elements down to the nearest integer.
+//
+// Asm: VROUNDPS, CPU Feature: AVX
+func (x Float32x4) Floor() Float32x4
+
+// Floor rounds elements down to the nearest integer.
+//
+// Asm: VROUNDPS, CPU Feature: AVX
+func (x Float32x8) Floor() Float32x8
+
+// Floor rounds elements down to the nearest integer.
+//
+// Asm: VROUNDPD, CPU Feature: AVX
+func (x Float64x2) Floor() Float64x2
+
+// Floor rounds elements down to the nearest integer.
+//
+// Asm: VROUNDPD, CPU Feature: AVX
+func (x Float64x4) Floor() Float64x4
+
+/* FloorWithPrecision */
+
+// FloorWithPrecision rounds elements down with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x4) FloorWithPrecision(prec uint8) Float32x4
+
+// FloorWithPrecision rounds elements down with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x8) FloorWithPrecision(prec uint8) Float32x8
+
+// FloorWithPrecision rounds elements down with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x16) FloorWithPrecision(prec uint8) Float32x16
+
+// FloorWithPrecision rounds elements down with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x2) FloorWithPrecision(prec uint8) Float64x2
+
+// FloorWithPrecision rounds elements down with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x4) FloorWithPrecision(prec uint8) Float64x4
+
+// FloorWithPrecision rounds elements down with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x8) FloorWithPrecision(prec uint8) Float64x8
+
+/* FloorWithPrecisionMasked */
+
+// FloorWithPrecisionMasked rounds elements down with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x4) FloorWithPrecisionMasked(prec uint8, mask Mask32x4) Float32x4
+
+// FloorWithPrecisionMasked rounds elements down with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x8) FloorWithPrecisionMasked(prec uint8, mask Mask32x8) Float32x8
+
+// FloorWithPrecisionMasked rounds elements down with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x16) FloorWithPrecisionMasked(prec uint8, mask Mask32x16) Float32x16
+
+// FloorWithPrecisionMasked rounds elements down with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x2) FloorWithPrecisionMasked(prec uint8, mask Mask64x2) Float64x2
+
+// FloorWithPrecisionMasked rounds elements down with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x4) FloorWithPrecisionMasked(prec uint8, mask Mask64x4) Float64x4
+
+// FloorWithPrecisionMasked rounds elements down with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x8) FloorWithPrecisionMasked(prec uint8, mask Mask64x8) Float64x8
+
+/* FusedMultiplyAdd */
+
+// FusedMultiplyAdd performs (x * y) + z.
+//
+// Asm: VFMADD213PS, CPU Feature: AVX512F
+func (x Float32x4) FusedMultiplyAdd(y Float32x4, z Float32x4) Float32x4
+
+// FusedMultiplyAdd performs (x * y) + z.
+//
+// Asm: VFMADD213PS, CPU Feature: AVX512F
+func (x Float32x8) FusedMultiplyAdd(y Float32x8, z Float32x8) Float32x8
+
+// FusedMultiplyAdd performs (x * y) + z.
+//
+// Asm: VFMADD213PS, CPU Feature: AVX512F
+func (x Float32x16) FusedMultiplyAdd(y Float32x16, z Float32x16) Float32x16
+
+// FusedMultiplyAdd performs (x * y) + z.
+//
+// Asm: VFMADD213PD, CPU Feature: AVX512F
+func (x Float64x2) FusedMultiplyAdd(y Float64x2, z Float64x2) Float64x2
+
+// FusedMultiplyAdd performs (x * y) + z.
+//
+// Asm: VFMADD213PD, CPU Feature: AVX512F
+func (x Float64x4) FusedMultiplyAdd(y Float64x4, z Float64x4) Float64x4
+
+// FusedMultiplyAdd performs (x * y) + z.
+//
+// Asm: VFMADD213PD, CPU Feature: AVX512F
+func (x Float64x8) FusedMultiplyAdd(y Float64x8, z Float64x8) Float64x8
+
+/* FusedMultiplyAddMasked */
+
+// FusedMultiplyAddMasked performs (x * y) + z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMADD213PS, CPU Feature: AVX512F
+func (x Float32x4) FusedMultiplyAddMasked(y Float32x4, z Float32x4, mask Mask32x4) Float32x4
+
+// FusedMultiplyAddMasked performs (x * y) + z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMADD213PS, CPU Feature: AVX512F
+func (x Float32x8) FusedMultiplyAddMasked(y Float32x8, z Float32x8, mask Mask32x8) Float32x8
+
+// FusedMultiplyAddMasked performs (x * y) + z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMADD213PS, CPU Feature: AVX512F
+func (x Float32x16) FusedMultiplyAddMasked(y Float32x16, z Float32x16, mask Mask32x16) Float32x16
+
+// FusedMultiplyAddMasked performs (x * y) + z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMADD213PD, CPU Feature: AVX512F
+func (x Float64x2) FusedMultiplyAddMasked(y Float64x2, z Float64x2, mask Mask64x2) Float64x2
+
+// FusedMultiplyAddMasked performs (x * y) + z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMADD213PD, CPU Feature: AVX512F
+func (x Float64x4) FusedMultiplyAddMasked(y Float64x4, z Float64x4, mask Mask64x4) Float64x4
+
+// FusedMultiplyAddMasked performs (x * y) + z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMADD213PD, CPU Feature: AVX512F
+func (x Float64x8) FusedMultiplyAddMasked(y Float64x8, z Float64x8, mask Mask64x8) Float64x8
+
+/* FusedMultiplyAddSub */
+
+// FusedMultiplyAddSub performs (x * y) - z for odd-indexed elements, and (x * y) + z for even-indexed elements.
+//
+// Asm: VFMADDSUB213PS, CPU Feature: AVX512F
+func (x Float32x4) FusedMultiplyAddSub(y Float32x4, z Float32x4) Float32x4
+
+// FusedMultiplyAddSub performs (x * y) - z for odd-indexed elements, and (x * y) + z for even-indexed elements.
+//
+// Asm: VFMADDSUB213PS, CPU Feature: AVX512F
+func (x Float32x8) FusedMultiplyAddSub(y Float32x8, z Float32x8) Float32x8
+
+// FusedMultiplyAddSub performs (x * y) - z for odd-indexed elements, and (x * y) + z for even-indexed elements.
+//
+// Asm: VFMADDSUB213PS, CPU Feature: AVX512F
+func (x Float32x16) FusedMultiplyAddSub(y Float32x16, z Float32x16) Float32x16
+
+// FusedMultiplyAddSub performs (x * y) - z for odd-indexed elements, and (x * y) + z for even-indexed elements.
+//
+// Asm: VFMADDSUB213PD, CPU Feature: AVX512F
+func (x Float64x2) FusedMultiplyAddSub(y Float64x2, z Float64x2) Float64x2
+
+// FusedMultiplyAddSub performs (x * y) - z for odd-indexed elements, and (x * y) + z for even-indexed elements.
+//
+// Asm: VFMADDSUB213PD, CPU Feature: AVX512F
+func (x Float64x4) FusedMultiplyAddSub(y Float64x4, z Float64x4) Float64x4
+
+// FusedMultiplyAddSub performs (x * y) - z for odd-indexed elements, and (x * y) + z for even-indexed elements.
+//
+// Asm: VFMADDSUB213PD, CPU Feature: AVX512F
+func (x Float64x8) FusedMultiplyAddSub(y Float64x8, z Float64x8) Float64x8
+
+/* FusedMultiplyAddSubMasked */
+
+// FusedMultiplyAddSubMasked performs (x * y) - z for odd-indexed elements, and (x * y) + z for even-indexed elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMADDSUB213PS, CPU Feature: AVX512F
+func (x Float32x4) FusedMultiplyAddSubMasked(y Float32x4, z Float32x4, mask Mask32x4) Float32x4
+
+// FusedMultiplyAddSubMasked performs (x * y) - z for odd-indexed elements, and (x * y) + z for even-indexed elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMADDSUB213PS, CPU Feature: AVX512F
+func (x Float32x8) FusedMultiplyAddSubMasked(y Float32x8, z Float32x8, mask Mask32x8) Float32x8
+
+// FusedMultiplyAddSubMasked performs (x * y) - z for odd-indexed elements, and (x * y) + z for even-indexed elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMADDSUB213PS, CPU Feature: AVX512F
+func (x Float32x16) FusedMultiplyAddSubMasked(y Float32x16, z Float32x16, mask Mask32x16) Float32x16
+
+// FusedMultiplyAddSubMasked performs (x * y) - z for odd-indexed elements, and (x * y) + z for even-indexed elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMADDSUB213PD, CPU Feature: AVX512F
+func (x Float64x2) FusedMultiplyAddSubMasked(y Float64x2, z Float64x2, mask Mask64x2) Float64x2
+
+// FusedMultiplyAddSubMasked performs (x * y) - z for odd-indexed elements, and (x * y) + z for even-indexed elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMADDSUB213PD, CPU Feature: AVX512F
+func (x Float64x4) FusedMultiplyAddSubMasked(y Float64x4, z Float64x4, mask Mask64x4) Float64x4
+
+// FusedMultiplyAddSubMasked performs (x * y) - z for odd-indexed elements, and (x * y) + z for even-indexed elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMADDSUB213PD, CPU Feature: AVX512F
+func (x Float64x8) FusedMultiplyAddSubMasked(y Float64x8, z Float64x8, mask Mask64x8) Float64x8
+
+/* FusedMultiplySubAdd */
+
+// FusedMultiplySubAdd performs (x * y) + z for odd-indexed elements, and (x * y) - z for even-indexed elements.
+//
+// Asm: VFMSUBADD213PS, CPU Feature: AVX512F
+func (x Float32x4) FusedMultiplySubAdd(y Float32x4, z Float32x4) Float32x4
+
+// FusedMultiplySubAdd performs (x * y) + z for odd-indexed elements, and (x * y) - z for even-indexed elements.
+//
+// Asm: VFMSUBADD213PS, CPU Feature: AVX512F
+func (x Float32x8) FusedMultiplySubAdd(y Float32x8, z Float32x8) Float32x8
+
+// FusedMultiplySubAdd performs (x * y) + z for odd-indexed elements, and (x * y) - z for even-indexed elements.
+//
+// Asm: VFMSUBADD213PS, CPU Feature: AVX512F
+func (x Float32x16) FusedMultiplySubAdd(y Float32x16, z Float32x16) Float32x16
+
+// FusedMultiplySubAdd performs (x * y) + z for odd-indexed elements, and (x * y) - z for even-indexed elements.
+//
+// Asm: VFMSUBADD213PD, CPU Feature: AVX512F
+func (x Float64x2) FusedMultiplySubAdd(y Float64x2, z Float64x2) Float64x2
+
+// FusedMultiplySubAdd performs (x * y) + z for odd-indexed elements, and (x * y) - z for even-indexed elements.
+//
+// Asm: VFMSUBADD213PD, CPU Feature: AVX512F
+func (x Float64x4) FusedMultiplySubAdd(y Float64x4, z Float64x4) Float64x4
+
+// FusedMultiplySubAdd performs (x * y) + z for odd-indexed elements, and (x * y) - z for even-indexed elements.
+//
+// Asm: VFMSUBADD213PD, CPU Feature: AVX512F
+func (x Float64x8) FusedMultiplySubAdd(y Float64x8, z Float64x8) Float64x8
+
+/* FusedMultiplySubAddMasked */
+
+// FusedMultiplySubAddMasked performs (x * y) + z for odd-indexed elements, and (x * y) - z for even-indexed elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMSUBADD213PS, CPU Feature: AVX512F
+func (x Float32x4) FusedMultiplySubAddMasked(y Float32x4, z Float32x4, mask Mask32x4) Float32x4
+
+// FusedMultiplySubAddMasked performs (x * y) + z for odd-indexed elements, and (x * y) - z for even-indexed elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMSUBADD213PS, CPU Feature: AVX512F
+func (x Float32x8) FusedMultiplySubAddMasked(y Float32x8, z Float32x8, mask Mask32x8) Float32x8
+
+// FusedMultiplySubAddMasked performs (x * y) + z for odd-indexed elements, and (x * y) - z for even-indexed elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMSUBADD213PS, CPU Feature: AVX512F
+func (x Float32x16) FusedMultiplySubAddMasked(y Float32x16, z Float32x16, mask Mask32x16) Float32x16
+
+// FusedMultiplySubAddMasked performs (x * y) + z for odd-indexed elements, and (x * y) - z for even-indexed elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMSUBADD213PD, CPU Feature: AVX512F
+func (x Float64x2) FusedMultiplySubAddMasked(y Float64x2, z Float64x2, mask Mask64x2) Float64x2
+
+// FusedMultiplySubAddMasked performs (x * y) + z for odd-indexed elements, and (x * y) - z for even-indexed elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMSUBADD213PD, CPU Feature: AVX512F
+func (x Float64x4) FusedMultiplySubAddMasked(y Float64x4, z Float64x4, mask Mask64x4) Float64x4
+
+// FusedMultiplySubAddMasked performs (x * y) + z for odd-indexed elements, and (x * y) - z for even-indexed elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VFMSUBADD213PD, CPU Feature: AVX512F
+func (x Float64x8) FusedMultiplySubAddMasked(y Float64x8, z Float64x8, mask Mask64x8) Float64x8
+
+/* GaloisFieldAffineTransform */
+
+// GaloisFieldAffineTransform computes an affine transformation in GF(2^8):
+// x is a vector of 8-bit vectors, with each adjacent 8 as a group; y is a vector of 8x8 1-bit matrixes;
+// b is an 8-bit vector. The affine transformation is y * x + b, with each element of y
+// corresponding to a group of 8 elements in x.
+//
+// b is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VGF2P8AFFINEQB, CPU Feature: AVX512GFNI
+func (x Uint8x16) GaloisFieldAffineTransform(y Uint64x2, b uint8) Uint8x16
+
+// GaloisFieldAffineTransform computes an affine transformation in GF(2^8):
+// x is a vector of 8-bit vectors, with each adjacent 8 as a group; y is a vector of 8x8 1-bit matrixes;
+// b is an 8-bit vector. The affine transformation is y * x + b, with each element of y
+// corresponding to a group of 8 elements in x.
+//
+// b is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VGF2P8AFFINEQB, CPU Feature: AVX512GFNI
+func (x Uint8x32) GaloisFieldAffineTransform(y Uint64x4, b uint8) Uint8x32
+
+// GaloisFieldAffineTransform computes an affine transformation in GF(2^8):
+// x is a vector of 8-bit vectors, with each adjacent 8 as a group; y is a vector of 8x8 1-bit matrixes;
+// b is an 8-bit vector. The affine transformation is y * x + b, with each element of y
+// corresponding to a group of 8 elements in x.
+//
+// b is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VGF2P8AFFINEQB, CPU Feature: AVX512GFNI
+func (x Uint8x64) GaloisFieldAffineTransform(y Uint64x8, b uint8) Uint8x64
+
+/* GaloisFieldAffineTransformInverse */
+
+// GaloisFieldAffineTransformInverse computes an affine transformation in GF(2^8),
+// with x inverted with respect to reduction polynomial x^8 + x^4 + x^3 + x + 1:
+// x is a vector of 8-bit vectors, with each adjacent 8 as a group; y is a vector of 8x8 1-bit matrixes;
+// b is an 8-bit vector. The affine transformation is y * x + b, with each element of y
+// corresponding to a group of 8 elements in x.
+//
+// b is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VGF2P8AFFINEINVQB, CPU Feature: AVX512GFNI
+func (x Uint8x16) GaloisFieldAffineTransformInverse(y Uint64x2, b uint8) Uint8x16
+
+// GaloisFieldAffineTransformInverse computes an affine transformation in GF(2^8),
+// with x inverted with respect to reduction polynomial x^8 + x^4 + x^3 + x + 1:
+// x is a vector of 8-bit vectors, with each adjacent 8 as a group; y is a vector of 8x8 1-bit matrixes;
+// b is an 8-bit vector. The affine transformation is y * x + b, with each element of y
+// corresponding to a group of 8 elements in x.
+//
+// b is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VGF2P8AFFINEINVQB, CPU Feature: AVX512GFNI
+func (x Uint8x32) GaloisFieldAffineTransformInverse(y Uint64x4, b uint8) Uint8x32
+
+// GaloisFieldAffineTransformInverse computes an affine transformation in GF(2^8),
+// with x inverted with respect to reduction polynomial x^8 + x^4 + x^3 + x + 1:
+// x is a vector of 8-bit vectors, with each adjacent 8 as a group; y is a vector of 8x8 1-bit matrixes;
+// b is an 8-bit vector. The affine transformation is y * x + b, with each element of y
+// corresponding to a group of 8 elements in x.
+//
+// b is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VGF2P8AFFINEINVQB, CPU Feature: AVX512GFNI
+func (x Uint8x64) GaloisFieldAffineTransformInverse(y Uint64x8, b uint8) Uint8x64
+
+/* GaloisFieldAffineTransformInverseMasked */
+
+// GaloisFieldAffineTransformInverseMasked computes an affine transformation in GF(2^8),
+// with x inverted with respect to reduction polynomial x^8 + x^4 + x^3 + x + 1:
+// x is a vector of 8-bit vectors, with each adjacent 8 as a group; y is a vector of 8x8 1-bit matrixes;
+// b is an 8-bit vector. The affine transformation is y * x + b, with each element of y
+// corresponding to a group of 8 elements in x.
+//
+// This operation is applied selectively under a write mask.
+//
+// b is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VGF2P8AFFINEINVQB, CPU Feature: AVX512GFNI
+func (x Uint8x16) GaloisFieldAffineTransformInverseMasked(y Uint64x2, b uint8, m Mask8x16) Uint8x16
+
+// GaloisFieldAffineTransformInverseMasked computes an affine transformation in GF(2^8),
+// with x inverted with respect to reduction polynomial x^8 + x^4 + x^3 + x + 1:
+// x is a vector of 8-bit vectors, with each adjacent 8 as a group; y is a vector of 8x8 1-bit matrixes;
+// b is an 8-bit vector. The affine transformation is y * x + b, with each element of y
+// corresponding to a group of 8 elements in x.
+//
+// This operation is applied selectively under a write mask.
+//
+// b is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VGF2P8AFFINEINVQB, CPU Feature: AVX512GFNI
+func (x Uint8x32) GaloisFieldAffineTransformInverseMasked(y Uint64x4, b uint8, m Mask8x32) Uint8x32
+
+// GaloisFieldAffineTransformInverseMasked computes an affine transformation in GF(2^8),
+// with x inverted with respect to reduction polynomial x^8 + x^4 + x^3 + x + 1:
+// x is a vector of 8-bit vectors, with each adjacent 8 as a group; y is a vector of 8x8 1-bit matrixes;
+// b is an 8-bit vector. The affine transformation is y * x + b, with each element of y
+// corresponding to a group of 8 elements in x.
+//
+// This operation is applied selectively under a write mask.
+//
+// b is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VGF2P8AFFINEINVQB, CPU Feature: AVX512GFNI
+func (x Uint8x64) GaloisFieldAffineTransformInverseMasked(y Uint64x8, b uint8, m Mask8x64) Uint8x64
+
+/* GaloisFieldAffineTransformMasked */
+
+// GaloisFieldAffineTransformMasked computes an affine transformation in GF(2^8):
+// x is a vector of 8-bit vectors, with each adjacent 8 as a group; y is a vector of 8x8 1-bit matrixes;
+// b is an 8-bit vector. The affine transformation is y * x + b, with each element of y
+// corresponding to a group of 8 elements in x.
+//
+// This operation is applied selectively under a write mask.
+//
+// b is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VGF2P8AFFINEQB, CPU Feature: AVX512GFNI
+func (x Uint8x16) GaloisFieldAffineTransformMasked(y Uint64x2, b uint8, m Mask8x16) Uint8x16
+
+// GaloisFieldAffineTransformMasked computes an affine transformation in GF(2^8):
+// x is a vector of 8-bit vectors, with each adjacent 8 as a group; y is a vector of 8x8 1-bit matrixes;
+// b is an 8-bit vector. The affine transformation is y * x + b, with each element of y
+// corresponding to a group of 8 elements in x.
+//
+// This operation is applied selectively under a write mask.
+//
+// b is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VGF2P8AFFINEQB, CPU Feature: AVX512GFNI
+func (x Uint8x32) GaloisFieldAffineTransformMasked(y Uint64x4, b uint8, m Mask8x32) Uint8x32
+
+// GaloisFieldAffineTransformMasked computes an affine transformation in GF(2^8):
+// x is a vector of 8-bit vectors, with each adjacent 8 as a group; y is a vector of 8x8 1-bit matrixes;
+// b is an 8-bit vector. The affine transformation is y * x + b, with each element of y
+// corresponding to a group of 8 elements in x.
+//
+// This operation is applied selectively under a write mask.
+//
+// b is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VGF2P8AFFINEQB, CPU Feature: AVX512GFNI
+func (x Uint8x64) GaloisFieldAffineTransformMasked(y Uint64x8, b uint8, m Mask8x64) Uint8x64
+
+/* GaloisFieldMul */
+
+// GaloisFieldMul computes element-wise GF(2^8) multiplication with
+// reduction polynomial x^8 + x^4 + x^3 + x + 1.
+//
+// Asm: VGF2P8MULB, CPU Feature: AVX512GFNI
+func (x Uint8x16) GaloisFieldMul(y Uint8x16) Uint8x16
+
+// GaloisFieldMul computes element-wise GF(2^8) multiplication with
+// reduction polynomial x^8 + x^4 + x^3 + x + 1.
+//
+// Asm: VGF2P8MULB, CPU Feature: AVX512GFNI
+func (x Uint8x32) GaloisFieldMul(y Uint8x32) Uint8x32
+
+// GaloisFieldMul computes element-wise GF(2^8) multiplication with
+// reduction polynomial x^8 + x^4 + x^3 + x + 1.
+//
+// Asm: VGF2P8MULB, CPU Feature: AVX512GFNI
+func (x Uint8x64) GaloisFieldMul(y Uint8x64) Uint8x64
+
+/* GaloisFieldMulMasked */
+
+// GaloisFieldMulMasked computes element-wise GF(2^8) multiplication with
+// reduction polynomial x^8 + x^4 + x^3 + x + 1.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VGF2P8MULB, CPU Feature: AVX512GFNI
+func (x Uint8x16) GaloisFieldMulMasked(y Uint8x16, mask Mask8x16) Uint8x16
+
+// GaloisFieldMulMasked computes element-wise GF(2^8) multiplication with
+// reduction polynomial x^8 + x^4 + x^3 + x + 1.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VGF2P8MULB, CPU Feature: AVX512GFNI
+func (x Uint8x32) GaloisFieldMulMasked(y Uint8x32, mask Mask8x32) Uint8x32
+
+// GaloisFieldMulMasked computes element-wise GF(2^8) multiplication with
+// reduction polynomial x^8 + x^4 + x^3 + x + 1.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VGF2P8MULB, CPU Feature: AVX512GFNI
+func (x Uint8x64) GaloisFieldMulMasked(y Uint8x64, mask Mask8x64) Uint8x64
+
+/* Get128 */
+
+// Get128 retrieves the upper (1) or lower (0) half of a 256-bit vector, depending on the constant operand.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VEXTRACTF128, CPU Feature: AVX
+func (x Float32x8) Get128(index uint8) Float32x4
+
+// Get128 retrieves the upper (1) or lower (0) half of a 256-bit vector, depending on the constant operand.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VEXTRACTF128, CPU Feature: AVX
+func (x Float64x4) Get128(index uint8) Float64x2
+
+// Get128 retrieves the upper (1) or lower (0) half of a 256-bit vector, depending on the constant operand.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VEXTRACTI128, CPU Feature: AVX2
+func (x Int8x32) Get128(index uint8) Int8x16
+
+// Get128 retrieves the upper (1) or lower (0) half of a 256-bit vector, depending on the constant operand.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VEXTRACTI128, CPU Feature: AVX2
+func (x Int16x16) Get128(index uint8) Int16x8
+
+// Get128 retrieves the upper (1) or lower (0) half of a 256-bit vector, depending on the constant operand.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VEXTRACTI128, CPU Feature: AVX2
+func (x Int32x8) Get128(index uint8) Int32x4
+
+// Get128 retrieves the upper (1) or lower (0) half of a 256-bit vector, depending on the constant operand.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VEXTRACTI128, CPU Feature: AVX2
+func (x Int64x4) Get128(index uint8) Int64x2
+
+// Get128 retrieves the upper (1) or lower (0) half of a 256-bit vector, depending on the constant operand.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VEXTRACTI128, CPU Feature: AVX2
+func (x Uint8x32) Get128(index uint8) Uint8x16
+
+// Get128 retrieves the upper (1) or lower (0) half of a 256-bit vector, depending on the constant operand.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VEXTRACTI128, CPU Feature: AVX2
+func (x Uint16x16) Get128(index uint8) Uint16x8
+
+// Get128 retrieves the upper (1) or lower (0) half of a 256-bit vector, depending on the constant operand.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VEXTRACTI128, CPU Feature: AVX2
+func (x Uint32x8) Get128(index uint8) Uint32x4
+
+// Get128 retrieves the upper (1) or lower (0) half of a 256-bit vector, depending on the constant operand.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VEXTRACTI128, CPU Feature: AVX2
+func (x Uint64x4) Get128(index uint8) Uint64x2
+
+/* GetElem */
+
+// GetElem retrieves a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPEXTRB, CPU Feature: AVX512BW
+func (x Int8x16) GetElem(index uint8) int8
+
+// GetElem retrieves a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPEXTRW, CPU Feature: AVX512BW
+func (x Int16x8) GetElem(index uint8) int16
+
+// GetElem retrieves a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPEXTRD, CPU Feature: AVX
+func (x Int32x4) GetElem(index uint8) int32
+
+// GetElem retrieves a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPEXTRQ, CPU Feature: AVX
+func (x Int64x2) GetElem(index uint8) int64
+
+// GetElem retrieves a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPEXTRB, CPU Feature: AVX512BW
+func (x Uint8x16) GetElem(index uint8) uint8
+
+// GetElem retrieves a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPEXTRW, CPU Feature: AVX512BW
+func (x Uint16x8) GetElem(index uint8) uint16
+
+// GetElem retrieves a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPEXTRD, CPU Feature: AVX
+func (x Uint32x4) GetElem(index uint8) uint32
+
+// GetElem retrieves a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPEXTRQ, CPU Feature: AVX
+func (x Uint64x2) GetElem(index uint8) uint64
+
+/* Greater */
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPGTB, CPU Feature: AVX
+func (x Int8x16) Greater(y Int8x16) Mask8x16
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPGTB, CPU Feature: AVX2
+func (x Int8x32) Greater(y Int8x32) Mask8x32
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPGTW, CPU Feature: AVX
+func (x Int16x8) Greater(y Int16x8) Mask16x8
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPGTW, CPU Feature: AVX2
+func (x Int16x16) Greater(y Int16x16) Mask16x16
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPGTD, CPU Feature: AVX
+func (x Int32x4) Greater(y Int32x4) Mask32x4
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPGTD, CPU Feature: AVX2
+func (x Int32x8) Greater(y Int32x8) Mask32x8
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPGTQ, CPU Feature: AVX
+func (x Int64x2) Greater(y Int64x2) Mask64x2
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPGTQ, CPU Feature: AVX2
+func (x Int64x4) Greater(y Int64x4) Mask64x4
+
+// Greater compares for greater than.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x4) Greater(y Float32x4) Mask32x4
+
+// Greater compares for greater than.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x8) Greater(y Float32x8) Mask32x8
+
+// Greater compares for greater than.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) Greater(y Float32x16) Mask32x16
+
+// Greater compares for greater than.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x2) Greater(y Float64x2) Mask64x2
+
+// Greater compares for greater than.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x4) Greater(y Float64x4) Mask64x4
+
+// Greater compares for greater than.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) Greater(y Float64x8) Mask64x8
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x64) Greater(y Int8x64) Mask8x64
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x32) Greater(y Int16x32) Mask16x32
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x16) Greater(y Int32x16) Mask32x16
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x8) Greater(y Int64x8) Mask64x8
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x16) Greater(y Uint8x16) Mask8x16
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x32) Greater(y Uint8x32) Mask8x32
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x64) Greater(y Uint8x64) Mask8x64
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x8) Greater(y Uint16x8) Mask16x8
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x16) Greater(y Uint16x16) Mask16x16
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x32) Greater(y Uint16x32) Mask16x32
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x4) Greater(y Uint32x4) Mask32x4
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x8) Greater(y Uint32x8) Mask32x8
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x16) Greater(y Uint32x16) Mask32x16
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x2) Greater(y Uint64x2) Mask64x2
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x4) Greater(y Uint64x4) Mask64x4
+
+// Greater compares for greater than.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x8) Greater(y Uint64x8) Mask64x8
+
+/* GreaterEqual */
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x4) GreaterEqual(y Float32x4) Mask32x4
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x8) GreaterEqual(y Float32x8) Mask32x8
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) GreaterEqual(y Float32x16) Mask32x16
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x2) GreaterEqual(y Float64x2) Mask64x2
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x4) GreaterEqual(y Float64x4) Mask64x4
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) GreaterEqual(y Float64x8) Mask64x8
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x16) GreaterEqual(y Int8x16) Mask8x16
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x32) GreaterEqual(y Int8x32) Mask8x32
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x64) GreaterEqual(y Int8x64) Mask8x64
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x8) GreaterEqual(y Int16x8) Mask16x8
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x16) GreaterEqual(y Int16x16) Mask16x16
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x32) GreaterEqual(y Int16x32) Mask16x32
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x4) GreaterEqual(y Int32x4) Mask32x4
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x8) GreaterEqual(y Int32x8) Mask32x8
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x16) GreaterEqual(y Int32x16) Mask32x16
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x2) GreaterEqual(y Int64x2) Mask64x2
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x4) GreaterEqual(y Int64x4) Mask64x4
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x8) GreaterEqual(y Int64x8) Mask64x8
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x16) GreaterEqual(y Uint8x16) Mask8x16
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x32) GreaterEqual(y Uint8x32) Mask8x32
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x64) GreaterEqual(y Uint8x64) Mask8x64
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x8) GreaterEqual(y Uint16x8) Mask16x8
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x16) GreaterEqual(y Uint16x16) Mask16x16
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x32) GreaterEqual(y Uint16x32) Mask16x32
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x4) GreaterEqual(y Uint32x4) Mask32x4
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x8) GreaterEqual(y Uint32x8) Mask32x8
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x16) GreaterEqual(y Uint32x16) Mask32x16
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x2) GreaterEqual(y Uint64x2) Mask64x2
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x4) GreaterEqual(y Uint64x4) Mask64x4
+
+// GreaterEqual compares for greater than or equal.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x8) GreaterEqual(y Uint64x8) Mask64x8
+
+/* GreaterEqualMasked */
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x4) GreaterEqualMasked(y Float32x4, mask Mask32x4) Mask32x4
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x8) GreaterEqualMasked(y Float32x8, mask Mask32x8) Mask32x8
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) GreaterEqualMasked(y Float32x16, mask Mask32x16) Mask32x16
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x2) GreaterEqualMasked(y Float64x2, mask Mask64x2) Mask64x2
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x4) GreaterEqualMasked(y Float64x4, mask Mask64x4) Mask64x4
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) GreaterEqualMasked(y Float64x8, mask Mask64x8) Mask64x8
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x16) GreaterEqualMasked(y Int8x16, mask Mask8x16) Mask8x16
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x32) GreaterEqualMasked(y Int8x32, mask Mask8x32) Mask8x32
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x64) GreaterEqualMasked(y Int8x64, mask Mask8x64) Mask8x64
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x8) GreaterEqualMasked(y Int16x8, mask Mask16x8) Mask16x8
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x16) GreaterEqualMasked(y Int16x16, mask Mask16x16) Mask16x16
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x32) GreaterEqualMasked(y Int16x32, mask Mask16x32) Mask16x32
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x4) GreaterEqualMasked(y Int32x4, mask Mask32x4) Mask32x4
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x8) GreaterEqualMasked(y Int32x8, mask Mask32x8) Mask32x8
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x16) GreaterEqualMasked(y Int32x16, mask Mask32x16) Mask32x16
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x2) GreaterEqualMasked(y Int64x2, mask Mask64x2) Mask64x2
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x4) GreaterEqualMasked(y Int64x4, mask Mask64x4) Mask64x4
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x8) GreaterEqualMasked(y Int64x8, mask Mask64x8) Mask64x8
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x16) GreaterEqualMasked(y Uint8x16, mask Mask8x16) Mask8x16
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x32) GreaterEqualMasked(y Uint8x32, mask Mask8x32) Mask8x32
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x64) GreaterEqualMasked(y Uint8x64, mask Mask8x64) Mask8x64
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x8) GreaterEqualMasked(y Uint16x8, mask Mask16x8) Mask16x8
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x16) GreaterEqualMasked(y Uint16x16, mask Mask16x16) Mask16x16
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x32) GreaterEqualMasked(y Uint16x32, mask Mask16x32) Mask16x32
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x4) GreaterEqualMasked(y Uint32x4, mask Mask32x4) Mask32x4
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x8) GreaterEqualMasked(y Uint32x8, mask Mask32x8) Mask32x8
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x16) GreaterEqualMasked(y Uint32x16, mask Mask32x16) Mask32x16
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x2) GreaterEqualMasked(y Uint64x2, mask Mask64x2) Mask64x2
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x4) GreaterEqualMasked(y Uint64x4, mask Mask64x4) Mask64x4
+
+// GreaterEqualMasked compares for greater than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x8) GreaterEqualMasked(y Uint64x8, mask Mask64x8) Mask64x8
+
+/* GreaterMasked */
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x4) GreaterMasked(y Float32x4, mask Mask32x4) Mask32x4
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x8) GreaterMasked(y Float32x8, mask Mask32x8) Mask32x8
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) GreaterMasked(y Float32x16, mask Mask32x16) Mask32x16
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x2) GreaterMasked(y Float64x2, mask Mask64x2) Mask64x2
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x4) GreaterMasked(y Float64x4, mask Mask64x4) Mask64x4
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) GreaterMasked(y Float64x8, mask Mask64x8) Mask64x8
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x16) GreaterMasked(y Int8x16, mask Mask8x16) Mask8x16
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x32) GreaterMasked(y Int8x32, mask Mask8x32) Mask8x32
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x64) GreaterMasked(y Int8x64, mask Mask8x64) Mask8x64
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x8) GreaterMasked(y Int16x8, mask Mask16x8) Mask16x8
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x16) GreaterMasked(y Int16x16, mask Mask16x16) Mask16x16
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x32) GreaterMasked(y Int16x32, mask Mask16x32) Mask16x32
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x4) GreaterMasked(y Int32x4, mask Mask32x4) Mask32x4
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x8) GreaterMasked(y Int32x8, mask Mask32x8) Mask32x8
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x16) GreaterMasked(y Int32x16, mask Mask32x16) Mask32x16
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x2) GreaterMasked(y Int64x2, mask Mask64x2) Mask64x2
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x4) GreaterMasked(y Int64x4, mask Mask64x4) Mask64x4
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x8) GreaterMasked(y Int64x8, mask Mask64x8) Mask64x8
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x16) GreaterMasked(y Uint8x16, mask Mask8x16) Mask8x16
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x32) GreaterMasked(y Uint8x32, mask Mask8x32) Mask8x32
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x64) GreaterMasked(y Uint8x64, mask Mask8x64) Mask8x64
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x8) GreaterMasked(y Uint16x8, mask Mask16x8) Mask16x8
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x16) GreaterMasked(y Uint16x16, mask Mask16x16) Mask16x16
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x32) GreaterMasked(y Uint16x32, mask Mask16x32) Mask16x32
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x4) GreaterMasked(y Uint32x4, mask Mask32x4) Mask32x4
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x8) GreaterMasked(y Uint32x8, mask Mask32x8) Mask32x8
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x16) GreaterMasked(y Uint32x16, mask Mask32x16) Mask32x16
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x2) GreaterMasked(y Uint64x2, mask Mask64x2) Mask64x2
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x4) GreaterMasked(y Uint64x4, mask Mask64x4) Mask64x4
+
+// GreaterMasked compares for greater than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x8) GreaterMasked(y Uint64x8, mask Mask64x8) Mask64x8
+
+/* IsNan */
+
+// IsNan checks if elements are NaN. Use as x.IsNan(x).
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x4) IsNan(y Float32x4) Mask32x4
+
+// IsNan checks if elements are NaN. Use as x.IsNan(x).
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x8) IsNan(y Float32x8) Mask32x8
+
+// IsNan checks if elements are NaN. Use as x.IsNan(x).
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) IsNan(y Float32x16) Mask32x16
+
+// IsNan checks if elements are NaN. Use as x.IsNan(x).
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x2) IsNan(y Float64x2) Mask64x2
+
+// IsNan checks if elements are NaN. Use as x.IsNan(x).
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x4) IsNan(y Float64x4) Mask64x4
+
+// IsNan checks if elements are NaN. Use as x.IsNan(x).
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) IsNan(y Float64x8) Mask64x8
+
+/* IsNanMasked */
+
+// IsNanMasked checks if elements are NaN. Use as x.IsNan(x).
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x4) IsNanMasked(y Float32x4, mask Mask32x4) Mask32x4
+
+// IsNanMasked checks if elements are NaN. Use as x.IsNan(x).
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x8) IsNanMasked(y Float32x8, mask Mask32x8) Mask32x8
+
+// IsNanMasked checks if elements are NaN. Use as x.IsNan(x).
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) IsNanMasked(y Float32x16, mask Mask32x16) Mask32x16
+
+// IsNanMasked checks if elements are NaN. Use as x.IsNan(x).
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x2) IsNanMasked(y Float64x2, mask Mask64x2) Mask64x2
+
+// IsNanMasked checks if elements are NaN. Use as x.IsNan(x).
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x4) IsNanMasked(y Float64x4, mask Mask64x4) Mask64x4
+
+// IsNanMasked checks if elements are NaN. Use as x.IsNan(x).
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) IsNanMasked(y Float64x8, mask Mask64x8) Mask64x8
+
+/* Less */
+
+// Less compares for less than.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x4) Less(y Float32x4) Mask32x4
+
+// Less compares for less than.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x8) Less(y Float32x8) Mask32x8
+
+// Less compares for less than.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) Less(y Float32x16) Mask32x16
+
+// Less compares for less than.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x2) Less(y Float64x2) Mask64x2
+
+// Less compares for less than.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x4) Less(y Float64x4) Mask64x4
+
+// Less compares for less than.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) Less(y Float64x8) Mask64x8
+
+// Less compares for less than.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x16) Less(y Int8x16) Mask8x16
+
+// Less compares for less than.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x32) Less(y Int8x32) Mask8x32
+
+// Less compares for less than.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x64) Less(y Int8x64) Mask8x64
+
+// Less compares for less than.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x8) Less(y Int16x8) Mask16x8
+
+// Less compares for less than.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x16) Less(y Int16x16) Mask16x16
+
+// Less compares for less than.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x32) Less(y Int16x32) Mask16x32
+
+// Less compares for less than.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x4) Less(y Int32x4) Mask32x4
+
+// Less compares for less than.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x8) Less(y Int32x8) Mask32x8
+
+// Less compares for less than.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x16) Less(y Int32x16) Mask32x16
+
+// Less compares for less than.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x2) Less(y Int64x2) Mask64x2
+
+// Less compares for less than.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x4) Less(y Int64x4) Mask64x4
+
+// Less compares for less than.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x8) Less(y Int64x8) Mask64x8
+
+// Less compares for less than.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x16) Less(y Uint8x16) Mask8x16
+
+// Less compares for less than.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x32) Less(y Uint8x32) Mask8x32
+
+// Less compares for less than.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x64) Less(y Uint8x64) Mask8x64
+
+// Less compares for less than.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x8) Less(y Uint16x8) Mask16x8
+
+// Less compares for less than.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x16) Less(y Uint16x16) Mask16x16
+
+// Less compares for less than.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x32) Less(y Uint16x32) Mask16x32
+
+// Less compares for less than.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x4) Less(y Uint32x4) Mask32x4
+
+// Less compares for less than.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x8) Less(y Uint32x8) Mask32x8
+
+// Less compares for less than.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x16) Less(y Uint32x16) Mask32x16
+
+// Less compares for less than.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x2) Less(y Uint64x2) Mask64x2
+
+// Less compares for less than.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x4) Less(y Uint64x4) Mask64x4
+
+// Less compares for less than.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x8) Less(y Uint64x8) Mask64x8
+
+/* LessEqual */
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x4) LessEqual(y Float32x4) Mask32x4
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x8) LessEqual(y Float32x8) Mask32x8
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) LessEqual(y Float32x16) Mask32x16
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x2) LessEqual(y Float64x2) Mask64x2
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x4) LessEqual(y Float64x4) Mask64x4
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) LessEqual(y Float64x8) Mask64x8
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x16) LessEqual(y Int8x16) Mask8x16
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x32) LessEqual(y Int8x32) Mask8x32
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x64) LessEqual(y Int8x64) Mask8x64
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x8) LessEqual(y Int16x8) Mask16x8
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x16) LessEqual(y Int16x16) Mask16x16
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x32) LessEqual(y Int16x32) Mask16x32
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x4) LessEqual(y Int32x4) Mask32x4
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x8) LessEqual(y Int32x8) Mask32x8
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x16) LessEqual(y Int32x16) Mask32x16
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x2) LessEqual(y Int64x2) Mask64x2
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x4) LessEqual(y Int64x4) Mask64x4
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x8) LessEqual(y Int64x8) Mask64x8
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x16) LessEqual(y Uint8x16) Mask8x16
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x32) LessEqual(y Uint8x32) Mask8x32
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x64) LessEqual(y Uint8x64) Mask8x64
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x8) LessEqual(y Uint16x8) Mask16x8
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x16) LessEqual(y Uint16x16) Mask16x16
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x32) LessEqual(y Uint16x32) Mask16x32
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x4) LessEqual(y Uint32x4) Mask32x4
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x8) LessEqual(y Uint32x8) Mask32x8
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x16) LessEqual(y Uint32x16) Mask32x16
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x2) LessEqual(y Uint64x2) Mask64x2
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x4) LessEqual(y Uint64x4) Mask64x4
+
+// LessEqual compares for less than or equal.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x8) LessEqual(y Uint64x8) Mask64x8
+
+/* LessEqualMasked */
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x4) LessEqualMasked(y Float32x4, mask Mask32x4) Mask32x4
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x8) LessEqualMasked(y Float32x8, mask Mask32x8) Mask32x8
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) LessEqualMasked(y Float32x16, mask Mask32x16) Mask32x16
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x2) LessEqualMasked(y Float64x2, mask Mask64x2) Mask64x2
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x4) LessEqualMasked(y Float64x4, mask Mask64x4) Mask64x4
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) LessEqualMasked(y Float64x8, mask Mask64x8) Mask64x8
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x16) LessEqualMasked(y Int8x16, mask Mask8x16) Mask8x16
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x32) LessEqualMasked(y Int8x32, mask Mask8x32) Mask8x32
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x64) LessEqualMasked(y Int8x64, mask Mask8x64) Mask8x64
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x8) LessEqualMasked(y Int16x8, mask Mask16x8) Mask16x8
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x16) LessEqualMasked(y Int16x16, mask Mask16x16) Mask16x16
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x32) LessEqualMasked(y Int16x32, mask Mask16x32) Mask16x32
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x4) LessEqualMasked(y Int32x4, mask Mask32x4) Mask32x4
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x8) LessEqualMasked(y Int32x8, mask Mask32x8) Mask32x8
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x16) LessEqualMasked(y Int32x16, mask Mask32x16) Mask32x16
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x2) LessEqualMasked(y Int64x2, mask Mask64x2) Mask64x2
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x4) LessEqualMasked(y Int64x4, mask Mask64x4) Mask64x4
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x8) LessEqualMasked(y Int64x8, mask Mask64x8) Mask64x8
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x16) LessEqualMasked(y Uint8x16, mask Mask8x16) Mask8x16
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x32) LessEqualMasked(y Uint8x32, mask Mask8x32) Mask8x32
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x64) LessEqualMasked(y Uint8x64, mask Mask8x64) Mask8x64
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x8) LessEqualMasked(y Uint16x8, mask Mask16x8) Mask16x8
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x16) LessEqualMasked(y Uint16x16, mask Mask16x16) Mask16x16
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x32) LessEqualMasked(y Uint16x32, mask Mask16x32) Mask16x32
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x4) LessEqualMasked(y Uint32x4, mask Mask32x4) Mask32x4
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x8) LessEqualMasked(y Uint32x8, mask Mask32x8) Mask32x8
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x16) LessEqualMasked(y Uint32x16, mask Mask32x16) Mask32x16
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x2) LessEqualMasked(y Uint64x2, mask Mask64x2) Mask64x2
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x4) LessEqualMasked(y Uint64x4, mask Mask64x4) Mask64x4
+
+// LessEqualMasked compares for less than or equal.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x8) LessEqualMasked(y Uint64x8, mask Mask64x8) Mask64x8
+
+/* LessMasked */
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x4) LessMasked(y Float32x4, mask Mask32x4) Mask32x4
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x8) LessMasked(y Float32x8, mask Mask32x8) Mask32x8
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) LessMasked(y Float32x16, mask Mask32x16) Mask32x16
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x2) LessMasked(y Float64x2, mask Mask64x2) Mask64x2
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x4) LessMasked(y Float64x4, mask Mask64x4) Mask64x4
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) LessMasked(y Float64x8, mask Mask64x8) Mask64x8
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x16) LessMasked(y Int8x16, mask Mask8x16) Mask8x16
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x32) LessMasked(y Int8x32, mask Mask8x32) Mask8x32
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x64) LessMasked(y Int8x64, mask Mask8x64) Mask8x64
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x8) LessMasked(y Int16x8, mask Mask16x8) Mask16x8
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x16) LessMasked(y Int16x16, mask Mask16x16) Mask16x16
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x32) LessMasked(y Int16x32, mask Mask16x32) Mask16x32
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x4) LessMasked(y Int32x4, mask Mask32x4) Mask32x4
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x8) LessMasked(y Int32x8, mask Mask32x8) Mask32x8
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x16) LessMasked(y Int32x16, mask Mask32x16) Mask32x16
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x2) LessMasked(y Int64x2, mask Mask64x2) Mask64x2
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x4) LessMasked(y Int64x4, mask Mask64x4) Mask64x4
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x8) LessMasked(y Int64x8, mask Mask64x8) Mask64x8
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x16) LessMasked(y Uint8x16, mask Mask8x16) Mask8x16
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x32) LessMasked(y Uint8x32, mask Mask8x32) Mask8x32
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x64) LessMasked(y Uint8x64, mask Mask8x64) Mask8x64
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x8) LessMasked(y Uint16x8, mask Mask16x8) Mask16x8
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x16) LessMasked(y Uint16x16, mask Mask16x16) Mask16x16
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x32) LessMasked(y Uint16x32, mask Mask16x32) Mask16x32
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x4) LessMasked(y Uint32x4, mask Mask32x4) Mask32x4
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x8) LessMasked(y Uint32x8, mask Mask32x8) Mask32x8
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x16) LessMasked(y Uint32x16, mask Mask32x16) Mask32x16
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x2) LessMasked(y Uint64x2, mask Mask64x2) Mask64x2
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x4) LessMasked(y Uint64x4, mask Mask64x4) Mask64x4
+
+// LessMasked compares for less than.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x8) LessMasked(y Uint64x8, mask Mask64x8) Mask64x8
+
+/* Max */
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VMAXPS, CPU Feature: AVX
+func (x Float32x4) Max(y Float32x4) Float32x4
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VMAXPS, CPU Feature: AVX
+func (x Float32x8) Max(y Float32x8) Float32x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VMAXPS, CPU Feature: AVX512F
+func (x Float32x16) Max(y Float32x16) Float32x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VMAXPD, CPU Feature: AVX
+func (x Float64x2) Max(y Float64x2) Float64x2
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VMAXPD, CPU Feature: AVX
+func (x Float64x4) Max(y Float64x4) Float64x4
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VMAXPD, CPU Feature: AVX512F
+func (x Float64x8) Max(y Float64x8) Float64x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSB, CPU Feature: AVX
+func (x Int8x16) Max(y Int8x16) Int8x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSB, CPU Feature: AVX2
+func (x Int8x32) Max(y Int8x32) Int8x32
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSB, CPU Feature: AVX512BW
+func (x Int8x64) Max(y Int8x64) Int8x64
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSW, CPU Feature: AVX
+func (x Int16x8) Max(y Int16x8) Int16x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSW, CPU Feature: AVX2
+func (x Int16x16) Max(y Int16x16) Int16x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSW, CPU Feature: AVX512BW
+func (x Int16x32) Max(y Int16x32) Int16x32
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSD, CPU Feature: AVX
+func (x Int32x4) Max(y Int32x4) Int32x4
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSD, CPU Feature: AVX2
+func (x Int32x8) Max(y Int32x8) Int32x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSD, CPU Feature: AVX512F
+func (x Int32x16) Max(y Int32x16) Int32x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSQ, CPU Feature: AVX512F
+func (x Int64x2) Max(y Int64x2) Int64x2
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSQ, CPU Feature: AVX512F
+func (x Int64x4) Max(y Int64x4) Int64x4
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSQ, CPU Feature: AVX512F
+func (x Int64x8) Max(y Int64x8) Int64x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUB, CPU Feature: AVX
+func (x Uint8x16) Max(y Uint8x16) Uint8x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUB, CPU Feature: AVX2
+func (x Uint8x32) Max(y Uint8x32) Uint8x32
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUB, CPU Feature: AVX512BW
+func (x Uint8x64) Max(y Uint8x64) Uint8x64
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUW, CPU Feature: AVX
+func (x Uint16x8) Max(y Uint16x8) Uint16x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUW, CPU Feature: AVX2
+func (x Uint16x16) Max(y Uint16x16) Uint16x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUW, CPU Feature: AVX512BW
+func (x Uint16x32) Max(y Uint16x32) Uint16x32
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUD, CPU Feature: AVX
+func (x Uint32x4) Max(y Uint32x4) Uint32x4
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUD, CPU Feature: AVX2
+func (x Uint32x8) Max(y Uint32x8) Uint32x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUD, CPU Feature: AVX512F
+func (x Uint32x16) Max(y Uint32x16) Uint32x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUQ, CPU Feature: AVX512F
+func (x Uint64x2) Max(y Uint64x2) Uint64x2
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUQ, CPU Feature: AVX512F
+func (x Uint64x4) Max(y Uint64x4) Uint64x4
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUQ, CPU Feature: AVX512F
+func (x Uint64x8) Max(y Uint64x8) Uint64x8
+
+/* MaxMasked */
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMAXPS, CPU Feature: AVX512F
+func (x Float32x4) MaxMasked(y Float32x4, mask Mask32x4) Float32x4
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMAXPS, CPU Feature: AVX512F
+func (x Float32x8) MaxMasked(y Float32x8, mask Mask32x8) Float32x8
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMAXPS, CPU Feature: AVX512F
+func (x Float32x16) MaxMasked(y Float32x16, mask Mask32x16) Float32x16
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMAXPD, CPU Feature: AVX512F
+func (x Float64x2) MaxMasked(y Float64x2, mask Mask64x2) Float64x2
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMAXPD, CPU Feature: AVX512F
+func (x Float64x4) MaxMasked(y Float64x4, mask Mask64x4) Float64x4
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMAXPD, CPU Feature: AVX512F
+func (x Float64x8) MaxMasked(y Float64x8, mask Mask64x8) Float64x8
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXSB, CPU Feature: AVX512BW
+func (x Int8x16) MaxMasked(y Int8x16, mask Mask8x16) Int8x16
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXSB, CPU Feature: AVX512BW
+func (x Int8x32) MaxMasked(y Int8x32, mask Mask8x32) Int8x32
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXSB, CPU Feature: AVX512BW
+func (x Int8x64) MaxMasked(y Int8x64, mask Mask8x64) Int8x64
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXSW, CPU Feature: AVX512BW
+func (x Int16x8) MaxMasked(y Int16x8, mask Mask16x8) Int16x8
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXSW, CPU Feature: AVX512BW
+func (x Int16x16) MaxMasked(y Int16x16, mask Mask16x16) Int16x16
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXSW, CPU Feature: AVX512BW
+func (x Int16x32) MaxMasked(y Int16x32, mask Mask16x32) Int16x32
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXSD, CPU Feature: AVX512F
+func (x Int32x4) MaxMasked(y Int32x4, mask Mask32x4) Int32x4
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXSD, CPU Feature: AVX512F
+func (x Int32x8) MaxMasked(y Int32x8, mask Mask32x8) Int32x8
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXSD, CPU Feature: AVX512F
+func (x Int32x16) MaxMasked(y Int32x16, mask Mask32x16) Int32x16
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXSQ, CPU Feature: AVX512F
+func (x Int64x2) MaxMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXSQ, CPU Feature: AVX512F
+func (x Int64x4) MaxMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXSQ, CPU Feature: AVX512F
+func (x Int64x8) MaxMasked(y Int64x8, mask Mask64x8) Int64x8
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXUB, CPU Feature: AVX512BW
+func (x Uint8x16) MaxMasked(y Uint8x16, mask Mask8x16) Uint8x16
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXUB, CPU Feature: AVX512BW
+func (x Uint8x32) MaxMasked(y Uint8x32, mask Mask8x32) Uint8x32
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXUB, CPU Feature: AVX512BW
+func (x Uint8x64) MaxMasked(y Uint8x64, mask Mask8x64) Uint8x64
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXUW, CPU Feature: AVX512BW
+func (x Uint16x8) MaxMasked(y Uint16x8, mask Mask16x8) Uint16x8
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXUW, CPU Feature: AVX512BW
+func (x Uint16x16) MaxMasked(y Uint16x16, mask Mask16x16) Uint16x16
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXUW, CPU Feature: AVX512BW
+func (x Uint16x32) MaxMasked(y Uint16x32, mask Mask16x32) Uint16x32
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXUD, CPU Feature: AVX512F
+func (x Uint32x4) MaxMasked(y Uint32x4, mask Mask32x4) Uint32x4
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXUD, CPU Feature: AVX512F
+func (x Uint32x8) MaxMasked(y Uint32x8, mask Mask32x8) Uint32x8
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXUD, CPU Feature: AVX512F
+func (x Uint32x16) MaxMasked(y Uint32x16, mask Mask32x16) Uint32x16
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXUQ, CPU Feature: AVX512F
+func (x Uint64x2) MaxMasked(y Uint64x2, mask Mask64x2) Uint64x2
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXUQ, CPU Feature: AVX512F
+func (x Uint64x4) MaxMasked(y Uint64x4, mask Mask64x4) Uint64x4
+
+// MaxMasked computes the maximum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMAXUQ, CPU Feature: AVX512F
+func (x Uint64x8) MaxMasked(y Uint64x8, mask Mask64x8) Uint64x8
+
+/* Min */
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VMINPS, CPU Feature: AVX
+func (x Float32x4) Min(y Float32x4) Float32x4
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VMINPS, CPU Feature: AVX
+func (x Float32x8) Min(y Float32x8) Float32x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VMINPS, CPU Feature: AVX512F
+func (x Float32x16) Min(y Float32x16) Float32x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VMINPD, CPU Feature: AVX
+func (x Float64x2) Min(y Float64x2) Float64x2
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VMINPD, CPU Feature: AVX
+func (x Float64x4) Min(y Float64x4) Float64x4
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VMINPD, CPU Feature: AVX512F
+func (x Float64x8) Min(y Float64x8) Float64x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSB, CPU Feature: AVX
+func (x Int8x16) Min(y Int8x16) Int8x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSB, CPU Feature: AVX2
+func (x Int8x32) Min(y Int8x32) Int8x32
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSB, CPU Feature: AVX512BW
+func (x Int8x64) Min(y Int8x64) Int8x64
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSW, CPU Feature: AVX
+func (x Int16x8) Min(y Int16x8) Int16x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSW, CPU Feature: AVX2
+func (x Int16x16) Min(y Int16x16) Int16x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSW, CPU Feature: AVX512BW
+func (x Int16x32) Min(y Int16x32) Int16x32
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSD, CPU Feature: AVX
+func (x Int32x4) Min(y Int32x4) Int32x4
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSD, CPU Feature: AVX2
+func (x Int32x8) Min(y Int32x8) Int32x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSD, CPU Feature: AVX512F
+func (x Int32x16) Min(y Int32x16) Int32x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSQ, CPU Feature: AVX512F
+func (x Int64x2) Min(y Int64x2) Int64x2
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSQ, CPU Feature: AVX512F
+func (x Int64x4) Min(y Int64x4) Int64x4
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSQ, CPU Feature: AVX512F
+func (x Int64x8) Min(y Int64x8) Int64x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUB, CPU Feature: AVX
+func (x Uint8x16) Min(y Uint8x16) Uint8x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUB, CPU Feature: AVX2
+func (x Uint8x32) Min(y Uint8x32) Uint8x32
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUB, CPU Feature: AVX512BW
+func (x Uint8x64) Min(y Uint8x64) Uint8x64
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUW, CPU Feature: AVX
+func (x Uint16x8) Min(y Uint16x8) Uint16x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUW, CPU Feature: AVX2
+func (x Uint16x16) Min(y Uint16x16) Uint16x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUW, CPU Feature: AVX512BW
+func (x Uint16x32) Min(y Uint16x32) Uint16x32
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUD, CPU Feature: AVX
+func (x Uint32x4) Min(y Uint32x4) Uint32x4
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUD, CPU Feature: AVX2
+func (x Uint32x8) Min(y Uint32x8) Uint32x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUD, CPU Feature: AVX512F
+func (x Uint32x16) Min(y Uint32x16) Uint32x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUQ, CPU Feature: AVX512F
+func (x Uint64x2) Min(y Uint64x2) Uint64x2
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUQ, CPU Feature: AVX512F
+func (x Uint64x4) Min(y Uint64x4) Uint64x4
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUQ, CPU Feature: AVX512F
+func (x Uint64x8) Min(y Uint64x8) Uint64x8
+
+/* MinMasked */
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMINPS, CPU Feature: AVX512F
+func (x Float32x4) MinMasked(y Float32x4, mask Mask32x4) Float32x4
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMINPS, CPU Feature: AVX512F
+func (x Float32x8) MinMasked(y Float32x8, mask Mask32x8) Float32x8
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMINPS, CPU Feature: AVX512F
+func (x Float32x16) MinMasked(y Float32x16, mask Mask32x16) Float32x16
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMINPD, CPU Feature: AVX512F
+func (x Float64x2) MinMasked(y Float64x2, mask Mask64x2) Float64x2
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMINPD, CPU Feature: AVX512F
+func (x Float64x4) MinMasked(y Float64x4, mask Mask64x4) Float64x4
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMINPD, CPU Feature: AVX512F
+func (x Float64x8) MinMasked(y Float64x8, mask Mask64x8) Float64x8
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINSB, CPU Feature: AVX512BW
+func (x Int8x16) MinMasked(y Int8x16, mask Mask8x16) Int8x16
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINSB, CPU Feature: AVX512BW
+func (x Int8x32) MinMasked(y Int8x32, mask Mask8x32) Int8x32
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINSB, CPU Feature: AVX512BW
+func (x Int8x64) MinMasked(y Int8x64, mask Mask8x64) Int8x64
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINSW, CPU Feature: AVX512BW
+func (x Int16x8) MinMasked(y Int16x8, mask Mask16x8) Int16x8
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINSW, CPU Feature: AVX512BW
+func (x Int16x16) MinMasked(y Int16x16, mask Mask16x16) Int16x16
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINSW, CPU Feature: AVX512BW
+func (x Int16x32) MinMasked(y Int16x32, mask Mask16x32) Int16x32
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINSD, CPU Feature: AVX512F
+func (x Int32x4) MinMasked(y Int32x4, mask Mask32x4) Int32x4
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINSD, CPU Feature: AVX512F
+func (x Int32x8) MinMasked(y Int32x8, mask Mask32x8) Int32x8
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINSD, CPU Feature: AVX512F
+func (x Int32x16) MinMasked(y Int32x16, mask Mask32x16) Int32x16
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINSQ, CPU Feature: AVX512F
+func (x Int64x2) MinMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINSQ, CPU Feature: AVX512F
+func (x Int64x4) MinMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINSQ, CPU Feature: AVX512F
+func (x Int64x8) MinMasked(y Int64x8, mask Mask64x8) Int64x8
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINUB, CPU Feature: AVX512BW
+func (x Uint8x16) MinMasked(y Uint8x16, mask Mask8x16) Uint8x16
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINUB, CPU Feature: AVX512BW
+func (x Uint8x32) MinMasked(y Uint8x32, mask Mask8x32) Uint8x32
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINUB, CPU Feature: AVX512BW
+func (x Uint8x64) MinMasked(y Uint8x64, mask Mask8x64) Uint8x64
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINUW, CPU Feature: AVX512BW
+func (x Uint16x8) MinMasked(y Uint16x8, mask Mask16x8) Uint16x8
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINUW, CPU Feature: AVX512BW
+func (x Uint16x16) MinMasked(y Uint16x16, mask Mask16x16) Uint16x16
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINUW, CPU Feature: AVX512BW
+func (x Uint16x32) MinMasked(y Uint16x32, mask Mask16x32) Uint16x32
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINUD, CPU Feature: AVX512F
+func (x Uint32x4) MinMasked(y Uint32x4, mask Mask32x4) Uint32x4
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINUD, CPU Feature: AVX512F
+func (x Uint32x8) MinMasked(y Uint32x8, mask Mask32x8) Uint32x8
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINUD, CPU Feature: AVX512F
+func (x Uint32x16) MinMasked(y Uint32x16, mask Mask32x16) Uint32x16
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINUQ, CPU Feature: AVX512F
+func (x Uint64x2) MinMasked(y Uint64x2, mask Mask64x2) Uint64x2
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINUQ, CPU Feature: AVX512F
+func (x Uint64x4) MinMasked(y Uint64x4, mask Mask64x4) Uint64x4
+
+// MinMasked computes the minimum of corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMINUQ, CPU Feature: AVX512F
+func (x Uint64x8) MinMasked(y Uint64x8, mask Mask64x8) Uint64x8
+
+/* Mul */
+
+// Mul multiplies corresponding elements of two vectors.
+//
+// Asm: VMULPS, CPU Feature: AVX
+func (x Float32x4) Mul(y Float32x4) Float32x4
+
+// Mul multiplies corresponding elements of two vectors.
+//
+// Asm: VMULPS, CPU Feature: AVX
+func (x Float32x8) Mul(y Float32x8) Float32x8
+
+// Mul multiplies corresponding elements of two vectors.
+//
+// Asm: VMULPS, CPU Feature: AVX512F
+func (x Float32x16) Mul(y Float32x16) Float32x16
+
+// Mul multiplies corresponding elements of two vectors.
+//
+// Asm: VMULPD, CPU Feature: AVX
+func (x Float64x2) Mul(y Float64x2) Float64x2
+
+// Mul multiplies corresponding elements of two vectors.
+//
+// Asm: VMULPD, CPU Feature: AVX
+func (x Float64x4) Mul(y Float64x4) Float64x4
+
+// Mul multiplies corresponding elements of two vectors.
+//
+// Asm: VMULPD, CPU Feature: AVX512F
+func (x Float64x8) Mul(y Float64x8) Float64x8
+
+/* MulByPowOf2 */
+
+// MulByPowOf2 multiplies elements by a power of 2.
+//
+// Asm: VSCALEFPS, CPU Feature: AVX512F
+func (x Float32x4) MulByPowOf2(y Float32x4) Float32x4
+
+// MulByPowOf2 multiplies elements by a power of 2.
+//
+// Asm: VSCALEFPS, CPU Feature: AVX512F
+func (x Float32x8) MulByPowOf2(y Float32x8) Float32x8
+
+// MulByPowOf2 multiplies elements by a power of 2.
+//
+// Asm: VSCALEFPS, CPU Feature: AVX512F
+func (x Float32x16) MulByPowOf2(y Float32x16) Float32x16
+
+// MulByPowOf2 multiplies elements by a power of 2.
+//
+// Asm: VSCALEFPD, CPU Feature: AVX512F
+func (x Float64x2) MulByPowOf2(y Float64x2) Float64x2
+
+// MulByPowOf2 multiplies elements by a power of 2.
+//
+// Asm: VSCALEFPD, CPU Feature: AVX512F
+func (x Float64x4) MulByPowOf2(y Float64x4) Float64x4
+
+// MulByPowOf2 multiplies elements by a power of 2.
+//
+// Asm: VSCALEFPD, CPU Feature: AVX512F
+func (x Float64x8) MulByPowOf2(y Float64x8) Float64x8
+
+/* MulByPowOf2Masked */
+
+// MulByPowOf2Masked multiplies elements by a power of 2.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSCALEFPS, CPU Feature: AVX512F
+func (x Float32x4) MulByPowOf2Masked(y Float32x4, mask Mask32x4) Float32x4
+
+// MulByPowOf2Masked multiplies elements by a power of 2.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSCALEFPS, CPU Feature: AVX512F
+func (x Float32x8) MulByPowOf2Masked(y Float32x8, mask Mask32x8) Float32x8
+
+// MulByPowOf2Masked multiplies elements by a power of 2.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSCALEFPS, CPU Feature: AVX512F
+func (x Float32x16) MulByPowOf2Masked(y Float32x16, mask Mask32x16) Float32x16
+
+// MulByPowOf2Masked multiplies elements by a power of 2.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSCALEFPD, CPU Feature: AVX512F
+func (x Float64x2) MulByPowOf2Masked(y Float64x2, mask Mask64x2) Float64x2
+
+// MulByPowOf2Masked multiplies elements by a power of 2.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSCALEFPD, CPU Feature: AVX512F
+func (x Float64x4) MulByPowOf2Masked(y Float64x4, mask Mask64x4) Float64x4
+
+// MulByPowOf2Masked multiplies elements by a power of 2.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSCALEFPD, CPU Feature: AVX512F
+func (x Float64x8) MulByPowOf2Masked(y Float64x8, mask Mask64x8) Float64x8
+
+/* MulEvenWiden */
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULDQ, CPU Feature: AVX
+func (x Int32x4) MulEvenWiden(y Int32x4) Int64x2
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULDQ, CPU Feature: AVX2
+func (x Int32x8) MulEvenWiden(y Int32x8) Int64x4
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULDQ, CPU Feature: AVX512F
+func (x Int64x2) MulEvenWiden(y Int64x2) Int64x2
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULDQ, CPU Feature: AVX512F
+func (x Int64x4) MulEvenWiden(y Int64x4) Int64x4
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULDQ, CPU Feature: AVX512F
+func (x Int64x8) MulEvenWiden(y Int64x8) Int64x8
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULUDQ, CPU Feature: AVX
+func (x Uint32x4) MulEvenWiden(y Uint32x4) Uint64x2
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULUDQ, CPU Feature: AVX2
+func (x Uint32x8) MulEvenWiden(y Uint32x8) Uint64x4
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULUDQ, CPU Feature: AVX512F
+func (x Uint64x2) MulEvenWiden(y Uint64x2) Uint64x2
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULUDQ, CPU Feature: AVX512F
+func (x Uint64x4) MulEvenWiden(y Uint64x4) Uint64x4
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULUDQ, CPU Feature: AVX512F
+func (x Uint64x8) MulEvenWiden(y Uint64x8) Uint64x8
+
+/* MulEvenWidenMasked */
+
+// MulEvenWidenMasked multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULDQ, CPU Feature: AVX512F
+func (x Int64x2) MulEvenWidenMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// MulEvenWidenMasked multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULDQ, CPU Feature: AVX512F
+func (x Int64x4) MulEvenWidenMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// MulEvenWidenMasked multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULDQ, CPU Feature: AVX512F
+func (x Int64x8) MulEvenWidenMasked(y Int64x8, mask Mask64x8) Int64x8
+
+// MulEvenWidenMasked multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULUDQ, CPU Feature: AVX512F
+func (x Uint64x2) MulEvenWidenMasked(y Uint64x2, mask Mask64x2) Uint64x2
+
+// MulEvenWidenMasked multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULUDQ, CPU Feature: AVX512F
+func (x Uint64x4) MulEvenWidenMasked(y Uint64x4, mask Mask64x4) Uint64x4
+
+// MulEvenWidenMasked multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULUDQ, CPU Feature: AVX512F
+func (x Uint64x8) MulEvenWidenMasked(y Uint64x8, mask Mask64x8) Uint64x8
+
+/* MulHigh */
+
+// MulHigh multiplies elements and stores the high part of the result.
+//
+// Asm: VPMULHW, CPU Feature: AVX
+func (x Int16x8) MulHigh(y Int16x8) Int16x8
+
+// MulHigh multiplies elements and stores the high part of the result.
+//
+// Asm: VPMULHW, CPU Feature: AVX2
+func (x Int16x16) MulHigh(y Int16x16) Int16x16
+
+// MulHigh multiplies elements and stores the high part of the result.
+//
+// Asm: VPMULHW, CPU Feature: AVX512BW
+func (x Int16x32) MulHigh(y Int16x32) Int16x32
+
+// MulHigh multiplies elements and stores the high part of the result.
+//
+// Asm: VPMULHUW, CPU Feature: AVX
+func (x Uint16x8) MulHigh(y Uint16x8) Uint16x8
+
+// MulHigh multiplies elements and stores the high part of the result.
+//
+// Asm: VPMULHUW, CPU Feature: AVX2
+func (x Uint16x16) MulHigh(y Uint16x16) Uint16x16
+
+// MulHigh multiplies elements and stores the high part of the result.
+//
+// Asm: VPMULHUW, CPU Feature: AVX512BW
+func (x Uint16x32) MulHigh(y Uint16x32) Uint16x32
+
+/* MulHighMasked */
+
+// MulHighMasked multiplies elements and stores the high part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULHW, CPU Feature: AVX512BW
+func (x Int16x8) MulHighMasked(y Int16x8, mask Mask16x8) Int16x8
+
+// MulHighMasked multiplies elements and stores the high part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULHW, CPU Feature: AVX512BW
+func (x Int16x16) MulHighMasked(y Int16x16, mask Mask16x16) Int16x16
+
+// MulHighMasked multiplies elements and stores the high part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULHW, CPU Feature: AVX512BW
+func (x Int16x32) MulHighMasked(y Int16x32, mask Mask16x32) Int16x32
+
+// MulHighMasked multiplies elements and stores the high part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULHUW, CPU Feature: AVX512BW
+func (x Uint16x8) MulHighMasked(y Uint16x8, mask Mask16x8) Uint16x8
+
+// MulHighMasked multiplies elements and stores the high part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULHUW, CPU Feature: AVX512BW
+func (x Uint16x16) MulHighMasked(y Uint16x16, mask Mask16x16) Uint16x16
+
+// MulHighMasked multiplies elements and stores the high part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULHUW, CPU Feature: AVX512BW
+func (x Uint16x32) MulHighMasked(y Uint16x32, mask Mask16x32) Uint16x32
+
+/* MulLow */
+
+// MulLow multiplies elements and stores the low part of the result.
+//
+// Asm: VPMULLW, CPU Feature: AVX
+func (x Int16x8) MulLow(y Int16x8) Int16x8
+
+// MulLow multiplies elements and stores the low part of the result.
+//
+// Asm: VPMULLW, CPU Feature: AVX2
+func (x Int16x16) MulLow(y Int16x16) Int16x16
+
+// MulLow multiplies elements and stores the low part of the result.
+//
+// Asm: VPMULLW, CPU Feature: AVX512BW
+func (x Int16x32) MulLow(y Int16x32) Int16x32
+
+// MulLow multiplies elements and stores the low part of the result.
+//
+// Asm: VPMULLD, CPU Feature: AVX
+func (x Int32x4) MulLow(y Int32x4) Int32x4
+
+// MulLow multiplies elements and stores the low part of the result.
+//
+// Asm: VPMULLD, CPU Feature: AVX2
+func (x Int32x8) MulLow(y Int32x8) Int32x8
+
+// MulLow multiplies elements and stores the low part of the result.
+//
+// Asm: VPMULLD, CPU Feature: AVX512F
+func (x Int32x16) MulLow(y Int32x16) Int32x16
+
+// MulLow multiplies elements and stores the low part of the result.
+//
+// Asm: VPMULLQ, CPU Feature: AVX512DQ
+func (x Int64x2) MulLow(y Int64x2) Int64x2
+
+// MulLow multiplies elements and stores the low part of the result.
+//
+// Asm: VPMULLQ, CPU Feature: AVX512DQ
+func (x Int64x4) MulLow(y Int64x4) Int64x4
+
+// MulLow multiplies elements and stores the low part of the result.
+//
+// Asm: VPMULLQ, CPU Feature: AVX512DQ
+func (x Int64x8) MulLow(y Int64x8) Int64x8
+
+/* MulLowMasked */
+
+// MulLowMasked multiplies elements and stores the low part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULLW, CPU Feature: AVX512BW
+func (x Int16x8) MulLowMasked(y Int16x8, mask Mask16x8) Int16x8
+
+// MulLowMasked multiplies elements and stores the low part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULLW, CPU Feature: AVX512BW
+func (x Int16x16) MulLowMasked(y Int16x16, mask Mask16x16) Int16x16
+
+// MulLowMasked multiplies elements and stores the low part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULLW, CPU Feature: AVX512BW
+func (x Int16x32) MulLowMasked(y Int16x32, mask Mask16x32) Int16x32
+
+// MulLowMasked multiplies elements and stores the low part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULLD, CPU Feature: AVX512F
+func (x Int32x4) MulLowMasked(y Int32x4, mask Mask32x4) Int32x4
+
+// MulLowMasked multiplies elements and stores the low part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULLD, CPU Feature: AVX512F
+func (x Int32x8) MulLowMasked(y Int32x8, mask Mask32x8) Int32x8
+
+// MulLowMasked multiplies elements and stores the low part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULLD, CPU Feature: AVX512F
+func (x Int32x16) MulLowMasked(y Int32x16, mask Mask32x16) Int32x16
+
+// MulLowMasked multiplies elements and stores the low part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULLQ, CPU Feature: AVX512DQ
+func (x Int64x2) MulLowMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// MulLowMasked multiplies elements and stores the low part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULLQ, CPU Feature: AVX512DQ
+func (x Int64x4) MulLowMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// MulLowMasked multiplies elements and stores the low part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULLQ, CPU Feature: AVX512DQ
+func (x Int64x8) MulLowMasked(y Int64x8, mask Mask64x8) Int64x8
+
+/* MulMasked */
+
+// MulMasked multiplies corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMULPS, CPU Feature: AVX512F
+func (x Float32x4) MulMasked(y Float32x4, mask Mask32x4) Float32x4
+
+// MulMasked multiplies corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMULPS, CPU Feature: AVX512F
+func (x Float32x8) MulMasked(y Float32x8, mask Mask32x8) Float32x8
+
+// MulMasked multiplies corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMULPS, CPU Feature: AVX512F
+func (x Float32x16) MulMasked(y Float32x16, mask Mask32x16) Float32x16
+
+// MulMasked multiplies corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMULPD, CPU Feature: AVX512F
+func (x Float64x2) MulMasked(y Float64x2, mask Mask64x2) Float64x2
+
+// MulMasked multiplies corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMULPD, CPU Feature: AVX512F
+func (x Float64x4) MulMasked(y Float64x4, mask Mask64x4) Float64x4
+
+// MulMasked multiplies corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VMULPD, CPU Feature: AVX512F
+func (x Float64x8) MulMasked(y Float64x8, mask Mask64x8) Float64x8
+
+/* NotEqual */
+
+// NotEqual compares for inequality.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x4) NotEqual(y Float32x4) Mask32x4
+
+// NotEqual compares for inequality.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x8) NotEqual(y Float32x8) Mask32x8
+
+// NotEqual compares for inequality.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) NotEqual(y Float32x16) Mask32x16
+
+// NotEqual compares for inequality.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x2) NotEqual(y Float64x2) Mask64x2
+
+// NotEqual compares for inequality.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x4) NotEqual(y Float64x4) Mask64x4
+
+// NotEqual compares for inequality.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) NotEqual(y Float64x8) Mask64x8
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x16) NotEqual(y Int8x16) Mask8x16
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x32) NotEqual(y Int8x32) Mask8x32
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x64) NotEqual(y Int8x64) Mask8x64
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x8) NotEqual(y Int16x8) Mask16x8
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x16) NotEqual(y Int16x16) Mask16x16
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x32) NotEqual(y Int16x32) Mask16x32
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x4) NotEqual(y Int32x4) Mask32x4
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x8) NotEqual(y Int32x8) Mask32x8
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x16) NotEqual(y Int32x16) Mask32x16
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x2) NotEqual(y Int64x2) Mask64x2
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x4) NotEqual(y Int64x4) Mask64x4
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x8) NotEqual(y Int64x8) Mask64x8
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x16) NotEqual(y Uint8x16) Mask8x16
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x32) NotEqual(y Uint8x32) Mask8x32
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x64) NotEqual(y Uint8x64) Mask8x64
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x8) NotEqual(y Uint16x8) Mask16x8
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x16) NotEqual(y Uint16x16) Mask16x16
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x32) NotEqual(y Uint16x32) Mask16x32
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x4) NotEqual(y Uint32x4) Mask32x4
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x8) NotEqual(y Uint32x8) Mask32x8
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x16) NotEqual(y Uint32x16) Mask32x16
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x2) NotEqual(y Uint64x2) Mask64x2
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x4) NotEqual(y Uint64x4) Mask64x4
+
+// NotEqual compares for inequality.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x8) NotEqual(y Uint64x8) Mask64x8
+
+/* NotEqualMasked */
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x4) NotEqualMasked(y Float32x4, mask Mask32x4) Mask32x4
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x8) NotEqualMasked(y Float32x8, mask Mask32x8) Mask32x8
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPS, CPU Feature: AVX512F
+func (x Float32x16) NotEqualMasked(y Float32x16, mask Mask32x16) Mask32x16
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x2) NotEqualMasked(y Float64x2, mask Mask64x2) Mask64x2
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x4) NotEqualMasked(y Float64x4, mask Mask64x4) Mask64x4
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VCMPPD, CPU Feature: AVX512F
+func (x Float64x8) NotEqualMasked(y Float64x8, mask Mask64x8) Mask64x8
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x16) NotEqualMasked(y Int8x16, mask Mask8x16) Mask8x16
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x32) NotEqualMasked(y Int8x32, mask Mask8x32) Mask8x32
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPB, CPU Feature: AVX512BW
+func (x Int8x64) NotEqualMasked(y Int8x64, mask Mask8x64) Mask8x64
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x8) NotEqualMasked(y Int16x8, mask Mask16x8) Mask16x8
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x16) NotEqualMasked(y Int16x16, mask Mask16x16) Mask16x16
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPW, CPU Feature: AVX512BW
+func (x Int16x32) NotEqualMasked(y Int16x32, mask Mask16x32) Mask16x32
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x4) NotEqualMasked(y Int32x4, mask Mask32x4) Mask32x4
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x8) NotEqualMasked(y Int32x8, mask Mask32x8) Mask32x8
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPD, CPU Feature: AVX512F
+func (x Int32x16) NotEqualMasked(y Int32x16, mask Mask32x16) Mask32x16
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x2) NotEqualMasked(y Int64x2, mask Mask64x2) Mask64x2
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x4) NotEqualMasked(y Int64x4, mask Mask64x4) Mask64x4
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512F
+func (x Int64x8) NotEqualMasked(y Int64x8, mask Mask64x8) Mask64x8
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x16) NotEqualMasked(y Uint8x16, mask Mask8x16) Mask8x16
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x32) NotEqualMasked(y Uint8x32, mask Mask8x32) Mask8x32
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512BW
+func (x Uint8x64) NotEqualMasked(y Uint8x64, mask Mask8x64) Mask8x64
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x8) NotEqualMasked(y Uint16x8, mask Mask16x8) Mask16x8
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x16) NotEqualMasked(y Uint16x16, mask Mask16x16) Mask16x16
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512BW
+func (x Uint16x32) NotEqualMasked(y Uint16x32, mask Mask16x32) Mask16x32
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x4) NotEqualMasked(y Uint32x4, mask Mask32x4) Mask32x4
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x8) NotEqualMasked(y Uint32x8, mask Mask32x8) Mask32x8
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512F
+func (x Uint32x16) NotEqualMasked(y Uint32x16, mask Mask32x16) Mask32x16
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x2) NotEqualMasked(y Uint64x2, mask Mask64x2) Mask64x2
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x4) NotEqualMasked(y Uint64x4, mask Mask64x4) Mask64x4
+
+// NotEqualMasked compares for inequality.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512F
+func (x Uint64x8) NotEqualMasked(y Uint64x8, mask Mask64x8) Mask64x8
+
+/* Or */
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Int8x16) Or(y Int8x16) Int8x16
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Int8x32) Or(y Int8x32) Int8x32
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Int16x8) Or(y Int16x8) Int16x8
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Int16x16) Or(y Int16x16) Int16x16
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Int32x4) Or(y Int32x4) Int32x4
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Int32x8) Or(y Int32x8) Int32x8
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPORD, CPU Feature: AVX512F
+func (x Int32x16) Or(y Int32x16) Int32x16
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Int64x2) Or(y Int64x2) Int64x2
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Int64x4) Or(y Int64x4) Int64x4
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPORQ, CPU Feature: AVX512F
+func (x Int64x8) Or(y Int64x8) Int64x8
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Uint8x16) Or(y Uint8x16) Uint8x16
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Uint8x32) Or(y Uint8x32) Uint8x32
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Uint16x8) Or(y Uint16x8) Uint16x8
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Uint16x16) Or(y Uint16x16) Uint16x16
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Uint32x4) Or(y Uint32x4) Uint32x4
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Uint32x8) Or(y Uint32x8) Uint32x8
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPORD, CPU Feature: AVX512F
+func (x Uint32x16) Or(y Uint32x16) Uint32x16
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Uint64x2) Or(y Uint64x2) Uint64x2
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Uint64x4) Or(y Uint64x4) Uint64x4
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPORQ, CPU Feature: AVX512F
+func (x Uint64x8) Or(y Uint64x8) Uint64x8
+
+/* OrMasked */
+
+// OrMasked performs a bitwise OR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPORD, CPU Feature: AVX512F
+func (x Int32x4) OrMasked(y Int32x4, mask Mask32x4) Int32x4
+
+// OrMasked performs a bitwise OR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPORD, CPU Feature: AVX512F
+func (x Int32x8) OrMasked(y Int32x8, mask Mask32x8) Int32x8
+
+// OrMasked performs a bitwise OR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPORD, CPU Feature: AVX512F
+func (x Int32x16) OrMasked(y Int32x16, mask Mask32x16) Int32x16
+
+// OrMasked performs a bitwise OR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPORQ, CPU Feature: AVX512F
+func (x Int64x2) OrMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// OrMasked performs a bitwise OR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPORQ, CPU Feature: AVX512F
+func (x Int64x4) OrMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// OrMasked performs a bitwise OR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPORQ, CPU Feature: AVX512F
+func (x Int64x8) OrMasked(y Int64x8, mask Mask64x8) Int64x8
+
+// OrMasked performs a bitwise OR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPORD, CPU Feature: AVX512F
+func (x Uint32x4) OrMasked(y Uint32x4, mask Mask32x4) Uint32x4
+
+// OrMasked performs a bitwise OR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPORD, CPU Feature: AVX512F
+func (x Uint32x8) OrMasked(y Uint32x8, mask Mask32x8) Uint32x8
+
+// OrMasked performs a bitwise OR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPORD, CPU Feature: AVX512F
+func (x Uint32x16) OrMasked(y Uint32x16, mask Mask32x16) Uint32x16
+
+// OrMasked performs a bitwise OR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPORQ, CPU Feature: AVX512F
+func (x Uint64x2) OrMasked(y Uint64x2, mask Mask64x2) Uint64x2
+
+// OrMasked performs a bitwise OR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPORQ, CPU Feature: AVX512F
+func (x Uint64x4) OrMasked(y Uint64x4, mask Mask64x4) Uint64x4
+
+// OrMasked performs a bitwise OR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPORQ, CPU Feature: AVX512F
+func (x Uint64x8) OrMasked(y Uint64x8, mask Mask64x8) Uint64x8
+
+/* PairDotProd */
+
+// PairDotProd multiplies the elements and add the pairs together,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// Asm: VPMADDWD, CPU Feature: AVX
+func (x Int16x8) PairDotProd(y Int16x8) Int32x4
+
+// PairDotProd multiplies the elements and add the pairs together,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// Asm: VPMADDWD, CPU Feature: AVX2
+func (x Int16x16) PairDotProd(y Int16x16) Int32x8
+
+// PairDotProd multiplies the elements and add the pairs together,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// Asm: VPMADDWD, CPU Feature: AVX512BW
+func (x Int16x32) PairDotProd(y Int16x32) Int32x16
+
+/* PairDotProdAccumulate */
+
+// PairDotProdAccumulate performs dot products on pairs of elements of x and y and then adds z.
+//
+// Asm: VPDPWSSD, CPU Feature: AVXVNNI
+func (x Int16x8) PairDotProdAccumulate(y Int16x8, z Int32x4) Int32x4
+
+// PairDotProdAccumulate performs dot products on pairs of elements of x and y and then adds z.
+//
+// Asm: VPDPWSSD, CPU Feature: AVXVNNI
+func (x Int16x16) PairDotProdAccumulate(y Int16x16, z Int32x8) Int32x8
+
+// PairDotProdAccumulate performs dot products on pairs of elements of x and y and then adds z.
+//
+// Asm: VPDPWSSD, CPU Feature: AVX512VNNI
+func (x Int16x32) PairDotProdAccumulate(y Int16x32, z Int32x16) Int32x16
+
+/* PairDotProdAccumulateMasked */
+
+// PairDotProdAccumulateMasked performs dot products on pairs of elements of x and y and then adds z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPDPWSSD, CPU Feature: AVX512VNNI
+func (x Int16x8) PairDotProdAccumulateMasked(y Int16x8, z Int32x4, mask Mask32x4) Int32x4
+
+// PairDotProdAccumulateMasked performs dot products on pairs of elements of x and y and then adds z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPDPWSSD, CPU Feature: AVX512VNNI
+func (x Int16x16) PairDotProdAccumulateMasked(y Int16x16, z Int32x8, mask Mask32x8) Int32x8
+
+// PairDotProdAccumulateMasked performs dot products on pairs of elements of x and y and then adds z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPDPWSSD, CPU Feature: AVX512VNNI
+func (x Int16x32) PairDotProdAccumulateMasked(y Int16x32, z Int32x16, mask Mask32x16) Int32x16
+
+/* PairDotProdMasked */
+
+// PairDotProdMasked multiplies the elements and add the pairs together,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMADDWD, CPU Feature: AVX512BW
+func (x Int16x8) PairDotProdMasked(y Int16x8, mask Mask16x8) Int32x4
+
+// PairDotProdMasked multiplies the elements and add the pairs together,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMADDWD, CPU Feature: AVX512BW
+func (x Int16x16) PairDotProdMasked(y Int16x16, mask Mask16x16) Int32x8
+
+// PairDotProdMasked multiplies the elements and add the pairs together,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMADDWD, CPU Feature: AVX512BW
+func (x Int16x32) PairDotProdMasked(y Int16x32, mask Mask16x32) Int32x16
+
+/* PairwiseAdd */
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VHADDPS, CPU Feature: AVX
+func (x Float32x4) PairwiseAdd(y Float32x4) Float32x4
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VHADDPS, CPU Feature: AVX
+func (x Float32x8) PairwiseAdd(y Float32x8) Float32x8
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VHADDPD, CPU Feature: AVX
+func (x Float64x2) PairwiseAdd(y Float64x2) Float64x2
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VHADDPD, CPU Feature: AVX
+func (x Float64x4) PairwiseAdd(y Float64x4) Float64x4
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDW, CPU Feature: AVX
+func (x Int16x8) PairwiseAdd(y Int16x8) Int16x8
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDW, CPU Feature: AVX2
+func (x Int16x16) PairwiseAdd(y Int16x16) Int16x16
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDD, CPU Feature: AVX
+func (x Int32x4) PairwiseAdd(y Int32x4) Int32x4
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDD, CPU Feature: AVX2
+func (x Int32x8) PairwiseAdd(y Int32x8) Int32x8
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDW, CPU Feature: AVX
+func (x Uint16x8) PairwiseAdd(y Uint16x8) Uint16x8
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDW, CPU Feature: AVX2
+func (x Uint16x16) PairwiseAdd(y Uint16x16) Uint16x16
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDD, CPU Feature: AVX
+func (x Uint32x4) PairwiseAdd(y Uint32x4) Uint32x4
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDD, CPU Feature: AVX2
+func (x Uint32x8) PairwiseAdd(y Uint32x8) Uint32x8
+
+/* PairwiseSub */
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VHSUBPS, CPU Feature: AVX
+func (x Float32x4) PairwiseSub(y Float32x4) Float32x4
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VHSUBPS, CPU Feature: AVX
+func (x Float32x8) PairwiseSub(y Float32x8) Float32x8
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VHSUBPD, CPU Feature: AVX
+func (x Float64x2) PairwiseSub(y Float64x2) Float64x2
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VHSUBPD, CPU Feature: AVX
+func (x Float64x4) PairwiseSub(y Float64x4) Float64x4
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBW, CPU Feature: AVX
+func (x Int16x8) PairwiseSub(y Int16x8) Int16x8
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBW, CPU Feature: AVX2
+func (x Int16x16) PairwiseSub(y Int16x16) Int16x16
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBD, CPU Feature: AVX
+func (x Int32x4) PairwiseSub(y Int32x4) Int32x4
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBD, CPU Feature: AVX2
+func (x Int32x8) PairwiseSub(y Int32x8) Int32x8
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBW, CPU Feature: AVX
+func (x Uint16x8) PairwiseSub(y Uint16x8) Uint16x8
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBW, CPU Feature: AVX2
+func (x Uint16x16) PairwiseSub(y Uint16x16) Uint16x16
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBD, CPU Feature: AVX
+func (x Uint32x4) PairwiseSub(y Uint32x4) Uint32x4
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBD, CPU Feature: AVX2
+func (x Uint32x8) PairwiseSub(y Uint32x8) Uint32x8
+
+/* Permute */
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMB, CPU Feature: AVX512VBMI
+func (x Int8x16) Permute(indices Uint8x16) Int8x16
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMB, CPU Feature: AVX512VBMI
+func (x Uint8x16) Permute(indices Uint8x16) Uint8x16
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMB, CPU Feature: AVX512VBMI
+func (x Int8x32) Permute(indices Uint8x32) Int8x32
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMB, CPU Feature: AVX512VBMI
+func (x Uint8x32) Permute(indices Uint8x32) Uint8x32
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMB, CPU Feature: AVX512VBMI
+func (x Int8x64) Permute(indices Uint8x64) Int8x64
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMB, CPU Feature: AVX512VBMI
+func (x Uint8x64) Permute(indices Uint8x64) Uint8x64
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMW, CPU Feature: AVX512BW
+func (x Int16x8) Permute(indices Uint16x8) Int16x8
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMW, CPU Feature: AVX512BW
+func (x Uint16x8) Permute(indices Uint16x8) Uint16x8
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMW, CPU Feature: AVX512BW
+func (x Int16x16) Permute(indices Uint16x16) Int16x16
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMW, CPU Feature: AVX512BW
+func (x Uint16x16) Permute(indices Uint16x16) Uint16x16
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMW, CPU Feature: AVX512BW
+func (x Int16x32) Permute(indices Uint16x32) Int16x32
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMW, CPU Feature: AVX512BW
+func (x Uint16x32) Permute(indices Uint16x32) Uint16x32
+
+// Permute performs a full permutation of vector x using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMPS, CPU Feature: AVX2
+func (x Float32x8) Permute(indices Uint32x8) Float32x8
+
+// Permute performs a full permutation of vector x using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMD, CPU Feature: AVX2
+func (x Int32x8) Permute(indices Uint32x8) Int32x8
+
+// Permute performs a full permutation of vector x using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMD, CPU Feature: AVX2
+func (x Uint32x8) Permute(indices Uint32x8) Uint32x8
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMPS, CPU Feature: AVX512F
+func (x Float32x16) Permute(indices Uint32x16) Float32x16
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMD, CPU Feature: AVX512F
+func (x Int32x16) Permute(indices Uint32x16) Int32x16
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMD, CPU Feature: AVX512F
+func (x Uint32x16) Permute(indices Uint32x16) Uint32x16
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMPD, CPU Feature: AVX512F
+func (x Float64x4) Permute(indices Uint64x4) Float64x4
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMQ, CPU Feature: AVX512F
+func (x Int64x4) Permute(indices Uint64x4) Int64x4
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMQ, CPU Feature: AVX512F
+func (x Uint64x4) Permute(indices Uint64x4) Uint64x4
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMPD, CPU Feature: AVX512F
+func (x Float64x8) Permute(indices Uint64x8) Float64x8
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMQ, CPU Feature: AVX512F
+func (x Int64x8) Permute(indices Uint64x8) Int64x8
+
+// Permute performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// Asm: VPERMQ, CPU Feature: AVX512F
+func (x Uint64x8) Permute(indices Uint64x8) Uint64x8
+
+/* Permute2 */
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2B, CPU Feature: AVX512VBMI
+func (x Int8x16) Permute2(y Int8x16, indices Uint8x16) Int8x16
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2B, CPU Feature: AVX512VBMI
+func (x Uint8x16) Permute2(y Uint8x16, indices Uint8x16) Uint8x16
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2B, CPU Feature: AVX512VBMI
+func (x Int8x32) Permute2(y Int8x32, indices Uint8x32) Int8x32
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2B, CPU Feature: AVX512VBMI
+func (x Uint8x32) Permute2(y Uint8x32, indices Uint8x32) Uint8x32
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2B, CPU Feature: AVX512VBMI
+func (x Int8x64) Permute2(y Int8x64, indices Uint8x64) Int8x64
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2B, CPU Feature: AVX512VBMI
+func (x Uint8x64) Permute2(y Uint8x64, indices Uint8x64) Uint8x64
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2W, CPU Feature: AVX512BW
+func (x Int16x8) Permute2(y Int16x8, indices Uint16x8) Int16x8
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2W, CPU Feature: AVX512BW
+func (x Uint16x8) Permute2(y Uint16x8, indices Uint16x8) Uint16x8
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2W, CPU Feature: AVX512BW
+func (x Int16x16) Permute2(y Int16x16, indices Uint16x16) Int16x16
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2W, CPU Feature: AVX512BW
+func (x Uint16x16) Permute2(y Uint16x16, indices Uint16x16) Uint16x16
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2W, CPU Feature: AVX512BW
+func (x Int16x32) Permute2(y Int16x32, indices Uint16x32) Int16x32
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2W, CPU Feature: AVX512BW
+func (x Uint16x32) Permute2(y Uint16x32, indices Uint16x32) Uint16x32
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2PS, CPU Feature: AVX512F
+func (x Float32x4) Permute2(y Float32x4, indices Uint32x4) Float32x4
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2D, CPU Feature: AVX512F
+func (x Int32x4) Permute2(y Int32x4, indices Uint32x4) Int32x4
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2D, CPU Feature: AVX512F
+func (x Uint32x4) Permute2(y Uint32x4, indices Uint32x4) Uint32x4
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2PS, CPU Feature: AVX512F
+func (x Float32x8) Permute2(y Float32x8, indices Uint32x8) Float32x8
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2D, CPU Feature: AVX512F
+func (x Int32x8) Permute2(y Int32x8, indices Uint32x8) Int32x8
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2D, CPU Feature: AVX512F
+func (x Uint32x8) Permute2(y Uint32x8, indices Uint32x8) Uint32x8
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2PS, CPU Feature: AVX512F
+func (x Float32x16) Permute2(y Float32x16, indices Uint32x16) Float32x16
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2D, CPU Feature: AVX512F
+func (x Int32x16) Permute2(y Int32x16, indices Uint32x16) Int32x16
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2D, CPU Feature: AVX512F
+func (x Uint32x16) Permute2(y Uint32x16, indices Uint32x16) Uint32x16
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2PD, CPU Feature: AVX512F
+func (x Float64x2) Permute2(y Float64x2, indices Uint64x2) Float64x2
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2Q, CPU Feature: AVX512F
+func (x Int64x2) Permute2(y Int64x2, indices Uint64x2) Int64x2
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2Q, CPU Feature: AVX512F
+func (x Uint64x2) Permute2(y Uint64x2, indices Uint64x2) Uint64x2
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2PD, CPU Feature: AVX512F
+func (x Float64x4) Permute2(y Float64x4, indices Uint64x4) Float64x4
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2Q, CPU Feature: AVX512F
+func (x Int64x4) Permute2(y Int64x4, indices Uint64x4) Int64x4
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2Q, CPU Feature: AVX512F
+func (x Uint64x4) Permute2(y Uint64x4, indices Uint64x4) Uint64x4
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2PD, CPU Feature: AVX512F
+func (x Float64x8) Permute2(y Float64x8, indices Uint64x8) Float64x8
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2Q, CPU Feature: AVX512F
+func (x Int64x8) Permute2(y Int64x8, indices Uint64x8) Int64x8
+
+// Permute2 performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// Asm: VPERMI2Q, CPU Feature: AVX512F
+func (x Uint64x8) Permute2(y Uint64x8, indices Uint64x8) Uint64x8
+
+/* Permute2Masked */
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2B, CPU Feature: AVX512VBMI
+func (x Int8x16) Permute2Masked(y Int8x16, indices Uint8x16, mask Mask8x16) Int8x16
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2B, CPU Feature: AVX512VBMI
+func (x Uint8x16) Permute2Masked(y Uint8x16, indices Uint8x16, mask Mask8x16) Uint8x16
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2B, CPU Feature: AVX512VBMI
+func (x Int8x32) Permute2Masked(y Int8x32, indices Uint8x32, mask Mask8x32) Int8x32
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2B, CPU Feature: AVX512VBMI
+func (x Uint8x32) Permute2Masked(y Uint8x32, indices Uint8x32, mask Mask8x32) Uint8x32
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2B, CPU Feature: AVX512VBMI
+func (x Int8x64) Permute2Masked(y Int8x64, indices Uint8x64, mask Mask8x64) Int8x64
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2B, CPU Feature: AVX512VBMI
+func (x Uint8x64) Permute2Masked(y Uint8x64, indices Uint8x64, mask Mask8x64) Uint8x64
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2W, CPU Feature: AVX512BW
+func (x Int16x8) Permute2Masked(y Int16x8, indices Uint16x8, mask Mask16x8) Int16x8
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2W, CPU Feature: AVX512BW
+func (x Uint16x8) Permute2Masked(y Uint16x8, indices Uint16x8, mask Mask16x8) Uint16x8
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2W, CPU Feature: AVX512BW
+func (x Int16x16) Permute2Masked(y Int16x16, indices Uint16x16, mask Mask16x16) Int16x16
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2W, CPU Feature: AVX512BW
+func (x Uint16x16) Permute2Masked(y Uint16x16, indices Uint16x16, mask Mask16x16) Uint16x16
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2W, CPU Feature: AVX512BW
+func (x Int16x32) Permute2Masked(y Int16x32, indices Uint16x32, mask Mask16x32) Int16x32
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2W, CPU Feature: AVX512BW
+func (x Uint16x32) Permute2Masked(y Uint16x32, indices Uint16x32, mask Mask16x32) Uint16x32
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2PS, CPU Feature: AVX512F
+func (x Float32x4) Permute2Masked(y Float32x4, indices Uint32x4, mask Mask32x4) Float32x4
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2D, CPU Feature: AVX512F
+func (x Int32x4) Permute2Masked(y Int32x4, indices Uint32x4, mask Mask32x4) Int32x4
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2D, CPU Feature: AVX512F
+func (x Uint32x4) Permute2Masked(y Uint32x4, indices Uint32x4, mask Mask32x4) Uint32x4
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2PS, CPU Feature: AVX512F
+func (x Float32x8) Permute2Masked(y Float32x8, indices Uint32x8, mask Mask32x8) Float32x8
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2D, CPU Feature: AVX512F
+func (x Int32x8) Permute2Masked(y Int32x8, indices Uint32x8, mask Mask32x8) Int32x8
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2D, CPU Feature: AVX512F
+func (x Uint32x8) Permute2Masked(y Uint32x8, indices Uint32x8, mask Mask32x8) Uint32x8
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2PS, CPU Feature: AVX512F
+func (x Float32x16) Permute2Masked(y Float32x16, indices Uint32x16, mask Mask32x16) Float32x16
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2D, CPU Feature: AVX512F
+func (x Int32x16) Permute2Masked(y Int32x16, indices Uint32x16, mask Mask32x16) Int32x16
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2D, CPU Feature: AVX512F
+func (x Uint32x16) Permute2Masked(y Uint32x16, indices Uint32x16, mask Mask32x16) Uint32x16
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2PD, CPU Feature: AVX512F
+func (x Float64x2) Permute2Masked(y Float64x2, indices Uint64x2, mask Mask64x2) Float64x2
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2Q, CPU Feature: AVX512F
+func (x Int64x2) Permute2Masked(y Int64x2, indices Uint64x2, mask Mask64x2) Int64x2
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2Q, CPU Feature: AVX512F
+func (x Uint64x2) Permute2Masked(y Uint64x2, indices Uint64x2, mask Mask64x2) Uint64x2
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2PD, CPU Feature: AVX512F
+func (x Float64x4) Permute2Masked(y Float64x4, indices Uint64x4, mask Mask64x4) Float64x4
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2Q, CPU Feature: AVX512F
+func (x Int64x4) Permute2Masked(y Int64x4, indices Uint64x4, mask Mask64x4) Int64x4
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2Q, CPU Feature: AVX512F
+func (x Uint64x4) Permute2Masked(y Uint64x4, indices Uint64x4, mask Mask64x4) Uint64x4
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2PD, CPU Feature: AVX512F
+func (x Float64x8) Permute2Masked(y Float64x8, indices Uint64x8, mask Mask64x8) Float64x8
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2Q, CPU Feature: AVX512F
+func (x Int64x8) Permute2Masked(y Int64x8, indices Uint64x8, mask Mask64x8) Int64x8
+
+// Permute2Masked performs a full permutation of vector x, y using indices:
+// result := {xy[indices[0]], xy[indices[1]], ..., xy[indices[n]]}
+// where xy is x appending y.
+// Only the needed bits to represent xy's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMI2Q, CPU Feature: AVX512F
+func (x Uint64x8) Permute2Masked(y Uint64x8, indices Uint64x8, mask Mask64x8) Uint64x8
+
+/* PermuteMasked */
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMB, CPU Feature: AVX512VBMI
+func (x Int8x16) PermuteMasked(indices Uint8x16, mask Mask8x16) Int8x16
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMB, CPU Feature: AVX512VBMI
+func (x Uint8x16) PermuteMasked(indices Uint8x16, mask Mask8x16) Uint8x16
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMB, CPU Feature: AVX512VBMI
+func (x Int8x32) PermuteMasked(indices Uint8x32, mask Mask8x32) Int8x32
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMB, CPU Feature: AVX512VBMI
+func (x Uint8x32) PermuteMasked(indices Uint8x32, mask Mask8x32) Uint8x32
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMB, CPU Feature: AVX512VBMI
+func (x Int8x64) PermuteMasked(indices Uint8x64, mask Mask8x64) Int8x64
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMB, CPU Feature: AVX512VBMI
+func (x Uint8x64) PermuteMasked(indices Uint8x64, mask Mask8x64) Uint8x64
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMW, CPU Feature: AVX512BW
+func (x Int16x8) PermuteMasked(indices Uint16x8, mask Mask16x8) Int16x8
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMW, CPU Feature: AVX512BW
+func (x Uint16x8) PermuteMasked(indices Uint16x8, mask Mask16x8) Uint16x8
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMW, CPU Feature: AVX512BW
+func (x Int16x16) PermuteMasked(indices Uint16x16, mask Mask16x16) Int16x16
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMW, CPU Feature: AVX512BW
+func (x Uint16x16) PermuteMasked(indices Uint16x16, mask Mask16x16) Uint16x16
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMW, CPU Feature: AVX512BW
+func (x Int16x32) PermuteMasked(indices Uint16x32, mask Mask16x32) Int16x32
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMW, CPU Feature: AVX512BW
+func (x Uint16x32) PermuteMasked(indices Uint16x32, mask Mask16x32) Uint16x32
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMPS, CPU Feature: AVX512F
+func (x Float32x8) PermuteMasked(indices Uint32x8, mask Mask32x8) Float32x8
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMD, CPU Feature: AVX512F
+func (x Int32x8) PermuteMasked(indices Uint32x8, mask Mask32x8) Int32x8
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMD, CPU Feature: AVX512F
+func (x Uint32x8) PermuteMasked(indices Uint32x8, mask Mask32x8) Uint32x8
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMPS, CPU Feature: AVX512F
+func (x Float32x16) PermuteMasked(indices Uint32x16, mask Mask32x16) Float32x16
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMD, CPU Feature: AVX512F
+func (x Int32x16) PermuteMasked(indices Uint32x16, mask Mask32x16) Int32x16
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMD, CPU Feature: AVX512F
+func (x Uint32x16) PermuteMasked(indices Uint32x16, mask Mask32x16) Uint32x16
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMPD, CPU Feature: AVX512F
+func (x Float64x4) PermuteMasked(indices Uint64x4, mask Mask64x4) Float64x4
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMQ, CPU Feature: AVX512F
+func (x Int64x4) PermuteMasked(indices Uint64x4, mask Mask64x4) Int64x4
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMQ, CPU Feature: AVX512F
+func (x Uint64x4) PermuteMasked(indices Uint64x4, mask Mask64x4) Uint64x4
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMPD, CPU Feature: AVX512F
+func (x Float64x8) PermuteMasked(indices Uint64x8, mask Mask64x8) Float64x8
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMQ, CPU Feature: AVX512F
+func (x Int64x8) PermuteMasked(indices Uint64x8, mask Mask64x8) Int64x8
+
+// PermuteMasked performs a full permutation of vector y using indices:
+// result := {x[indices[0]], x[indices[1]], ..., x[indices[n]]}
+// Only the needed bits to represent x's index are used in indices' elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPERMQ, CPU Feature: AVX512F
+func (x Uint64x8) PermuteMasked(indices Uint64x8, mask Mask64x8) Uint64x8
+
+/* PopCount */
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512BITALG
+func (x Int8x16) PopCount() Int8x16
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512BITALG
+func (x Int8x32) PopCount() Int8x32
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512BITALG
+func (x Int8x64) PopCount() Int8x64
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512BITALG
+func (x Int16x8) PopCount() Int16x8
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512BITALG
+func (x Int16x16) PopCount() Int16x16
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512BITALG
+func (x Int16x32) PopCount() Int16x32
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512VPOPCNTDQ
+func (x Int32x4) PopCount() Int32x4
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512VPOPCNTDQ
+func (x Int32x8) PopCount() Int32x8
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512VPOPCNTDQ
+func (x Int32x16) PopCount() Int32x16
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512VPOPCNTDQ
+func (x Int64x2) PopCount() Int64x2
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512VPOPCNTDQ
+func (x Int64x4) PopCount() Int64x4
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512VPOPCNTDQ
+func (x Int64x8) PopCount() Int64x8
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512BITALG
+func (x Uint8x16) PopCount() Uint8x16
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512BITALG
+func (x Uint8x32) PopCount() Uint8x32
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512BITALG
+func (x Uint8x64) PopCount() Uint8x64
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512BITALG
+func (x Uint16x8) PopCount() Uint16x8
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512BITALG
+func (x Uint16x16) PopCount() Uint16x16
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512BITALG
+func (x Uint16x32) PopCount() Uint16x32
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512VPOPCNTDQ
+func (x Uint32x4) PopCount() Uint32x4
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512VPOPCNTDQ
+func (x Uint32x8) PopCount() Uint32x8
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512VPOPCNTDQ
+func (x Uint32x16) PopCount() Uint32x16
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512VPOPCNTDQ
+func (x Uint64x2) PopCount() Uint64x2
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512VPOPCNTDQ
+func (x Uint64x4) PopCount() Uint64x4
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512VPOPCNTDQ
+func (x Uint64x8) PopCount() Uint64x8
+
+/* PopCountMasked */
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512BITALG
+func (x Int8x16) PopCountMasked(mask Mask8x16) Int8x16
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512BITALG
+func (x Int8x32) PopCountMasked(mask Mask8x32) Int8x32
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512BITALG
+func (x Int8x64) PopCountMasked(mask Mask8x64) Int8x64
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512BITALG
+func (x Int16x8) PopCountMasked(mask Mask16x8) Int16x8
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512BITALG
+func (x Int16x16) PopCountMasked(mask Mask16x16) Int16x16
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512BITALG
+func (x Int16x32) PopCountMasked(mask Mask16x32) Int16x32
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512VPOPCNTDQ
+func (x Int32x4) PopCountMasked(mask Mask32x4) Int32x4
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512VPOPCNTDQ
+func (x Int32x8) PopCountMasked(mask Mask32x8) Int32x8
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512VPOPCNTDQ
+func (x Int32x16) PopCountMasked(mask Mask32x16) Int32x16
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512VPOPCNTDQ
+func (x Int64x2) PopCountMasked(mask Mask64x2) Int64x2
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512VPOPCNTDQ
+func (x Int64x4) PopCountMasked(mask Mask64x4) Int64x4
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512VPOPCNTDQ
+func (x Int64x8) PopCountMasked(mask Mask64x8) Int64x8
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512BITALG
+func (x Uint8x16) PopCountMasked(mask Mask8x16) Uint8x16
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512BITALG
+func (x Uint8x32) PopCountMasked(mask Mask8x32) Uint8x32
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512BITALG
+func (x Uint8x64) PopCountMasked(mask Mask8x64) Uint8x64
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512BITALG
+func (x Uint16x8) PopCountMasked(mask Mask16x8) Uint16x8
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512BITALG
+func (x Uint16x16) PopCountMasked(mask Mask16x16) Uint16x16
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512BITALG
+func (x Uint16x32) PopCountMasked(mask Mask16x32) Uint16x32
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512VPOPCNTDQ
+func (x Uint32x4) PopCountMasked(mask Mask32x4) Uint32x4
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512VPOPCNTDQ
+func (x Uint32x8) PopCountMasked(mask Mask32x8) Uint32x8
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512VPOPCNTDQ
+func (x Uint32x16) PopCountMasked(mask Mask32x16) Uint32x16
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512VPOPCNTDQ
+func (x Uint64x2) PopCountMasked(mask Mask64x2) Uint64x2
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512VPOPCNTDQ
+func (x Uint64x4) PopCountMasked(mask Mask64x4) Uint64x4
+
+// PopCountMasked counts the number of set bits in each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512VPOPCNTDQ
+func (x Uint64x8) PopCountMasked(mask Mask64x8) Uint64x8
+
+/* RotateAllLeft */
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLD, CPU Feature: AVX512F
+func (x Int32x4) RotateAllLeft(shift uint8) Int32x4
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLD, CPU Feature: AVX512F
+func (x Int32x8) RotateAllLeft(shift uint8) Int32x8
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLD, CPU Feature: AVX512F
+func (x Int32x16) RotateAllLeft(shift uint8) Int32x16
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLQ, CPU Feature: AVX512F
+func (x Int64x2) RotateAllLeft(shift uint8) Int64x2
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLQ, CPU Feature: AVX512F
+func (x Int64x4) RotateAllLeft(shift uint8) Int64x4
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLQ, CPU Feature: AVX512F
+func (x Int64x8) RotateAllLeft(shift uint8) Int64x8
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLD, CPU Feature: AVX512F
+func (x Uint32x4) RotateAllLeft(shift uint8) Uint32x4
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLD, CPU Feature: AVX512F
+func (x Uint32x8) RotateAllLeft(shift uint8) Uint32x8
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLD, CPU Feature: AVX512F
+func (x Uint32x16) RotateAllLeft(shift uint8) Uint32x16
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLQ, CPU Feature: AVX512F
+func (x Uint64x2) RotateAllLeft(shift uint8) Uint64x2
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLQ, CPU Feature: AVX512F
+func (x Uint64x4) RotateAllLeft(shift uint8) Uint64x4
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLQ, CPU Feature: AVX512F
+func (x Uint64x8) RotateAllLeft(shift uint8) Uint64x8
+
+/* RotateAllLeftMasked */
+
+// RotateAllLeftMasked rotates each element to the left by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLD, CPU Feature: AVX512F
+func (x Int32x4) RotateAllLeftMasked(shift uint8, mask Mask32x4) Int32x4
+
+// RotateAllLeftMasked rotates each element to the left by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLD, CPU Feature: AVX512F
+func (x Int32x8) RotateAllLeftMasked(shift uint8, mask Mask32x8) Int32x8
+
+// RotateAllLeftMasked rotates each element to the left by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLD, CPU Feature: AVX512F
+func (x Int32x16) RotateAllLeftMasked(shift uint8, mask Mask32x16) Int32x16
+
+// RotateAllLeftMasked rotates each element to the left by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLQ, CPU Feature: AVX512F
+func (x Int64x2) RotateAllLeftMasked(shift uint8, mask Mask64x2) Int64x2
+
+// RotateAllLeftMasked rotates each element to the left by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLQ, CPU Feature: AVX512F
+func (x Int64x4) RotateAllLeftMasked(shift uint8, mask Mask64x4) Int64x4
+
+// RotateAllLeftMasked rotates each element to the left by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLQ, CPU Feature: AVX512F
+func (x Int64x8) RotateAllLeftMasked(shift uint8, mask Mask64x8) Int64x8
+
+// RotateAllLeftMasked rotates each element to the left by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLD, CPU Feature: AVX512F
+func (x Uint32x4) RotateAllLeftMasked(shift uint8, mask Mask32x4) Uint32x4
+
+// RotateAllLeftMasked rotates each element to the left by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLD, CPU Feature: AVX512F
+func (x Uint32x8) RotateAllLeftMasked(shift uint8, mask Mask32x8) Uint32x8
+
+// RotateAllLeftMasked rotates each element to the left by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLD, CPU Feature: AVX512F
+func (x Uint32x16) RotateAllLeftMasked(shift uint8, mask Mask32x16) Uint32x16
+
+// RotateAllLeftMasked rotates each element to the left by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLQ, CPU Feature: AVX512F
+func (x Uint64x2) RotateAllLeftMasked(shift uint8, mask Mask64x2) Uint64x2
+
+// RotateAllLeftMasked rotates each element to the left by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLQ, CPU Feature: AVX512F
+func (x Uint64x4) RotateAllLeftMasked(shift uint8, mask Mask64x4) Uint64x4
+
+// RotateAllLeftMasked rotates each element to the left by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPROLQ, CPU Feature: AVX512F
+func (x Uint64x8) RotateAllLeftMasked(shift uint8, mask Mask64x8) Uint64x8
+
+/* RotateAllRight */
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORD, CPU Feature: AVX512F
+func (x Int32x4) RotateAllRight(shift uint8) Int32x4
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORD, CPU Feature: AVX512F
+func (x Int32x8) RotateAllRight(shift uint8) Int32x8
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORD, CPU Feature: AVX512F
+func (x Int32x16) RotateAllRight(shift uint8) Int32x16
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORQ, CPU Feature: AVX512F
+func (x Int64x2) RotateAllRight(shift uint8) Int64x2
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORQ, CPU Feature: AVX512F
+func (x Int64x4) RotateAllRight(shift uint8) Int64x4
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORQ, CPU Feature: AVX512F
+func (x Int64x8) RotateAllRight(shift uint8) Int64x8
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORD, CPU Feature: AVX512F
+func (x Uint32x4) RotateAllRight(shift uint8) Uint32x4
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORD, CPU Feature: AVX512F
+func (x Uint32x8) RotateAllRight(shift uint8) Uint32x8
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORD, CPU Feature: AVX512F
+func (x Uint32x16) RotateAllRight(shift uint8) Uint32x16
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORQ, CPU Feature: AVX512F
+func (x Uint64x2) RotateAllRight(shift uint8) Uint64x2
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORQ, CPU Feature: AVX512F
+func (x Uint64x4) RotateAllRight(shift uint8) Uint64x4
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORQ, CPU Feature: AVX512F
+func (x Uint64x8) RotateAllRight(shift uint8) Uint64x8
+
+/* RotateAllRightMasked */
+
+// RotateAllRightMasked rotates each element to the right by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORD, CPU Feature: AVX512F
+func (x Int32x4) RotateAllRightMasked(shift uint8, mask Mask32x4) Int32x4
+
+// RotateAllRightMasked rotates each element to the right by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORD, CPU Feature: AVX512F
+func (x Int32x8) RotateAllRightMasked(shift uint8, mask Mask32x8) Int32x8
+
+// RotateAllRightMasked rotates each element to the right by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORD, CPU Feature: AVX512F
+func (x Int32x16) RotateAllRightMasked(shift uint8, mask Mask32x16) Int32x16
+
+// RotateAllRightMasked rotates each element to the right by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORQ, CPU Feature: AVX512F
+func (x Int64x2) RotateAllRightMasked(shift uint8, mask Mask64x2) Int64x2
+
+// RotateAllRightMasked rotates each element to the right by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORQ, CPU Feature: AVX512F
+func (x Int64x4) RotateAllRightMasked(shift uint8, mask Mask64x4) Int64x4
+
+// RotateAllRightMasked rotates each element to the right by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORQ, CPU Feature: AVX512F
+func (x Int64x8) RotateAllRightMasked(shift uint8, mask Mask64x8) Int64x8
+
+// RotateAllRightMasked rotates each element to the right by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORD, CPU Feature: AVX512F
+func (x Uint32x4) RotateAllRightMasked(shift uint8, mask Mask32x4) Uint32x4
+
+// RotateAllRightMasked rotates each element to the right by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORD, CPU Feature: AVX512F
+func (x Uint32x8) RotateAllRightMasked(shift uint8, mask Mask32x8) Uint32x8
+
+// RotateAllRightMasked rotates each element to the right by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORD, CPU Feature: AVX512F
+func (x Uint32x16) RotateAllRightMasked(shift uint8, mask Mask32x16) Uint32x16
+
+// RotateAllRightMasked rotates each element to the right by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORQ, CPU Feature: AVX512F
+func (x Uint64x2) RotateAllRightMasked(shift uint8, mask Mask64x2) Uint64x2
+
+// RotateAllRightMasked rotates each element to the right by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORQ, CPU Feature: AVX512F
+func (x Uint64x4) RotateAllRightMasked(shift uint8, mask Mask64x4) Uint64x4
+
+// RotateAllRightMasked rotates each element to the right by the number of bits specified by the immediate.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPRORQ, CPU Feature: AVX512F
+func (x Uint64x8) RotateAllRightMasked(shift uint8, mask Mask64x8) Uint64x8
+
+/* RotateLeft */
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512F
+func (x Int32x4) RotateLeft(y Int32x4) Int32x4
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512F
+func (x Int32x8) RotateLeft(y Int32x8) Int32x8
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512F
+func (x Int32x16) RotateLeft(y Int32x16) Int32x16
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512F
+func (x Int64x2) RotateLeft(y Int64x2) Int64x2
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512F
+func (x Int64x4) RotateLeft(y Int64x4) Int64x4
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512F
+func (x Int64x8) RotateLeft(y Int64x8) Int64x8
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512F
+func (x Uint32x4) RotateLeft(y Uint32x4) Uint32x4
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512F
+func (x Uint32x8) RotateLeft(y Uint32x8) Uint32x8
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512F
+func (x Uint32x16) RotateLeft(y Uint32x16) Uint32x16
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512F
+func (x Uint64x2) RotateLeft(y Uint64x2) Uint64x2
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512F
+func (x Uint64x4) RotateLeft(y Uint64x4) Uint64x4
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512F
+func (x Uint64x8) RotateLeft(y Uint64x8) Uint64x8
+
+/* RotateLeftMasked */
+
+// RotateLeftMasked rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPROLVD, CPU Feature: AVX512F
+func (x Int32x4) RotateLeftMasked(y Int32x4, mask Mask32x4) Int32x4
+
+// RotateLeftMasked rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPROLVD, CPU Feature: AVX512F
+func (x Int32x8) RotateLeftMasked(y Int32x8, mask Mask32x8) Int32x8
+
+// RotateLeftMasked rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPROLVD, CPU Feature: AVX512F
+func (x Int32x16) RotateLeftMasked(y Int32x16, mask Mask32x16) Int32x16
+
+// RotateLeftMasked rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512F
+func (x Int64x2) RotateLeftMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// RotateLeftMasked rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512F
+func (x Int64x4) RotateLeftMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// RotateLeftMasked rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512F
+func (x Int64x8) RotateLeftMasked(y Int64x8, mask Mask64x8) Int64x8
+
+// RotateLeftMasked rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPROLVD, CPU Feature: AVX512F
+func (x Uint32x4) RotateLeftMasked(y Uint32x4, mask Mask32x4) Uint32x4
+
+// RotateLeftMasked rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPROLVD, CPU Feature: AVX512F
+func (x Uint32x8) RotateLeftMasked(y Uint32x8, mask Mask32x8) Uint32x8
+
+// RotateLeftMasked rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPROLVD, CPU Feature: AVX512F
+func (x Uint32x16) RotateLeftMasked(y Uint32x16, mask Mask32x16) Uint32x16
+
+// RotateLeftMasked rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512F
+func (x Uint64x2) RotateLeftMasked(y Uint64x2, mask Mask64x2) Uint64x2
+
+// RotateLeftMasked rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512F
+func (x Uint64x4) RotateLeftMasked(y Uint64x4, mask Mask64x4) Uint64x4
+
+// RotateLeftMasked rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512F
+func (x Uint64x8) RotateLeftMasked(y Uint64x8, mask Mask64x8) Uint64x8
+
+/* RotateRight */
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512F
+func (x Int32x4) RotateRight(y Int32x4) Int32x4
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512F
+func (x Int32x8) RotateRight(y Int32x8) Int32x8
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512F
+func (x Int32x16) RotateRight(y Int32x16) Int32x16
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512F
+func (x Int64x2) RotateRight(y Int64x2) Int64x2
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512F
+func (x Int64x4) RotateRight(y Int64x4) Int64x4
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512F
+func (x Int64x8) RotateRight(y Int64x8) Int64x8
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512F
+func (x Uint32x4) RotateRight(y Uint32x4) Uint32x4
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512F
+func (x Uint32x8) RotateRight(y Uint32x8) Uint32x8
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512F
+func (x Uint32x16) RotateRight(y Uint32x16) Uint32x16
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512F
+func (x Uint64x2) RotateRight(y Uint64x2) Uint64x2
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512F
+func (x Uint64x4) RotateRight(y Uint64x4) Uint64x4
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512F
+func (x Uint64x8) RotateRight(y Uint64x8) Uint64x8
+
+/* RotateRightMasked */
+
+// RotateRightMasked rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPRORVD, CPU Feature: AVX512F
+func (x Int32x4) RotateRightMasked(y Int32x4, mask Mask32x4) Int32x4
+
+// RotateRightMasked rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPRORVD, CPU Feature: AVX512F
+func (x Int32x8) RotateRightMasked(y Int32x8, mask Mask32x8) Int32x8
+
+// RotateRightMasked rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPRORVD, CPU Feature: AVX512F
+func (x Int32x16) RotateRightMasked(y Int32x16, mask Mask32x16) Int32x16
+
+// RotateRightMasked rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512F
+func (x Int64x2) RotateRightMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// RotateRightMasked rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512F
+func (x Int64x4) RotateRightMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// RotateRightMasked rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512F
+func (x Int64x8) RotateRightMasked(y Int64x8, mask Mask64x8) Int64x8
+
+// RotateRightMasked rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPRORVD, CPU Feature: AVX512F
+func (x Uint32x4) RotateRightMasked(y Uint32x4, mask Mask32x4) Uint32x4
+
+// RotateRightMasked rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPRORVD, CPU Feature: AVX512F
+func (x Uint32x8) RotateRightMasked(y Uint32x8, mask Mask32x8) Uint32x8
+
+// RotateRightMasked rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPRORVD, CPU Feature: AVX512F
+func (x Uint32x16) RotateRightMasked(y Uint32x16, mask Mask32x16) Uint32x16
+
+// RotateRightMasked rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512F
+func (x Uint64x2) RotateRightMasked(y Uint64x2, mask Mask64x2) Uint64x2
+
+// RotateRightMasked rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512F
+func (x Uint64x4) RotateRightMasked(y Uint64x4, mask Mask64x4) Uint64x4
+
+// RotateRightMasked rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512F
+func (x Uint64x8) RotateRightMasked(y Uint64x8, mask Mask64x8) Uint64x8
+
+/* Round */
+
+// Round rounds elements to the nearest integer.
+//
+// Asm: VROUNDPS, CPU Feature: AVX
+func (x Float32x4) Round() Float32x4
+
+// Round rounds elements to the nearest integer.
+//
+// Asm: VROUNDPS, CPU Feature: AVX
+func (x Float32x8) Round() Float32x8
+
+// Round rounds elements to the nearest integer.
+//
+// Asm: VROUNDPD, CPU Feature: AVX
+func (x Float64x2) Round() Float64x2
+
+// Round rounds elements to the nearest integer.
+//
+// Asm: VROUNDPD, CPU Feature: AVX
+func (x Float64x4) Round() Float64x4
+
+/* RoundWithPrecision */
+
+// RoundWithPrecision rounds elements with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x4) RoundWithPrecision(prec uint8) Float32x4
+
+// RoundWithPrecision rounds elements with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x8) RoundWithPrecision(prec uint8) Float32x8
+
+// RoundWithPrecision rounds elements with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x16) RoundWithPrecision(prec uint8) Float32x16
+
+// RoundWithPrecision rounds elements with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x2) RoundWithPrecision(prec uint8) Float64x2
+
+// RoundWithPrecision rounds elements with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x4) RoundWithPrecision(prec uint8) Float64x4
+
+// RoundWithPrecision rounds elements with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x8) RoundWithPrecision(prec uint8) Float64x8
+
+/* RoundWithPrecisionMasked */
+
+// RoundWithPrecisionMasked rounds elements with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x4) RoundWithPrecisionMasked(prec uint8, mask Mask32x4) Float32x4
+
+// RoundWithPrecisionMasked rounds elements with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x8) RoundWithPrecisionMasked(prec uint8, mask Mask32x8) Float32x8
+
+// RoundWithPrecisionMasked rounds elements with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x16) RoundWithPrecisionMasked(prec uint8, mask Mask32x16) Float32x16
+
+// RoundWithPrecisionMasked rounds elements with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x2) RoundWithPrecisionMasked(prec uint8, mask Mask64x2) Float64x2
+
+// RoundWithPrecisionMasked rounds elements with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x4) RoundWithPrecisionMasked(prec uint8, mask Mask64x4) Float64x4
+
+// RoundWithPrecisionMasked rounds elements with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x8) RoundWithPrecisionMasked(prec uint8, mask Mask64x8) Float64x8
+
+/* SaturatedAdd */
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSB, CPU Feature: AVX
+func (x Int8x16) SaturatedAdd(y Int8x16) Int8x16
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSB, CPU Feature: AVX2
+func (x Int8x32) SaturatedAdd(y Int8x32) Int8x32
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSB, CPU Feature: AVX512BW
+func (x Int8x64) SaturatedAdd(y Int8x64) Int8x64
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSW, CPU Feature: AVX
+func (x Int16x8) SaturatedAdd(y Int16x8) Int16x8
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSW, CPU Feature: AVX2
+func (x Int16x16) SaturatedAdd(y Int16x16) Int16x16
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSW, CPU Feature: AVX512BW
+func (x Int16x32) SaturatedAdd(y Int16x32) Int16x32
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSB, CPU Feature: AVX
+func (x Uint8x16) SaturatedAdd(y Uint8x16) Uint8x16
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSB, CPU Feature: AVX2
+func (x Uint8x32) SaturatedAdd(y Uint8x32) Uint8x32
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSB, CPU Feature: AVX512BW
+func (x Uint8x64) SaturatedAdd(y Uint8x64) Uint8x64
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSW, CPU Feature: AVX
+func (x Uint16x8) SaturatedAdd(y Uint16x8) Uint16x8
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSW, CPU Feature: AVX2
+func (x Uint16x16) SaturatedAdd(y Uint16x16) Uint16x16
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSW, CPU Feature: AVX512BW
+func (x Uint16x32) SaturatedAdd(y Uint16x32) Uint16x32
+
+/* SaturatedAddMasked */
+
+// SaturatedAddMasked adds corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDSB, CPU Feature: AVX512BW
+func (x Int8x16) SaturatedAddMasked(y Int8x16, mask Mask8x16) Int8x16
+
+// SaturatedAddMasked adds corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDSB, CPU Feature: AVX512BW
+func (x Int8x32) SaturatedAddMasked(y Int8x32, mask Mask8x32) Int8x32
+
+// SaturatedAddMasked adds corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDSB, CPU Feature: AVX512BW
+func (x Int8x64) SaturatedAddMasked(y Int8x64, mask Mask8x64) Int8x64
+
+// SaturatedAddMasked adds corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDSW, CPU Feature: AVX512BW
+func (x Int16x8) SaturatedAddMasked(y Int16x8, mask Mask16x8) Int16x8
+
+// SaturatedAddMasked adds corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDSW, CPU Feature: AVX512BW
+func (x Int16x16) SaturatedAddMasked(y Int16x16, mask Mask16x16) Int16x16
+
+// SaturatedAddMasked adds corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDSW, CPU Feature: AVX512BW
+func (x Int16x32) SaturatedAddMasked(y Int16x32, mask Mask16x32) Int16x32
+
+// SaturatedAddMasked adds corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDSB, CPU Feature: AVX512BW
+func (x Uint8x16) SaturatedAddMasked(y Uint8x16, mask Mask8x16) Uint8x16
+
+// SaturatedAddMasked adds corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDSB, CPU Feature: AVX512BW
+func (x Uint8x32) SaturatedAddMasked(y Uint8x32, mask Mask8x32) Uint8x32
+
+// SaturatedAddMasked adds corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDSB, CPU Feature: AVX512BW
+func (x Uint8x64) SaturatedAddMasked(y Uint8x64, mask Mask8x64) Uint8x64
+
+// SaturatedAddMasked adds corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDSW, CPU Feature: AVX512BW
+func (x Uint16x8) SaturatedAddMasked(y Uint16x8, mask Mask16x8) Uint16x8
+
+// SaturatedAddMasked adds corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDSW, CPU Feature: AVX512BW
+func (x Uint16x16) SaturatedAddMasked(y Uint16x16, mask Mask16x16) Uint16x16
+
+// SaturatedAddMasked adds corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPADDSW, CPU Feature: AVX512BW
+func (x Uint16x32) SaturatedAddMasked(y Uint16x32, mask Mask16x32) Uint16x32
+
+/* SaturatedPairDotProdAccumulate */
+
+// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of x and y and then adds z.
+//
+// Asm: VPDPWSSDS, CPU Feature: AVXVNNI
+func (x Int16x8) SaturatedPairDotProdAccumulate(y Int16x8, z Int32x4) Int32x4
+
+// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of x and y and then adds z.
+//
+// Asm: VPDPWSSDS, CPU Feature: AVXVNNI
+func (x Int16x16) SaturatedPairDotProdAccumulate(y Int16x16, z Int32x8) Int32x8
+
+// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of x and y and then adds z.
+//
+// Asm: VPDPWSSDS, CPU Feature: AVX512VNNI
+func (x Int16x32) SaturatedPairDotProdAccumulate(y Int16x32, z Int32x16) Int32x16
+
+/* SaturatedPairDotProdAccumulateMasked */
+
+// SaturatedPairDotProdAccumulateMasked performs dot products on pairs of elements of x and y and then adds z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPDPWSSDS, CPU Feature: AVX512VNNI
+func (x Int16x8) SaturatedPairDotProdAccumulateMasked(y Int16x8, z Int32x4, mask Mask32x4) Int32x4
+
+// SaturatedPairDotProdAccumulateMasked performs dot products on pairs of elements of x and y and then adds z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPDPWSSDS, CPU Feature: AVX512VNNI
+func (x Int16x16) SaturatedPairDotProdAccumulateMasked(y Int16x16, z Int32x8, mask Mask32x8) Int32x8
+
+// SaturatedPairDotProdAccumulateMasked performs dot products on pairs of elements of x and y and then adds z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPDPWSSDS, CPU Feature: AVX512VNNI
+func (x Int16x32) SaturatedPairDotProdAccumulateMasked(y Int16x32, z Int32x16, mask Mask32x16) Int32x16
+
+/* SaturatedPairwiseAdd */
+
+// SaturatedPairwiseAdd horizontally adds adjacent pairs of elements with saturation.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDSW, CPU Feature: AVX
+func (x Int16x8) SaturatedPairwiseAdd(y Int16x8) Int16x8
+
+// SaturatedPairwiseAdd horizontally adds adjacent pairs of elements with saturation.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDSW, CPU Feature: AVX2
+func (x Int16x16) SaturatedPairwiseAdd(y Int16x16) Int16x16
+
+/* SaturatedPairwiseSub */
+
+// SaturatedPairwiseSub horizontally subtracts adjacent pairs of elements with saturation.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBSW, CPU Feature: AVX
+func (x Int16x8) SaturatedPairwiseSub(y Int16x8) Int16x8
+
+// SaturatedPairwiseSub horizontally subtracts adjacent pairs of elements with saturation.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBSW, CPU Feature: AVX2
+func (x Int16x16) SaturatedPairwiseSub(y Int16x16) Int16x16
+
+/* SaturatedSub */
+
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+//
+// Asm: VPSUBSB, CPU Feature: AVX
+func (x Int8x16) SaturatedSub(y Int8x16) Int8x16
+
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+//
+// Asm: VPSUBSB, CPU Feature: AVX2
+func (x Int8x32) SaturatedSub(y Int8x32) Int8x32
+
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+//
+// Asm: VPSUBSB, CPU Feature: AVX512BW
+func (x Int8x64) SaturatedSub(y Int8x64) Int8x64
+
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+//
+// Asm: VPSUBSW, CPU Feature: AVX
+func (x Int16x8) SaturatedSub(y Int16x8) Int16x8
+
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+//
+// Asm: VPSUBSW, CPU Feature: AVX2
+func (x Int16x16) SaturatedSub(y Int16x16) Int16x16
+
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+//
+// Asm: VPSUBSW, CPU Feature: AVX512BW
+func (x Int16x32) SaturatedSub(y Int16x32) Int16x32
+
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+//
+// Asm: VPSUBSB, CPU Feature: AVX
+func (x Uint8x16) SaturatedSub(y Uint8x16) Uint8x16
+
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+//
+// Asm: VPSUBSB, CPU Feature: AVX2
+func (x Uint8x32) SaturatedSub(y Uint8x32) Uint8x32
+
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+//
+// Asm: VPSUBSB, CPU Feature: AVX512BW
+func (x Uint8x64) SaturatedSub(y Uint8x64) Uint8x64
+
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+//
+// Asm: VPSUBSW, CPU Feature: AVX
+func (x Uint16x8) SaturatedSub(y Uint16x8) Uint16x8
+
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+//
+// Asm: VPSUBSW, CPU Feature: AVX2
+func (x Uint16x16) SaturatedSub(y Uint16x16) Uint16x16
+
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+//
+// Asm: VPSUBSW, CPU Feature: AVX512BW
+func (x Uint16x32) SaturatedSub(y Uint16x32) Uint16x32
+
+/* SaturatedSubMasked */
+
+// SaturatedSubMasked subtracts corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBSB, CPU Feature: AVX512BW
+func (x Int8x16) SaturatedSubMasked(y Int8x16, mask Mask8x16) Int8x16
+
+// SaturatedSubMasked subtracts corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBSB, CPU Feature: AVX512BW
+func (x Int8x32) SaturatedSubMasked(y Int8x32, mask Mask8x32) Int8x32
+
+// SaturatedSubMasked subtracts corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBSB, CPU Feature: AVX512BW
+func (x Int8x64) SaturatedSubMasked(y Int8x64, mask Mask8x64) Int8x64
+
+// SaturatedSubMasked subtracts corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBSW, CPU Feature: AVX512BW
+func (x Int16x8) SaturatedSubMasked(y Int16x8, mask Mask16x8) Int16x8
+
+// SaturatedSubMasked subtracts corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBSW, CPU Feature: AVX512BW
+func (x Int16x16) SaturatedSubMasked(y Int16x16, mask Mask16x16) Int16x16
+
+// SaturatedSubMasked subtracts corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBSW, CPU Feature: AVX512BW
+func (x Int16x32) SaturatedSubMasked(y Int16x32, mask Mask16x32) Int16x32
+
+// SaturatedSubMasked subtracts corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBSB, CPU Feature: AVX512BW
+func (x Uint8x16) SaturatedSubMasked(y Uint8x16, mask Mask8x16) Uint8x16
+
+// SaturatedSubMasked subtracts corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBSB, CPU Feature: AVX512BW
+func (x Uint8x32) SaturatedSubMasked(y Uint8x32, mask Mask8x32) Uint8x32
+
+// SaturatedSubMasked subtracts corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBSB, CPU Feature: AVX512BW
+func (x Uint8x64) SaturatedSubMasked(y Uint8x64, mask Mask8x64) Uint8x64
+
+// SaturatedSubMasked subtracts corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBSW, CPU Feature: AVX512BW
+func (x Uint16x8) SaturatedSubMasked(y Uint16x8, mask Mask16x8) Uint16x8
+
+// SaturatedSubMasked subtracts corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBSW, CPU Feature: AVX512BW
+func (x Uint16x16) SaturatedSubMasked(y Uint16x16, mask Mask16x16) Uint16x16
+
+// SaturatedSubMasked subtracts corresponding elements of two vectors with saturation.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBSW, CPU Feature: AVX512BW
+func (x Uint16x32) SaturatedSubMasked(y Uint16x32, mask Mask16x32) Uint16x32
+
+/* SaturatedUnsignedSignedPairDotProd */
+
+// SaturatedUnsignedSignedPairDotProd multiplies the elements and add the pairs together with saturation,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// Asm: VPMADDUBSW, CPU Feature: AVX
+func (x Uint8x16) SaturatedUnsignedSignedPairDotProd(y Int8x16) Int16x8
+
+// SaturatedUnsignedSignedPairDotProd multiplies the elements and add the pairs together with saturation,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// Asm: VPMADDUBSW, CPU Feature: AVX2
+func (x Uint8x32) SaturatedUnsignedSignedPairDotProd(y Int8x32) Int16x16
+
+// SaturatedUnsignedSignedPairDotProd multiplies the elements and add the pairs together with saturation,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// Asm: VPMADDUBSW, CPU Feature: AVX512BW
+func (x Uint8x64) SaturatedUnsignedSignedPairDotProd(y Int8x64) Int16x32
+
+/* SaturatedUnsignedSignedPairDotProdMasked */
+
+// SaturatedUnsignedSignedPairDotProdMasked multiplies the elements and add the pairs together with saturation,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMADDUBSW, CPU Feature: AVX512BW
+func (x Uint8x16) SaturatedUnsignedSignedPairDotProdMasked(y Int8x16, mask Mask16x8) Int16x8
+
+// SaturatedUnsignedSignedPairDotProdMasked multiplies the elements and add the pairs together with saturation,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMADDUBSW, CPU Feature: AVX512BW
+func (x Uint8x32) SaturatedUnsignedSignedPairDotProdMasked(y Int8x32, mask Mask16x16) Int16x16
+
+// SaturatedUnsignedSignedPairDotProdMasked multiplies the elements and add the pairs together with saturation,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMADDUBSW, CPU Feature: AVX512BW
+func (x Uint8x64) SaturatedUnsignedSignedPairDotProdMasked(y Int8x64, mask Mask16x32) Int16x32
+
+/* SaturatedUnsignedSignedQuadDotProdAccumulate */
+
+// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of x and y and then adds z.
+//
+// Asm: VPDPBUSDS, CPU Feature: AVXVNNI
+func (x Int8x16) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int32x4) Int32x4
+
+// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of x and y and then adds z.
+//
+// Asm: VPDPBUSDS, CPU Feature: AVXVNNI
+func (x Int8x32) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int32x8) Int32x8
+
+// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of x and y and then adds z.
+//
+// Asm: VPDPBUSDS, CPU Feature: AVX512VNNI
+func (x Int8x64) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int32x16) Int32x16
+
+/* SaturatedUnsignedSignedQuadDotProdAccumulateMasked */
+
+// SaturatedUnsignedSignedQuadDotProdAccumulateMasked multiplies performs dot products on groups of 4 elements of x and y and then adds z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPDPBUSDS, CPU Feature: AVX512VNNI
+func (x Int8x16) SaturatedUnsignedSignedQuadDotProdAccumulateMasked(y Uint8x16, z Int32x4, mask Mask32x4) Int32x4
+
+// SaturatedUnsignedSignedQuadDotProdAccumulateMasked multiplies performs dot products on groups of 4 elements of x and y and then adds z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPDPBUSDS, CPU Feature: AVX512VNNI
+func (x Int8x32) SaturatedUnsignedSignedQuadDotProdAccumulateMasked(y Uint8x32, z Int32x8, mask Mask32x8) Int32x8
+
+// SaturatedUnsignedSignedQuadDotProdAccumulateMasked multiplies performs dot products on groups of 4 elements of x and y and then adds z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPDPBUSDS, CPU Feature: AVX512VNNI
+func (x Int8x64) SaturatedUnsignedSignedQuadDotProdAccumulateMasked(y Uint8x64, z Int32x16, mask Mask32x16) Int32x16
+
+/* Set128 */
+
+// Set128 combines a 128-bit vector with a 256-bit vector, where the constant operand specifies whether the low (0) or high (1) half is receives the smaller vector.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VINSERTF128, CPU Feature: AVX
+func (x Float32x8) Set128(index uint8, y Float32x4) Float32x8
+
+// Set128 combines a 128-bit vector with a 256-bit vector, where the constant operand specifies whether the low (0) or high (1) half is receives the smaller vector.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VINSERTF128, CPU Feature: AVX
+func (x Float64x4) Set128(index uint8, y Float64x2) Float64x4
+
+// Set128 combines a 128-bit vector with a 256-bit vector, where the constant operand specifies whether the low (0) or high (1) half is receives the smaller vector.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VINSERTI128, CPU Feature: AVX2
+func (x Int8x32) Set128(index uint8, y Int8x16) Int8x32
+
+// Set128 combines a 128-bit vector with a 256-bit vector, where the constant operand specifies whether the low (0) or high (1) half is receives the smaller vector.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VINSERTI128, CPU Feature: AVX2
+func (x Int16x16) Set128(index uint8, y Int16x8) Int16x16
+
+// Set128 combines a 128-bit vector with a 256-bit vector, where the constant operand specifies whether the low (0) or high (1) half is receives the smaller vector.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VINSERTI128, CPU Feature: AVX2
+func (x Int32x8) Set128(index uint8, y Int32x4) Int32x8
+
+// Set128 combines a 128-bit vector with a 256-bit vector, where the constant operand specifies whether the low (0) or high (1) half is receives the smaller vector.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VINSERTI128, CPU Feature: AVX2
+func (x Int64x4) Set128(index uint8, y Int64x2) Int64x4
+
+// Set128 combines a 128-bit vector with a 256-bit vector, where the constant operand specifies whether the low (0) or high (1) half is receives the smaller vector.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VINSERTI128, CPU Feature: AVX2
+func (x Uint8x32) Set128(index uint8, y Uint8x16) Uint8x32
+
+// Set128 combines a 128-bit vector with a 256-bit vector, where the constant operand specifies whether the low (0) or high (1) half is receives the smaller vector.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VINSERTI128, CPU Feature: AVX2
+func (x Uint16x16) Set128(index uint8, y Uint16x8) Uint16x16
+
+// Set128 combines a 128-bit vector with a 256-bit vector, where the constant operand specifies whether the low (0) or high (1) half is receives the smaller vector.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VINSERTI128, CPU Feature: AVX2
+func (x Uint32x8) Set128(index uint8, y Uint32x4) Uint32x8
+
+// Set128 combines a 128-bit vector with a 256-bit vector, where the constant operand specifies whether the low (0) or high (1) half is receives the smaller vector.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VINSERTI128, CPU Feature: AVX2
+func (x Uint64x4) Set128(index uint8, y Uint64x2) Uint64x4
+
+/* SetElem */
+
+// SetElem sets a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPINSRB, CPU Feature: AVX
+func (x Int8x16) SetElem(index uint8, y int8) Int8x16
+
+// SetElem sets a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPINSRW, CPU Feature: AVX
+func (x Int16x8) SetElem(index uint8, y int16) Int16x8
+
+// SetElem sets a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPINSRD, CPU Feature: AVX
+func (x Int32x4) SetElem(index uint8, y int32) Int32x4
+
+// SetElem sets a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPINSRQ, CPU Feature: AVX
+func (x Int64x2) SetElem(index uint8, y int64) Int64x2
+
+// SetElem sets a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPINSRB, CPU Feature: AVX
+func (x Uint8x16) SetElem(index uint8, y uint8) Uint8x16
+
+// SetElem sets a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPINSRW, CPU Feature: AVX
+func (x Uint16x8) SetElem(index uint8, y uint16) Uint16x8
+
+// SetElem sets a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPINSRD, CPU Feature: AVX
+func (x Uint32x4) SetElem(index uint8, y uint32) Uint32x4
+
+// SetElem sets a single constant-indexed element's value.
+//
+// index is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPINSRQ, CPU Feature: AVX
+func (x Uint64x2) SetElem(index uint8, y uint64) Uint64x2
+
+/* ShiftAllLeft */
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLW, CPU Feature: AVX
+func (x Int16x8) ShiftAllLeft(y uint64) Int16x8
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLW, CPU Feature: AVX2
+func (x Int16x16) ShiftAllLeft(y uint64) Int16x16
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLW, CPU Feature: AVX512BW
+func (x Int16x32) ShiftAllLeft(y uint64) Int16x32
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLD, CPU Feature: AVX
+func (x Int32x4) ShiftAllLeft(y uint64) Int32x4
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLD, CPU Feature: AVX2
+func (x Int32x8) ShiftAllLeft(y uint64) Int32x8
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLD, CPU Feature: AVX512F
+func (x Int32x16) ShiftAllLeft(y uint64) Int32x16
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLQ, CPU Feature: AVX
+func (x Int64x2) ShiftAllLeft(y uint64) Int64x2
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLQ, CPU Feature: AVX2
+func (x Int64x4) ShiftAllLeft(y uint64) Int64x4
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLQ, CPU Feature: AVX512F
+func (x Int64x8) ShiftAllLeft(y uint64) Int64x8
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLW, CPU Feature: AVX
+func (x Uint16x8) ShiftAllLeft(y uint64) Uint16x8
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLW, CPU Feature: AVX2
+func (x Uint16x16) ShiftAllLeft(y uint64) Uint16x16
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLW, CPU Feature: AVX512BW
+func (x Uint16x32) ShiftAllLeft(y uint64) Uint16x32
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLD, CPU Feature: AVX
+func (x Uint32x4) ShiftAllLeft(y uint64) Uint32x4
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLD, CPU Feature: AVX2
+func (x Uint32x8) ShiftAllLeft(y uint64) Uint32x8
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLD, CPU Feature: AVX512F
+func (x Uint32x16) ShiftAllLeft(y uint64) Uint32x16
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLQ, CPU Feature: AVX
+func (x Uint64x2) ShiftAllLeft(y uint64) Uint64x2
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLQ, CPU Feature: AVX2
+func (x Uint64x4) ShiftAllLeft(y uint64) Uint64x4
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLQ, CPU Feature: AVX512F
+func (x Uint64x8) ShiftAllLeft(y uint64) Uint64x8
+
+/* ShiftAllLeftAndFillUpperFrom */
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDW, CPU Feature: AVX512VBMI2
+func (x Int16x8) ShiftAllLeftAndFillUpperFrom(shift uint8, y Int16x8) Int16x8
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDW, CPU Feature: AVX512VBMI2
+func (x Int16x16) ShiftAllLeftAndFillUpperFrom(shift uint8, y Int16x16) Int16x16
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDW, CPU Feature: AVX512VBMI2
+func (x Int16x32) ShiftAllLeftAndFillUpperFrom(shift uint8, y Int16x32) Int16x32
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDD, CPU Feature: AVX512VBMI2
+func (x Int32x4) ShiftAllLeftAndFillUpperFrom(shift uint8, y Int32x4) Int32x4
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDD, CPU Feature: AVX512VBMI2
+func (x Int32x8) ShiftAllLeftAndFillUpperFrom(shift uint8, y Int32x8) Int32x8
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDD, CPU Feature: AVX512VBMI2
+func (x Int32x16) ShiftAllLeftAndFillUpperFrom(shift uint8, y Int32x16) Int32x16
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDQ, CPU Feature: AVX512VBMI2
+func (x Int64x2) ShiftAllLeftAndFillUpperFrom(shift uint8, y Int64x2) Int64x2
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDQ, CPU Feature: AVX512VBMI2
+func (x Int64x4) ShiftAllLeftAndFillUpperFrom(shift uint8, y Int64x4) Int64x4
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDQ, CPU Feature: AVX512VBMI2
+func (x Int64x8) ShiftAllLeftAndFillUpperFrom(shift uint8, y Int64x8) Int64x8
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDW, CPU Feature: AVX512VBMI2
+func (x Uint16x8) ShiftAllLeftAndFillUpperFrom(shift uint8, y Uint16x8) Uint16x8
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDW, CPU Feature: AVX512VBMI2
+func (x Uint16x16) ShiftAllLeftAndFillUpperFrom(shift uint8, y Uint16x16) Uint16x16
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDW, CPU Feature: AVX512VBMI2
+func (x Uint16x32) ShiftAllLeftAndFillUpperFrom(shift uint8, y Uint16x32) Uint16x32
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDD, CPU Feature: AVX512VBMI2
+func (x Uint32x4) ShiftAllLeftAndFillUpperFrom(shift uint8, y Uint32x4) Uint32x4
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDD, CPU Feature: AVX512VBMI2
+func (x Uint32x8) ShiftAllLeftAndFillUpperFrom(shift uint8, y Uint32x8) Uint32x8
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDD, CPU Feature: AVX512VBMI2
+func (x Uint32x16) ShiftAllLeftAndFillUpperFrom(shift uint8, y Uint32x16) Uint32x16
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDQ, CPU Feature: AVX512VBMI2
+func (x Uint64x2) ShiftAllLeftAndFillUpperFrom(shift uint8, y Uint64x2) Uint64x2
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDQ, CPU Feature: AVX512VBMI2
+func (x Uint64x4) ShiftAllLeftAndFillUpperFrom(shift uint8, y Uint64x4) Uint64x4
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDQ, CPU Feature: AVX512VBMI2
+func (x Uint64x8) ShiftAllLeftAndFillUpperFrom(shift uint8, y Uint64x8) Uint64x8
+
+/* ShiftAllLeftAndFillUpperFromMasked */
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDW, CPU Feature: AVX512VBMI2
+func (x Int16x8) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Int16x8, mask Mask16x8) Int16x8
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDW, CPU Feature: AVX512VBMI2
+func (x Int16x16) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Int16x16, mask Mask16x16) Int16x16
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDW, CPU Feature: AVX512VBMI2
+func (x Int16x32) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Int16x32, mask Mask16x32) Int16x32
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDD, CPU Feature: AVX512VBMI2
+func (x Int32x4) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Int32x4, mask Mask32x4) Int32x4
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDD, CPU Feature: AVX512VBMI2
+func (x Int32x8) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Int32x8, mask Mask32x8) Int32x8
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDD, CPU Feature: AVX512VBMI2
+func (x Int32x16) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Int32x16, mask Mask32x16) Int32x16
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDQ, CPU Feature: AVX512VBMI2
+func (x Int64x2) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Int64x2, mask Mask64x2) Int64x2
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDQ, CPU Feature: AVX512VBMI2
+func (x Int64x4) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Int64x4, mask Mask64x4) Int64x4
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDQ, CPU Feature: AVX512VBMI2
+func (x Int64x8) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Int64x8, mask Mask64x8) Int64x8
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDW, CPU Feature: AVX512VBMI2
+func (x Uint16x8) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Uint16x8, mask Mask16x8) Uint16x8
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDW, CPU Feature: AVX512VBMI2
+func (x Uint16x16) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Uint16x16, mask Mask16x16) Uint16x16
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDW, CPU Feature: AVX512VBMI2
+func (x Uint16x32) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Uint16x32, mask Mask16x32) Uint16x32
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDD, CPU Feature: AVX512VBMI2
+func (x Uint32x4) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Uint32x4, mask Mask32x4) Uint32x4
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDD, CPU Feature: AVX512VBMI2
+func (x Uint32x8) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Uint32x8, mask Mask32x8) Uint32x8
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDD, CPU Feature: AVX512VBMI2
+func (x Uint32x16) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Uint32x16, mask Mask32x16) Uint32x16
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDQ, CPU Feature: AVX512VBMI2
+func (x Uint64x2) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Uint64x2, mask Mask64x2) Uint64x2
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDQ, CPU Feature: AVX512VBMI2
+func (x Uint64x4) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Uint64x4, mask Mask64x4) Uint64x4
+
+// ShiftAllLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHLDQ, CPU Feature: AVX512VBMI2
+func (x Uint64x8) ShiftAllLeftAndFillUpperFromMasked(shift uint8, y Uint64x8, mask Mask64x8) Uint64x8
+
+/* ShiftAllLeftMasked */
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLW, CPU Feature: AVX512BW
+func (x Int16x8) ShiftAllLeftMasked(y uint64, mask Mask16x8) Int16x8
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLW, CPU Feature: AVX512BW
+func (x Int16x16) ShiftAllLeftMasked(y uint64, mask Mask16x16) Int16x16
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLW, CPU Feature: AVX512BW
+func (x Int16x32) ShiftAllLeftMasked(y uint64, mask Mask16x32) Int16x32
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLD, CPU Feature: AVX512F
+func (x Int32x4) ShiftAllLeftMasked(y uint64, mask Mask32x4) Int32x4
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLD, CPU Feature: AVX512F
+func (x Int32x8) ShiftAllLeftMasked(y uint64, mask Mask32x8) Int32x8
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLD, CPU Feature: AVX512F
+func (x Int32x16) ShiftAllLeftMasked(y uint64, mask Mask32x16) Int32x16
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLQ, CPU Feature: AVX512F
+func (x Int64x2) ShiftAllLeftMasked(y uint64, mask Mask64x2) Int64x2
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLQ, CPU Feature: AVX512F
+func (x Int64x4) ShiftAllLeftMasked(y uint64, mask Mask64x4) Int64x4
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLQ, CPU Feature: AVX512F
+func (x Int64x8) ShiftAllLeftMasked(y uint64, mask Mask64x8) Int64x8
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLW, CPU Feature: AVX512BW
+func (x Uint16x8) ShiftAllLeftMasked(y uint64, mask Mask16x8) Uint16x8
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLW, CPU Feature: AVX512BW
+func (x Uint16x16) ShiftAllLeftMasked(y uint64, mask Mask16x16) Uint16x16
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLW, CPU Feature: AVX512BW
+func (x Uint16x32) ShiftAllLeftMasked(y uint64, mask Mask16x32) Uint16x32
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLD, CPU Feature: AVX512F
+func (x Uint32x4) ShiftAllLeftMasked(y uint64, mask Mask32x4) Uint32x4
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLD, CPU Feature: AVX512F
+func (x Uint32x8) ShiftAllLeftMasked(y uint64, mask Mask32x8) Uint32x8
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLD, CPU Feature: AVX512F
+func (x Uint32x16) ShiftAllLeftMasked(y uint64, mask Mask32x16) Uint32x16
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLQ, CPU Feature: AVX512F
+func (x Uint64x2) ShiftAllLeftMasked(y uint64, mask Mask64x2) Uint64x2
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLQ, CPU Feature: AVX512F
+func (x Uint64x4) ShiftAllLeftMasked(y uint64, mask Mask64x4) Uint64x4
+
+// ShiftAllLeftMasked shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLQ, CPU Feature: AVX512F
+func (x Uint64x8) ShiftAllLeftMasked(y uint64, mask Mask64x8) Uint64x8
+
+/* ShiftAllRight */
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAW, CPU Feature: AVX
+func (x Int16x8) ShiftAllRight(y uint64) Int16x8
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAW, CPU Feature: AVX2
+func (x Int16x16) ShiftAllRight(y uint64) Int16x16
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAW, CPU Feature: AVX512BW
+func (x Int16x32) ShiftAllRight(y uint64) Int16x32
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAD, CPU Feature: AVX
+func (x Int32x4) ShiftAllRight(y uint64) Int32x4
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAD, CPU Feature: AVX2
+func (x Int32x8) ShiftAllRight(y uint64) Int32x8
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAD, CPU Feature: AVX512F
+func (x Int32x16) ShiftAllRight(y uint64) Int32x16
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAQ, CPU Feature: AVX512F
+func (x Int64x2) ShiftAllRight(y uint64) Int64x2
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAQ, CPU Feature: AVX512F
+func (x Int64x4) ShiftAllRight(y uint64) Int64x4
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAQ, CPU Feature: AVX512F
+func (x Int64x8) ShiftAllRight(y uint64) Int64x8
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLW, CPU Feature: AVX
+func (x Uint16x8) ShiftAllRight(y uint64) Uint16x8
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLW, CPU Feature: AVX2
+func (x Uint16x16) ShiftAllRight(y uint64) Uint16x16
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLW, CPU Feature: AVX512BW
+func (x Uint16x32) ShiftAllRight(y uint64) Uint16x32
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLD, CPU Feature: AVX
+func (x Uint32x4) ShiftAllRight(y uint64) Uint32x4
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLD, CPU Feature: AVX2
+func (x Uint32x8) ShiftAllRight(y uint64) Uint32x8
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLD, CPU Feature: AVX512F
+func (x Uint32x16) ShiftAllRight(y uint64) Uint32x16
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLQ, CPU Feature: AVX
+func (x Uint64x2) ShiftAllRight(y uint64) Uint64x2
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLQ, CPU Feature: AVX2
+func (x Uint64x4) ShiftAllRight(y uint64) Uint64x4
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLQ, CPU Feature: AVX512F
+func (x Uint64x8) ShiftAllRight(y uint64) Uint64x8
+
+/* ShiftAllRightAndFillUpperFrom */
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDW, CPU Feature: AVX512VBMI2
+func (x Int16x8) ShiftAllRightAndFillUpperFrom(shift uint8, y Int16x8) Int16x8
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDW, CPU Feature: AVX512VBMI2
+func (x Int16x16) ShiftAllRightAndFillUpperFrom(shift uint8, y Int16x16) Int16x16
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDW, CPU Feature: AVX512VBMI2
+func (x Int16x32) ShiftAllRightAndFillUpperFrom(shift uint8, y Int16x32) Int16x32
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512VBMI2
+func (x Int32x4) ShiftAllRightAndFillUpperFrom(shift uint8, y Int32x4) Int32x4
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512VBMI2
+func (x Int32x8) ShiftAllRightAndFillUpperFrom(shift uint8, y Int32x8) Int32x8
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512VBMI2
+func (x Int32x16) ShiftAllRightAndFillUpperFrom(shift uint8, y Int32x16) Int32x16
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDQ, CPU Feature: AVX512VBMI2
+func (x Int64x2) ShiftAllRightAndFillUpperFrom(shift uint8, y Int64x2) Int64x2
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDQ, CPU Feature: AVX512VBMI2
+func (x Int64x4) ShiftAllRightAndFillUpperFrom(shift uint8, y Int64x4) Int64x4
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDQ, CPU Feature: AVX512VBMI2
+func (x Int64x8) ShiftAllRightAndFillUpperFrom(shift uint8, y Int64x8) Int64x8
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDW, CPU Feature: AVX512VBMI2
+func (x Uint16x8) ShiftAllRightAndFillUpperFrom(shift uint8, y Uint16x8) Uint16x8
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDW, CPU Feature: AVX512VBMI2
+func (x Uint16x16) ShiftAllRightAndFillUpperFrom(shift uint8, y Uint16x16) Uint16x16
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDW, CPU Feature: AVX512VBMI2
+func (x Uint16x32) ShiftAllRightAndFillUpperFrom(shift uint8, y Uint16x32) Uint16x32
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512VBMI2
+func (x Uint32x4) ShiftAllRightAndFillUpperFrom(shift uint8, y Uint32x4) Uint32x4
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512VBMI2
+func (x Uint32x8) ShiftAllRightAndFillUpperFrom(shift uint8, y Uint32x8) Uint32x8
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512VBMI2
+func (x Uint32x16) ShiftAllRightAndFillUpperFrom(shift uint8, y Uint32x16) Uint32x16
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDQ, CPU Feature: AVX512VBMI2
+func (x Uint64x2) ShiftAllRightAndFillUpperFrom(shift uint8, y Uint64x2) Uint64x2
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDQ, CPU Feature: AVX512VBMI2
+func (x Uint64x4) ShiftAllRightAndFillUpperFrom(shift uint8, y Uint64x4) Uint64x4
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDQ, CPU Feature: AVX512VBMI2
+func (x Uint64x8) ShiftAllRightAndFillUpperFrom(shift uint8, y Uint64x8) Uint64x8
+
+/* ShiftAllRightAndFillUpperFromMasked */
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDW, CPU Feature: AVX512VBMI2
+func (x Int16x8) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Int16x8, mask Mask16x8) Int16x8
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDW, CPU Feature: AVX512VBMI2
+func (x Int16x16) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Int16x16, mask Mask16x16) Int16x16
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDW, CPU Feature: AVX512VBMI2
+func (x Int16x32) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Int16x32, mask Mask16x32) Int16x32
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512VBMI2
+func (x Int32x4) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Int32x4, mask Mask32x4) Int32x4
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512VBMI2
+func (x Int32x8) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Int32x8, mask Mask32x8) Int32x8
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512VBMI2
+func (x Int32x16) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Int32x16, mask Mask32x16) Int32x16
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDQ, CPU Feature: AVX512VBMI2
+func (x Int64x2) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Int64x2, mask Mask64x2) Int64x2
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDQ, CPU Feature: AVX512VBMI2
+func (x Int64x4) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Int64x4, mask Mask64x4) Int64x4
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDQ, CPU Feature: AVX512VBMI2
+func (x Int64x8) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Int64x8, mask Mask64x8) Int64x8
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDW, CPU Feature: AVX512VBMI2
+func (x Uint16x8) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Uint16x8, mask Mask16x8) Uint16x8
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDW, CPU Feature: AVX512VBMI2
+func (x Uint16x16) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Uint16x16, mask Mask16x16) Uint16x16
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDW, CPU Feature: AVX512VBMI2
+func (x Uint16x32) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Uint16x32, mask Mask16x32) Uint16x32
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512VBMI2
+func (x Uint32x4) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Uint32x4, mask Mask32x4) Uint32x4
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512VBMI2
+func (x Uint32x8) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Uint32x8, mask Mask32x8) Uint32x8
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512VBMI2
+func (x Uint32x16) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Uint32x16, mask Mask32x16) Uint32x16
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDQ, CPU Feature: AVX512VBMI2
+func (x Uint64x2) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Uint64x2, mask Mask64x2) Uint64x2
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDQ, CPU Feature: AVX512VBMI2
+func (x Uint64x4) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Uint64x4, mask Mask64x4) Uint64x4
+
+// ShiftAllRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// shift is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VPSHRDQ, CPU Feature: AVX512VBMI2
+func (x Uint64x8) ShiftAllRightAndFillUpperFromMasked(shift uint8, y Uint64x8, mask Mask64x8) Uint64x8
+
+/* ShiftAllRightMasked */
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAW, CPU Feature: AVX512BW
+func (x Int16x8) ShiftAllRightMasked(y uint64, mask Mask16x8) Int16x8
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAW, CPU Feature: AVX512BW
+func (x Int16x16) ShiftAllRightMasked(y uint64, mask Mask16x16) Int16x16
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAW, CPU Feature: AVX512BW
+func (x Int16x32) ShiftAllRightMasked(y uint64, mask Mask16x32) Int16x32
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAD, CPU Feature: AVX512F
+func (x Int32x4) ShiftAllRightMasked(y uint64, mask Mask32x4) Int32x4
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAD, CPU Feature: AVX512F
+func (x Int32x8) ShiftAllRightMasked(y uint64, mask Mask32x8) Int32x8
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAD, CPU Feature: AVX512F
+func (x Int32x16) ShiftAllRightMasked(y uint64, mask Mask32x16) Int32x16
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAQ, CPU Feature: AVX512F
+func (x Int64x2) ShiftAllRightMasked(y uint64, mask Mask64x2) Int64x2
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAQ, CPU Feature: AVX512F
+func (x Int64x4) ShiftAllRightMasked(y uint64, mask Mask64x4) Int64x4
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAQ, CPU Feature: AVX512F
+func (x Int64x8) ShiftAllRightMasked(y uint64, mask Mask64x8) Int64x8
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLW, CPU Feature: AVX512BW
+func (x Uint16x8) ShiftAllRightMasked(y uint64, mask Mask16x8) Uint16x8
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLW, CPU Feature: AVX512BW
+func (x Uint16x16) ShiftAllRightMasked(y uint64, mask Mask16x16) Uint16x16
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLW, CPU Feature: AVX512BW
+func (x Uint16x32) ShiftAllRightMasked(y uint64, mask Mask16x32) Uint16x32
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLD, CPU Feature: AVX512F
+func (x Uint32x4) ShiftAllRightMasked(y uint64, mask Mask32x4) Uint32x4
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLD, CPU Feature: AVX512F
+func (x Uint32x8) ShiftAllRightMasked(y uint64, mask Mask32x8) Uint32x8
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLD, CPU Feature: AVX512F
+func (x Uint32x16) ShiftAllRightMasked(y uint64, mask Mask32x16) Uint32x16
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLQ, CPU Feature: AVX512F
+func (x Uint64x2) ShiftAllRightMasked(y uint64, mask Mask64x2) Uint64x2
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLQ, CPU Feature: AVX512F
+func (x Uint64x4) ShiftAllRightMasked(y uint64, mask Mask64x4) Uint64x4
+
+// ShiftAllRightMasked shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLQ, CPU Feature: AVX512F
+func (x Uint64x8) ShiftAllRightMasked(y uint64, mask Mask64x8) Uint64x8
+
+/* ShiftLeft */
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVW, CPU Feature: AVX512BW
+func (x Int16x8) ShiftLeft(y Int16x8) Int16x8
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVW, CPU Feature: AVX512BW
+func (x Int16x16) ShiftLeft(y Int16x16) Int16x16
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVW, CPU Feature: AVX512BW
+func (x Int16x32) ShiftLeft(y Int16x32) Int16x32
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVD, CPU Feature: AVX2
+func (x Int32x4) ShiftLeft(y Int32x4) Int32x4
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVD, CPU Feature: AVX2
+func (x Int32x8) ShiftLeft(y Int32x8) Int32x8
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVD, CPU Feature: AVX512F
+func (x Int32x16) ShiftLeft(y Int32x16) Int32x16
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVQ, CPU Feature: AVX2
+func (x Int64x2) ShiftLeft(y Int64x2) Int64x2
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVQ, CPU Feature: AVX2
+func (x Int64x4) ShiftLeft(y Int64x4) Int64x4
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVQ, CPU Feature: AVX512F
+func (x Int64x8) ShiftLeft(y Int64x8) Int64x8
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVW, CPU Feature: AVX512BW
+func (x Uint16x8) ShiftLeft(y Uint16x8) Uint16x8
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVW, CPU Feature: AVX512BW
+func (x Uint16x16) ShiftLeft(y Uint16x16) Uint16x16
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVW, CPU Feature: AVX512BW
+func (x Uint16x32) ShiftLeft(y Uint16x32) Uint16x32
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVD, CPU Feature: AVX2
+func (x Uint32x4) ShiftLeft(y Uint32x4) Uint32x4
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVD, CPU Feature: AVX2
+func (x Uint32x8) ShiftLeft(y Uint32x8) Uint32x8
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVD, CPU Feature: AVX512F
+func (x Uint32x16) ShiftLeft(y Uint32x16) Uint32x16
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVQ, CPU Feature: AVX2
+func (x Uint64x2) ShiftLeft(y Uint64x2) Uint64x2
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVQ, CPU Feature: AVX2
+func (x Uint64x4) ShiftLeft(y Uint64x4) Uint64x4
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVQ, CPU Feature: AVX512F
+func (x Uint64x8) ShiftLeft(y Uint64x8) Uint64x8
+
+/* ShiftLeftAndFillUpperFrom */
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVW, CPU Feature: AVX512VBMI2
+func (x Int16x8) ShiftLeftAndFillUpperFrom(y Int16x8, z Int16x8) Int16x8
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVW, CPU Feature: AVX512VBMI2
+func (x Int16x16) ShiftLeftAndFillUpperFrom(y Int16x16, z Int16x16) Int16x16
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVW, CPU Feature: AVX512VBMI2
+func (x Int16x32) ShiftLeftAndFillUpperFrom(y Int16x32, z Int16x32) Int16x32
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVD, CPU Feature: AVX512VBMI2
+func (x Int32x4) ShiftLeftAndFillUpperFrom(y Int32x4, z Int32x4) Int32x4
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVD, CPU Feature: AVX512VBMI2
+func (x Int32x8) ShiftLeftAndFillUpperFrom(y Int32x8, z Int32x8) Int32x8
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVD, CPU Feature: AVX512VBMI2
+func (x Int32x16) ShiftLeftAndFillUpperFrom(y Int32x16, z Int32x16) Int32x16
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVQ, CPU Feature: AVX512VBMI2
+func (x Int64x2) ShiftLeftAndFillUpperFrom(y Int64x2, z Int64x2) Int64x2
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVQ, CPU Feature: AVX512VBMI2
+func (x Int64x4) ShiftLeftAndFillUpperFrom(y Int64x4, z Int64x4) Int64x4
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVQ, CPU Feature: AVX512VBMI2
+func (x Int64x8) ShiftLeftAndFillUpperFrom(y Int64x8, z Int64x8) Int64x8
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVW, CPU Feature: AVX512VBMI2
+func (x Uint16x8) ShiftLeftAndFillUpperFrom(y Uint16x8, z Uint16x8) Uint16x8
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVW, CPU Feature: AVX512VBMI2
+func (x Uint16x16) ShiftLeftAndFillUpperFrom(y Uint16x16, z Uint16x16) Uint16x16
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVW, CPU Feature: AVX512VBMI2
+func (x Uint16x32) ShiftLeftAndFillUpperFrom(y Uint16x32, z Uint16x32) Uint16x32
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVD, CPU Feature: AVX512VBMI2
+func (x Uint32x4) ShiftLeftAndFillUpperFrom(y Uint32x4, z Uint32x4) Uint32x4
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVD, CPU Feature: AVX512VBMI2
+func (x Uint32x8) ShiftLeftAndFillUpperFrom(y Uint32x8, z Uint32x8) Uint32x8
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVD, CPU Feature: AVX512VBMI2
+func (x Uint32x16) ShiftLeftAndFillUpperFrom(y Uint32x16, z Uint32x16) Uint32x16
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVQ, CPU Feature: AVX512VBMI2
+func (x Uint64x2) ShiftLeftAndFillUpperFrom(y Uint64x2, z Uint64x2) Uint64x2
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVQ, CPU Feature: AVX512VBMI2
+func (x Uint64x4) ShiftLeftAndFillUpperFrom(y Uint64x4, z Uint64x4) Uint64x4
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVQ, CPU Feature: AVX512VBMI2
+func (x Uint64x8) ShiftLeftAndFillUpperFrom(y Uint64x8, z Uint64x8) Uint64x8
+
+/* ShiftLeftAndFillUpperFromMasked */
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVW, CPU Feature: AVX512VBMI2
+func (x Int16x8) ShiftLeftAndFillUpperFromMasked(y Int16x8, z Int16x8, mask Mask16x8) Int16x8
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVW, CPU Feature: AVX512VBMI2
+func (x Int16x16) ShiftLeftAndFillUpperFromMasked(y Int16x16, z Int16x16, mask Mask16x16) Int16x16
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVW, CPU Feature: AVX512VBMI2
+func (x Int16x32) ShiftLeftAndFillUpperFromMasked(y Int16x32, z Int16x32, mask Mask16x32) Int16x32
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVD, CPU Feature: AVX512VBMI2
+func (x Int32x4) ShiftLeftAndFillUpperFromMasked(y Int32x4, z Int32x4, mask Mask32x4) Int32x4
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVD, CPU Feature: AVX512VBMI2
+func (x Int32x8) ShiftLeftAndFillUpperFromMasked(y Int32x8, z Int32x8, mask Mask32x8) Int32x8
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVD, CPU Feature: AVX512VBMI2
+func (x Int32x16) ShiftLeftAndFillUpperFromMasked(y Int32x16, z Int32x16, mask Mask32x16) Int32x16
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVQ, CPU Feature: AVX512VBMI2
+func (x Int64x2) ShiftLeftAndFillUpperFromMasked(y Int64x2, z Int64x2, mask Mask64x2) Int64x2
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVQ, CPU Feature: AVX512VBMI2
+func (x Int64x4) ShiftLeftAndFillUpperFromMasked(y Int64x4, z Int64x4, mask Mask64x4) Int64x4
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVQ, CPU Feature: AVX512VBMI2
+func (x Int64x8) ShiftLeftAndFillUpperFromMasked(y Int64x8, z Int64x8, mask Mask64x8) Int64x8
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVW, CPU Feature: AVX512VBMI2
+func (x Uint16x8) ShiftLeftAndFillUpperFromMasked(y Uint16x8, z Uint16x8, mask Mask16x8) Uint16x8
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVW, CPU Feature: AVX512VBMI2
+func (x Uint16x16) ShiftLeftAndFillUpperFromMasked(y Uint16x16, z Uint16x16, mask Mask16x16) Uint16x16
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVW, CPU Feature: AVX512VBMI2
+func (x Uint16x32) ShiftLeftAndFillUpperFromMasked(y Uint16x32, z Uint16x32, mask Mask16x32) Uint16x32
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVD, CPU Feature: AVX512VBMI2
+func (x Uint32x4) ShiftLeftAndFillUpperFromMasked(y Uint32x4, z Uint32x4, mask Mask32x4) Uint32x4
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVD, CPU Feature: AVX512VBMI2
+func (x Uint32x8) ShiftLeftAndFillUpperFromMasked(y Uint32x8, z Uint32x8, mask Mask32x8) Uint32x8
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVD, CPU Feature: AVX512VBMI2
+func (x Uint32x16) ShiftLeftAndFillUpperFromMasked(y Uint32x16, z Uint32x16, mask Mask32x16) Uint32x16
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVQ, CPU Feature: AVX512VBMI2
+func (x Uint64x2) ShiftLeftAndFillUpperFromMasked(y Uint64x2, z Uint64x2, mask Mask64x2) Uint64x2
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVQ, CPU Feature: AVX512VBMI2
+func (x Uint64x4) ShiftLeftAndFillUpperFromMasked(y Uint64x4, z Uint64x4, mask Mask64x4) Uint64x4
+
+// ShiftLeftAndFillUpperFromMasked shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHLDVQ, CPU Feature: AVX512VBMI2
+func (x Uint64x8) ShiftLeftAndFillUpperFromMasked(y Uint64x8, z Uint64x8, mask Mask64x8) Uint64x8
+
+/* ShiftLeftMasked */
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVW, CPU Feature: AVX512BW
+func (x Int16x8) ShiftLeftMasked(y Int16x8, mask Mask16x8) Int16x8
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVW, CPU Feature: AVX512BW
+func (x Int16x16) ShiftLeftMasked(y Int16x16, mask Mask16x16) Int16x16
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVW, CPU Feature: AVX512BW
+func (x Int16x32) ShiftLeftMasked(y Int16x32, mask Mask16x32) Int16x32
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVD, CPU Feature: AVX512F
+func (x Int32x4) ShiftLeftMasked(y Int32x4, mask Mask32x4) Int32x4
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVD, CPU Feature: AVX512F
+func (x Int32x8) ShiftLeftMasked(y Int32x8, mask Mask32x8) Int32x8
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVD, CPU Feature: AVX512F
+func (x Int32x16) ShiftLeftMasked(y Int32x16, mask Mask32x16) Int32x16
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVQ, CPU Feature: AVX512F
+func (x Int64x2) ShiftLeftMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVQ, CPU Feature: AVX512F
+func (x Int64x4) ShiftLeftMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVQ, CPU Feature: AVX512F
+func (x Int64x8) ShiftLeftMasked(y Int64x8, mask Mask64x8) Int64x8
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVW, CPU Feature: AVX512BW
+func (x Uint16x8) ShiftLeftMasked(y Uint16x8, mask Mask16x8) Uint16x8
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVW, CPU Feature: AVX512BW
+func (x Uint16x16) ShiftLeftMasked(y Uint16x16, mask Mask16x16) Uint16x16
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVW, CPU Feature: AVX512BW
+func (x Uint16x32) ShiftLeftMasked(y Uint16x32, mask Mask16x32) Uint16x32
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVD, CPU Feature: AVX512F
+func (x Uint32x4) ShiftLeftMasked(y Uint32x4, mask Mask32x4) Uint32x4
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVD, CPU Feature: AVX512F
+func (x Uint32x8) ShiftLeftMasked(y Uint32x8, mask Mask32x8) Uint32x8
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVD, CPU Feature: AVX512F
+func (x Uint32x16) ShiftLeftMasked(y Uint32x16, mask Mask32x16) Uint32x16
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVQ, CPU Feature: AVX512F
+func (x Uint64x2) ShiftLeftMasked(y Uint64x2, mask Mask64x2) Uint64x2
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVQ, CPU Feature: AVX512F
+func (x Uint64x4) ShiftLeftMasked(y Uint64x4, mask Mask64x4) Uint64x4
+
+// ShiftLeftMasked shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSLLVQ, CPU Feature: AVX512F
+func (x Uint64x8) ShiftLeftMasked(y Uint64x8, mask Mask64x8) Uint64x8
+
+/* ShiftRight */
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAVW, CPU Feature: AVX512BW
+func (x Int16x8) ShiftRight(y Int16x8) Int16x8
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAVW, CPU Feature: AVX512BW
+func (x Int16x16) ShiftRight(y Int16x16) Int16x16
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAVW, CPU Feature: AVX512BW
+func (x Int16x32) ShiftRight(y Int16x32) Int16x32
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAVD, CPU Feature: AVX2
+func (x Int32x4) ShiftRight(y Int32x4) Int32x4
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAVD, CPU Feature: AVX2
+func (x Int32x8) ShiftRight(y Int32x8) Int32x8
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAVD, CPU Feature: AVX512F
+func (x Int32x16) ShiftRight(y Int32x16) Int32x16
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAVQ, CPU Feature: AVX512F
+func (x Int64x2) ShiftRight(y Int64x2) Int64x2
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAVQ, CPU Feature: AVX512F
+func (x Int64x4) ShiftRight(y Int64x4) Int64x4
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAVQ, CPU Feature: AVX512F
+func (x Int64x8) ShiftRight(y Int64x8) Int64x8
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLVW, CPU Feature: AVX512BW
+func (x Uint16x8) ShiftRight(y Uint16x8) Uint16x8
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLVW, CPU Feature: AVX512BW
+func (x Uint16x16) ShiftRight(y Uint16x16) Uint16x16
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLVW, CPU Feature: AVX512BW
+func (x Uint16x32) ShiftRight(y Uint16x32) Uint16x32
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLVD, CPU Feature: AVX2
+func (x Uint32x4) ShiftRight(y Uint32x4) Uint32x4
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLVD, CPU Feature: AVX2
+func (x Uint32x8) ShiftRight(y Uint32x8) Uint32x8
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLVD, CPU Feature: AVX512F
+func (x Uint32x16) ShiftRight(y Uint32x16) Uint32x16
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLVQ, CPU Feature: AVX2
+func (x Uint64x2) ShiftRight(y Uint64x2) Uint64x2
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLVQ, CPU Feature: AVX2
+func (x Uint64x4) ShiftRight(y Uint64x4) Uint64x4
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLVQ, CPU Feature: AVX512F
+func (x Uint64x8) ShiftRight(y Uint64x8) Uint64x8
+
+/* ShiftRightAndFillUpperFrom */
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512VBMI2
+func (x Int16x8) ShiftRightAndFillUpperFrom(y Int16x8, z Int16x8) Int16x8
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512VBMI2
+func (x Int16x16) ShiftRightAndFillUpperFrom(y Int16x16, z Int16x16) Int16x16
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512VBMI2
+func (x Int16x32) ShiftRightAndFillUpperFrom(y Int16x32, z Int16x32) Int16x32
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVD, CPU Feature: AVX512VBMI2
+func (x Int32x4) ShiftRightAndFillUpperFrom(y Int32x4, z Int32x4) Int32x4
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVD, CPU Feature: AVX512VBMI2
+func (x Int32x8) ShiftRightAndFillUpperFrom(y Int32x8, z Int32x8) Int32x8
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVD, CPU Feature: AVX512VBMI2
+func (x Int32x16) ShiftRightAndFillUpperFrom(y Int32x16, z Int32x16) Int32x16
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVQ, CPU Feature: AVX512VBMI2
+func (x Int64x2) ShiftRightAndFillUpperFrom(y Int64x2, z Int64x2) Int64x2
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVQ, CPU Feature: AVX512VBMI2
+func (x Int64x4) ShiftRightAndFillUpperFrom(y Int64x4, z Int64x4) Int64x4
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVQ, CPU Feature: AVX512VBMI2
+func (x Int64x8) ShiftRightAndFillUpperFrom(y Int64x8, z Int64x8) Int64x8
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512VBMI2
+func (x Uint16x8) ShiftRightAndFillUpperFrom(y Uint16x8, z Uint16x8) Uint16x8
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512VBMI2
+func (x Uint16x16) ShiftRightAndFillUpperFrom(y Uint16x16, z Uint16x16) Uint16x16
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512VBMI2
+func (x Uint16x32) ShiftRightAndFillUpperFrom(y Uint16x32, z Uint16x32) Uint16x32
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVD, CPU Feature: AVX512VBMI2
+func (x Uint32x4) ShiftRightAndFillUpperFrom(y Uint32x4, z Uint32x4) Uint32x4
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVD, CPU Feature: AVX512VBMI2
+func (x Uint32x8) ShiftRightAndFillUpperFrom(y Uint32x8, z Uint32x8) Uint32x8
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVD, CPU Feature: AVX512VBMI2
+func (x Uint32x16) ShiftRightAndFillUpperFrom(y Uint32x16, z Uint32x16) Uint32x16
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVQ, CPU Feature: AVX512VBMI2
+func (x Uint64x2) ShiftRightAndFillUpperFrom(y Uint64x2, z Uint64x2) Uint64x2
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVQ, CPU Feature: AVX512VBMI2
+func (x Uint64x4) ShiftRightAndFillUpperFrom(y Uint64x4, z Uint64x4) Uint64x4
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVQ, CPU Feature: AVX512VBMI2
+func (x Uint64x8) ShiftRightAndFillUpperFrom(y Uint64x8, z Uint64x8) Uint64x8
+
+/* ShiftRightAndFillUpperFromMasked */
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512VBMI2
+func (x Int16x8) ShiftRightAndFillUpperFromMasked(y Int16x8, z Int16x8, mask Mask16x8) Int16x8
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512VBMI2
+func (x Int16x16) ShiftRightAndFillUpperFromMasked(y Int16x16, z Int16x16, mask Mask16x16) Int16x16
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512VBMI2
+func (x Int16x32) ShiftRightAndFillUpperFromMasked(y Int16x32, z Int16x32, mask Mask16x32) Int16x32
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVD, CPU Feature: AVX512VBMI2
+func (x Int32x4) ShiftRightAndFillUpperFromMasked(y Int32x4, z Int32x4, mask Mask32x4) Int32x4
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVD, CPU Feature: AVX512VBMI2
+func (x Int32x8) ShiftRightAndFillUpperFromMasked(y Int32x8, z Int32x8, mask Mask32x8) Int32x8
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVD, CPU Feature: AVX512VBMI2
+func (x Int32x16) ShiftRightAndFillUpperFromMasked(y Int32x16, z Int32x16, mask Mask32x16) Int32x16
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVQ, CPU Feature: AVX512VBMI2
+func (x Int64x2) ShiftRightAndFillUpperFromMasked(y Int64x2, z Int64x2, mask Mask64x2) Int64x2
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVQ, CPU Feature: AVX512VBMI2
+func (x Int64x4) ShiftRightAndFillUpperFromMasked(y Int64x4, z Int64x4, mask Mask64x4) Int64x4
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVQ, CPU Feature: AVX512VBMI2
+func (x Int64x8) ShiftRightAndFillUpperFromMasked(y Int64x8, z Int64x8, mask Mask64x8) Int64x8
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512VBMI2
+func (x Uint16x8) ShiftRightAndFillUpperFromMasked(y Uint16x8, z Uint16x8, mask Mask16x8) Uint16x8
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512VBMI2
+func (x Uint16x16) ShiftRightAndFillUpperFromMasked(y Uint16x16, z Uint16x16, mask Mask16x16) Uint16x16
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512VBMI2
+func (x Uint16x32) ShiftRightAndFillUpperFromMasked(y Uint16x32, z Uint16x32, mask Mask16x32) Uint16x32
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVD, CPU Feature: AVX512VBMI2
+func (x Uint32x4) ShiftRightAndFillUpperFromMasked(y Uint32x4, z Uint32x4, mask Mask32x4) Uint32x4
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVD, CPU Feature: AVX512VBMI2
+func (x Uint32x8) ShiftRightAndFillUpperFromMasked(y Uint32x8, z Uint32x8, mask Mask32x8) Uint32x8
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVD, CPU Feature: AVX512VBMI2
+func (x Uint32x16) ShiftRightAndFillUpperFromMasked(y Uint32x16, z Uint32x16, mask Mask32x16) Uint32x16
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVQ, CPU Feature: AVX512VBMI2
+func (x Uint64x2) ShiftRightAndFillUpperFromMasked(y Uint64x2, z Uint64x2, mask Mask64x2) Uint64x2
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVQ, CPU Feature: AVX512VBMI2
+func (x Uint64x4) ShiftRightAndFillUpperFromMasked(y Uint64x4, z Uint64x4, mask Mask64x4) Uint64x4
+
+// ShiftRightAndFillUpperFromMasked shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSHRDVQ, CPU Feature: AVX512VBMI2
+func (x Uint64x8) ShiftRightAndFillUpperFromMasked(y Uint64x8, z Uint64x8, mask Mask64x8) Uint64x8
+
+/* ShiftRightMasked */
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAVW, CPU Feature: AVX512BW
+func (x Int16x8) ShiftRightMasked(y Int16x8, mask Mask16x8) Int16x8
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAVW, CPU Feature: AVX512BW
+func (x Int16x16) ShiftRightMasked(y Int16x16, mask Mask16x16) Int16x16
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAVW, CPU Feature: AVX512BW
+func (x Int16x32) ShiftRightMasked(y Int16x32, mask Mask16x32) Int16x32
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAVD, CPU Feature: AVX512F
+func (x Int32x4) ShiftRightMasked(y Int32x4, mask Mask32x4) Int32x4
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAVD, CPU Feature: AVX512F
+func (x Int32x8) ShiftRightMasked(y Int32x8, mask Mask32x8) Int32x8
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAVD, CPU Feature: AVX512F
+func (x Int32x16) ShiftRightMasked(y Int32x16, mask Mask32x16) Int32x16
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAVQ, CPU Feature: AVX512F
+func (x Int64x2) ShiftRightMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAVQ, CPU Feature: AVX512F
+func (x Int64x4) ShiftRightMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRAVQ, CPU Feature: AVX512F
+func (x Int64x8) ShiftRightMasked(y Int64x8, mask Mask64x8) Int64x8
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLVW, CPU Feature: AVX512BW
+func (x Uint16x8) ShiftRightMasked(y Uint16x8, mask Mask16x8) Uint16x8
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLVW, CPU Feature: AVX512BW
+func (x Uint16x16) ShiftRightMasked(y Uint16x16, mask Mask16x16) Uint16x16
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLVW, CPU Feature: AVX512BW
+func (x Uint16x32) ShiftRightMasked(y Uint16x32, mask Mask16x32) Uint16x32
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLVD, CPU Feature: AVX512F
+func (x Uint32x4) ShiftRightMasked(y Uint32x4, mask Mask32x4) Uint32x4
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLVD, CPU Feature: AVX512F
+func (x Uint32x8) ShiftRightMasked(y Uint32x8, mask Mask32x8) Uint32x8
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLVD, CPU Feature: AVX512F
+func (x Uint32x16) ShiftRightMasked(y Uint32x16, mask Mask32x16) Uint32x16
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLVQ, CPU Feature: AVX512F
+func (x Uint64x2) ShiftRightMasked(y Uint64x2, mask Mask64x2) Uint64x2
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLVQ, CPU Feature: AVX512F
+func (x Uint64x4) ShiftRightMasked(y Uint64x4, mask Mask64x4) Uint64x4
+
+// ShiftRightMasked shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSRLVQ, CPU Feature: AVX512F
+func (x Uint64x8) ShiftRightMasked(y Uint64x8, mask Mask64x8) Uint64x8
+
+/* Sign */
+
+// Sign returns the product of the first operand with -1, 0, or 1,
+// whichever constant is nearest to the value of the second operand.
+//
+// Asm: VPSIGNB, CPU Feature: AVX
+func (x Int8x16) Sign(y Int8x16) Int8x16
+
+// Sign returns the product of the first operand with -1, 0, or 1,
+// whichever constant is nearest to the value of the second operand.
+//
+// Asm: VPSIGNB, CPU Feature: AVX2
+func (x Int8x32) Sign(y Int8x32) Int8x32
+
+// Sign returns the product of the first operand with -1, 0, or 1,
+// whichever constant is nearest to the value of the second operand.
+//
+// Asm: VPSIGNW, CPU Feature: AVX
+func (x Int16x8) Sign(y Int16x8) Int16x8
+
+// Sign returns the product of the first operand with -1, 0, or 1,
+// whichever constant is nearest to the value of the second operand.
+//
+// Asm: VPSIGNW, CPU Feature: AVX2
+func (x Int16x16) Sign(y Int16x16) Int16x16
+
+// Sign returns the product of the first operand with -1, 0, or 1,
+// whichever constant is nearest to the value of the second operand.
+//
+// Asm: VPSIGND, CPU Feature: AVX
+func (x Int32x4) Sign(y Int32x4) Int32x4
+
+// Sign returns the product of the first operand with -1, 0, or 1,
+// whichever constant is nearest to the value of the second operand.
+//
+// Asm: VPSIGND, CPU Feature: AVX2
+func (x Int32x8) Sign(y Int32x8) Int32x8
+
+/* Sqrt */
+
+// Sqrt computes the square root of each element.
+//
+// Asm: VSQRTPS, CPU Feature: AVX
+func (x Float32x4) Sqrt() Float32x4
+
+// Sqrt computes the square root of each element.
+//
+// Asm: VSQRTPS, CPU Feature: AVX
+func (x Float32x8) Sqrt() Float32x8
+
+// Sqrt computes the square root of each element.
+//
+// Asm: VSQRTPS, CPU Feature: AVX512F
+func (x Float32x16) Sqrt() Float32x16
+
+// Sqrt computes the square root of each element.
+//
+// Asm: VSQRTPD, CPU Feature: AVX
+func (x Float64x2) Sqrt() Float64x2
+
+// Sqrt computes the square root of each element.
+//
+// Asm: VSQRTPD, CPU Feature: AVX
+func (x Float64x4) Sqrt() Float64x4
+
+// Sqrt computes the square root of each element.
+//
+// Asm: VSQRTPD, CPU Feature: AVX512F
+func (x Float64x8) Sqrt() Float64x8
+
+/* SqrtMasked */
+
+// SqrtMasked computes the square root of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSQRTPS, CPU Feature: AVX512F
+func (x Float32x4) SqrtMasked(mask Mask32x4) Float32x4
+
+// SqrtMasked computes the square root of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSQRTPS, CPU Feature: AVX512F
+func (x Float32x8) SqrtMasked(mask Mask32x8) Float32x8
+
+// SqrtMasked computes the square root of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSQRTPS, CPU Feature: AVX512F
+func (x Float32x16) SqrtMasked(mask Mask32x16) Float32x16
+
+// SqrtMasked computes the square root of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSQRTPD, CPU Feature: AVX512F
+func (x Float64x2) SqrtMasked(mask Mask64x2) Float64x2
+
+// SqrtMasked computes the square root of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSQRTPD, CPU Feature: AVX512F
+func (x Float64x4) SqrtMasked(mask Mask64x4) Float64x4
+
+// SqrtMasked computes the square root of each element.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSQRTPD, CPU Feature: AVX512F
+func (x Float64x8) SqrtMasked(mask Mask64x8) Float64x8
+
+/* Sub */
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VSUBPS, CPU Feature: AVX
+func (x Float32x4) Sub(y Float32x4) Float32x4
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VSUBPS, CPU Feature: AVX
+func (x Float32x8) Sub(y Float32x8) Float32x8
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VSUBPS, CPU Feature: AVX512F
+func (x Float32x16) Sub(y Float32x16) Float32x16
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VSUBPD, CPU Feature: AVX
+func (x Float64x2) Sub(y Float64x2) Float64x2
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VSUBPD, CPU Feature: AVX
+func (x Float64x4) Sub(y Float64x4) Float64x4
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VSUBPD, CPU Feature: AVX512F
+func (x Float64x8) Sub(y Float64x8) Float64x8
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBB, CPU Feature: AVX
+func (x Int8x16) Sub(y Int8x16) Int8x16
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBB, CPU Feature: AVX2
+func (x Int8x32) Sub(y Int8x32) Int8x32
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBB, CPU Feature: AVX512BW
+func (x Int8x64) Sub(y Int8x64) Int8x64
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBW, CPU Feature: AVX
+func (x Int16x8) Sub(y Int16x8) Int16x8
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBW, CPU Feature: AVX2
+func (x Int16x16) Sub(y Int16x16) Int16x16
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBW, CPU Feature: AVX512BW
+func (x Int16x32) Sub(y Int16x32) Int16x32
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBD, CPU Feature: AVX
+func (x Int32x4) Sub(y Int32x4) Int32x4
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBD, CPU Feature: AVX2
+func (x Int32x8) Sub(y Int32x8) Int32x8
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBD, CPU Feature: AVX512F
+func (x Int32x16) Sub(y Int32x16) Int32x16
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBQ, CPU Feature: AVX
+func (x Int64x2) Sub(y Int64x2) Int64x2
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBQ, CPU Feature: AVX2
+func (x Int64x4) Sub(y Int64x4) Int64x4
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBQ, CPU Feature: AVX512F
+func (x Int64x8) Sub(y Int64x8) Int64x8
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBB, CPU Feature: AVX
+func (x Uint8x16) Sub(y Uint8x16) Uint8x16
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBB, CPU Feature: AVX2
+func (x Uint8x32) Sub(y Uint8x32) Uint8x32
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBB, CPU Feature: AVX512BW
+func (x Uint8x64) Sub(y Uint8x64) Uint8x64
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBW, CPU Feature: AVX
+func (x Uint16x8) Sub(y Uint16x8) Uint16x8
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBW, CPU Feature: AVX2
+func (x Uint16x16) Sub(y Uint16x16) Uint16x16
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBW, CPU Feature: AVX512BW
+func (x Uint16x32) Sub(y Uint16x32) Uint16x32
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBD, CPU Feature: AVX
+func (x Uint32x4) Sub(y Uint32x4) Uint32x4
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBD, CPU Feature: AVX2
+func (x Uint32x8) Sub(y Uint32x8) Uint32x8
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBD, CPU Feature: AVX512F
+func (x Uint32x16) Sub(y Uint32x16) Uint32x16
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBQ, CPU Feature: AVX
+func (x Uint64x2) Sub(y Uint64x2) Uint64x2
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBQ, CPU Feature: AVX2
+func (x Uint64x4) Sub(y Uint64x4) Uint64x4
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBQ, CPU Feature: AVX512F
+func (x Uint64x8) Sub(y Uint64x8) Uint64x8
+
+/* SubMasked */
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSUBPS, CPU Feature: AVX512F
+func (x Float32x4) SubMasked(y Float32x4, mask Mask32x4) Float32x4
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSUBPS, CPU Feature: AVX512F
+func (x Float32x8) SubMasked(y Float32x8, mask Mask32x8) Float32x8
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSUBPS, CPU Feature: AVX512F
+func (x Float32x16) SubMasked(y Float32x16, mask Mask32x16) Float32x16
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSUBPD, CPU Feature: AVX512F
+func (x Float64x2) SubMasked(y Float64x2, mask Mask64x2) Float64x2
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSUBPD, CPU Feature: AVX512F
+func (x Float64x4) SubMasked(y Float64x4, mask Mask64x4) Float64x4
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VSUBPD, CPU Feature: AVX512F
+func (x Float64x8) SubMasked(y Float64x8, mask Mask64x8) Float64x8
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBB, CPU Feature: AVX512BW
+func (x Int8x16) SubMasked(y Int8x16, mask Mask8x16) Int8x16
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBB, CPU Feature: AVX512BW
+func (x Int8x32) SubMasked(y Int8x32, mask Mask8x32) Int8x32
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBB, CPU Feature: AVX512BW
+func (x Int8x64) SubMasked(y Int8x64, mask Mask8x64) Int8x64
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBW, CPU Feature: AVX512BW
+func (x Int16x8) SubMasked(y Int16x8, mask Mask16x8) Int16x8
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBW, CPU Feature: AVX512BW
+func (x Int16x16) SubMasked(y Int16x16, mask Mask16x16) Int16x16
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBW, CPU Feature: AVX512BW
+func (x Int16x32) SubMasked(y Int16x32, mask Mask16x32) Int16x32
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBD, CPU Feature: AVX512F
+func (x Int32x4) SubMasked(y Int32x4, mask Mask32x4) Int32x4
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBD, CPU Feature: AVX512F
+func (x Int32x8) SubMasked(y Int32x8, mask Mask32x8) Int32x8
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBD, CPU Feature: AVX512F
+func (x Int32x16) SubMasked(y Int32x16, mask Mask32x16) Int32x16
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBQ, CPU Feature: AVX512F
+func (x Int64x2) SubMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBQ, CPU Feature: AVX512F
+func (x Int64x4) SubMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBQ, CPU Feature: AVX512F
+func (x Int64x8) SubMasked(y Int64x8, mask Mask64x8) Int64x8
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBB, CPU Feature: AVX512BW
+func (x Uint8x16) SubMasked(y Uint8x16, mask Mask8x16) Uint8x16
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBB, CPU Feature: AVX512BW
+func (x Uint8x32) SubMasked(y Uint8x32, mask Mask8x32) Uint8x32
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBB, CPU Feature: AVX512BW
+func (x Uint8x64) SubMasked(y Uint8x64, mask Mask8x64) Uint8x64
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBW, CPU Feature: AVX512BW
+func (x Uint16x8) SubMasked(y Uint16x8, mask Mask16x8) Uint16x8
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBW, CPU Feature: AVX512BW
+func (x Uint16x16) SubMasked(y Uint16x16, mask Mask16x16) Uint16x16
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBW, CPU Feature: AVX512BW
+func (x Uint16x32) SubMasked(y Uint16x32, mask Mask16x32) Uint16x32
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBD, CPU Feature: AVX512F
+func (x Uint32x4) SubMasked(y Uint32x4, mask Mask32x4) Uint32x4
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBD, CPU Feature: AVX512F
+func (x Uint32x8) SubMasked(y Uint32x8, mask Mask32x8) Uint32x8
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBD, CPU Feature: AVX512F
+func (x Uint32x16) SubMasked(y Uint32x16, mask Mask32x16) Uint32x16
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBQ, CPU Feature: AVX512F
+func (x Uint64x2) SubMasked(y Uint64x2, mask Mask64x2) Uint64x2
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBQ, CPU Feature: AVX512F
+func (x Uint64x4) SubMasked(y Uint64x4, mask Mask64x4) Uint64x4
+
+// SubMasked subtracts corresponding elements of two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPSUBQ, CPU Feature: AVX512F
+func (x Uint64x8) SubMasked(y Uint64x8, mask Mask64x8) Uint64x8
+
+/* Trunc */
+
+// Trunc truncates elements towards zero.
+//
+// Asm: VROUNDPS, CPU Feature: AVX
+func (x Float32x4) Trunc() Float32x4
+
+// Trunc truncates elements towards zero.
+//
+// Asm: VROUNDPS, CPU Feature: AVX
+func (x Float32x8) Trunc() Float32x8
+
+// Trunc truncates elements towards zero.
+//
+// Asm: VROUNDPD, CPU Feature: AVX
+func (x Float64x2) Trunc() Float64x2
+
+// Trunc truncates elements towards zero.
+//
+// Asm: VROUNDPD, CPU Feature: AVX
+func (x Float64x4) Trunc() Float64x4
+
+/* TruncWithPrecision */
+
+// TruncWithPrecision truncates elements with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x4) TruncWithPrecision(prec uint8) Float32x4
+
+// TruncWithPrecision truncates elements with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x8) TruncWithPrecision(prec uint8) Float32x8
+
+// TruncWithPrecision truncates elements with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x16) TruncWithPrecision(prec uint8) Float32x16
+
+// TruncWithPrecision truncates elements with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x2) TruncWithPrecision(prec uint8) Float64x2
+
+// TruncWithPrecision truncates elements with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x4) TruncWithPrecision(prec uint8) Float64x4
+
+// TruncWithPrecision truncates elements with specified precision.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x8) TruncWithPrecision(prec uint8) Float64x8
+
+/* TruncWithPrecisionMasked */
+
+// TruncWithPrecisionMasked truncates elements with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x4) TruncWithPrecisionMasked(prec uint8, mask Mask32x4) Float32x4
+
+// TruncWithPrecisionMasked truncates elements with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x8) TruncWithPrecisionMasked(prec uint8, mask Mask32x8) Float32x8
+
+// TruncWithPrecisionMasked truncates elements with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512F
+func (x Float32x16) TruncWithPrecisionMasked(prec uint8, mask Mask32x16) Float32x16
+
+// TruncWithPrecisionMasked truncates elements with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x2) TruncWithPrecisionMasked(prec uint8, mask Mask64x2) Float64x2
+
+// TruncWithPrecisionMasked truncates elements with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x4) TruncWithPrecisionMasked(prec uint8, mask Mask64x4) Float64x4
+
+// TruncWithPrecisionMasked truncates elements with specified precision.
+//
+// This operation is applied selectively under a write mask.
+//
+// prec is expected to be a constant, non-constant value will trigger a runtime panic.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512F
+func (x Float64x8) TruncWithPrecisionMasked(prec uint8, mask Mask64x8) Float64x8
+
+/* UnsignedSignedQuadDotProdAccumulate */
+
+// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of x and y and then adds z.
+//
+// Asm: VPDPBUSD, CPU Feature: AVXVNNI
+func (x Int8x16) UnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int32x4) Int32x4
+
+// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of x and y and then adds z.
+//
+// Asm: VPDPBUSD, CPU Feature: AVXVNNI
+func (x Int8x32) UnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int32x8) Int32x8
+
+// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of x and y and then adds z.
+//
+// Asm: VPDPBUSD, CPU Feature: AVX512VNNI
+func (x Int8x64) UnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int32x16) Int32x16
+
+/* UnsignedSignedQuadDotProdAccumulateMasked */
+
+// UnsignedSignedQuadDotProdAccumulateMasked performs dot products on groups of 4 elements of x and y and then adds z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPDPBUSD, CPU Feature: AVX512VNNI
+func (x Int8x16) UnsignedSignedQuadDotProdAccumulateMasked(y Uint8x16, z Int32x4, mask Mask32x4) Int32x4
+
+// UnsignedSignedQuadDotProdAccumulateMasked performs dot products on groups of 4 elements of x and y and then adds z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPDPBUSD, CPU Feature: AVX512VNNI
+func (x Int8x32) UnsignedSignedQuadDotProdAccumulateMasked(y Uint8x32, z Int32x8, mask Mask32x8) Int32x8
+
+// UnsignedSignedQuadDotProdAccumulateMasked performs dot products on groups of 4 elements of x and y and then adds z.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPDPBUSD, CPU Feature: AVX512VNNI
+func (x Int8x64) UnsignedSignedQuadDotProdAccumulateMasked(y Uint8x64, z Int32x16, mask Mask32x16) Int32x16
+
+/* Xor */
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX
+func (x Int8x16) Xor(y Int8x16) Int8x16
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX2
+func (x Int8x32) Xor(y Int8x32) Int8x32
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX
+func (x Int16x8) Xor(y Int16x8) Int16x8
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX2
+func (x Int16x16) Xor(y Int16x16) Int16x16
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX
+func (x Int32x4) Xor(y Int32x4) Int32x4
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX2
+func (x Int32x8) Xor(y Int32x8) Int32x8
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXORD, CPU Feature: AVX512F
+func (x Int32x16) Xor(y Int32x16) Int32x16
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX
+func (x Int64x2) Xor(y Int64x2) Int64x2
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX2
+func (x Int64x4) Xor(y Int64x4) Int64x4
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXORQ, CPU Feature: AVX512F
+func (x Int64x8) Xor(y Int64x8) Int64x8
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX
+func (x Uint8x16) Xor(y Uint8x16) Uint8x16
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX2
+func (x Uint8x32) Xor(y Uint8x32) Uint8x32
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX
+func (x Uint16x8) Xor(y Uint16x8) Uint16x8
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX2
+func (x Uint16x16) Xor(y Uint16x16) Uint16x16
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX
+func (x Uint32x4) Xor(y Uint32x4) Uint32x4
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX2
+func (x Uint32x8) Xor(y Uint32x8) Uint32x8
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXORD, CPU Feature: AVX512F
+func (x Uint32x16) Xor(y Uint32x16) Uint32x16
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX
+func (x Uint64x2) Xor(y Uint64x2) Uint64x2
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXOR, CPU Feature: AVX2
+func (x Uint64x4) Xor(y Uint64x4) Uint64x4
+
+// Xor performs a bitwise XOR operation between two vectors.
+//
+// Asm: VPXORQ, CPU Feature: AVX512F
+func (x Uint64x8) Xor(y Uint64x8) Uint64x8
+
+/* XorMasked */
+
+// XorMasked performs a bitwise XOR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPXORD, CPU Feature: AVX512F
+func (x Int32x4) XorMasked(y Int32x4, mask Mask32x4) Int32x4
+
+// XorMasked performs a bitwise XOR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPXORD, CPU Feature: AVX512F
+func (x Int32x8) XorMasked(y Int32x8, mask Mask32x8) Int32x8
+
+// XorMasked performs a bitwise XOR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPXORD, CPU Feature: AVX512F
+func (x Int32x16) XorMasked(y Int32x16, mask Mask32x16) Int32x16
+
+// XorMasked performs a bitwise XOR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPXORQ, CPU Feature: AVX512F
+func (x Int64x2) XorMasked(y Int64x2, mask Mask64x2) Int64x2
+
+// XorMasked performs a bitwise XOR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPXORQ, CPU Feature: AVX512F
+func (x Int64x4) XorMasked(y Int64x4, mask Mask64x4) Int64x4
+
+// XorMasked performs a bitwise XOR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPXORQ, CPU Feature: AVX512F
+func (x Int64x8) XorMasked(y Int64x8, mask Mask64x8) Int64x8
+
+// XorMasked performs a bitwise XOR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPXORD, CPU Feature: AVX512F
+func (x Uint32x4) XorMasked(y Uint32x4, mask Mask32x4) Uint32x4
+
+// XorMasked performs a bitwise XOR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPXORD, CPU Feature: AVX512F
+func (x Uint32x8) XorMasked(y Uint32x8, mask Mask32x8) Uint32x8
+
+// XorMasked performs a bitwise XOR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPXORD, CPU Feature: AVX512F
+func (x Uint32x16) XorMasked(y Uint32x16, mask Mask32x16) Uint32x16
+
+// XorMasked performs a bitwise XOR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPXORQ, CPU Feature: AVX512F
+func (x Uint64x2) XorMasked(y Uint64x2, mask Mask64x2) Uint64x2
+
+// XorMasked performs a bitwise XOR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPXORQ, CPU Feature: AVX512F
+func (x Uint64x4) XorMasked(y Uint64x4, mask Mask64x4) Uint64x4
+
+// XorMasked performs a bitwise XOR operation between two vectors.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPXORQ, CPU Feature: AVX512F
+func (x Uint64x8) XorMasked(y Uint64x8, mask Mask64x8) Uint64x8
+
+// Float64x2 converts from Float32x4 to Float64x2
+func (from Float32x4) AsFloat64x2() (to Float64x2)
+
+// Int8x16 converts from Float32x4 to Int8x16
+func (from Float32x4) AsInt8x16() (to Int8x16)
+
+// Int16x8 converts from Float32x4 to Int16x8
+func (from Float32x4) AsInt16x8() (to Int16x8)
+
+// Int32x4 converts from Float32x4 to Int32x4
+func (from Float32x4) AsInt32x4() (to Int32x4)
+
+// Int64x2 converts from Float32x4 to Int64x2
+func (from Float32x4) AsInt64x2() (to Int64x2)
+
+// Uint8x16 converts from Float32x4 to Uint8x16
+func (from Float32x4) AsUint8x16() (to Uint8x16)
+
+// Uint16x8 converts from Float32x4 to Uint16x8
+func (from Float32x4) AsUint16x8() (to Uint16x8)
+
+// Uint32x4 converts from Float32x4 to Uint32x4
+func (from Float32x4) AsUint32x4() (to Uint32x4)
+
+// Uint64x2 converts from Float32x4 to Uint64x2
+func (from Float32x4) AsUint64x2() (to Uint64x2)
+
+// Float64x4 converts from Float32x8 to Float64x4
+func (from Float32x8) AsFloat64x4() (to Float64x4)
+
+// Int8x32 converts from Float32x8 to Int8x32
+func (from Float32x8) AsInt8x32() (to Int8x32)
+
+// Int16x16 converts from Float32x8 to Int16x16
+func (from Float32x8) AsInt16x16() (to Int16x16)
+
+// Int32x8 converts from Float32x8 to Int32x8
+func (from Float32x8) AsInt32x8() (to Int32x8)
+
+// Int64x4 converts from Float32x8 to Int64x4
+func (from Float32x8) AsInt64x4() (to Int64x4)
+
+// Uint8x32 converts from Float32x8 to Uint8x32
+func (from Float32x8) AsUint8x32() (to Uint8x32)
+
+// Uint16x16 converts from Float32x8 to Uint16x16
+func (from Float32x8) AsUint16x16() (to Uint16x16)
+
+// Uint32x8 converts from Float32x8 to Uint32x8
+func (from Float32x8) AsUint32x8() (to Uint32x8)
+
+// Uint64x4 converts from Float32x8 to Uint64x4
+func (from Float32x8) AsUint64x4() (to Uint64x4)
+
+// Float64x8 converts from Float32x16 to Float64x8
+func (from Float32x16) AsFloat64x8() (to Float64x8)
+
+// Int8x64 converts from Float32x16 to Int8x64
+func (from Float32x16) AsInt8x64() (to Int8x64)
+
+// Int16x32 converts from Float32x16 to Int16x32
+func (from Float32x16) AsInt16x32() (to Int16x32)
+
+// Int32x16 converts from Float32x16 to Int32x16
+func (from Float32x16) AsInt32x16() (to Int32x16)
+
+// Int64x8 converts from Float32x16 to Int64x8
+func (from Float32x16) AsInt64x8() (to Int64x8)
+
+// Uint8x64 converts from Float32x16 to Uint8x64
+func (from Float32x16) AsUint8x64() (to Uint8x64)
+
+// Uint16x32 converts from Float32x16 to Uint16x32
+func (from Float32x16) AsUint16x32() (to Uint16x32)
+
+// Uint32x16 converts from Float32x16 to Uint32x16
+func (from Float32x16) AsUint32x16() (to Uint32x16)
+
+// Uint64x8 converts from Float32x16 to Uint64x8
+func (from Float32x16) AsUint64x8() (to Uint64x8)
+
+// Float32x4 converts from Float64x2 to Float32x4
+func (from Float64x2) AsFloat32x4() (to Float32x4)
+
+// Int8x16 converts from Float64x2 to Int8x16
+func (from Float64x2) AsInt8x16() (to Int8x16)
+
+// Int16x8 converts from Float64x2 to Int16x8
+func (from Float64x2) AsInt16x8() (to Int16x8)
+
+// Int32x4 converts from Float64x2 to Int32x4
+func (from Float64x2) AsInt32x4() (to Int32x4)
+
+// Int64x2 converts from Float64x2 to Int64x2
+func (from Float64x2) AsInt64x2() (to Int64x2)
+
+// Uint8x16 converts from Float64x2 to Uint8x16
+func (from Float64x2) AsUint8x16() (to Uint8x16)
+
+// Uint16x8 converts from Float64x2 to Uint16x8
+func (from Float64x2) AsUint16x8() (to Uint16x8)
+
+// Uint32x4 converts from Float64x2 to Uint32x4
+func (from Float64x2) AsUint32x4() (to Uint32x4)
+
+// Uint64x2 converts from Float64x2 to Uint64x2
+func (from Float64x2) AsUint64x2() (to Uint64x2)
+
+// Float32x8 converts from Float64x4 to Float32x8
+func (from Float64x4) AsFloat32x8() (to Float32x8)
+
+// Int8x32 converts from Float64x4 to Int8x32
+func (from Float64x4) AsInt8x32() (to Int8x32)
+
+// Int16x16 converts from Float64x4 to Int16x16
+func (from Float64x4) AsInt16x16() (to Int16x16)
+
+// Int32x8 converts from Float64x4 to Int32x8
+func (from Float64x4) AsInt32x8() (to Int32x8)
+
+// Int64x4 converts from Float64x4 to Int64x4
+func (from Float64x4) AsInt64x4() (to Int64x4)
+
+// Uint8x32 converts from Float64x4 to Uint8x32
+func (from Float64x4) AsUint8x32() (to Uint8x32)
+
+// Uint16x16 converts from Float64x4 to Uint16x16
+func (from Float64x4) AsUint16x16() (to Uint16x16)
+
+// Uint32x8 converts from Float64x4 to Uint32x8
+func (from Float64x4) AsUint32x8() (to Uint32x8)
+
+// Uint64x4 converts from Float64x4 to Uint64x4
+func (from Float64x4) AsUint64x4() (to Uint64x4)
+
+// Float32x16 converts from Float64x8 to Float32x16
+func (from Float64x8) AsFloat32x16() (to Float32x16)
+
+// Int8x64 converts from Float64x8 to Int8x64
+func (from Float64x8) AsInt8x64() (to Int8x64)
+
+// Int16x32 converts from Float64x8 to Int16x32
+func (from Float64x8) AsInt16x32() (to Int16x32)
+
+// Int32x16 converts from Float64x8 to Int32x16
+func (from Float64x8) AsInt32x16() (to Int32x16)
+
+// Int64x8 converts from Float64x8 to Int64x8
+func (from Float64x8) AsInt64x8() (to Int64x8)
+
+// Uint8x64 converts from Float64x8 to Uint8x64
+func (from Float64x8) AsUint8x64() (to Uint8x64)
+
+// Uint16x32 converts from Float64x8 to Uint16x32
+func (from Float64x8) AsUint16x32() (to Uint16x32)
+
+// Uint32x16 converts from Float64x8 to Uint32x16
+func (from Float64x8) AsUint32x16() (to Uint32x16)
+
+// Uint64x8 converts from Float64x8 to Uint64x8
+func (from Float64x8) AsUint64x8() (to Uint64x8)
+
+// Float32x4 converts from Int8x16 to Float32x4
+func (from Int8x16) AsFloat32x4() (to Float32x4)
+
+// Float64x2 converts from Int8x16 to Float64x2
+func (from Int8x16) AsFloat64x2() (to Float64x2)
+
+// Int16x8 converts from Int8x16 to Int16x8
+func (from Int8x16) AsInt16x8() (to Int16x8)
+
+// Int32x4 converts from Int8x16 to Int32x4
+func (from Int8x16) AsInt32x4() (to Int32x4)
+
+// Int64x2 converts from Int8x16 to Int64x2
+func (from Int8x16) AsInt64x2() (to Int64x2)
+
+// Uint8x16 converts from Int8x16 to Uint8x16
+func (from Int8x16) AsUint8x16() (to Uint8x16)
+
+// Uint16x8 converts from Int8x16 to Uint16x8
+func (from Int8x16) AsUint16x8() (to Uint16x8)
+
+// Uint32x4 converts from Int8x16 to Uint32x4
+func (from Int8x16) AsUint32x4() (to Uint32x4)
+
+// Uint64x2 converts from Int8x16 to Uint64x2
+func (from Int8x16) AsUint64x2() (to Uint64x2)
+
+// Float32x8 converts from Int8x32 to Float32x8
+func (from Int8x32) AsFloat32x8() (to Float32x8)
+
+// Float64x4 converts from Int8x32 to Float64x4
+func (from Int8x32) AsFloat64x4() (to Float64x4)
+
+// Int16x16 converts from Int8x32 to Int16x16
+func (from Int8x32) AsInt16x16() (to Int16x16)
+
+// Int32x8 converts from Int8x32 to Int32x8
+func (from Int8x32) AsInt32x8() (to Int32x8)
+
+// Int64x4 converts from Int8x32 to Int64x4
+func (from Int8x32) AsInt64x4() (to Int64x4)
+
+// Uint8x32 converts from Int8x32 to Uint8x32
+func (from Int8x32) AsUint8x32() (to Uint8x32)
+
+// Uint16x16 converts from Int8x32 to Uint16x16
+func (from Int8x32) AsUint16x16() (to Uint16x16)
+
+// Uint32x8 converts from Int8x32 to Uint32x8
+func (from Int8x32) AsUint32x8() (to Uint32x8)
+
+// Uint64x4 converts from Int8x32 to Uint64x4
+func (from Int8x32) AsUint64x4() (to Uint64x4)
+
+// Float32x16 converts from Int8x64 to Float32x16
+func (from Int8x64) AsFloat32x16() (to Float32x16)
+
+// Float64x8 converts from Int8x64 to Float64x8
+func (from Int8x64) AsFloat64x8() (to Float64x8)
+
+// Int16x32 converts from Int8x64 to Int16x32
+func (from Int8x64) AsInt16x32() (to Int16x32)
+
+// Int32x16 converts from Int8x64 to Int32x16
+func (from Int8x64) AsInt32x16() (to Int32x16)
+
+// Int64x8 converts from Int8x64 to Int64x8
+func (from Int8x64) AsInt64x8() (to Int64x8)
+
+// Uint8x64 converts from Int8x64 to Uint8x64
+func (from Int8x64) AsUint8x64() (to Uint8x64)
+
+// Uint16x32 converts from Int8x64 to Uint16x32
+func (from Int8x64) AsUint16x32() (to Uint16x32)
+
+// Uint32x16 converts from Int8x64 to Uint32x16
+func (from Int8x64) AsUint32x16() (to Uint32x16)
+
+// Uint64x8 converts from Int8x64 to Uint64x8
+func (from Int8x64) AsUint64x8() (to Uint64x8)
+
+// Float32x4 converts from Int16x8 to Float32x4
+func (from Int16x8) AsFloat32x4() (to Float32x4)
+
+// Float64x2 converts from Int16x8 to Float64x2
+func (from Int16x8) AsFloat64x2() (to Float64x2)
+
+// Int8x16 converts from Int16x8 to Int8x16
+func (from Int16x8) AsInt8x16() (to Int8x16)
+
+// Int32x4 converts from Int16x8 to Int32x4
+func (from Int16x8) AsInt32x4() (to Int32x4)
+
+// Int64x2 converts from Int16x8 to Int64x2
+func (from Int16x8) AsInt64x2() (to Int64x2)
+
+// Uint8x16 converts from Int16x8 to Uint8x16
+func (from Int16x8) AsUint8x16() (to Uint8x16)
+
+// Uint16x8 converts from Int16x8 to Uint16x8
+func (from Int16x8) AsUint16x8() (to Uint16x8)
+
+// Uint32x4 converts from Int16x8 to Uint32x4
+func (from Int16x8) AsUint32x4() (to Uint32x4)
+
+// Uint64x2 converts from Int16x8 to Uint64x2
+func (from Int16x8) AsUint64x2() (to Uint64x2)
+
+// Float32x8 converts from Int16x16 to Float32x8
+func (from Int16x16) AsFloat32x8() (to Float32x8)
+
+// Float64x4 converts from Int16x16 to Float64x4
+func (from Int16x16) AsFloat64x4() (to Float64x4)
+
+// Int8x32 converts from Int16x16 to Int8x32
+func (from Int16x16) AsInt8x32() (to Int8x32)
+
+// Int32x8 converts from Int16x16 to Int32x8
+func (from Int16x16) AsInt32x8() (to Int32x8)
+
+// Int64x4 converts from Int16x16 to Int64x4
+func (from Int16x16) AsInt64x4() (to Int64x4)
+
+// Uint8x32 converts from Int16x16 to Uint8x32
+func (from Int16x16) AsUint8x32() (to Uint8x32)
+
+// Uint16x16 converts from Int16x16 to Uint16x16
+func (from Int16x16) AsUint16x16() (to Uint16x16)
+
+// Uint32x8 converts from Int16x16 to Uint32x8
+func (from Int16x16) AsUint32x8() (to Uint32x8)
+
+// Uint64x4 converts from Int16x16 to Uint64x4
+func (from Int16x16) AsUint64x4() (to Uint64x4)
+
+// Float32x16 converts from Int16x32 to Float32x16
+func (from Int16x32) AsFloat32x16() (to Float32x16)
+
+// Float64x8 converts from Int16x32 to Float64x8
+func (from Int16x32) AsFloat64x8() (to Float64x8)
+
+// Int8x64 converts from Int16x32 to Int8x64
+func (from Int16x32) AsInt8x64() (to Int8x64)
+
+// Int32x16 converts from Int16x32 to Int32x16
+func (from Int16x32) AsInt32x16() (to Int32x16)
+
+// Int64x8 converts from Int16x32 to Int64x8
+func (from Int16x32) AsInt64x8() (to Int64x8)
+
+// Uint8x64 converts from Int16x32 to Uint8x64
+func (from Int16x32) AsUint8x64() (to Uint8x64)
+
+// Uint16x32 converts from Int16x32 to Uint16x32
+func (from Int16x32) AsUint16x32() (to Uint16x32)
+
+// Uint32x16 converts from Int16x32 to Uint32x16
+func (from Int16x32) AsUint32x16() (to Uint32x16)
+
+// Uint64x8 converts from Int16x32 to Uint64x8
+func (from Int16x32) AsUint64x8() (to Uint64x8)
+
+// Float32x4 converts from Int32x4 to Float32x4
+func (from Int32x4) AsFloat32x4() (to Float32x4)
+
+// Float64x2 converts from Int32x4 to Float64x2
+func (from Int32x4) AsFloat64x2() (to Float64x2)
+
+// Int8x16 converts from Int32x4 to Int8x16
+func (from Int32x4) AsInt8x16() (to Int8x16)
+
+// Int16x8 converts from Int32x4 to Int16x8
+func (from Int32x4) AsInt16x8() (to Int16x8)
+
+// Int64x2 converts from Int32x4 to Int64x2
+func (from Int32x4) AsInt64x2() (to Int64x2)
+
+// Uint8x16 converts from Int32x4 to Uint8x16
+func (from Int32x4) AsUint8x16() (to Uint8x16)
+
+// Uint16x8 converts from Int32x4 to Uint16x8
+func (from Int32x4) AsUint16x8() (to Uint16x8)
+
+// Uint32x4 converts from Int32x4 to Uint32x4
+func (from Int32x4) AsUint32x4() (to Uint32x4)
+
+// Uint64x2 converts from Int32x4 to Uint64x2
+func (from Int32x4) AsUint64x2() (to Uint64x2)
+
+// Float32x8 converts from Int32x8 to Float32x8
+func (from Int32x8) AsFloat32x8() (to Float32x8)
+
+// Float64x4 converts from Int32x8 to Float64x4
+func (from Int32x8) AsFloat64x4() (to Float64x4)
+
+// Int8x32 converts from Int32x8 to Int8x32
+func (from Int32x8) AsInt8x32() (to Int8x32)
+
+// Int16x16 converts from Int32x8 to Int16x16
+func (from Int32x8) AsInt16x16() (to Int16x16)
+
+// Int64x4 converts from Int32x8 to Int64x4
+func (from Int32x8) AsInt64x4() (to Int64x4)
+
+// Uint8x32 converts from Int32x8 to Uint8x32
+func (from Int32x8) AsUint8x32() (to Uint8x32)
+
+// Uint16x16 converts from Int32x8 to Uint16x16
+func (from Int32x8) AsUint16x16() (to Uint16x16)
+
+// Uint32x8 converts from Int32x8 to Uint32x8
+func (from Int32x8) AsUint32x8() (to Uint32x8)
+
+// Uint64x4 converts from Int32x8 to Uint64x4
+func (from Int32x8) AsUint64x4() (to Uint64x4)
+
+// Float32x16 converts from Int32x16 to Float32x16
+func (from Int32x16) AsFloat32x16() (to Float32x16)
+
+// Float64x8 converts from Int32x16 to Float64x8
+func (from Int32x16) AsFloat64x8() (to Float64x8)
+
+// Int8x64 converts from Int32x16 to Int8x64
+func (from Int32x16) AsInt8x64() (to Int8x64)
+
+// Int16x32 converts from Int32x16 to Int16x32
+func (from Int32x16) AsInt16x32() (to Int16x32)
+
+// Int64x8 converts from Int32x16 to Int64x8
+func (from Int32x16) AsInt64x8() (to Int64x8)
+
+// Uint8x64 converts from Int32x16 to Uint8x64
+func (from Int32x16) AsUint8x64() (to Uint8x64)
+
+// Uint16x32 converts from Int32x16 to Uint16x32
+func (from Int32x16) AsUint16x32() (to Uint16x32)
+
+// Uint32x16 converts from Int32x16 to Uint32x16
+func (from Int32x16) AsUint32x16() (to Uint32x16)
+
+// Uint64x8 converts from Int32x16 to Uint64x8
+func (from Int32x16) AsUint64x8() (to Uint64x8)
+
+// Float32x4 converts from Int64x2 to Float32x4
+func (from Int64x2) AsFloat32x4() (to Float32x4)
+
+// Float64x2 converts from Int64x2 to Float64x2
+func (from Int64x2) AsFloat64x2() (to Float64x2)
+
+// Int8x16 converts from Int64x2 to Int8x16
+func (from Int64x2) AsInt8x16() (to Int8x16)
+
+// Int16x8 converts from Int64x2 to Int16x8
+func (from Int64x2) AsInt16x8() (to Int16x8)
+
+// Int32x4 converts from Int64x2 to Int32x4
+func (from Int64x2) AsInt32x4() (to Int32x4)
+
+// Uint8x16 converts from Int64x2 to Uint8x16
+func (from Int64x2) AsUint8x16() (to Uint8x16)
+
+// Uint16x8 converts from Int64x2 to Uint16x8
+func (from Int64x2) AsUint16x8() (to Uint16x8)
+
+// Uint32x4 converts from Int64x2 to Uint32x4
+func (from Int64x2) AsUint32x4() (to Uint32x4)
+
+// Uint64x2 converts from Int64x2 to Uint64x2
+func (from Int64x2) AsUint64x2() (to Uint64x2)
+
+// Float32x8 converts from Int64x4 to Float32x8
+func (from Int64x4) AsFloat32x8() (to Float32x8)
+
+// Float64x4 converts from Int64x4 to Float64x4
+func (from Int64x4) AsFloat64x4() (to Float64x4)
+
+// Int8x32 converts from Int64x4 to Int8x32
+func (from Int64x4) AsInt8x32() (to Int8x32)
+
+// Int16x16 converts from Int64x4 to Int16x16
+func (from Int64x4) AsInt16x16() (to Int16x16)
+
+// Int32x8 converts from Int64x4 to Int32x8
+func (from Int64x4) AsInt32x8() (to Int32x8)
+
+// Uint8x32 converts from Int64x4 to Uint8x32
+func (from Int64x4) AsUint8x32() (to Uint8x32)
+
+// Uint16x16 converts from Int64x4 to Uint16x16
+func (from Int64x4) AsUint16x16() (to Uint16x16)
+
+// Uint32x8 converts from Int64x4 to Uint32x8
+func (from Int64x4) AsUint32x8() (to Uint32x8)
+
+// Uint64x4 converts from Int64x4 to Uint64x4
+func (from Int64x4) AsUint64x4() (to Uint64x4)
+
+// Float32x16 converts from Int64x8 to Float32x16
+func (from Int64x8) AsFloat32x16() (to Float32x16)
+
+// Float64x8 converts from Int64x8 to Float64x8
+func (from Int64x8) AsFloat64x8() (to Float64x8)
+
+// Int8x64 converts from Int64x8 to Int8x64
+func (from Int64x8) AsInt8x64() (to Int8x64)
+
+// Int16x32 converts from Int64x8 to Int16x32
+func (from Int64x8) AsInt16x32() (to Int16x32)
+
+// Int32x16 converts from Int64x8 to Int32x16
+func (from Int64x8) AsInt32x16() (to Int32x16)
+
+// Uint8x64 converts from Int64x8 to Uint8x64
+func (from Int64x8) AsUint8x64() (to Uint8x64)
+
+// Uint16x32 converts from Int64x8 to Uint16x32
+func (from Int64x8) AsUint16x32() (to Uint16x32)
+
+// Uint32x16 converts from Int64x8 to Uint32x16
+func (from Int64x8) AsUint32x16() (to Uint32x16)
+
+// Uint64x8 converts from Int64x8 to Uint64x8
+func (from Int64x8) AsUint64x8() (to Uint64x8)
+
+// Float32x4 converts from Uint8x16 to Float32x4
+func (from Uint8x16) AsFloat32x4() (to Float32x4)
+
+// Float64x2 converts from Uint8x16 to Float64x2
+func (from Uint8x16) AsFloat64x2() (to Float64x2)
+
+// Int8x16 converts from Uint8x16 to Int8x16
+func (from Uint8x16) AsInt8x16() (to Int8x16)
+
+// Int16x8 converts from Uint8x16 to Int16x8
+func (from Uint8x16) AsInt16x8() (to Int16x8)
+
+// Int32x4 converts from Uint8x16 to Int32x4
+func (from Uint8x16) AsInt32x4() (to Int32x4)
+
+// Int64x2 converts from Uint8x16 to Int64x2
+func (from Uint8x16) AsInt64x2() (to Int64x2)
+
+// Uint16x8 converts from Uint8x16 to Uint16x8
+func (from Uint8x16) AsUint16x8() (to Uint16x8)
+
+// Uint32x4 converts from Uint8x16 to Uint32x4
+func (from Uint8x16) AsUint32x4() (to Uint32x4)
+
+// Uint64x2 converts from Uint8x16 to Uint64x2
+func (from Uint8x16) AsUint64x2() (to Uint64x2)
+
+// Float32x8 converts from Uint8x32 to Float32x8
+func (from Uint8x32) AsFloat32x8() (to Float32x8)
+
+// Float64x4 converts from Uint8x32 to Float64x4
+func (from Uint8x32) AsFloat64x4() (to Float64x4)
+
+// Int8x32 converts from Uint8x32 to Int8x32
+func (from Uint8x32) AsInt8x32() (to Int8x32)
+
+// Int16x16 converts from Uint8x32 to Int16x16
+func (from Uint8x32) AsInt16x16() (to Int16x16)
+
+// Int32x8 converts from Uint8x32 to Int32x8
+func (from Uint8x32) AsInt32x8() (to Int32x8)
+
+// Int64x4 converts from Uint8x32 to Int64x4
+func (from Uint8x32) AsInt64x4() (to Int64x4)
+
+// Uint16x16 converts from Uint8x32 to Uint16x16
+func (from Uint8x32) AsUint16x16() (to Uint16x16)
+
+// Uint32x8 converts from Uint8x32 to Uint32x8
+func (from Uint8x32) AsUint32x8() (to Uint32x8)
+
+// Uint64x4 converts from Uint8x32 to Uint64x4
+func (from Uint8x32) AsUint64x4() (to Uint64x4)
+
+// Float32x16 converts from Uint8x64 to Float32x16
+func (from Uint8x64) AsFloat32x16() (to Float32x16)
+
+// Float64x8 converts from Uint8x64 to Float64x8
+func (from Uint8x64) AsFloat64x8() (to Float64x8)
+
+// Int8x64 converts from Uint8x64 to Int8x64
+func (from Uint8x64) AsInt8x64() (to Int8x64)
+
+// Int16x32 converts from Uint8x64 to Int16x32
+func (from Uint8x64) AsInt16x32() (to Int16x32)
+
+// Int32x16 converts from Uint8x64 to Int32x16
+func (from Uint8x64) AsInt32x16() (to Int32x16)
+
+// Int64x8 converts from Uint8x64 to Int64x8
+func (from Uint8x64) AsInt64x8() (to Int64x8)
+
+// Uint16x32 converts from Uint8x64 to Uint16x32
+func (from Uint8x64) AsUint16x32() (to Uint16x32)
+
+// Uint32x16 converts from Uint8x64 to Uint32x16
+func (from Uint8x64) AsUint32x16() (to Uint32x16)
+
+// Uint64x8 converts from Uint8x64 to Uint64x8
+func (from Uint8x64) AsUint64x8() (to Uint64x8)
+
+// Float32x4 converts from Uint16x8 to Float32x4
+func (from Uint16x8) AsFloat32x4() (to Float32x4)
+
+// Float64x2 converts from Uint16x8 to Float64x2
+func (from Uint16x8) AsFloat64x2() (to Float64x2)
+
+// Int8x16 converts from Uint16x8 to Int8x16
+func (from Uint16x8) AsInt8x16() (to Int8x16)
+
+// Int16x8 converts from Uint16x8 to Int16x8
+func (from Uint16x8) AsInt16x8() (to Int16x8)
+
+// Int32x4 converts from Uint16x8 to Int32x4
+func (from Uint16x8) AsInt32x4() (to Int32x4)
+
+// Int64x2 converts from Uint16x8 to Int64x2
+func (from Uint16x8) AsInt64x2() (to Int64x2)
+
+// Uint8x16 converts from Uint16x8 to Uint8x16
+func (from Uint16x8) AsUint8x16() (to Uint8x16)
+
+// Uint32x4 converts from Uint16x8 to Uint32x4
+func (from Uint16x8) AsUint32x4() (to Uint32x4)
+
+// Uint64x2 converts from Uint16x8 to Uint64x2
+func (from Uint16x8) AsUint64x2() (to Uint64x2)
+
+// Float32x8 converts from Uint16x16 to Float32x8
+func (from Uint16x16) AsFloat32x8() (to Float32x8)
+
+// Float64x4 converts from Uint16x16 to Float64x4
+func (from Uint16x16) AsFloat64x4() (to Float64x4)
+
+// Int8x32 converts from Uint16x16 to Int8x32
+func (from Uint16x16) AsInt8x32() (to Int8x32)
+
+// Int16x16 converts from Uint16x16 to Int16x16
+func (from Uint16x16) AsInt16x16() (to Int16x16)
+
+// Int32x8 converts from Uint16x16 to Int32x8
+func (from Uint16x16) AsInt32x8() (to Int32x8)
+
+// Int64x4 converts from Uint16x16 to Int64x4
+func (from Uint16x16) AsInt64x4() (to Int64x4)
+
+// Uint8x32 converts from Uint16x16 to Uint8x32
+func (from Uint16x16) AsUint8x32() (to Uint8x32)
+
+// Uint32x8 converts from Uint16x16 to Uint32x8
+func (from Uint16x16) AsUint32x8() (to Uint32x8)
+
+// Uint64x4 converts from Uint16x16 to Uint64x4
+func (from Uint16x16) AsUint64x4() (to Uint64x4)
+
+// Float32x16 converts from Uint16x32 to Float32x16
+func (from Uint16x32) AsFloat32x16() (to Float32x16)
+
+// Float64x8 converts from Uint16x32 to Float64x8
+func (from Uint16x32) AsFloat64x8() (to Float64x8)
+
+// Int8x64 converts from Uint16x32 to Int8x64
+func (from Uint16x32) AsInt8x64() (to Int8x64)
+
+// Int16x32 converts from Uint16x32 to Int16x32
+func (from Uint16x32) AsInt16x32() (to Int16x32)
+
+// Int32x16 converts from Uint16x32 to Int32x16
+func (from Uint16x32) AsInt32x16() (to Int32x16)
+
+// Int64x8 converts from Uint16x32 to Int64x8
+func (from Uint16x32) AsInt64x8() (to Int64x8)
+
+// Uint8x64 converts from Uint16x32 to Uint8x64
+func (from Uint16x32) AsUint8x64() (to Uint8x64)
+
+// Uint32x16 converts from Uint16x32 to Uint32x16
+func (from Uint16x32) AsUint32x16() (to Uint32x16)
+
+// Uint64x8 converts from Uint16x32 to Uint64x8
+func (from Uint16x32) AsUint64x8() (to Uint64x8)
+
+// Float32x4 converts from Uint32x4 to Float32x4
+func (from Uint32x4) AsFloat32x4() (to Float32x4)
+
+// Float64x2 converts from Uint32x4 to Float64x2
+func (from Uint32x4) AsFloat64x2() (to Float64x2)
+
+// Int8x16 converts from Uint32x4 to Int8x16
+func (from Uint32x4) AsInt8x16() (to Int8x16)
+
+// Int16x8 converts from Uint32x4 to Int16x8
+func (from Uint32x4) AsInt16x8() (to Int16x8)
+
+// Int32x4 converts from Uint32x4 to Int32x4
+func (from Uint32x4) AsInt32x4() (to Int32x4)
+
+// Int64x2 converts from Uint32x4 to Int64x2
+func (from Uint32x4) AsInt64x2() (to Int64x2)
+
+// Uint8x16 converts from Uint32x4 to Uint8x16
+func (from Uint32x4) AsUint8x16() (to Uint8x16)
+
+// Uint16x8 converts from Uint32x4 to Uint16x8
+func (from Uint32x4) AsUint16x8() (to Uint16x8)
+
+// Uint64x2 converts from Uint32x4 to Uint64x2
+func (from Uint32x4) AsUint64x2() (to Uint64x2)
+
+// Float32x8 converts from Uint32x8 to Float32x8
+func (from Uint32x8) AsFloat32x8() (to Float32x8)
+
+// Float64x4 converts from Uint32x8 to Float64x4
+func (from Uint32x8) AsFloat64x4() (to Float64x4)
+
+// Int8x32 converts from Uint32x8 to Int8x32
+func (from Uint32x8) AsInt8x32() (to Int8x32)
+
+// Int16x16 converts from Uint32x8 to Int16x16
+func (from Uint32x8) AsInt16x16() (to Int16x16)
+
+// Int32x8 converts from Uint32x8 to Int32x8
+func (from Uint32x8) AsInt32x8() (to Int32x8)
+
+// Int64x4 converts from Uint32x8 to Int64x4
+func (from Uint32x8) AsInt64x4() (to Int64x4)
+
+// Uint8x32 converts from Uint32x8 to Uint8x32
+func (from Uint32x8) AsUint8x32() (to Uint8x32)
+
+// Uint16x16 converts from Uint32x8 to Uint16x16
+func (from Uint32x8) AsUint16x16() (to Uint16x16)
+
+// Uint64x4 converts from Uint32x8 to Uint64x4
+func (from Uint32x8) AsUint64x4() (to Uint64x4)
+
+// Float32x16 converts from Uint32x16 to Float32x16
+func (from Uint32x16) AsFloat32x16() (to Float32x16)
+
+// Float64x8 converts from Uint32x16 to Float64x8
+func (from Uint32x16) AsFloat64x8() (to Float64x8)
+
+// Int8x64 converts from Uint32x16 to Int8x64
+func (from Uint32x16) AsInt8x64() (to Int8x64)
+
+// Int16x32 converts from Uint32x16 to Int16x32
+func (from Uint32x16) AsInt16x32() (to Int16x32)
+
+// Int32x16 converts from Uint32x16 to Int32x16
+func (from Uint32x16) AsInt32x16() (to Int32x16)
+
+// Int64x8 converts from Uint32x16 to Int64x8
+func (from Uint32x16) AsInt64x8() (to Int64x8)
+
+// Uint8x64 converts from Uint32x16 to Uint8x64
+func (from Uint32x16) AsUint8x64() (to Uint8x64)
+
+// Uint16x32 converts from Uint32x16 to Uint16x32
+func (from Uint32x16) AsUint16x32() (to Uint16x32)
+
+// Uint64x8 converts from Uint32x16 to Uint64x8
+func (from Uint32x16) AsUint64x8() (to Uint64x8)
+
+// Float32x4 converts from Uint64x2 to Float32x4
+func (from Uint64x2) AsFloat32x4() (to Float32x4)
+
+// Float64x2 converts from Uint64x2 to Float64x2
+func (from Uint64x2) AsFloat64x2() (to Float64x2)
+
+// Int8x16 converts from Uint64x2 to Int8x16
+func (from Uint64x2) AsInt8x16() (to Int8x16)
+
+// Int16x8 converts from Uint64x2 to Int16x8
+func (from Uint64x2) AsInt16x8() (to Int16x8)
+
+// Int32x4 converts from Uint64x2 to Int32x4
+func (from Uint64x2) AsInt32x4() (to Int32x4)
+
+// Int64x2 converts from Uint64x2 to Int64x2
+func (from Uint64x2) AsInt64x2() (to Int64x2)
+
+// Uint8x16 converts from Uint64x2 to Uint8x16
+func (from Uint64x2) AsUint8x16() (to Uint8x16)
+
+// Uint16x8 converts from Uint64x2 to Uint16x8
+func (from Uint64x2) AsUint16x8() (to Uint16x8)
+
+// Uint32x4 converts from Uint64x2 to Uint32x4
+func (from Uint64x2) AsUint32x4() (to Uint32x4)
+
+// Float32x8 converts from Uint64x4 to Float32x8
+func (from Uint64x4) AsFloat32x8() (to Float32x8)
+
+// Float64x4 converts from Uint64x4 to Float64x4
+func (from Uint64x4) AsFloat64x4() (to Float64x4)
+
+// Int8x32 converts from Uint64x4 to Int8x32
+func (from Uint64x4) AsInt8x32() (to Int8x32)
+
+// Int16x16 converts from Uint64x4 to Int16x16
+func (from Uint64x4) AsInt16x16() (to Int16x16)
+
+// Int32x8 converts from Uint64x4 to Int32x8
+func (from Uint64x4) AsInt32x8() (to Int32x8)
+
+// Int64x4 converts from Uint64x4 to Int64x4
+func (from Uint64x4) AsInt64x4() (to Int64x4)
+
+// Uint8x32 converts from Uint64x4 to Uint8x32
+func (from Uint64x4) AsUint8x32() (to Uint8x32)
+
+// Uint16x16 converts from Uint64x4 to Uint16x16
+func (from Uint64x4) AsUint16x16() (to Uint16x16)
+
+// Uint32x8 converts from Uint64x4 to Uint32x8
+func (from Uint64x4) AsUint32x8() (to Uint32x8)
+
+// Float32x16 converts from Uint64x8 to Float32x16
+func (from Uint64x8) AsFloat32x16() (to Float32x16)
+
+// Float64x8 converts from Uint64x8 to Float64x8
+func (from Uint64x8) AsFloat64x8() (to Float64x8)
+
+// Int8x64 converts from Uint64x8 to Int8x64
+func (from Uint64x8) AsInt8x64() (to Int8x64)
+
+// Int16x32 converts from Uint64x8 to Int16x32
+func (from Uint64x8) AsInt16x32() (to Int16x32)
+
+// Int32x16 converts from Uint64x8 to Int32x16
+func (from Uint64x8) AsInt32x16() (to Int32x16)
+
+// Int64x8 converts from Uint64x8 to Int64x8
+func (from Uint64x8) AsInt64x8() (to Int64x8)
+
+// Uint8x64 converts from Uint64x8 to Uint8x64
+func (from Uint64x8) AsUint8x64() (to Uint8x64)
+
+// Uint16x32 converts from Uint64x8 to Uint16x32
+func (from Uint64x8) AsUint16x32() (to Uint16x32)
+
+// Uint32x16 converts from Uint64x8 to Uint32x16
+func (from Uint64x8) AsUint32x16() (to Uint32x16)
+
+// converts from Mask8x16 to Int8x16
+func (from Mask8x16) AsInt8x16() (to Int8x16)
+
+// converts from Int8x16 to Mask8x16
+func (from Int8x16) AsMask8x16() (to Mask8x16)
+
+func (x Mask8x16) And(y Mask8x16) Mask8x16
+
+func (x Mask8x16) Or(y Mask8x16) Mask8x16
+
+// converts from Mask8x32 to Int8x32
+func (from Mask8x32) AsInt8x32() (to Int8x32)
+
+// converts from Int8x32 to Mask8x32
+func (from Int8x32) AsMask8x32() (to Mask8x32)
+
+func (x Mask8x32) And(y Mask8x32) Mask8x32
+
+func (x Mask8x32) Or(y Mask8x32) Mask8x32
+
+// converts from Mask8x64 to Int8x64
+func (from Mask8x64) AsInt8x64() (to Int8x64)
+
+// converts from Int8x64 to Mask8x64
+func (from Int8x64) AsMask8x64() (to Mask8x64)
+
+func (x Mask8x64) And(y Mask8x64) Mask8x64
+
+func (x Mask8x64) Or(y Mask8x64) Mask8x64
+
+// converts from Mask16x8 to Int16x8
+func (from Mask16x8) AsInt16x8() (to Int16x8)
+
+// converts from Int16x8 to Mask16x8
+func (from Int16x8) AsMask16x8() (to Mask16x8)
+
+func (x Mask16x8) And(y Mask16x8) Mask16x8
+
+func (x Mask16x8) Or(y Mask16x8) Mask16x8
+
+// converts from Mask16x16 to Int16x16
+func (from Mask16x16) AsInt16x16() (to Int16x16)
+
+// converts from Int16x16 to Mask16x16
+func (from Int16x16) AsMask16x16() (to Mask16x16)
+
+func (x Mask16x16) And(y Mask16x16) Mask16x16
+
+func (x Mask16x16) Or(y Mask16x16) Mask16x16
+
+// converts from Mask16x32 to Int16x32
+func (from Mask16x32) AsInt16x32() (to Int16x32)
+
+// converts from Int16x32 to Mask16x32
+func (from Int16x32) AsMask16x32() (to Mask16x32)
+
+func (x Mask16x32) And(y Mask16x32) Mask16x32
+
+func (x Mask16x32) Or(y Mask16x32) Mask16x32
+
+// converts from Mask32x4 to Int32x4
+func (from Mask32x4) AsInt32x4() (to Int32x4)
+
+// converts from Int32x4 to Mask32x4
+func (from Int32x4) AsMask32x4() (to Mask32x4)
+
+func (x Mask32x4) And(y Mask32x4) Mask32x4
+
+func (x Mask32x4) Or(y Mask32x4) Mask32x4
+
+// converts from Mask32x8 to Int32x8
+func (from Mask32x8) AsInt32x8() (to Int32x8)
+
+// converts from Int32x8 to Mask32x8
+func (from Int32x8) AsMask32x8() (to Mask32x8)
+
+func (x Mask32x8) And(y Mask32x8) Mask32x8
+
+func (x Mask32x8) Or(y Mask32x8) Mask32x8
+
+// converts from Mask32x16 to Int32x16
+func (from Mask32x16) AsInt32x16() (to Int32x16)
+
+// converts from Int32x16 to Mask32x16
+func (from Int32x16) AsMask32x16() (to Mask32x16)
+
+func (x Mask32x16) And(y Mask32x16) Mask32x16
+
+func (x Mask32x16) Or(y Mask32x16) Mask32x16
+
+// converts from Mask64x2 to Int64x2
+func (from Mask64x2) AsInt64x2() (to Int64x2)
+
+// converts from Int64x2 to Mask64x2
+func (from Int64x2) AsMask64x2() (to Mask64x2)
+
+func (x Mask64x2) And(y Mask64x2) Mask64x2
+
+func (x Mask64x2) Or(y Mask64x2) Mask64x2
+
+// converts from Mask64x4 to Int64x4
+func (from Mask64x4) AsInt64x4() (to Int64x4)
+
+// converts from Int64x4 to Mask64x4
+func (from Int64x4) AsMask64x4() (to Mask64x4)
+
+func (x Mask64x4) And(y Mask64x4) Mask64x4
+
+func (x Mask64x4) Or(y Mask64x4) Mask64x4
+
+// converts from Mask64x8 to Int64x8
+func (from Mask64x8) AsInt64x8() (to Int64x8)
+
+// converts from Int64x8 to Mask64x8
+func (from Int64x8) AsMask64x8() (to Mask64x8)
+
+func (x Mask64x8) And(y Mask64x8) Mask64x8
+
+func (x Mask64x8) Or(y Mask64x8) Mask64x8
diff --git a/src/simd/simd_test.go b/src/simd/simd_test.go
new file mode 100644
index 00000000000000..14e5fe31794f99
--- /dev/null
+++ b/src/simd/simd_test.go
@@ -0,0 +1,462 @@
+// Copyright 2025 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+//go:build goexperiment.simd && amd64
+
+package simd_test
+
+import (
+	"reflect"
+	"simd"
+	"testing"
+)
+
+var sink any
+
+func TestType(t *testing.T) {
+	// Testing:
+	// - Defined as another struct's field is ok
+	// - Pointer is ok
+	// - Type defition is ok
+	// - Type alias is ok
+	// - Type conversion is ok
+	// - Conversion to interface is ok
+	type alias = simd.Int32x4
+	type maskT simd.Mask32x4
+	type myStruct struct {
+		x alias
+		y *simd.Int32x4
+		z maskT
+	}
+	vals := [4]int32{1, 2, 3, 4}
+	v := myStruct{x: simd.LoadInt32x4(&vals)}
+	// masking elements 1 and 2.
+	maskv := [4]int32{-1, -1, 0, 0}
+	want := []int32{2, 4, 0, 0}
+	y := simd.LoadInt32x4(&vals)
+	v.y = &y
+	sink = y
+
+	if !simd.HasAVX512GFNI() {
+		t.Skip("Test requires HasAVX512, not available on this hardware")
+		return
+	}
+	v.z = maskT(simd.LoadInt32x4(&maskv).AsMask32x4())
+	*v.y = v.y.AddMasked(v.x, simd.Mask32x4(v.z))
+
+	got := [4]int32{}
+	v.y.Store(&got)
+	for i := range 4 {
+		if want[i] != got[i] {
+			t.Errorf("Result at %d incorrect: want %d, got %d", i, want[i], got[i])
+		}
+	}
+}
+
+func TestFuncValue(t *testing.T) {
+	// Test that simd intrinsic can be used as a function value.
+	xv := [4]int32{1, 2, 3, 4}
+	yv := [4]int32{5, 6, 7, 8}
+	want := []int32{6, 8, 10, 12}
+	x := simd.LoadInt32x4(&xv)
+	y := simd.LoadInt32x4(&yv)
+	fn := simd.Int32x4.Add
+	sink = fn
+	x = fn(x, y)
+	got := [4]int32{}
+	x.Store(&got)
+	for i := range 4 {
+		if want[i] != got[i] {
+			t.Errorf("Result at %d incorrect: want %d, got %d", i, want[i], got[i])
+		}
+	}
+}
+
+func TestReflectMethod(t *testing.T) {
+	// Test that simd intrinsic can be accessed via reflection.
+	// NOTE: we don't yet support reflect method.Call.
+	xv := [4]int32{1, 2, 3, 4}
+	yv := [4]int32{5, 6, 7, 8}
+	want := []int32{6, 8, 10, 12}
+	x := simd.LoadInt32x4(&xv)
+	y := simd.LoadInt32x4(&yv)
+	m, ok := reflect.TypeOf(x).MethodByName("Add")
+	if !ok {
+		t.Fatal("Add method not found")
+	}
+	fn := m.Func.Interface().(func(x, y simd.Int32x4) simd.Int32x4)
+	x = fn(x, y)
+	got := [4]int32{}
+	x.Store(&got)
+	for i := range 4 {
+		if want[i] != got[i] {
+			t.Errorf("Result at %d incorrect: want %d, got %d", i, want[i], got[i])
+		}
+	}
+}
+
+func TestVectorConversion(t *testing.T) {
+	if !simd.HasAVX512GFNI() {
+		t.Skip("Test requires HasAVX512, not available on this hardware")
+		return
+	}
+	xv := [4]int32{1, 2, 3, 4}
+	x := simd.LoadInt32x4(&xv)
+	xPromoted := x.AsInt64x2()
+	xPromotedDemoted := xPromoted.AsInt32x4()
+	got := [4]int32{}
+	xPromotedDemoted.Store(&got)
+	for i := range 4 {
+		if xv[i] != got[i] {
+			t.Errorf("Result at %d incorrect: want %d, got %d", i, xv[i], got[i])
+		}
+	}
+}
+
+func TestMaskConversion(t *testing.T) {
+	if !simd.HasAVX512GFNI() {
+		t.Skip("Test requires HasAVX512, not available on this hardware")
+		return
+	}
+	v := [4]int32{1, 0, 1, 0}
+	x := simd.LoadInt32x4(&v)
+	var y simd.Int32x4
+	mask := y.Sub(x).AsMask32x4()
+	v = [4]int32{5, 6, 7, 8}
+	y = simd.LoadInt32x4(&v)
+	y = y.AddMasked(x, mask)
+	got := [4]int32{6, 0, 8, 0}
+	y.Store(&v)
+	for i := range 4 {
+		if v[i] != got[i] {
+			t.Errorf("Result at %d incorrect: want %d, got %d", i, v[i], got[i])
+		}
+	}
+}
+
+func TestAdd(t *testing.T) {
+	testInt32x4Binary(t, []int32{1, 2, 3, 4}, []int32{5, 6, 7, 8}, []int32{6, 8, 10, 12}, "Add")
+}
+
+func TestSub(t *testing.T) {
+	testInt32x4Binary(t, []int32{5, 5, 5, 3}, []int32{3, 3, 3, 3}, []int32{2, 2, 2, 0}, "Sub")
+}
+
+func TestMaskedAdd(t *testing.T) {
+	if !simd.HasAVX512GFNI() {
+		t.Skip("Test requires HasAVX512, not available on this hardware")
+		return
+	}
+	testInt32x4BinaryMasked(t, []int32{1, 2, 3, 4}, []int32{5, 6, 7, 8}, []int32{-1, -1, 0, 0}, []int32{6, 8, 0, 0}, "AddMasked")
+}
+
+func TestPermute(t *testing.T) {
+	if !simd.HasAVX512() {
+		t.Skip("Test requires HasAVX512, not available on this hardware")
+		return
+	}
+	x := []int64{1, 2, 3, 4, 5, 6, 7, 8}
+	indices := []uint64{7, 6, 5, 4, 3, 2, 1, 0}
+	want := []int64{8, 7, 6, 5, 4, 3, 2, 1}
+	got := make([]int64, 8)
+	simd.LoadInt64x8Slice(x).Permute(simd.LoadUint64x8Slice(indices)).StoreSlice(got)
+	for i := range 8 {
+		if want[i] != got[i] {
+			t.Errorf("want and got differ at index %d, want=%d, got=%d", i, want[i], got[i])
+		}
+	}
+}
+
+func TestPermute2(t *testing.T) {
+	if !simd.HasAVX512() {
+		t.Skip("Test requires HasAVX512, not available on this hardware")
+		return
+	}
+	x := []int64{1, 2, 3, 4, 5, 6, 7, 8}
+	y := []int64{-1, -2, -3, -4, -5, -6, -7, -8}
+	indices := []uint64{7 + 8, 6, 5 + 8, 4, 3 + 8, 2, 1 + 8, 0}
+	want := []int64{-8, 7, -6, 5, -4, 3, -2, 1}
+	got := make([]int64, 8)
+	simd.LoadInt64x8Slice(x).Permute2(simd.LoadInt64x8Slice(y), simd.LoadUint64x8Slice(indices)).StoreSlice(got)
+	for i := range 8 {
+		if want[i] != got[i] {
+			t.Errorf("want and got differ at index %d, want=%d, got=%d", i, want[i], got[i])
+		}
+	}
+}
+
+func TestCompress(t *testing.T) {
+	if !simd.HasAVX512() {
+		t.Skip("Test requires HasAVX512, not available on this hardware")
+		return
+	}
+	testInt32x4Mask32x4Int32x4(t, []int32{1, 2, 3, 4},
+		[]int32{0, -1, 0, -1},
+		[]int32{2, 4, 0, 0}, "Compress")
+}
+
+func TestAndNot(t *testing.T) {
+	testInt32x4Binary(t, []int32{0b11, 0b00, 0b11, 0b00},
+		[]int32{0b01, 0b01, 0b01, 0b01},
+		[]int32{0b10, 0b00, 0b10, 0b00}, "AndNot")
+}
+
+func TestPairDotProdAccumulate(t *testing.T) {
+	if !simd.HasAVX512GFNI() {
+		// TODO: this function is actually VNNI, let's implement and call the right check.
+		t.Skip("Test requires HasAVX512GFNI, not available on this hardware")
+		return
+	}
+	x := simd.LoadInt16x8Slice([]int16{2, 2, 2, 2, 2, 2, 2, 2})
+	z := simd.LoadInt32x4Slice([]int32{3, 3, 3, 3})
+	want := []int32{11, 11, 11, 11}
+	got := make([]int32, 4)
+	z = x.PairDotProdAccumulate(x, z)
+	z.StoreSlice(got)
+	for i := range 4 {
+		if got[i] != want[i] {
+			t.Errorf("a and b differ at index %d, got=%d, want=%d", i, got[i], want[i])
+		}
+	}
+}
+
+// checkInt8Slices ensures that b and a are equal, to the end of b.
+// also serves to use the slices, to prevent accidental optimization.
+func checkInt8Slices(t *testing.T, a, b []int8) {
+	for i := range b {
+		if a[i] != b[i] {
+			t.Errorf("a and b differ at index %d, a=%d, b=%d", i, a[i], b[i])
+		}
+	}
+}
+
+func checkUint8Slices(t *testing.T, a, b []uint8) {
+	for i := range b {
+		if a[i] != b[i] {
+			t.Errorf("a and b differ at index %d, a=%d, b=%d", i, a[i], b[i])
+		}
+	}
+}
+
+func checkInt16Slices(t *testing.T, a, b []int16) {
+	for i := range b {
+		if a[i] != b[i] {
+			t.Errorf("a and b differ at index %d, a=%d, b=%d", i, a[i], b[i])
+		}
+	}
+}
+
+func checkUint16Slices(t *testing.T, a, b []uint16) {
+	for i := range b {
+		if a[i] != b[i] {
+			t.Errorf("a and b differ at index %d, a=%d, b=%d", i, a[i], b[i])
+		}
+	}
+}
+
+func checkFloat32Slices(t *testing.T, a, b []float32) {
+	for i := range b {
+		if a[i] != b[i] {
+			t.Errorf("a and b differ at index %d, a=%3.0f, b=%3.0f", i, a[i], b[i])
+		}
+	}
+}
+
+func checkFloat64Slices(t *testing.T, a, b []float64) {
+	for i := range b {
+		if a[i] != b[i] {
+			t.Errorf("a and b differ at index %d, a=%3.0f, b=%3.0f", i, a[i], b[i])
+		}
+	}
+}
+
+func TestSlicesInt8(t *testing.T) {
+	a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	v := simd.LoadInt8x32Slice(a)
+	b := make([]int8, 32, 32)
+	v.StoreSlice(b)
+	checkInt8Slices(t, a, b)
+}
+
+func TestSlicesInt8SetElem(t *testing.T) {
+	a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	v := simd.LoadInt8x16Slice(a)
+
+	v = v.SetElem(3, 13)
+	a[3] = 13
+
+	b := make([]int8, 16, 16)
+	v.StoreSlice(b)
+	checkInt8Slices(t, a, b)
+}
+
+func TestSlicesInt8GetElem(t *testing.T) {
+	a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	v := simd.LoadInt8x16Slice(a)
+	e := v.GetElem(2)
+	if e != a[2] {
+		t.Errorf("GetElem(2) = %d != a[2] = %d", e, a[2])
+	}
+
+}
+
+func TestSlicesInt8Set128(t *testing.T) {
+	a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	v := simd.LoadInt8x16Slice(a) // 1-16
+	u := simd.LoadInt8x32Slice(a) // 1-32
+
+	w := u.Set128(1, v) // 1-16:1-16
+
+	b := make([]int8, 32, 32)
+	w.StoreSlice(b)
+
+	checkInt8Slices(t, a, b[:16])
+	checkInt8Slices(t, a, b[16:])
+}
+
+func TestSlicesInt8Get128(t *testing.T) {
+	a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	u := simd.LoadInt8x32Slice(a) // 1-32
+	v := u.Get128(0)              // 1-16
+	w := u.Get128(1)              // 17-32
+
+	b := make([]int8, 32, 32)
+	v.StoreSlice(b[:16])
+	w.StoreSlice(b[16:])
+
+	checkInt8Slices(t, a, b)
+}
+
+func TestSlicesFloat32Set128(t *testing.T) {
+	a := []float32{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	v := simd.LoadFloat32x4Slice(a) // 1-4
+	u := simd.LoadFloat32x8Slice(a) // 1-4
+
+	w := u.Set128(1, v) // 1-4:1-4
+
+	b := make([]float32, 8, 8)
+	w.StoreSlice(b)
+
+	checkFloat32Slices(t, a, b[:4])
+	checkFloat32Slices(t, a, b[4:])
+}
+
+func TestSlicesFloat32Get128(t *testing.T) {
+	a := []float32{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	u := simd.LoadFloat32x8Slice(a) // 1-8
+	v := u.Get128(0)                // 1-4
+	w := u.Get128(1)                // 5-8
+
+	b := make([]float32, 8, 8)
+	v.StoreSlice(b[:4])
+	w.StoreSlice(b[4:])
+
+	checkFloat32Slices(t, a, b)
+}
+
+func TestSlicesFloat64Set128(t *testing.T) {
+	a := []float64{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	v := simd.LoadFloat64x2Slice(a) // 1-2
+	u := simd.LoadFloat64x4Slice(a) // 1-2
+
+	w := u.Set128(1, v) // 1-2:1-2
+
+	b := make([]float64, 4, 4)
+	w.StoreSlice(b)
+
+	checkFloat64Slices(t, a, b[:2])
+	checkFloat64Slices(t, a, b[2:])
+}
+
+func TestSlicesFloat64Get128(t *testing.T) {
+	a := []float64{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	u := simd.LoadFloat64x4Slice(a) // 1-4
+	v := u.Get128(0)                // 1-2
+	w := u.Get128(1)                // 3-4
+
+	b := make([]float64, 4, 4)
+	v.StoreSlice(b[:2])
+	w.StoreSlice(b[2:])
+
+	checkFloat64Slices(t, a, b)
+}
+
+func TestSlicesInt8TooShortLoad(t *testing.T) {
+	defer func() {
+		if r := recover(); r != nil {
+			t.Logf("Saw EXPECTED panic %v", r)
+		} else {
+			t.Errorf("Did not see expected panic")
+		}
+	}()
+	a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31} // TOO SHORT, should panic
+	v := simd.LoadInt8x32Slice(a)
+	b := make([]int8, 32, 32)
+	v.StoreSlice(b)
+	checkInt8Slices(t, a, b)
+}
+
+func TestSlicesInt8TooShortStore(t *testing.T) {
+	defer func() {
+		if r := recover(); r != nil {
+			t.Logf("Saw EXPECTED panic %v", r)
+		} else {
+			t.Errorf("Did not see expected panic")
+		}
+	}()
+	a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	v := simd.LoadInt8x32Slice(a)
+	b := make([]int8, 31) // TOO SHORT, should panic
+	v.StoreSlice(b)
+	checkInt8Slices(t, a, b)
+}
+
+func TestSlicesFloat64(t *testing.T) {
+	a := []float64{1, 2, 3, 4, 5, 6, 7, 8} // too long, should be fine
+	v := simd.LoadFloat64x4Slice(a)
+	b := make([]float64, 4, 4)
+	v.StoreSlice(b)
+	for i := range b {
+		if a[i] != b[i] {
+			t.Errorf("a and b differ at index %d, a=%f, b=%f", i, a[i], b[i])
+		}
+	}
+}
+
+// TODO: try to reduce this test to be smaller.
+func TestMergeLocals(t *testing.T) {
+	testMergeLocalswrapper(t, simd.Int64x4.Add)
+}
+
+//go:noinline
+func forceSpill() {}
+
+func testMergeLocalswrapper(t *testing.T, op func(simd.Int64x4, simd.Int64x4) simd.Int64x4) {
+	t.Helper()
+	s0 := []int64{0, 1, 2, 3}
+	s1 := []int64{-1, 0, -1, 0}
+	want := []int64{-1, 1, 1, 3}
+	v := simd.LoadInt64x4Slice(s0)
+	m := simd.LoadInt64x4Slice(s1)
+	forceSpill()
+	got := make([]int64, 4)
+	gotv := op(v, m)
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if !(got[i] == want[i]) {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
diff --git a/src/simd/simd_wrapped_test.go b/src/simd/simd_wrapped_test.go
new file mode 100644
index 00000000000000..d46c05e5290c4e
--- /dev/null
+++ b/src/simd/simd_wrapped_test.go
@@ -0,0 +1,8021 @@
+// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT.
+
+//go:build goexperiment.simd
+
+package simd_test
+
+import (
+	"simd"
+	"testing"
+)
+
+func testFloat32x4Binary(t *testing.T, v0 []float32, v1 []float32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x4
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x4Slice(v0)
+	vec1 := simd.LoadFloat32x4Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "AddSub":
+		gotv = vec0.AddSub(vec1)
+	case "Div":
+		gotv = vec0.Div(vec1)
+	case "DotProdBroadcast":
+		gotv = vec0.DotProdBroadcast(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "Mul":
+		gotv = vec0.Mul(vec1)
+	case "MulByPowOf2":
+		gotv = vec0.MulByPowOf2(vec1)
+	case "PairwiseAdd":
+		gotv = vec0.PairwiseAdd(vec1)
+	case "PairwiseSub":
+		gotv = vec0.PairwiseSub(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+
+	default:
+		t.Errorf("Unknown method: Float32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x4BinaryMasked(t *testing.T, v0 []float32, v1 []float32, v2 []int32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x4
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x4Slice(v0)
+	vec1 := simd.LoadFloat32x4Slice(v1)
+	vec2 := simd.LoadInt32x4Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask32x4())
+	case "DivMasked":
+		gotv = vec0.DivMasked(vec1, vec2.AsMask32x4())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask32x4())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask32x4())
+	case "MulByPowOf2Masked":
+		gotv = vec0.MulByPowOf2Masked(vec1, vec2.AsMask32x4())
+	case "MulMasked":
+		gotv = vec0.MulMasked(vec1, vec2.AsMask32x4())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask32x4())
+
+	default:
+		t.Errorf("Unknown method: Float32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x4Compare(t *testing.T, v0 []float32, v1 []float32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadFloat32x4Slice(v0)
+	vec1 := simd.LoadFloat32x4Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt32x4()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt32x4()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt32x4()
+	case "IsNan":
+		gotv = vec0.IsNan(vec1).AsInt32x4()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt32x4()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt32x4()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt32x4()
+
+	default:
+		t.Errorf("Unknown method: Float32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x4Mask32x4Float32x4(t *testing.T, v0 []float32, v1 []int32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x4
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x4Slice(v0)
+	vec1 := simd.LoadInt32x4Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask32x4())
+
+	default:
+		t.Errorf("Unknown method: Float32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x4MaskedCompare(t *testing.T, v0 []float32, v1 []float32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadFloat32x4Slice(v0)
+	vec1 := simd.LoadFloat32x4Slice(v1)
+	vec2 := simd.LoadInt32x4Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "IsNanMasked":
+		gotv = vec0.IsNanMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+
+	default:
+		t.Errorf("Unknown method: Float32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x4Ternary(t *testing.T, v0 []float32, v1 []float32, v2 []float32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x4
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x4Slice(v0)
+	vec1 := simd.LoadFloat32x4Slice(v1)
+	vec2 := simd.LoadFloat32x4Slice(v2)
+	switch which {
+	case "FusedMultiplyAdd":
+		gotv = vec0.FusedMultiplyAdd(vec1, vec2)
+	case "FusedMultiplyAddSub":
+		gotv = vec0.FusedMultiplyAddSub(vec1, vec2)
+	case "FusedMultiplySubAdd":
+		gotv = vec0.FusedMultiplySubAdd(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Float32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x4TernaryMasked(t *testing.T, v0 []float32, v1 []float32, v2 []float32, v3 []int32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x4
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x4Slice(v0)
+	vec1 := simd.LoadFloat32x4Slice(v1)
+	vec2 := simd.LoadFloat32x4Slice(v2)
+	vec3 := simd.LoadInt32x4Slice(v3)
+	switch which {
+	case "FusedMultiplyAddMasked":
+		gotv = vec0.FusedMultiplyAddMasked(vec1, vec2, vec3.AsMask32x4())
+	case "FusedMultiplyAddSubMasked":
+		gotv = vec0.FusedMultiplyAddSubMasked(vec1, vec2, vec3.AsMask32x4())
+	case "FusedMultiplySubAddMasked":
+		gotv = vec0.FusedMultiplySubAddMasked(vec1, vec2, vec3.AsMask32x4())
+
+	default:
+		t.Errorf("Unknown method: Float32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x4Unary(t *testing.T, v0 []float32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x4
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x4Slice(v0)
+	switch which {
+	case "ApproximateReciprocal":
+		gotv = vec0.ApproximateReciprocal()
+	case "ApproximateReciprocalOfSqrt":
+		gotv = vec0.ApproximateReciprocalOfSqrt()
+	case "Ceil":
+		gotv = vec0.Ceil()
+	case "Floor":
+		gotv = vec0.Floor()
+	case "Round":
+		gotv = vec0.Round()
+	case "Sqrt":
+		gotv = vec0.Sqrt()
+	case "Trunc":
+		gotv = vec0.Trunc()
+
+	default:
+		t.Errorf("Unknown method: Float32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x4UnaryMasked(t *testing.T, v0 []float32, v1 []int32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x4
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x4Slice(v0)
+	vec1 := simd.LoadInt32x4Slice(v1)
+	switch which {
+	case "ApproximateReciprocalMasked":
+		gotv = vec0.ApproximateReciprocalMasked(vec1.AsMask32x4())
+	case "ApproximateReciprocalOfSqrtMasked":
+		gotv = vec0.ApproximateReciprocalOfSqrtMasked(vec1.AsMask32x4())
+	case "SqrtMasked":
+		gotv = vec0.SqrtMasked(vec1.AsMask32x4())
+
+	default:
+		t.Errorf("Unknown method: Float32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x8Binary(t *testing.T, v0 []float32, v1 []float32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x8
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x8Slice(v0)
+	vec1 := simd.LoadFloat32x8Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "AddSub":
+		gotv = vec0.AddSub(vec1)
+	case "Div":
+		gotv = vec0.Div(vec1)
+	case "DotProdBroadcast":
+		gotv = vec0.DotProdBroadcast(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "Mul":
+		gotv = vec0.Mul(vec1)
+	case "MulByPowOf2":
+		gotv = vec0.MulByPowOf2(vec1)
+	case "PairwiseAdd":
+		gotv = vec0.PairwiseAdd(vec1)
+	case "PairwiseSub":
+		gotv = vec0.PairwiseSub(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+
+	default:
+		t.Errorf("Unknown method: Float32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x8BinaryMasked(t *testing.T, v0 []float32, v1 []float32, v2 []int32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x8
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x8Slice(v0)
+	vec1 := simd.LoadFloat32x8Slice(v1)
+	vec2 := simd.LoadInt32x8Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask32x8())
+	case "DivMasked":
+		gotv = vec0.DivMasked(vec1, vec2.AsMask32x8())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask32x8())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask32x8())
+	case "MulByPowOf2Masked":
+		gotv = vec0.MulByPowOf2Masked(vec1, vec2.AsMask32x8())
+	case "MulMasked":
+		gotv = vec0.MulMasked(vec1, vec2.AsMask32x8())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask32x8())
+
+	default:
+		t.Errorf("Unknown method: Float32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x8Compare(t *testing.T, v0 []float32, v1 []float32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadFloat32x8Slice(v0)
+	vec1 := simd.LoadFloat32x8Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt32x8()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt32x8()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt32x8()
+	case "IsNan":
+		gotv = vec0.IsNan(vec1).AsInt32x8()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt32x8()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt32x8()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt32x8()
+
+	default:
+		t.Errorf("Unknown method: Float32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x8Mask32x8Float32x8(t *testing.T, v0 []float32, v1 []int32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x8
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x8Slice(v0)
+	vec1 := simd.LoadInt32x8Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask32x8())
+
+	default:
+		t.Errorf("Unknown method: Float32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x8MaskedCompare(t *testing.T, v0 []float32, v1 []float32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadFloat32x8Slice(v0)
+	vec1 := simd.LoadFloat32x8Slice(v1)
+	vec2 := simd.LoadInt32x8Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "IsNanMasked":
+		gotv = vec0.IsNanMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+
+	default:
+		t.Errorf("Unknown method: Float32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x8Ternary(t *testing.T, v0 []float32, v1 []float32, v2 []float32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x8
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x8Slice(v0)
+	vec1 := simd.LoadFloat32x8Slice(v1)
+	vec2 := simd.LoadFloat32x8Slice(v2)
+	switch which {
+	case "FusedMultiplyAdd":
+		gotv = vec0.FusedMultiplyAdd(vec1, vec2)
+	case "FusedMultiplyAddSub":
+		gotv = vec0.FusedMultiplyAddSub(vec1, vec2)
+	case "FusedMultiplySubAdd":
+		gotv = vec0.FusedMultiplySubAdd(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Float32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x8TernaryMasked(t *testing.T, v0 []float32, v1 []float32, v2 []float32, v3 []int32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x8
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x8Slice(v0)
+	vec1 := simd.LoadFloat32x8Slice(v1)
+	vec2 := simd.LoadFloat32x8Slice(v2)
+	vec3 := simd.LoadInt32x8Slice(v3)
+	switch which {
+	case "FusedMultiplyAddMasked":
+		gotv = vec0.FusedMultiplyAddMasked(vec1, vec2, vec3.AsMask32x8())
+	case "FusedMultiplyAddSubMasked":
+		gotv = vec0.FusedMultiplyAddSubMasked(vec1, vec2, vec3.AsMask32x8())
+	case "FusedMultiplySubAddMasked":
+		gotv = vec0.FusedMultiplySubAddMasked(vec1, vec2, vec3.AsMask32x8())
+
+	default:
+		t.Errorf("Unknown method: Float32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x8Unary(t *testing.T, v0 []float32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x8
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x8Slice(v0)
+	switch which {
+	case "ApproximateReciprocal":
+		gotv = vec0.ApproximateReciprocal()
+	case "ApproximateReciprocalOfSqrt":
+		gotv = vec0.ApproximateReciprocalOfSqrt()
+	case "Ceil":
+		gotv = vec0.Ceil()
+	case "Floor":
+		gotv = vec0.Floor()
+	case "Round":
+		gotv = vec0.Round()
+	case "Sqrt":
+		gotv = vec0.Sqrt()
+	case "Trunc":
+		gotv = vec0.Trunc()
+
+	default:
+		t.Errorf("Unknown method: Float32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x8UnaryMasked(t *testing.T, v0 []float32, v1 []int32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x8
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x8Slice(v0)
+	vec1 := simd.LoadInt32x8Slice(v1)
+	switch which {
+	case "ApproximateReciprocalMasked":
+		gotv = vec0.ApproximateReciprocalMasked(vec1.AsMask32x8())
+	case "ApproximateReciprocalOfSqrtMasked":
+		gotv = vec0.ApproximateReciprocalOfSqrtMasked(vec1.AsMask32x8())
+	case "SqrtMasked":
+		gotv = vec0.SqrtMasked(vec1.AsMask32x8())
+
+	default:
+		t.Errorf("Unknown method: Float32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x16Binary(t *testing.T, v0 []float32, v1 []float32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x16
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x16Slice(v0)
+	vec1 := simd.LoadFloat32x16Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "Div":
+		gotv = vec0.Div(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "Mul":
+		gotv = vec0.Mul(vec1)
+	case "MulByPowOf2":
+		gotv = vec0.MulByPowOf2(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+
+	default:
+		t.Errorf("Unknown method: Float32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x16BinaryMasked(t *testing.T, v0 []float32, v1 []float32, v2 []int32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x16
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x16Slice(v0)
+	vec1 := simd.LoadFloat32x16Slice(v1)
+	vec2 := simd.LoadInt32x16Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask32x16())
+	case "DivMasked":
+		gotv = vec0.DivMasked(vec1, vec2.AsMask32x16())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask32x16())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask32x16())
+	case "MulByPowOf2Masked":
+		gotv = vec0.MulByPowOf2Masked(vec1, vec2.AsMask32x16())
+	case "MulMasked":
+		gotv = vec0.MulMasked(vec1, vec2.AsMask32x16())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask32x16())
+
+	default:
+		t.Errorf("Unknown method: Float32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x16Compare(t *testing.T, v0 []float32, v1 []float32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadFloat32x16Slice(v0)
+	vec1 := simd.LoadFloat32x16Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt32x16()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt32x16()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt32x16()
+	case "IsNan":
+		gotv = vec0.IsNan(vec1).AsInt32x16()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt32x16()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt32x16()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt32x16()
+
+	default:
+		t.Errorf("Unknown method: Float32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x16Mask32x16Float32x16(t *testing.T, v0 []float32, v1 []int32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x16
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x16Slice(v0)
+	vec1 := simd.LoadInt32x16Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask32x16())
+
+	default:
+		t.Errorf("Unknown method: Float32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x16MaskedCompare(t *testing.T, v0 []float32, v1 []float32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadFloat32x16Slice(v0)
+	vec1 := simd.LoadFloat32x16Slice(v1)
+	vec2 := simd.LoadInt32x16Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "IsNanMasked":
+		gotv = vec0.IsNanMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+
+	default:
+		t.Errorf("Unknown method: Float32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x16Ternary(t *testing.T, v0 []float32, v1 []float32, v2 []float32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x16
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x16Slice(v0)
+	vec1 := simd.LoadFloat32x16Slice(v1)
+	vec2 := simd.LoadFloat32x16Slice(v2)
+	switch which {
+	case "FusedMultiplyAdd":
+		gotv = vec0.FusedMultiplyAdd(vec1, vec2)
+	case "FusedMultiplyAddSub":
+		gotv = vec0.FusedMultiplyAddSub(vec1, vec2)
+	case "FusedMultiplySubAdd":
+		gotv = vec0.FusedMultiplySubAdd(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Float32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x16TernaryMasked(t *testing.T, v0 []float32, v1 []float32, v2 []float32, v3 []int32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x16
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x16Slice(v0)
+	vec1 := simd.LoadFloat32x16Slice(v1)
+	vec2 := simd.LoadFloat32x16Slice(v2)
+	vec3 := simd.LoadInt32x16Slice(v3)
+	switch which {
+	case "FusedMultiplyAddMasked":
+		gotv = vec0.FusedMultiplyAddMasked(vec1, vec2, vec3.AsMask32x16())
+	case "FusedMultiplyAddSubMasked":
+		gotv = vec0.FusedMultiplyAddSubMasked(vec1, vec2, vec3.AsMask32x16())
+	case "FusedMultiplySubAddMasked":
+		gotv = vec0.FusedMultiplySubAddMasked(vec1, vec2, vec3.AsMask32x16())
+
+	default:
+		t.Errorf("Unknown method: Float32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x16Unary(t *testing.T, v0 []float32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x16
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x16Slice(v0)
+	switch which {
+	case "ApproximateReciprocal":
+		gotv = vec0.ApproximateReciprocal()
+	case "ApproximateReciprocalOfSqrt":
+		gotv = vec0.ApproximateReciprocalOfSqrt()
+	case "Sqrt":
+		gotv = vec0.Sqrt()
+
+	default:
+		t.Errorf("Unknown method: Float32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat32x16UnaryMasked(t *testing.T, v0 []float32, v1 []int32, want []float32, which string) {
+	t.Helper()
+	var gotv simd.Float32x16
+	got := make([]float32, len(want))
+	vec0 := simd.LoadFloat32x16Slice(v0)
+	vec1 := simd.LoadInt32x16Slice(v1)
+	switch which {
+	case "ApproximateReciprocalMasked":
+		gotv = vec0.ApproximateReciprocalMasked(vec1.AsMask32x16())
+	case "ApproximateReciprocalOfSqrtMasked":
+		gotv = vec0.ApproximateReciprocalOfSqrtMasked(vec1.AsMask32x16())
+	case "SqrtMasked":
+		gotv = vec0.SqrtMasked(vec1.AsMask32x16())
+
+	default:
+		t.Errorf("Unknown method: Float32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x2Binary(t *testing.T, v0 []float64, v1 []float64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x2
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x2Slice(v0)
+	vec1 := simd.LoadFloat64x2Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "AddSub":
+		gotv = vec0.AddSub(vec1)
+	case "Div":
+		gotv = vec0.Div(vec1)
+	case "DotProdBroadcast":
+		gotv = vec0.DotProdBroadcast(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "Mul":
+		gotv = vec0.Mul(vec1)
+	case "MulByPowOf2":
+		gotv = vec0.MulByPowOf2(vec1)
+	case "PairwiseAdd":
+		gotv = vec0.PairwiseAdd(vec1)
+	case "PairwiseSub":
+		gotv = vec0.PairwiseSub(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+
+	default:
+		t.Errorf("Unknown method: Float64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x2BinaryMasked(t *testing.T, v0 []float64, v1 []float64, v2 []int64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x2
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x2Slice(v0)
+	vec1 := simd.LoadFloat64x2Slice(v1)
+	vec2 := simd.LoadInt64x2Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask64x2())
+	case "DivMasked":
+		gotv = vec0.DivMasked(vec1, vec2.AsMask64x2())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask64x2())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask64x2())
+	case "MulByPowOf2Masked":
+		gotv = vec0.MulByPowOf2Masked(vec1, vec2.AsMask64x2())
+	case "MulMasked":
+		gotv = vec0.MulMasked(vec1, vec2.AsMask64x2())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask64x2())
+
+	default:
+		t.Errorf("Unknown method: Float64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x2Compare(t *testing.T, v0 []float64, v1 []float64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadFloat64x2Slice(v0)
+	vec1 := simd.LoadFloat64x2Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt64x2()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt64x2()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt64x2()
+	case "IsNan":
+		gotv = vec0.IsNan(vec1).AsInt64x2()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt64x2()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt64x2()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt64x2()
+
+	default:
+		t.Errorf("Unknown method: Float64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x2Mask64x2Float64x2(t *testing.T, v0 []float64, v1 []int64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x2
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x2Slice(v0)
+	vec1 := simd.LoadInt64x2Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask64x2())
+
+	default:
+		t.Errorf("Unknown method: Float64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x2MaskedCompare(t *testing.T, v0 []float64, v1 []float64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadFloat64x2Slice(v0)
+	vec1 := simd.LoadFloat64x2Slice(v1)
+	vec2 := simd.LoadInt64x2Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "IsNanMasked":
+		gotv = vec0.IsNanMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+
+	default:
+		t.Errorf("Unknown method: Float64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x2Ternary(t *testing.T, v0 []float64, v1 []float64, v2 []float64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x2
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x2Slice(v0)
+	vec1 := simd.LoadFloat64x2Slice(v1)
+	vec2 := simd.LoadFloat64x2Slice(v2)
+	switch which {
+	case "FusedMultiplyAdd":
+		gotv = vec0.FusedMultiplyAdd(vec1, vec2)
+	case "FusedMultiplyAddSub":
+		gotv = vec0.FusedMultiplyAddSub(vec1, vec2)
+	case "FusedMultiplySubAdd":
+		gotv = vec0.FusedMultiplySubAdd(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Float64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x2TernaryMasked(t *testing.T, v0 []float64, v1 []float64, v2 []float64, v3 []int64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x2
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x2Slice(v0)
+	vec1 := simd.LoadFloat64x2Slice(v1)
+	vec2 := simd.LoadFloat64x2Slice(v2)
+	vec3 := simd.LoadInt64x2Slice(v3)
+	switch which {
+	case "FusedMultiplyAddMasked":
+		gotv = vec0.FusedMultiplyAddMasked(vec1, vec2, vec3.AsMask64x2())
+	case "FusedMultiplyAddSubMasked":
+		gotv = vec0.FusedMultiplyAddSubMasked(vec1, vec2, vec3.AsMask64x2())
+	case "FusedMultiplySubAddMasked":
+		gotv = vec0.FusedMultiplySubAddMasked(vec1, vec2, vec3.AsMask64x2())
+
+	default:
+		t.Errorf("Unknown method: Float64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x2Unary(t *testing.T, v0 []float64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x2
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x2Slice(v0)
+	switch which {
+	case "ApproximateReciprocal":
+		gotv = vec0.ApproximateReciprocal()
+	case "ApproximateReciprocalOfSqrt":
+		gotv = vec0.ApproximateReciprocalOfSqrt()
+	case "Ceil":
+		gotv = vec0.Ceil()
+	case "Floor":
+		gotv = vec0.Floor()
+	case "Round":
+		gotv = vec0.Round()
+	case "Sqrt":
+		gotv = vec0.Sqrt()
+	case "Trunc":
+		gotv = vec0.Trunc()
+
+	default:
+		t.Errorf("Unknown method: Float64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x2UnaryMasked(t *testing.T, v0 []float64, v1 []int64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x2
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x2Slice(v0)
+	vec1 := simd.LoadInt64x2Slice(v1)
+	switch which {
+	case "ApproximateReciprocalMasked":
+		gotv = vec0.ApproximateReciprocalMasked(vec1.AsMask64x2())
+	case "ApproximateReciprocalOfSqrtMasked":
+		gotv = vec0.ApproximateReciprocalOfSqrtMasked(vec1.AsMask64x2())
+	case "SqrtMasked":
+		gotv = vec0.SqrtMasked(vec1.AsMask64x2())
+
+	default:
+		t.Errorf("Unknown method: Float64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x4Binary(t *testing.T, v0 []float64, v1 []float64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x4
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x4Slice(v0)
+	vec1 := simd.LoadFloat64x4Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "AddSub":
+		gotv = vec0.AddSub(vec1)
+	case "Div":
+		gotv = vec0.Div(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "Mul":
+		gotv = vec0.Mul(vec1)
+	case "MulByPowOf2":
+		gotv = vec0.MulByPowOf2(vec1)
+	case "PairwiseAdd":
+		gotv = vec0.PairwiseAdd(vec1)
+	case "PairwiseSub":
+		gotv = vec0.PairwiseSub(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+
+	default:
+		t.Errorf("Unknown method: Float64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x4BinaryMasked(t *testing.T, v0 []float64, v1 []float64, v2 []int64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x4
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x4Slice(v0)
+	vec1 := simd.LoadFloat64x4Slice(v1)
+	vec2 := simd.LoadInt64x4Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask64x4())
+	case "DivMasked":
+		gotv = vec0.DivMasked(vec1, vec2.AsMask64x4())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask64x4())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask64x4())
+	case "MulByPowOf2Masked":
+		gotv = vec0.MulByPowOf2Masked(vec1, vec2.AsMask64x4())
+	case "MulMasked":
+		gotv = vec0.MulMasked(vec1, vec2.AsMask64x4())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask64x4())
+
+	default:
+		t.Errorf("Unknown method: Float64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x4Compare(t *testing.T, v0 []float64, v1 []float64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadFloat64x4Slice(v0)
+	vec1 := simd.LoadFloat64x4Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt64x4()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt64x4()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt64x4()
+	case "IsNan":
+		gotv = vec0.IsNan(vec1).AsInt64x4()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt64x4()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt64x4()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt64x4()
+
+	default:
+		t.Errorf("Unknown method: Float64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x4Mask64x4Float64x4(t *testing.T, v0 []float64, v1 []int64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x4
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x4Slice(v0)
+	vec1 := simd.LoadInt64x4Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask64x4())
+
+	default:
+		t.Errorf("Unknown method: Float64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x4MaskedCompare(t *testing.T, v0 []float64, v1 []float64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadFloat64x4Slice(v0)
+	vec1 := simd.LoadFloat64x4Slice(v1)
+	vec2 := simd.LoadInt64x4Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "IsNanMasked":
+		gotv = vec0.IsNanMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+
+	default:
+		t.Errorf("Unknown method: Float64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x4Ternary(t *testing.T, v0 []float64, v1 []float64, v2 []float64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x4
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x4Slice(v0)
+	vec1 := simd.LoadFloat64x4Slice(v1)
+	vec2 := simd.LoadFloat64x4Slice(v2)
+	switch which {
+	case "FusedMultiplyAdd":
+		gotv = vec0.FusedMultiplyAdd(vec1, vec2)
+	case "FusedMultiplyAddSub":
+		gotv = vec0.FusedMultiplyAddSub(vec1, vec2)
+	case "FusedMultiplySubAdd":
+		gotv = vec0.FusedMultiplySubAdd(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Float64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x4TernaryMasked(t *testing.T, v0 []float64, v1 []float64, v2 []float64, v3 []int64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x4
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x4Slice(v0)
+	vec1 := simd.LoadFloat64x4Slice(v1)
+	vec2 := simd.LoadFloat64x4Slice(v2)
+	vec3 := simd.LoadInt64x4Slice(v3)
+	switch which {
+	case "FusedMultiplyAddMasked":
+		gotv = vec0.FusedMultiplyAddMasked(vec1, vec2, vec3.AsMask64x4())
+	case "FusedMultiplyAddSubMasked":
+		gotv = vec0.FusedMultiplyAddSubMasked(vec1, vec2, vec3.AsMask64x4())
+	case "FusedMultiplySubAddMasked":
+		gotv = vec0.FusedMultiplySubAddMasked(vec1, vec2, vec3.AsMask64x4())
+
+	default:
+		t.Errorf("Unknown method: Float64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x4Unary(t *testing.T, v0 []float64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x4
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x4Slice(v0)
+	switch which {
+	case "ApproximateReciprocal":
+		gotv = vec0.ApproximateReciprocal()
+	case "ApproximateReciprocalOfSqrt":
+		gotv = vec0.ApproximateReciprocalOfSqrt()
+	case "Ceil":
+		gotv = vec0.Ceil()
+	case "Floor":
+		gotv = vec0.Floor()
+	case "Round":
+		gotv = vec0.Round()
+	case "Sqrt":
+		gotv = vec0.Sqrt()
+	case "Trunc":
+		gotv = vec0.Trunc()
+
+	default:
+		t.Errorf("Unknown method: Float64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x4UnaryMasked(t *testing.T, v0 []float64, v1 []int64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x4
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x4Slice(v0)
+	vec1 := simd.LoadInt64x4Slice(v1)
+	switch which {
+	case "ApproximateReciprocalMasked":
+		gotv = vec0.ApproximateReciprocalMasked(vec1.AsMask64x4())
+	case "ApproximateReciprocalOfSqrtMasked":
+		gotv = vec0.ApproximateReciprocalOfSqrtMasked(vec1.AsMask64x4())
+	case "SqrtMasked":
+		gotv = vec0.SqrtMasked(vec1.AsMask64x4())
+
+	default:
+		t.Errorf("Unknown method: Float64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x8Binary(t *testing.T, v0 []float64, v1 []float64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x8
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x8Slice(v0)
+	vec1 := simd.LoadFloat64x8Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "Div":
+		gotv = vec0.Div(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "Mul":
+		gotv = vec0.Mul(vec1)
+	case "MulByPowOf2":
+		gotv = vec0.MulByPowOf2(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+
+	default:
+		t.Errorf("Unknown method: Float64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x8BinaryMasked(t *testing.T, v0 []float64, v1 []float64, v2 []int64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x8
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x8Slice(v0)
+	vec1 := simd.LoadFloat64x8Slice(v1)
+	vec2 := simd.LoadInt64x8Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask64x8())
+	case "DivMasked":
+		gotv = vec0.DivMasked(vec1, vec2.AsMask64x8())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask64x8())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask64x8())
+	case "MulByPowOf2Masked":
+		gotv = vec0.MulByPowOf2Masked(vec1, vec2.AsMask64x8())
+	case "MulMasked":
+		gotv = vec0.MulMasked(vec1, vec2.AsMask64x8())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask64x8())
+
+	default:
+		t.Errorf("Unknown method: Float64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x8Compare(t *testing.T, v0 []float64, v1 []float64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x8
+	got := make([]int64, len(want))
+	vec0 := simd.LoadFloat64x8Slice(v0)
+	vec1 := simd.LoadFloat64x8Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt64x8()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt64x8()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt64x8()
+	case "IsNan":
+		gotv = vec0.IsNan(vec1).AsInt64x8()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt64x8()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt64x8()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt64x8()
+
+	default:
+		t.Errorf("Unknown method: Float64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x8Mask64x8Float64x8(t *testing.T, v0 []float64, v1 []int64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x8
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x8Slice(v0)
+	vec1 := simd.LoadInt64x8Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask64x8())
+
+	default:
+		t.Errorf("Unknown method: Float64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x8MaskedCompare(t *testing.T, v0 []float64, v1 []float64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x8
+	got := make([]int64, len(want))
+	vec0 := simd.LoadFloat64x8Slice(v0)
+	vec1 := simd.LoadFloat64x8Slice(v1)
+	vec2 := simd.LoadInt64x8Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "IsNanMasked":
+		gotv = vec0.IsNanMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+
+	default:
+		t.Errorf("Unknown method: Float64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x8Ternary(t *testing.T, v0 []float64, v1 []float64, v2 []float64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x8
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x8Slice(v0)
+	vec1 := simd.LoadFloat64x8Slice(v1)
+	vec2 := simd.LoadFloat64x8Slice(v2)
+	switch which {
+	case "FusedMultiplyAdd":
+		gotv = vec0.FusedMultiplyAdd(vec1, vec2)
+	case "FusedMultiplyAddSub":
+		gotv = vec0.FusedMultiplyAddSub(vec1, vec2)
+	case "FusedMultiplySubAdd":
+		gotv = vec0.FusedMultiplySubAdd(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Float64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x8TernaryMasked(t *testing.T, v0 []float64, v1 []float64, v2 []float64, v3 []int64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x8
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x8Slice(v0)
+	vec1 := simd.LoadFloat64x8Slice(v1)
+	vec2 := simd.LoadFloat64x8Slice(v2)
+	vec3 := simd.LoadInt64x8Slice(v3)
+	switch which {
+	case "FusedMultiplyAddMasked":
+		gotv = vec0.FusedMultiplyAddMasked(vec1, vec2, vec3.AsMask64x8())
+	case "FusedMultiplyAddSubMasked":
+		gotv = vec0.FusedMultiplyAddSubMasked(vec1, vec2, vec3.AsMask64x8())
+	case "FusedMultiplySubAddMasked":
+		gotv = vec0.FusedMultiplySubAddMasked(vec1, vec2, vec3.AsMask64x8())
+
+	default:
+		t.Errorf("Unknown method: Float64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x8Unary(t *testing.T, v0 []float64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x8
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x8Slice(v0)
+	switch which {
+	case "ApproximateReciprocal":
+		gotv = vec0.ApproximateReciprocal()
+	case "ApproximateReciprocalOfSqrt":
+		gotv = vec0.ApproximateReciprocalOfSqrt()
+	case "Sqrt":
+		gotv = vec0.Sqrt()
+
+	default:
+		t.Errorf("Unknown method: Float64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testFloat64x8UnaryMasked(t *testing.T, v0 []float64, v1 []int64, want []float64, which string) {
+	t.Helper()
+	var gotv simd.Float64x8
+	got := make([]float64, len(want))
+	vec0 := simd.LoadFloat64x8Slice(v0)
+	vec1 := simd.LoadInt64x8Slice(v1)
+	switch which {
+	case "ApproximateReciprocalMasked":
+		gotv = vec0.ApproximateReciprocalMasked(vec1.AsMask64x8())
+	case "ApproximateReciprocalOfSqrtMasked":
+		gotv = vec0.ApproximateReciprocalOfSqrtMasked(vec1.AsMask64x8())
+	case "SqrtMasked":
+		gotv = vec0.SqrtMasked(vec1.AsMask64x8())
+
+	default:
+		t.Errorf("Unknown method: Float64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x16Binary(t *testing.T, v0 []int8, v1 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x16
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x16Slice(v0)
+	vec1 := simd.LoadInt8x16Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "SaturatedAdd":
+		gotv = vec0.SaturatedAdd(vec1)
+	case "SaturatedSub":
+		gotv = vec0.SaturatedSub(vec1)
+	case "Sign":
+		gotv = vec0.Sign(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x16BinaryMasked(t *testing.T, v0 []int8, v1 []int8, v2 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x16
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x16Slice(v0)
+	vec1 := simd.LoadInt8x16Slice(v1)
+	vec2 := simd.LoadInt8x16Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask8x16())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask8x16())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask8x16())
+	case "SaturatedAddMasked":
+		gotv = vec0.SaturatedAddMasked(vec1, vec2.AsMask8x16())
+	case "SaturatedSubMasked":
+		gotv = vec0.SaturatedSubMasked(vec1, vec2.AsMask8x16())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask8x16())
+
+	default:
+		t.Errorf("Unknown method: Int8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x16Compare(t *testing.T, v0 []int8, v1 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x16
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x16Slice(v0)
+	vec1 := simd.LoadInt8x16Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt8x16()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt8x16()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt8x16()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt8x16()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt8x16()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt8x16()
+
+	default:
+		t.Errorf("Unknown method: Int8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x16Mask8x16Int8x16(t *testing.T, v0 []int8, v1 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x16
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x16Slice(v0)
+	vec1 := simd.LoadInt8x16Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask8x16())
+
+	default:
+		t.Errorf("Unknown method: Int8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x16MaskedCompare(t *testing.T, v0 []int8, v1 []int8, v2 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x16
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x16Slice(v0)
+	vec1 := simd.LoadInt8x16Slice(v1)
+	vec2 := simd.LoadInt8x16Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask8x16()).AsInt8x16()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask8x16()).AsInt8x16()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask8x16()).AsInt8x16()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask8x16()).AsInt8x16()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask8x16()).AsInt8x16()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask8x16()).AsInt8x16()
+
+	default:
+		t.Errorf("Unknown method: Int8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x16Unary(t *testing.T, v0 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x16
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x16Slice(v0)
+	switch which {
+	case "Absolute":
+		gotv = vec0.Absolute()
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Int8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x16UnaryMasked(t *testing.T, v0 []int8, v1 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x16
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x16Slice(v0)
+	vec1 := simd.LoadInt8x16Slice(v1)
+	switch which {
+	case "AbsoluteMasked":
+		gotv = vec0.AbsoluteMasked(vec1.AsMask8x16())
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask8x16())
+
+	default:
+		t.Errorf("Unknown method: Int8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x32Binary(t *testing.T, v0 []int8, v1 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x32
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x32Slice(v0)
+	vec1 := simd.LoadInt8x32Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "SaturatedAdd":
+		gotv = vec0.SaturatedAdd(vec1)
+	case "SaturatedSub":
+		gotv = vec0.SaturatedSub(vec1)
+	case "Sign":
+		gotv = vec0.Sign(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x32BinaryMasked(t *testing.T, v0 []int8, v1 []int8, v2 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x32
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x32Slice(v0)
+	vec1 := simd.LoadInt8x32Slice(v1)
+	vec2 := simd.LoadInt8x32Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask8x32())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask8x32())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask8x32())
+	case "SaturatedAddMasked":
+		gotv = vec0.SaturatedAddMasked(vec1, vec2.AsMask8x32())
+	case "SaturatedSubMasked":
+		gotv = vec0.SaturatedSubMasked(vec1, vec2.AsMask8x32())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask8x32())
+
+	default:
+		t.Errorf("Unknown method: Int8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x32Compare(t *testing.T, v0 []int8, v1 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x32
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x32Slice(v0)
+	vec1 := simd.LoadInt8x32Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt8x32()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt8x32()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt8x32()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt8x32()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt8x32()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt8x32()
+
+	default:
+		t.Errorf("Unknown method: Int8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x32Mask8x32Int8x32(t *testing.T, v0 []int8, v1 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x32
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x32Slice(v0)
+	vec1 := simd.LoadInt8x32Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask8x32())
+
+	default:
+		t.Errorf("Unknown method: Int8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x32MaskedCompare(t *testing.T, v0 []int8, v1 []int8, v2 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x32
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x32Slice(v0)
+	vec1 := simd.LoadInt8x32Slice(v1)
+	vec2 := simd.LoadInt8x32Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask8x32()).AsInt8x32()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask8x32()).AsInt8x32()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask8x32()).AsInt8x32()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask8x32()).AsInt8x32()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask8x32()).AsInt8x32()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask8x32()).AsInt8x32()
+
+	default:
+		t.Errorf("Unknown method: Int8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x32Unary(t *testing.T, v0 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x32
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x32Slice(v0)
+	switch which {
+	case "Absolute":
+		gotv = vec0.Absolute()
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Int8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x32UnaryMasked(t *testing.T, v0 []int8, v1 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x32
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x32Slice(v0)
+	vec1 := simd.LoadInt8x32Slice(v1)
+	switch which {
+	case "AbsoluteMasked":
+		gotv = vec0.AbsoluteMasked(vec1.AsMask8x32())
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask8x32())
+
+	default:
+		t.Errorf("Unknown method: Int8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x64Binary(t *testing.T, v0 []int8, v1 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x64
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x64Slice(v0)
+	vec1 := simd.LoadInt8x64Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "SaturatedAdd":
+		gotv = vec0.SaturatedAdd(vec1)
+	case "SaturatedSub":
+		gotv = vec0.SaturatedSub(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x64BinaryMasked(t *testing.T, v0 []int8, v1 []int8, v2 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x64
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x64Slice(v0)
+	vec1 := simd.LoadInt8x64Slice(v1)
+	vec2 := simd.LoadInt8x64Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask8x64())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask8x64())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask8x64())
+	case "SaturatedAddMasked":
+		gotv = vec0.SaturatedAddMasked(vec1, vec2.AsMask8x64())
+	case "SaturatedSubMasked":
+		gotv = vec0.SaturatedSubMasked(vec1, vec2.AsMask8x64())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask8x64())
+
+	default:
+		t.Errorf("Unknown method: Int8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x64Compare(t *testing.T, v0 []int8, v1 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x64
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x64Slice(v0)
+	vec1 := simd.LoadInt8x64Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt8x64()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt8x64()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt8x64()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt8x64()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt8x64()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt8x64()
+
+	default:
+		t.Errorf("Unknown method: Int8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x64Mask8x64Int8x64(t *testing.T, v0 []int8, v1 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x64
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x64Slice(v0)
+	vec1 := simd.LoadInt8x64Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask8x64())
+
+	default:
+		t.Errorf("Unknown method: Int8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x64MaskedCompare(t *testing.T, v0 []int8, v1 []int8, v2 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x64
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x64Slice(v0)
+	vec1 := simd.LoadInt8x64Slice(v1)
+	vec2 := simd.LoadInt8x64Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask8x64()).AsInt8x64()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask8x64()).AsInt8x64()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask8x64()).AsInt8x64()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask8x64()).AsInt8x64()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask8x64()).AsInt8x64()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask8x64()).AsInt8x64()
+
+	default:
+		t.Errorf("Unknown method: Int8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x64Unary(t *testing.T, v0 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x64
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x64Slice(v0)
+	switch which {
+	case "Absolute":
+		gotv = vec0.Absolute()
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Int8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt8x64UnaryMasked(t *testing.T, v0 []int8, v1 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x64
+	got := make([]int8, len(want))
+	vec0 := simd.LoadInt8x64Slice(v0)
+	vec1 := simd.LoadInt8x64Slice(v1)
+	switch which {
+	case "AbsoluteMasked":
+		gotv = vec0.AbsoluteMasked(vec1.AsMask8x64())
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask8x64())
+
+	default:
+		t.Errorf("Unknown method: Int8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x8Binary(t *testing.T, v0 []int16, v1 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x8
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x8Slice(v0)
+	vec1 := simd.LoadInt16x8Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulHigh":
+		gotv = vec0.MulHigh(vec1)
+	case "MulLow":
+		gotv = vec0.MulLow(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "PairwiseAdd":
+		gotv = vec0.PairwiseAdd(vec1)
+	case "PairwiseSub":
+		gotv = vec0.PairwiseSub(vec1)
+	case "SaturatedAdd":
+		gotv = vec0.SaturatedAdd(vec1)
+	case "SaturatedPairwiseAdd":
+		gotv = vec0.SaturatedPairwiseAdd(vec1)
+	case "SaturatedPairwiseSub":
+		gotv = vec0.SaturatedPairwiseSub(vec1)
+	case "SaturatedSub":
+		gotv = vec0.SaturatedSub(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sign":
+		gotv = vec0.Sign(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x8BinaryMasked(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x8
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x8Slice(v0)
+	vec1 := simd.LoadInt16x8Slice(v1)
+	vec2 := simd.LoadInt16x8Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask16x8())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask16x8())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask16x8())
+	case "MulHighMasked":
+		gotv = vec0.MulHighMasked(vec1, vec2.AsMask16x8())
+	case "MulLowMasked":
+		gotv = vec0.MulLowMasked(vec1, vec2.AsMask16x8())
+	case "SaturatedAddMasked":
+		gotv = vec0.SaturatedAddMasked(vec1, vec2.AsMask16x8())
+	case "SaturatedSubMasked":
+		gotv = vec0.SaturatedSubMasked(vec1, vec2.AsMask16x8())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask16x8())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask16x8())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask16x8())
+
+	default:
+		t.Errorf("Unknown method: Int16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x8BinaryMaskedWiden(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt16x8Slice(v0)
+	vec1 := simd.LoadInt16x8Slice(v1)
+	vec2 := simd.LoadInt16x8Slice(v2)
+	switch which {
+	case "PairDotProdMasked":
+		gotv = vec0.PairDotProdMasked(vec1, vec2.AsMask16x8())
+
+	default:
+		t.Errorf("Unknown method: Int16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x8BinaryWiden(t *testing.T, v0 []int16, v1 []int16, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt16x8Slice(v0)
+	vec1 := simd.LoadInt16x8Slice(v1)
+	switch which {
+	case "PairDotProd":
+		gotv = vec0.PairDotProd(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x8Compare(t *testing.T, v0 []int16, v1 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x8
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x8Slice(v0)
+	vec1 := simd.LoadInt16x8Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt16x8()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt16x8()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt16x8()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt16x8()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt16x8()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt16x8()
+
+	default:
+		t.Errorf("Unknown method: Int16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x8Mask16x8Int16x8(t *testing.T, v0 []int16, v1 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x8
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x8Slice(v0)
+	vec1 := simd.LoadInt16x8Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask16x8())
+
+	default:
+		t.Errorf("Unknown method: Int16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x8MaskedCompare(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x8
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x8Slice(v0)
+	vec1 := simd.LoadInt16x8Slice(v1)
+	vec2 := simd.LoadInt16x8Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask16x8()).AsInt16x8()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask16x8()).AsInt16x8()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask16x8()).AsInt16x8()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask16x8()).AsInt16x8()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask16x8()).AsInt16x8()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask16x8()).AsInt16x8()
+
+	default:
+		t.Errorf("Unknown method: Int16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x8Ternary(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x8
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x8Slice(v0)
+	vec1 := simd.LoadInt16x8Slice(v1)
+	vec2 := simd.LoadInt16x8Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Int16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x8TernaryMasked(t *testing.T, v0 []int16, v1 []int16, v2 []int16, v3 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x8
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x8Slice(v0)
+	vec1 := simd.LoadInt16x8Slice(v1)
+	vec2 := simd.LoadInt16x8Slice(v2)
+	vec3 := simd.LoadInt16x8Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask16x8())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask16x8())
+
+	default:
+		t.Errorf("Unknown method: Int16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x8Unary(t *testing.T, v0 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x8
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x8Slice(v0)
+	switch which {
+	case "Absolute":
+		gotv = vec0.Absolute()
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Int16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x8UnaryMasked(t *testing.T, v0 []int16, v1 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x8
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x8Slice(v0)
+	vec1 := simd.LoadInt16x8Slice(v1)
+	switch which {
+	case "AbsoluteMasked":
+		gotv = vec0.AbsoluteMasked(vec1.AsMask16x8())
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask16x8())
+
+	default:
+		t.Errorf("Unknown method: Int16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x16Binary(t *testing.T, v0 []int16, v1 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x16
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x16Slice(v0)
+	vec1 := simd.LoadInt16x16Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulHigh":
+		gotv = vec0.MulHigh(vec1)
+	case "MulLow":
+		gotv = vec0.MulLow(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "PairwiseAdd":
+		gotv = vec0.PairwiseAdd(vec1)
+	case "PairwiseSub":
+		gotv = vec0.PairwiseSub(vec1)
+	case "SaturatedAdd":
+		gotv = vec0.SaturatedAdd(vec1)
+	case "SaturatedPairwiseAdd":
+		gotv = vec0.SaturatedPairwiseAdd(vec1)
+	case "SaturatedPairwiseSub":
+		gotv = vec0.SaturatedPairwiseSub(vec1)
+	case "SaturatedSub":
+		gotv = vec0.SaturatedSub(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sign":
+		gotv = vec0.Sign(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x16BinaryMasked(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x16
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x16Slice(v0)
+	vec1 := simd.LoadInt16x16Slice(v1)
+	vec2 := simd.LoadInt16x16Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask16x16())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask16x16())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask16x16())
+	case "MulHighMasked":
+		gotv = vec0.MulHighMasked(vec1, vec2.AsMask16x16())
+	case "MulLowMasked":
+		gotv = vec0.MulLowMasked(vec1, vec2.AsMask16x16())
+	case "SaturatedAddMasked":
+		gotv = vec0.SaturatedAddMasked(vec1, vec2.AsMask16x16())
+	case "SaturatedSubMasked":
+		gotv = vec0.SaturatedSubMasked(vec1, vec2.AsMask16x16())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask16x16())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask16x16())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask16x16())
+
+	default:
+		t.Errorf("Unknown method: Int16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x16BinaryMaskedWiden(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt16x16Slice(v0)
+	vec1 := simd.LoadInt16x16Slice(v1)
+	vec2 := simd.LoadInt16x16Slice(v2)
+	switch which {
+	case "PairDotProdMasked":
+		gotv = vec0.PairDotProdMasked(vec1, vec2.AsMask16x16())
+
+	default:
+		t.Errorf("Unknown method: Int16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x16BinaryWiden(t *testing.T, v0 []int16, v1 []int16, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt16x16Slice(v0)
+	vec1 := simd.LoadInt16x16Slice(v1)
+	switch which {
+	case "PairDotProd":
+		gotv = vec0.PairDotProd(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x16Compare(t *testing.T, v0 []int16, v1 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x16
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x16Slice(v0)
+	vec1 := simd.LoadInt16x16Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt16x16()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt16x16()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt16x16()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt16x16()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt16x16()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt16x16()
+
+	default:
+		t.Errorf("Unknown method: Int16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x16Mask16x16Int16x16(t *testing.T, v0 []int16, v1 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x16
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x16Slice(v0)
+	vec1 := simd.LoadInt16x16Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask16x16())
+
+	default:
+		t.Errorf("Unknown method: Int16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x16MaskedCompare(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x16
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x16Slice(v0)
+	vec1 := simd.LoadInt16x16Slice(v1)
+	vec2 := simd.LoadInt16x16Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask16x16()).AsInt16x16()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask16x16()).AsInt16x16()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask16x16()).AsInt16x16()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask16x16()).AsInt16x16()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask16x16()).AsInt16x16()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask16x16()).AsInt16x16()
+
+	default:
+		t.Errorf("Unknown method: Int16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x16Ternary(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x16
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x16Slice(v0)
+	vec1 := simd.LoadInt16x16Slice(v1)
+	vec2 := simd.LoadInt16x16Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Int16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x16TernaryMasked(t *testing.T, v0 []int16, v1 []int16, v2 []int16, v3 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x16
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x16Slice(v0)
+	vec1 := simd.LoadInt16x16Slice(v1)
+	vec2 := simd.LoadInt16x16Slice(v2)
+	vec3 := simd.LoadInt16x16Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask16x16())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask16x16())
+
+	default:
+		t.Errorf("Unknown method: Int16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x16Unary(t *testing.T, v0 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x16
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x16Slice(v0)
+	switch which {
+	case "Absolute":
+		gotv = vec0.Absolute()
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Int16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x16UnaryMasked(t *testing.T, v0 []int16, v1 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x16
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x16Slice(v0)
+	vec1 := simd.LoadInt16x16Slice(v1)
+	switch which {
+	case "AbsoluteMasked":
+		gotv = vec0.AbsoluteMasked(vec1.AsMask16x16())
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask16x16())
+
+	default:
+		t.Errorf("Unknown method: Int16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x32Binary(t *testing.T, v0 []int16, v1 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x32
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x32Slice(v0)
+	vec1 := simd.LoadInt16x32Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulHigh":
+		gotv = vec0.MulHigh(vec1)
+	case "MulLow":
+		gotv = vec0.MulLow(vec1)
+	case "SaturatedAdd":
+		gotv = vec0.SaturatedAdd(vec1)
+	case "SaturatedSub":
+		gotv = vec0.SaturatedSub(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x32BinaryMasked(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x32
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x32Slice(v0)
+	vec1 := simd.LoadInt16x32Slice(v1)
+	vec2 := simd.LoadInt16x32Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask16x32())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask16x32())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask16x32())
+	case "MulHighMasked":
+		gotv = vec0.MulHighMasked(vec1, vec2.AsMask16x32())
+	case "MulLowMasked":
+		gotv = vec0.MulLowMasked(vec1, vec2.AsMask16x32())
+	case "SaturatedAddMasked":
+		gotv = vec0.SaturatedAddMasked(vec1, vec2.AsMask16x32())
+	case "SaturatedSubMasked":
+		gotv = vec0.SaturatedSubMasked(vec1, vec2.AsMask16x32())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask16x32())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask16x32())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask16x32())
+
+	default:
+		t.Errorf("Unknown method: Int16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x32BinaryMaskedWiden(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt16x32Slice(v0)
+	vec1 := simd.LoadInt16x32Slice(v1)
+	vec2 := simd.LoadInt16x32Slice(v2)
+	switch which {
+	case "PairDotProdMasked":
+		gotv = vec0.PairDotProdMasked(vec1, vec2.AsMask16x32())
+
+	default:
+		t.Errorf("Unknown method: Int16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x32BinaryWiden(t *testing.T, v0 []int16, v1 []int16, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt16x32Slice(v0)
+	vec1 := simd.LoadInt16x32Slice(v1)
+	switch which {
+	case "PairDotProd":
+		gotv = vec0.PairDotProd(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x32Compare(t *testing.T, v0 []int16, v1 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x32
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x32Slice(v0)
+	vec1 := simd.LoadInt16x32Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt16x32()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt16x32()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt16x32()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt16x32()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt16x32()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt16x32()
+
+	default:
+		t.Errorf("Unknown method: Int16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x32Mask16x32Int16x32(t *testing.T, v0 []int16, v1 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x32
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x32Slice(v0)
+	vec1 := simd.LoadInt16x32Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask16x32())
+
+	default:
+		t.Errorf("Unknown method: Int16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x32MaskedCompare(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x32
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x32Slice(v0)
+	vec1 := simd.LoadInt16x32Slice(v1)
+	vec2 := simd.LoadInt16x32Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask16x32()).AsInt16x32()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask16x32()).AsInt16x32()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask16x32()).AsInt16x32()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask16x32()).AsInt16x32()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask16x32()).AsInt16x32()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask16x32()).AsInt16x32()
+
+	default:
+		t.Errorf("Unknown method: Int16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x32Ternary(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x32
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x32Slice(v0)
+	vec1 := simd.LoadInt16x32Slice(v1)
+	vec2 := simd.LoadInt16x32Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Int16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x32TernaryMasked(t *testing.T, v0 []int16, v1 []int16, v2 []int16, v3 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x32
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x32Slice(v0)
+	vec1 := simd.LoadInt16x32Slice(v1)
+	vec2 := simd.LoadInt16x32Slice(v2)
+	vec3 := simd.LoadInt16x32Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask16x32())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask16x32())
+
+	default:
+		t.Errorf("Unknown method: Int16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x32Unary(t *testing.T, v0 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x32
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x32Slice(v0)
+	switch which {
+	case "Absolute":
+		gotv = vec0.Absolute()
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Int16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt16x32UnaryMasked(t *testing.T, v0 []int16, v1 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x32
+	got := make([]int16, len(want))
+	vec0 := simd.LoadInt16x32Slice(v0)
+	vec1 := simd.LoadInt16x32Slice(v1)
+	switch which {
+	case "AbsoluteMasked":
+		gotv = vec0.AbsoluteMasked(vec1.AsMask16x32())
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask16x32())
+
+	default:
+		t.Errorf("Unknown method: Int16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x4Binary(t *testing.T, v0 []int32, v1 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x4Slice(v0)
+	vec1 := simd.LoadInt32x4Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulLow":
+		gotv = vec0.MulLow(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "PairwiseAdd":
+		gotv = vec0.PairwiseAdd(vec1)
+	case "PairwiseSub":
+		gotv = vec0.PairwiseSub(vec1)
+	case "RotateLeft":
+		gotv = vec0.RotateLeft(vec1)
+	case "RotateRight":
+		gotv = vec0.RotateRight(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sign":
+		gotv = vec0.Sign(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x4BinaryMasked(t *testing.T, v0 []int32, v1 []int32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x4Slice(v0)
+	vec1 := simd.LoadInt32x4Slice(v1)
+	vec2 := simd.LoadInt32x4Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask32x4())
+	case "AndMasked":
+		gotv = vec0.AndMasked(vec1, vec2.AsMask32x4())
+	case "AndNotMasked":
+		gotv = vec0.AndNotMasked(vec1, vec2.AsMask32x4())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask32x4())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask32x4())
+	case "MulLowMasked":
+		gotv = vec0.MulLowMasked(vec1, vec2.AsMask32x4())
+	case "OrMasked":
+		gotv = vec0.OrMasked(vec1, vec2.AsMask32x4())
+	case "RotateLeftMasked":
+		gotv = vec0.RotateLeftMasked(vec1, vec2.AsMask32x4())
+	case "RotateRightMasked":
+		gotv = vec0.RotateRightMasked(vec1, vec2.AsMask32x4())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask32x4())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask32x4())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask32x4())
+	case "XorMasked":
+		gotv = vec0.XorMasked(vec1, vec2.AsMask32x4())
+
+	default:
+		t.Errorf("Unknown method: Int32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x4BinaryWiden(t *testing.T, v0 []int32, v1 []int32, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt32x4Slice(v0)
+	vec1 := simd.LoadInt32x4Slice(v1)
+	switch which {
+	case "MulEvenWiden":
+		gotv = vec0.MulEvenWiden(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x4Compare(t *testing.T, v0 []int32, v1 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x4Slice(v0)
+	vec1 := simd.LoadInt32x4Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt32x4()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt32x4()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt32x4()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt32x4()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt32x4()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt32x4()
+
+	default:
+		t.Errorf("Unknown method: Int32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x4Mask32x4Int32x4(t *testing.T, v0 []int32, v1 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x4Slice(v0)
+	vec1 := simd.LoadInt32x4Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask32x4())
+
+	default:
+		t.Errorf("Unknown method: Int32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x4MaskedCompare(t *testing.T, v0 []int32, v1 []int32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x4Slice(v0)
+	vec1 := simd.LoadInt32x4Slice(v1)
+	vec2 := simd.LoadInt32x4Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+
+	default:
+		t.Errorf("Unknown method: Int32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x4Ternary(t *testing.T, v0 []int32, v1 []int32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x4Slice(v0)
+	vec1 := simd.LoadInt32x4Slice(v1)
+	vec2 := simd.LoadInt32x4Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Int32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x4TernaryMasked(t *testing.T, v0 []int32, v1 []int32, v2 []int32, v3 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x4Slice(v0)
+	vec1 := simd.LoadInt32x4Slice(v1)
+	vec2 := simd.LoadInt32x4Slice(v2)
+	vec3 := simd.LoadInt32x4Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask32x4())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask32x4())
+
+	default:
+		t.Errorf("Unknown method: Int32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x4Unary(t *testing.T, v0 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x4Slice(v0)
+	switch which {
+	case "Absolute":
+		gotv = vec0.Absolute()
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Int32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x4UnaryMasked(t *testing.T, v0 []int32, v1 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x4Slice(v0)
+	vec1 := simd.LoadInt32x4Slice(v1)
+	switch which {
+	case "AbsoluteMasked":
+		gotv = vec0.AbsoluteMasked(vec1.AsMask32x4())
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask32x4())
+
+	default:
+		t.Errorf("Unknown method: Int32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x8Binary(t *testing.T, v0 []int32, v1 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x8Slice(v0)
+	vec1 := simd.LoadInt32x8Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulLow":
+		gotv = vec0.MulLow(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "PairwiseAdd":
+		gotv = vec0.PairwiseAdd(vec1)
+	case "PairwiseSub":
+		gotv = vec0.PairwiseSub(vec1)
+	case "RotateLeft":
+		gotv = vec0.RotateLeft(vec1)
+	case "RotateRight":
+		gotv = vec0.RotateRight(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sign":
+		gotv = vec0.Sign(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x8BinaryMasked(t *testing.T, v0 []int32, v1 []int32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x8Slice(v0)
+	vec1 := simd.LoadInt32x8Slice(v1)
+	vec2 := simd.LoadInt32x8Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask32x8())
+	case "AndMasked":
+		gotv = vec0.AndMasked(vec1, vec2.AsMask32x8())
+	case "AndNotMasked":
+		gotv = vec0.AndNotMasked(vec1, vec2.AsMask32x8())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask32x8())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask32x8())
+	case "MulLowMasked":
+		gotv = vec0.MulLowMasked(vec1, vec2.AsMask32x8())
+	case "OrMasked":
+		gotv = vec0.OrMasked(vec1, vec2.AsMask32x8())
+	case "RotateLeftMasked":
+		gotv = vec0.RotateLeftMasked(vec1, vec2.AsMask32x8())
+	case "RotateRightMasked":
+		gotv = vec0.RotateRightMasked(vec1, vec2.AsMask32x8())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask32x8())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask32x8())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask32x8())
+	case "XorMasked":
+		gotv = vec0.XorMasked(vec1, vec2.AsMask32x8())
+
+	default:
+		t.Errorf("Unknown method: Int32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x8BinaryWiden(t *testing.T, v0 []int32, v1 []int32, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt32x8Slice(v0)
+	vec1 := simd.LoadInt32x8Slice(v1)
+	switch which {
+	case "MulEvenWiden":
+		gotv = vec0.MulEvenWiden(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x8Compare(t *testing.T, v0 []int32, v1 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x8Slice(v0)
+	vec1 := simd.LoadInt32x8Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt32x8()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt32x8()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt32x8()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt32x8()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt32x8()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt32x8()
+
+	default:
+		t.Errorf("Unknown method: Int32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x8Mask32x8Int32x8(t *testing.T, v0 []int32, v1 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x8Slice(v0)
+	vec1 := simd.LoadInt32x8Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask32x8())
+
+	default:
+		t.Errorf("Unknown method: Int32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x8MaskedCompare(t *testing.T, v0 []int32, v1 []int32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x8Slice(v0)
+	vec1 := simd.LoadInt32x8Slice(v1)
+	vec2 := simd.LoadInt32x8Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+
+	default:
+		t.Errorf("Unknown method: Int32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x8Ternary(t *testing.T, v0 []int32, v1 []int32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x8Slice(v0)
+	vec1 := simd.LoadInt32x8Slice(v1)
+	vec2 := simd.LoadInt32x8Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Int32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x8TernaryMasked(t *testing.T, v0 []int32, v1 []int32, v2 []int32, v3 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x8Slice(v0)
+	vec1 := simd.LoadInt32x8Slice(v1)
+	vec2 := simd.LoadInt32x8Slice(v2)
+	vec3 := simd.LoadInt32x8Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask32x8())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask32x8())
+
+	default:
+		t.Errorf("Unknown method: Int32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x8Unary(t *testing.T, v0 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x8Slice(v0)
+	switch which {
+	case "Absolute":
+		gotv = vec0.Absolute()
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Int32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x8UnaryMasked(t *testing.T, v0 []int32, v1 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x8Slice(v0)
+	vec1 := simd.LoadInt32x8Slice(v1)
+	switch which {
+	case "AbsoluteMasked":
+		gotv = vec0.AbsoluteMasked(vec1.AsMask32x8())
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask32x8())
+
+	default:
+		t.Errorf("Unknown method: Int32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x16Binary(t *testing.T, v0 []int32, v1 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x16Slice(v0)
+	vec1 := simd.LoadInt32x16Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulLow":
+		gotv = vec0.MulLow(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "RotateLeft":
+		gotv = vec0.RotateLeft(vec1)
+	case "RotateRight":
+		gotv = vec0.RotateRight(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x16BinaryMasked(t *testing.T, v0 []int32, v1 []int32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x16Slice(v0)
+	vec1 := simd.LoadInt32x16Slice(v1)
+	vec2 := simd.LoadInt32x16Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask32x16())
+	case "AndMasked":
+		gotv = vec0.AndMasked(vec1, vec2.AsMask32x16())
+	case "AndNotMasked":
+		gotv = vec0.AndNotMasked(vec1, vec2.AsMask32x16())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask32x16())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask32x16())
+	case "MulLowMasked":
+		gotv = vec0.MulLowMasked(vec1, vec2.AsMask32x16())
+	case "OrMasked":
+		gotv = vec0.OrMasked(vec1, vec2.AsMask32x16())
+	case "RotateLeftMasked":
+		gotv = vec0.RotateLeftMasked(vec1, vec2.AsMask32x16())
+	case "RotateRightMasked":
+		gotv = vec0.RotateRightMasked(vec1, vec2.AsMask32x16())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask32x16())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask32x16())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask32x16())
+	case "XorMasked":
+		gotv = vec0.XorMasked(vec1, vec2.AsMask32x16())
+
+	default:
+		t.Errorf("Unknown method: Int32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x16Compare(t *testing.T, v0 []int32, v1 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x16Slice(v0)
+	vec1 := simd.LoadInt32x16Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt32x16()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt32x16()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt32x16()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt32x16()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt32x16()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt32x16()
+
+	default:
+		t.Errorf("Unknown method: Int32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x16Mask32x16Int32x16(t *testing.T, v0 []int32, v1 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x16Slice(v0)
+	vec1 := simd.LoadInt32x16Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask32x16())
+
+	default:
+		t.Errorf("Unknown method: Int32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x16MaskedCompare(t *testing.T, v0 []int32, v1 []int32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x16Slice(v0)
+	vec1 := simd.LoadInt32x16Slice(v1)
+	vec2 := simd.LoadInt32x16Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+
+	default:
+		t.Errorf("Unknown method: Int32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x16Ternary(t *testing.T, v0 []int32, v1 []int32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x16Slice(v0)
+	vec1 := simd.LoadInt32x16Slice(v1)
+	vec2 := simd.LoadInt32x16Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Int32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x16TernaryMasked(t *testing.T, v0 []int32, v1 []int32, v2 []int32, v3 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x16Slice(v0)
+	vec1 := simd.LoadInt32x16Slice(v1)
+	vec2 := simd.LoadInt32x16Slice(v2)
+	vec3 := simd.LoadInt32x16Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask32x16())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask32x16())
+
+	default:
+		t.Errorf("Unknown method: Int32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x16Unary(t *testing.T, v0 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x16Slice(v0)
+	switch which {
+	case "Absolute":
+		gotv = vec0.Absolute()
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Int32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt32x16UnaryMasked(t *testing.T, v0 []int32, v1 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadInt32x16Slice(v0)
+	vec1 := simd.LoadInt32x16Slice(v1)
+	switch which {
+	case "AbsoluteMasked":
+		gotv = vec0.AbsoluteMasked(vec1.AsMask32x16())
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask32x16())
+
+	default:
+		t.Errorf("Unknown method: Int32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x2Binary(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x2Slice(v0)
+	vec1 := simd.LoadInt64x2Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulEvenWiden":
+		gotv = vec0.MulEvenWiden(vec1)
+	case "MulLow":
+		gotv = vec0.MulLow(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "RotateLeft":
+		gotv = vec0.RotateLeft(vec1)
+	case "RotateRight":
+		gotv = vec0.RotateRight(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x2BinaryMasked(t *testing.T, v0 []int64, v1 []int64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x2Slice(v0)
+	vec1 := simd.LoadInt64x2Slice(v1)
+	vec2 := simd.LoadInt64x2Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask64x2())
+	case "AndMasked":
+		gotv = vec0.AndMasked(vec1, vec2.AsMask64x2())
+	case "AndNotMasked":
+		gotv = vec0.AndNotMasked(vec1, vec2.AsMask64x2())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask64x2())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask64x2())
+	case "MulEvenWidenMasked":
+		gotv = vec0.MulEvenWidenMasked(vec1, vec2.AsMask64x2())
+	case "MulLowMasked":
+		gotv = vec0.MulLowMasked(vec1, vec2.AsMask64x2())
+	case "OrMasked":
+		gotv = vec0.OrMasked(vec1, vec2.AsMask64x2())
+	case "RotateLeftMasked":
+		gotv = vec0.RotateLeftMasked(vec1, vec2.AsMask64x2())
+	case "RotateRightMasked":
+		gotv = vec0.RotateRightMasked(vec1, vec2.AsMask64x2())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask64x2())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask64x2())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask64x2())
+	case "XorMasked":
+		gotv = vec0.XorMasked(vec1, vec2.AsMask64x2())
+
+	default:
+		t.Errorf("Unknown method: Int64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x2Compare(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x2Slice(v0)
+	vec1 := simd.LoadInt64x2Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt64x2()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt64x2()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt64x2()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt64x2()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt64x2()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt64x2()
+
+	default:
+		t.Errorf("Unknown method: Int64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x2Mask64x2Int64x2(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x2Slice(v0)
+	vec1 := simd.LoadInt64x2Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask64x2())
+
+	default:
+		t.Errorf("Unknown method: Int64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x2MaskedCompare(t *testing.T, v0 []int64, v1 []int64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x2Slice(v0)
+	vec1 := simd.LoadInt64x2Slice(v1)
+	vec2 := simd.LoadInt64x2Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+
+	default:
+		t.Errorf("Unknown method: Int64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x2Ternary(t *testing.T, v0 []int64, v1 []int64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x2Slice(v0)
+	vec1 := simd.LoadInt64x2Slice(v1)
+	vec2 := simd.LoadInt64x2Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Int64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x2TernaryMasked(t *testing.T, v0 []int64, v1 []int64, v2 []int64, v3 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x2Slice(v0)
+	vec1 := simd.LoadInt64x2Slice(v1)
+	vec2 := simd.LoadInt64x2Slice(v2)
+	vec3 := simd.LoadInt64x2Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask64x2())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask64x2())
+
+	default:
+		t.Errorf("Unknown method: Int64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x2Unary(t *testing.T, v0 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x2Slice(v0)
+	switch which {
+	case "Absolute":
+		gotv = vec0.Absolute()
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Int64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x2UnaryMasked(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x2Slice(v0)
+	vec1 := simd.LoadInt64x2Slice(v1)
+	switch which {
+	case "AbsoluteMasked":
+		gotv = vec0.AbsoluteMasked(vec1.AsMask64x2())
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask64x2())
+
+	default:
+		t.Errorf("Unknown method: Int64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x4Binary(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x4Slice(v0)
+	vec1 := simd.LoadInt64x4Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulEvenWiden":
+		gotv = vec0.MulEvenWiden(vec1)
+	case "MulLow":
+		gotv = vec0.MulLow(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "RotateLeft":
+		gotv = vec0.RotateLeft(vec1)
+	case "RotateRight":
+		gotv = vec0.RotateRight(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x4BinaryMasked(t *testing.T, v0 []int64, v1 []int64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x4Slice(v0)
+	vec1 := simd.LoadInt64x4Slice(v1)
+	vec2 := simd.LoadInt64x4Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask64x4())
+	case "AndMasked":
+		gotv = vec0.AndMasked(vec1, vec2.AsMask64x4())
+	case "AndNotMasked":
+		gotv = vec0.AndNotMasked(vec1, vec2.AsMask64x4())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask64x4())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask64x4())
+	case "MulEvenWidenMasked":
+		gotv = vec0.MulEvenWidenMasked(vec1, vec2.AsMask64x4())
+	case "MulLowMasked":
+		gotv = vec0.MulLowMasked(vec1, vec2.AsMask64x4())
+	case "OrMasked":
+		gotv = vec0.OrMasked(vec1, vec2.AsMask64x4())
+	case "RotateLeftMasked":
+		gotv = vec0.RotateLeftMasked(vec1, vec2.AsMask64x4())
+	case "RotateRightMasked":
+		gotv = vec0.RotateRightMasked(vec1, vec2.AsMask64x4())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask64x4())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask64x4())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask64x4())
+	case "XorMasked":
+		gotv = vec0.XorMasked(vec1, vec2.AsMask64x4())
+
+	default:
+		t.Errorf("Unknown method: Int64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x4Compare(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x4Slice(v0)
+	vec1 := simd.LoadInt64x4Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt64x4()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt64x4()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt64x4()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt64x4()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt64x4()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt64x4()
+
+	default:
+		t.Errorf("Unknown method: Int64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x4Mask64x4Int64x4(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x4Slice(v0)
+	vec1 := simd.LoadInt64x4Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask64x4())
+
+	default:
+		t.Errorf("Unknown method: Int64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x4MaskedCompare(t *testing.T, v0 []int64, v1 []int64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x4Slice(v0)
+	vec1 := simd.LoadInt64x4Slice(v1)
+	vec2 := simd.LoadInt64x4Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+
+	default:
+		t.Errorf("Unknown method: Int64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x4Ternary(t *testing.T, v0 []int64, v1 []int64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x4Slice(v0)
+	vec1 := simd.LoadInt64x4Slice(v1)
+	vec2 := simd.LoadInt64x4Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Int64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x4TernaryMasked(t *testing.T, v0 []int64, v1 []int64, v2 []int64, v3 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x4Slice(v0)
+	vec1 := simd.LoadInt64x4Slice(v1)
+	vec2 := simd.LoadInt64x4Slice(v2)
+	vec3 := simd.LoadInt64x4Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask64x4())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask64x4())
+
+	default:
+		t.Errorf("Unknown method: Int64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x4Unary(t *testing.T, v0 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x4Slice(v0)
+	switch which {
+	case "Absolute":
+		gotv = vec0.Absolute()
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Int64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x4UnaryMasked(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x4Slice(v0)
+	vec1 := simd.LoadInt64x4Slice(v1)
+	switch which {
+	case "AbsoluteMasked":
+		gotv = vec0.AbsoluteMasked(vec1.AsMask64x4())
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask64x4())
+
+	default:
+		t.Errorf("Unknown method: Int64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x8Binary(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x8
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x8Slice(v0)
+	vec1 := simd.LoadInt64x8Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulEvenWiden":
+		gotv = vec0.MulEvenWiden(vec1)
+	case "MulLow":
+		gotv = vec0.MulLow(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "RotateLeft":
+		gotv = vec0.RotateLeft(vec1)
+	case "RotateRight":
+		gotv = vec0.RotateRight(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Int64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x8BinaryMasked(t *testing.T, v0 []int64, v1 []int64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x8
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x8Slice(v0)
+	vec1 := simd.LoadInt64x8Slice(v1)
+	vec2 := simd.LoadInt64x8Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask64x8())
+	case "AndMasked":
+		gotv = vec0.AndMasked(vec1, vec2.AsMask64x8())
+	case "AndNotMasked":
+		gotv = vec0.AndNotMasked(vec1, vec2.AsMask64x8())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask64x8())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask64x8())
+	case "MulEvenWidenMasked":
+		gotv = vec0.MulEvenWidenMasked(vec1, vec2.AsMask64x8())
+	case "MulLowMasked":
+		gotv = vec0.MulLowMasked(vec1, vec2.AsMask64x8())
+	case "OrMasked":
+		gotv = vec0.OrMasked(vec1, vec2.AsMask64x8())
+	case "RotateLeftMasked":
+		gotv = vec0.RotateLeftMasked(vec1, vec2.AsMask64x8())
+	case "RotateRightMasked":
+		gotv = vec0.RotateRightMasked(vec1, vec2.AsMask64x8())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask64x8())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask64x8())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask64x8())
+	case "XorMasked":
+		gotv = vec0.XorMasked(vec1, vec2.AsMask64x8())
+
+	default:
+		t.Errorf("Unknown method: Int64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x8Compare(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x8
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x8Slice(v0)
+	vec1 := simd.LoadInt64x8Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt64x8()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt64x8()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt64x8()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt64x8()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt64x8()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt64x8()
+
+	default:
+		t.Errorf("Unknown method: Int64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x8Mask64x8Int64x8(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x8
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x8Slice(v0)
+	vec1 := simd.LoadInt64x8Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask64x8())
+
+	default:
+		t.Errorf("Unknown method: Int64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x8MaskedCompare(t *testing.T, v0 []int64, v1 []int64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x8
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x8Slice(v0)
+	vec1 := simd.LoadInt64x8Slice(v1)
+	vec2 := simd.LoadInt64x8Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+
+	default:
+		t.Errorf("Unknown method: Int64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x8Ternary(t *testing.T, v0 []int64, v1 []int64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x8
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x8Slice(v0)
+	vec1 := simd.LoadInt64x8Slice(v1)
+	vec2 := simd.LoadInt64x8Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Int64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x8TernaryMasked(t *testing.T, v0 []int64, v1 []int64, v2 []int64, v3 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x8
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x8Slice(v0)
+	vec1 := simd.LoadInt64x8Slice(v1)
+	vec2 := simd.LoadInt64x8Slice(v2)
+	vec3 := simd.LoadInt64x8Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask64x8())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask64x8())
+
+	default:
+		t.Errorf("Unknown method: Int64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x8Unary(t *testing.T, v0 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x8
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x8Slice(v0)
+	switch which {
+	case "Absolute":
+		gotv = vec0.Absolute()
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Int64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testInt64x8UnaryMasked(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x8
+	got := make([]int64, len(want))
+	vec0 := simd.LoadInt64x8Slice(v0)
+	vec1 := simd.LoadInt64x8Slice(v1)
+	switch which {
+	case "AbsoluteMasked":
+		gotv = vec0.AbsoluteMasked(vec1.AsMask64x8())
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask64x8())
+
+	default:
+		t.Errorf("Unknown method: Int64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x16Binary(t *testing.T, v0 []uint8, v1 []uint8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x16
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x16Slice(v0)
+	vec1 := simd.LoadUint8x16Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Average":
+		gotv = vec0.Average(vec1)
+	case "GaloisFieldMul":
+		gotv = vec0.GaloisFieldMul(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "SaturatedAdd":
+		gotv = vec0.SaturatedAdd(vec1)
+	case "SaturatedSub":
+		gotv = vec0.SaturatedSub(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x16BinaryMasked(t *testing.T, v0 []uint8, v1 []uint8, v2 []int8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x16
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x16Slice(v0)
+	vec1 := simd.LoadUint8x16Slice(v1)
+	vec2 := simd.LoadInt8x16Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask8x16())
+	case "AverageMasked":
+		gotv = vec0.AverageMasked(vec1, vec2.AsMask8x16())
+	case "GaloisFieldMulMasked":
+		gotv = vec0.GaloisFieldMulMasked(vec1, vec2.AsMask8x16())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask8x16())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask8x16())
+	case "SaturatedAddMasked":
+		gotv = vec0.SaturatedAddMasked(vec1, vec2.AsMask8x16())
+	case "SaturatedSubMasked":
+		gotv = vec0.SaturatedSubMasked(vec1, vec2.AsMask8x16())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask8x16())
+
+	default:
+		t.Errorf("Unknown method: Uint8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x16Compare(t *testing.T, v0 []uint8, v1 []uint8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x16
+	got := make([]int8, len(want))
+	vec0 := simd.LoadUint8x16Slice(v0)
+	vec1 := simd.LoadUint8x16Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt8x16()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt8x16()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt8x16()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt8x16()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt8x16()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt8x16()
+
+	default:
+		t.Errorf("Unknown method: Uint8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x16Int8x16Int16x8(t *testing.T, v0 []uint8, v1 []int8, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x8
+	got := make([]int16, len(want))
+	vec0 := simd.LoadUint8x16Slice(v0)
+	vec1 := simd.LoadInt8x16Slice(v1)
+	switch which {
+	case "SaturatedUnsignedSignedPairDotProd":
+		gotv = vec0.SaturatedUnsignedSignedPairDotProd(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x16Int8x16Mask16x8Int16x8(t *testing.T, v0 []uint8, v1 []int8, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x8
+	got := make([]int16, len(want))
+	vec0 := simd.LoadUint8x16Slice(v0)
+	vec1 := simd.LoadInt8x16Slice(v1)
+	vec2 := simd.LoadInt16x8Slice(v2)
+	switch which {
+	case "SaturatedUnsignedSignedPairDotProdMasked":
+		gotv = vec0.SaturatedUnsignedSignedPairDotProdMasked(vec1, vec2.AsMask16x8())
+
+	default:
+		t.Errorf("Unknown method: Uint8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x16Mask8x16Uint8x16(t *testing.T, v0 []uint8, v1 []int8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x16
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x16Slice(v0)
+	vec1 := simd.LoadInt8x16Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask8x16())
+
+	default:
+		t.Errorf("Unknown method: Uint8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x16MaskedCompare(t *testing.T, v0 []uint8, v1 []uint8, v2 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x16
+	got := make([]int8, len(want))
+	vec0 := simd.LoadUint8x16Slice(v0)
+	vec1 := simd.LoadUint8x16Slice(v1)
+	vec2 := simd.LoadInt8x16Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask8x16()).AsInt8x16()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask8x16()).AsInt8x16()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask8x16()).AsInt8x16()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask8x16()).AsInt8x16()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask8x16()).AsInt8x16()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask8x16()).AsInt8x16()
+
+	default:
+		t.Errorf("Unknown method: Uint8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x16Unary(t *testing.T, v0 []uint8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x16
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x16Slice(v0)
+	switch which {
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Uint8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x16UnaryMasked(t *testing.T, v0 []uint8, v1 []int8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x16
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x16Slice(v0)
+	vec1 := simd.LoadInt8x16Slice(v1)
+	switch which {
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask8x16())
+
+	default:
+		t.Errorf("Unknown method: Uint8x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x32Binary(t *testing.T, v0 []uint8, v1 []uint8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x32
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x32Slice(v0)
+	vec1 := simd.LoadUint8x32Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Average":
+		gotv = vec0.Average(vec1)
+	case "GaloisFieldMul":
+		gotv = vec0.GaloisFieldMul(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "SaturatedAdd":
+		gotv = vec0.SaturatedAdd(vec1)
+	case "SaturatedSub":
+		gotv = vec0.SaturatedSub(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x32BinaryMasked(t *testing.T, v0 []uint8, v1 []uint8, v2 []int8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x32
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x32Slice(v0)
+	vec1 := simd.LoadUint8x32Slice(v1)
+	vec2 := simd.LoadInt8x32Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask8x32())
+	case "AverageMasked":
+		gotv = vec0.AverageMasked(vec1, vec2.AsMask8x32())
+	case "GaloisFieldMulMasked":
+		gotv = vec0.GaloisFieldMulMasked(vec1, vec2.AsMask8x32())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask8x32())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask8x32())
+	case "SaturatedAddMasked":
+		gotv = vec0.SaturatedAddMasked(vec1, vec2.AsMask8x32())
+	case "SaturatedSubMasked":
+		gotv = vec0.SaturatedSubMasked(vec1, vec2.AsMask8x32())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask8x32())
+
+	default:
+		t.Errorf("Unknown method: Uint8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x32Compare(t *testing.T, v0 []uint8, v1 []uint8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x32
+	got := make([]int8, len(want))
+	vec0 := simd.LoadUint8x32Slice(v0)
+	vec1 := simd.LoadUint8x32Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt8x32()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt8x32()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt8x32()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt8x32()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt8x32()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt8x32()
+
+	default:
+		t.Errorf("Unknown method: Uint8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x32Int8x32Int16x16(t *testing.T, v0 []uint8, v1 []int8, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x16
+	got := make([]int16, len(want))
+	vec0 := simd.LoadUint8x32Slice(v0)
+	vec1 := simd.LoadInt8x32Slice(v1)
+	switch which {
+	case "SaturatedUnsignedSignedPairDotProd":
+		gotv = vec0.SaturatedUnsignedSignedPairDotProd(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x32Int8x32Mask16x16Int16x16(t *testing.T, v0 []uint8, v1 []int8, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x16
+	got := make([]int16, len(want))
+	vec0 := simd.LoadUint8x32Slice(v0)
+	vec1 := simd.LoadInt8x32Slice(v1)
+	vec2 := simd.LoadInt16x16Slice(v2)
+	switch which {
+	case "SaturatedUnsignedSignedPairDotProdMasked":
+		gotv = vec0.SaturatedUnsignedSignedPairDotProdMasked(vec1, vec2.AsMask16x16())
+
+	default:
+		t.Errorf("Unknown method: Uint8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x32Mask8x32Uint8x32(t *testing.T, v0 []uint8, v1 []int8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x32
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x32Slice(v0)
+	vec1 := simd.LoadInt8x32Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask8x32())
+
+	default:
+		t.Errorf("Unknown method: Uint8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x32MaskedCompare(t *testing.T, v0 []uint8, v1 []uint8, v2 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x32
+	got := make([]int8, len(want))
+	vec0 := simd.LoadUint8x32Slice(v0)
+	vec1 := simd.LoadUint8x32Slice(v1)
+	vec2 := simd.LoadInt8x32Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask8x32()).AsInt8x32()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask8x32()).AsInt8x32()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask8x32()).AsInt8x32()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask8x32()).AsInt8x32()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask8x32()).AsInt8x32()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask8x32()).AsInt8x32()
+
+	default:
+		t.Errorf("Unknown method: Uint8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x32Unary(t *testing.T, v0 []uint8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x32
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x32Slice(v0)
+	switch which {
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Uint8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x32UnaryMasked(t *testing.T, v0 []uint8, v1 []int8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x32
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x32Slice(v0)
+	vec1 := simd.LoadInt8x32Slice(v1)
+	switch which {
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask8x32())
+
+	default:
+		t.Errorf("Unknown method: Uint8x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x64Binary(t *testing.T, v0 []uint8, v1 []uint8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x64
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x64Slice(v0)
+	vec1 := simd.LoadUint8x64Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "Average":
+		gotv = vec0.Average(vec1)
+	case "GaloisFieldMul":
+		gotv = vec0.GaloisFieldMul(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "SaturatedAdd":
+		gotv = vec0.SaturatedAdd(vec1)
+	case "SaturatedSub":
+		gotv = vec0.SaturatedSub(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x64BinaryMasked(t *testing.T, v0 []uint8, v1 []uint8, v2 []int8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x64
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x64Slice(v0)
+	vec1 := simd.LoadUint8x64Slice(v1)
+	vec2 := simd.LoadInt8x64Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask8x64())
+	case "AverageMasked":
+		gotv = vec0.AverageMasked(vec1, vec2.AsMask8x64())
+	case "GaloisFieldMulMasked":
+		gotv = vec0.GaloisFieldMulMasked(vec1, vec2.AsMask8x64())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask8x64())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask8x64())
+	case "SaturatedAddMasked":
+		gotv = vec0.SaturatedAddMasked(vec1, vec2.AsMask8x64())
+	case "SaturatedSubMasked":
+		gotv = vec0.SaturatedSubMasked(vec1, vec2.AsMask8x64())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask8x64())
+
+	default:
+		t.Errorf("Unknown method: Uint8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x64Compare(t *testing.T, v0 []uint8, v1 []uint8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x64
+	got := make([]int8, len(want))
+	vec0 := simd.LoadUint8x64Slice(v0)
+	vec1 := simd.LoadUint8x64Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt8x64()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt8x64()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt8x64()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt8x64()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt8x64()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt8x64()
+
+	default:
+		t.Errorf("Unknown method: Uint8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x64Int8x64Int16x32(t *testing.T, v0 []uint8, v1 []int8, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x32
+	got := make([]int16, len(want))
+	vec0 := simd.LoadUint8x64Slice(v0)
+	vec1 := simd.LoadInt8x64Slice(v1)
+	switch which {
+	case "SaturatedUnsignedSignedPairDotProd":
+		gotv = vec0.SaturatedUnsignedSignedPairDotProd(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x64Int8x64Mask16x32Int16x32(t *testing.T, v0 []uint8, v1 []int8, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x32
+	got := make([]int16, len(want))
+	vec0 := simd.LoadUint8x64Slice(v0)
+	vec1 := simd.LoadInt8x64Slice(v1)
+	vec2 := simd.LoadInt16x32Slice(v2)
+	switch which {
+	case "SaturatedUnsignedSignedPairDotProdMasked":
+		gotv = vec0.SaturatedUnsignedSignedPairDotProdMasked(vec1, vec2.AsMask16x32())
+
+	default:
+		t.Errorf("Unknown method: Uint8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x64Mask8x64Uint8x64(t *testing.T, v0 []uint8, v1 []int8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x64
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x64Slice(v0)
+	vec1 := simd.LoadInt8x64Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask8x64())
+
+	default:
+		t.Errorf("Unknown method: Uint8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x64MaskedCompare(t *testing.T, v0 []uint8, v1 []uint8, v2 []int8, want []int8, which string) {
+	t.Helper()
+	var gotv simd.Int8x64
+	got := make([]int8, len(want))
+	vec0 := simd.LoadUint8x64Slice(v0)
+	vec1 := simd.LoadUint8x64Slice(v1)
+	vec2 := simd.LoadInt8x64Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask8x64()).AsInt8x64()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask8x64()).AsInt8x64()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask8x64()).AsInt8x64()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask8x64()).AsInt8x64()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask8x64()).AsInt8x64()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask8x64()).AsInt8x64()
+
+	default:
+		t.Errorf("Unknown method: Uint8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x64Unary(t *testing.T, v0 []uint8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x64
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x64Slice(v0)
+	switch which {
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Uint8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint8x64UnaryMasked(t *testing.T, v0 []uint8, v1 []int8, want []uint8, which string) {
+	t.Helper()
+	var gotv simd.Uint8x64
+	got := make([]uint8, len(want))
+	vec0 := simd.LoadUint8x64Slice(v0)
+	vec1 := simd.LoadInt8x64Slice(v1)
+	switch which {
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask8x64())
+
+	default:
+		t.Errorf("Unknown method: Uint8x64.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x8Binary(t *testing.T, v0 []uint16, v1 []uint16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x8
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x8Slice(v0)
+	vec1 := simd.LoadUint16x8Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Average":
+		gotv = vec0.Average(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulHigh":
+		gotv = vec0.MulHigh(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "PairwiseAdd":
+		gotv = vec0.PairwiseAdd(vec1)
+	case "PairwiseSub":
+		gotv = vec0.PairwiseSub(vec1)
+	case "SaturatedAdd":
+		gotv = vec0.SaturatedAdd(vec1)
+	case "SaturatedSub":
+		gotv = vec0.SaturatedSub(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x8BinaryMasked(t *testing.T, v0 []uint16, v1 []uint16, v2 []int16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x8
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x8Slice(v0)
+	vec1 := simd.LoadUint16x8Slice(v1)
+	vec2 := simd.LoadInt16x8Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask16x8())
+	case "AverageMasked":
+		gotv = vec0.AverageMasked(vec1, vec2.AsMask16x8())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask16x8())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask16x8())
+	case "MulHighMasked":
+		gotv = vec0.MulHighMasked(vec1, vec2.AsMask16x8())
+	case "SaturatedAddMasked":
+		gotv = vec0.SaturatedAddMasked(vec1, vec2.AsMask16x8())
+	case "SaturatedSubMasked":
+		gotv = vec0.SaturatedSubMasked(vec1, vec2.AsMask16x8())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask16x8())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask16x8())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask16x8())
+
+	default:
+		t.Errorf("Unknown method: Uint16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x8Compare(t *testing.T, v0 []uint16, v1 []uint16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x8
+	got := make([]int16, len(want))
+	vec0 := simd.LoadUint16x8Slice(v0)
+	vec1 := simd.LoadUint16x8Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt16x8()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt16x8()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt16x8()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt16x8()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt16x8()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt16x8()
+
+	default:
+		t.Errorf("Unknown method: Uint16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x8Mask16x8Uint16x8(t *testing.T, v0 []uint16, v1 []int16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x8
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x8Slice(v0)
+	vec1 := simd.LoadInt16x8Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask16x8())
+
+	default:
+		t.Errorf("Unknown method: Uint16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x8MaskedCompare(t *testing.T, v0 []uint16, v1 []uint16, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x8
+	got := make([]int16, len(want))
+	vec0 := simd.LoadUint16x8Slice(v0)
+	vec1 := simd.LoadUint16x8Slice(v1)
+	vec2 := simd.LoadInt16x8Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask16x8()).AsInt16x8()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask16x8()).AsInt16x8()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask16x8()).AsInt16x8()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask16x8()).AsInt16x8()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask16x8()).AsInt16x8()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask16x8()).AsInt16x8()
+
+	default:
+		t.Errorf("Unknown method: Uint16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x8Ternary(t *testing.T, v0 []uint16, v1 []uint16, v2 []uint16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x8
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x8Slice(v0)
+	vec1 := simd.LoadUint16x8Slice(v1)
+	vec2 := simd.LoadUint16x8Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Uint16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x8TernaryMasked(t *testing.T, v0 []uint16, v1 []uint16, v2 []uint16, v3 []int16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x8
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x8Slice(v0)
+	vec1 := simd.LoadUint16x8Slice(v1)
+	vec2 := simd.LoadUint16x8Slice(v2)
+	vec3 := simd.LoadInt16x8Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask16x8())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask16x8())
+
+	default:
+		t.Errorf("Unknown method: Uint16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x8Unary(t *testing.T, v0 []uint16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x8
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x8Slice(v0)
+	switch which {
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Uint16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x8UnaryMasked(t *testing.T, v0 []uint16, v1 []int16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x8
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x8Slice(v0)
+	vec1 := simd.LoadInt16x8Slice(v1)
+	switch which {
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask16x8())
+
+	default:
+		t.Errorf("Unknown method: Uint16x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x16Binary(t *testing.T, v0 []uint16, v1 []uint16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x16
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x16Slice(v0)
+	vec1 := simd.LoadUint16x16Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Average":
+		gotv = vec0.Average(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulHigh":
+		gotv = vec0.MulHigh(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "PairwiseAdd":
+		gotv = vec0.PairwiseAdd(vec1)
+	case "PairwiseSub":
+		gotv = vec0.PairwiseSub(vec1)
+	case "SaturatedAdd":
+		gotv = vec0.SaturatedAdd(vec1)
+	case "SaturatedSub":
+		gotv = vec0.SaturatedSub(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x16BinaryMasked(t *testing.T, v0 []uint16, v1 []uint16, v2 []int16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x16
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x16Slice(v0)
+	vec1 := simd.LoadUint16x16Slice(v1)
+	vec2 := simd.LoadInt16x16Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask16x16())
+	case "AverageMasked":
+		gotv = vec0.AverageMasked(vec1, vec2.AsMask16x16())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask16x16())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask16x16())
+	case "MulHighMasked":
+		gotv = vec0.MulHighMasked(vec1, vec2.AsMask16x16())
+	case "SaturatedAddMasked":
+		gotv = vec0.SaturatedAddMasked(vec1, vec2.AsMask16x16())
+	case "SaturatedSubMasked":
+		gotv = vec0.SaturatedSubMasked(vec1, vec2.AsMask16x16())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask16x16())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask16x16())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask16x16())
+
+	default:
+		t.Errorf("Unknown method: Uint16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x16Compare(t *testing.T, v0 []uint16, v1 []uint16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x16
+	got := make([]int16, len(want))
+	vec0 := simd.LoadUint16x16Slice(v0)
+	vec1 := simd.LoadUint16x16Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt16x16()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt16x16()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt16x16()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt16x16()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt16x16()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt16x16()
+
+	default:
+		t.Errorf("Unknown method: Uint16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x16Mask16x16Uint16x16(t *testing.T, v0 []uint16, v1 []int16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x16
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x16Slice(v0)
+	vec1 := simd.LoadInt16x16Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask16x16())
+
+	default:
+		t.Errorf("Unknown method: Uint16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x16MaskedCompare(t *testing.T, v0 []uint16, v1 []uint16, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x16
+	got := make([]int16, len(want))
+	vec0 := simd.LoadUint16x16Slice(v0)
+	vec1 := simd.LoadUint16x16Slice(v1)
+	vec2 := simd.LoadInt16x16Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask16x16()).AsInt16x16()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask16x16()).AsInt16x16()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask16x16()).AsInt16x16()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask16x16()).AsInt16x16()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask16x16()).AsInt16x16()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask16x16()).AsInt16x16()
+
+	default:
+		t.Errorf("Unknown method: Uint16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x16Ternary(t *testing.T, v0 []uint16, v1 []uint16, v2 []uint16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x16
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x16Slice(v0)
+	vec1 := simd.LoadUint16x16Slice(v1)
+	vec2 := simd.LoadUint16x16Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Uint16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x16TernaryMasked(t *testing.T, v0 []uint16, v1 []uint16, v2 []uint16, v3 []int16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x16
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x16Slice(v0)
+	vec1 := simd.LoadUint16x16Slice(v1)
+	vec2 := simd.LoadUint16x16Slice(v2)
+	vec3 := simd.LoadInt16x16Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask16x16())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask16x16())
+
+	default:
+		t.Errorf("Unknown method: Uint16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x16Unary(t *testing.T, v0 []uint16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x16
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x16Slice(v0)
+	switch which {
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Uint16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x16UnaryMasked(t *testing.T, v0 []uint16, v1 []int16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x16
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x16Slice(v0)
+	vec1 := simd.LoadInt16x16Slice(v1)
+	switch which {
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask16x16())
+
+	default:
+		t.Errorf("Unknown method: Uint16x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x32Binary(t *testing.T, v0 []uint16, v1 []uint16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x32
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x32Slice(v0)
+	vec1 := simd.LoadUint16x32Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "Average":
+		gotv = vec0.Average(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulHigh":
+		gotv = vec0.MulHigh(vec1)
+	case "SaturatedAdd":
+		gotv = vec0.SaturatedAdd(vec1)
+	case "SaturatedSub":
+		gotv = vec0.SaturatedSub(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x32BinaryMasked(t *testing.T, v0 []uint16, v1 []uint16, v2 []int16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x32
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x32Slice(v0)
+	vec1 := simd.LoadUint16x32Slice(v1)
+	vec2 := simd.LoadInt16x32Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask16x32())
+	case "AverageMasked":
+		gotv = vec0.AverageMasked(vec1, vec2.AsMask16x32())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask16x32())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask16x32())
+	case "MulHighMasked":
+		gotv = vec0.MulHighMasked(vec1, vec2.AsMask16x32())
+	case "SaturatedAddMasked":
+		gotv = vec0.SaturatedAddMasked(vec1, vec2.AsMask16x32())
+	case "SaturatedSubMasked":
+		gotv = vec0.SaturatedSubMasked(vec1, vec2.AsMask16x32())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask16x32())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask16x32())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask16x32())
+
+	default:
+		t.Errorf("Unknown method: Uint16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x32Compare(t *testing.T, v0 []uint16, v1 []uint16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x32
+	got := make([]int16, len(want))
+	vec0 := simd.LoadUint16x32Slice(v0)
+	vec1 := simd.LoadUint16x32Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt16x32()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt16x32()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt16x32()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt16x32()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt16x32()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt16x32()
+
+	default:
+		t.Errorf("Unknown method: Uint16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x32Mask16x32Uint16x32(t *testing.T, v0 []uint16, v1 []int16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x32
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x32Slice(v0)
+	vec1 := simd.LoadInt16x32Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask16x32())
+
+	default:
+		t.Errorf("Unknown method: Uint16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x32MaskedCompare(t *testing.T, v0 []uint16, v1 []uint16, v2 []int16, want []int16, which string) {
+	t.Helper()
+	var gotv simd.Int16x32
+	got := make([]int16, len(want))
+	vec0 := simd.LoadUint16x32Slice(v0)
+	vec1 := simd.LoadUint16x32Slice(v1)
+	vec2 := simd.LoadInt16x32Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask16x32()).AsInt16x32()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask16x32()).AsInt16x32()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask16x32()).AsInt16x32()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask16x32()).AsInt16x32()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask16x32()).AsInt16x32()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask16x32()).AsInt16x32()
+
+	default:
+		t.Errorf("Unknown method: Uint16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x32Ternary(t *testing.T, v0 []uint16, v1 []uint16, v2 []uint16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x32
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x32Slice(v0)
+	vec1 := simd.LoadUint16x32Slice(v1)
+	vec2 := simd.LoadUint16x32Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Uint16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x32TernaryMasked(t *testing.T, v0 []uint16, v1 []uint16, v2 []uint16, v3 []int16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x32
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x32Slice(v0)
+	vec1 := simd.LoadUint16x32Slice(v1)
+	vec2 := simd.LoadUint16x32Slice(v2)
+	vec3 := simd.LoadInt16x32Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask16x32())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask16x32())
+
+	default:
+		t.Errorf("Unknown method: Uint16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x32Unary(t *testing.T, v0 []uint16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x32
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x32Slice(v0)
+	switch which {
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Uint16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint16x32UnaryMasked(t *testing.T, v0 []uint16, v1 []int16, want []uint16, which string) {
+	t.Helper()
+	var gotv simd.Uint16x32
+	got := make([]uint16, len(want))
+	vec0 := simd.LoadUint16x32Slice(v0)
+	vec1 := simd.LoadInt16x32Slice(v1)
+	switch which {
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask16x32())
+
+	default:
+		t.Errorf("Unknown method: Uint16x32.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x4Binary(t *testing.T, v0 []uint32, v1 []uint32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x4
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x4Slice(v0)
+	vec1 := simd.LoadUint32x4Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "PairwiseAdd":
+		gotv = vec0.PairwiseAdd(vec1)
+	case "PairwiseSub":
+		gotv = vec0.PairwiseSub(vec1)
+	case "RotateLeft":
+		gotv = vec0.RotateLeft(vec1)
+	case "RotateRight":
+		gotv = vec0.RotateRight(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x4BinaryMasked(t *testing.T, v0 []uint32, v1 []uint32, v2 []int32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x4
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x4Slice(v0)
+	vec1 := simd.LoadUint32x4Slice(v1)
+	vec2 := simd.LoadInt32x4Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask32x4())
+	case "AndMasked":
+		gotv = vec0.AndMasked(vec1, vec2.AsMask32x4())
+	case "AndNotMasked":
+		gotv = vec0.AndNotMasked(vec1, vec2.AsMask32x4())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask32x4())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask32x4())
+	case "OrMasked":
+		gotv = vec0.OrMasked(vec1, vec2.AsMask32x4())
+	case "RotateLeftMasked":
+		gotv = vec0.RotateLeftMasked(vec1, vec2.AsMask32x4())
+	case "RotateRightMasked":
+		gotv = vec0.RotateRightMasked(vec1, vec2.AsMask32x4())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask32x4())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask32x4())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask32x4())
+	case "XorMasked":
+		gotv = vec0.XorMasked(vec1, vec2.AsMask32x4())
+
+	default:
+		t.Errorf("Unknown method: Uint32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x4BinaryWiden(t *testing.T, v0 []uint32, v1 []uint32, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x2
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint32x4Slice(v0)
+	vec1 := simd.LoadUint32x4Slice(v1)
+	switch which {
+	case "MulEvenWiden":
+		gotv = vec0.MulEvenWiden(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x4Compare(t *testing.T, v0 []uint32, v1 []uint32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadUint32x4Slice(v0)
+	vec1 := simd.LoadUint32x4Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt32x4()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt32x4()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt32x4()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt32x4()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt32x4()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt32x4()
+
+	default:
+		t.Errorf("Unknown method: Uint32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x4Mask32x4Uint32x4(t *testing.T, v0 []uint32, v1 []int32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x4
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x4Slice(v0)
+	vec1 := simd.LoadInt32x4Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask32x4())
+
+	default:
+		t.Errorf("Unknown method: Uint32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x4MaskedCompare(t *testing.T, v0 []uint32, v1 []uint32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x4
+	got := make([]int32, len(want))
+	vec0 := simd.LoadUint32x4Slice(v0)
+	vec1 := simd.LoadUint32x4Slice(v1)
+	vec2 := simd.LoadInt32x4Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask32x4()).AsInt32x4()
+
+	default:
+		t.Errorf("Unknown method: Uint32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x4Ternary(t *testing.T, v0 []uint32, v1 []uint32, v2 []uint32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x4
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x4Slice(v0)
+	vec1 := simd.LoadUint32x4Slice(v1)
+	vec2 := simd.LoadUint32x4Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Uint32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x4TernaryMasked(t *testing.T, v0 []uint32, v1 []uint32, v2 []uint32, v3 []int32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x4
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x4Slice(v0)
+	vec1 := simd.LoadUint32x4Slice(v1)
+	vec2 := simd.LoadUint32x4Slice(v2)
+	vec3 := simd.LoadInt32x4Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask32x4())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask32x4())
+
+	default:
+		t.Errorf("Unknown method: Uint32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x4Unary(t *testing.T, v0 []uint32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x4
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x4Slice(v0)
+	switch which {
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Uint32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x4UnaryMasked(t *testing.T, v0 []uint32, v1 []int32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x4
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x4Slice(v0)
+	vec1 := simd.LoadInt32x4Slice(v1)
+	switch which {
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask32x4())
+
+	default:
+		t.Errorf("Unknown method: Uint32x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x8Binary(t *testing.T, v0 []uint32, v1 []uint32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x8
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x8Slice(v0)
+	vec1 := simd.LoadUint32x8Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "PairwiseAdd":
+		gotv = vec0.PairwiseAdd(vec1)
+	case "PairwiseSub":
+		gotv = vec0.PairwiseSub(vec1)
+	case "RotateLeft":
+		gotv = vec0.RotateLeft(vec1)
+	case "RotateRight":
+		gotv = vec0.RotateRight(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x8BinaryMasked(t *testing.T, v0 []uint32, v1 []uint32, v2 []int32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x8
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x8Slice(v0)
+	vec1 := simd.LoadUint32x8Slice(v1)
+	vec2 := simd.LoadInt32x8Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask32x8())
+	case "AndMasked":
+		gotv = vec0.AndMasked(vec1, vec2.AsMask32x8())
+	case "AndNotMasked":
+		gotv = vec0.AndNotMasked(vec1, vec2.AsMask32x8())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask32x8())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask32x8())
+	case "OrMasked":
+		gotv = vec0.OrMasked(vec1, vec2.AsMask32x8())
+	case "RotateLeftMasked":
+		gotv = vec0.RotateLeftMasked(vec1, vec2.AsMask32x8())
+	case "RotateRightMasked":
+		gotv = vec0.RotateRightMasked(vec1, vec2.AsMask32x8())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask32x8())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask32x8())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask32x8())
+	case "XorMasked":
+		gotv = vec0.XorMasked(vec1, vec2.AsMask32x8())
+
+	default:
+		t.Errorf("Unknown method: Uint32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x8BinaryWiden(t *testing.T, v0 []uint32, v1 []uint32, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x4
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint32x8Slice(v0)
+	vec1 := simd.LoadUint32x8Slice(v1)
+	switch which {
+	case "MulEvenWiden":
+		gotv = vec0.MulEvenWiden(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x8Compare(t *testing.T, v0 []uint32, v1 []uint32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadUint32x8Slice(v0)
+	vec1 := simd.LoadUint32x8Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt32x8()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt32x8()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt32x8()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt32x8()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt32x8()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt32x8()
+
+	default:
+		t.Errorf("Unknown method: Uint32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x8Mask32x8Uint32x8(t *testing.T, v0 []uint32, v1 []int32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x8
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x8Slice(v0)
+	vec1 := simd.LoadInt32x8Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask32x8())
+
+	default:
+		t.Errorf("Unknown method: Uint32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x8MaskedCompare(t *testing.T, v0 []uint32, v1 []uint32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x8
+	got := make([]int32, len(want))
+	vec0 := simd.LoadUint32x8Slice(v0)
+	vec1 := simd.LoadUint32x8Slice(v1)
+	vec2 := simd.LoadInt32x8Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask32x8()).AsInt32x8()
+
+	default:
+		t.Errorf("Unknown method: Uint32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x8Ternary(t *testing.T, v0 []uint32, v1 []uint32, v2 []uint32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x8
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x8Slice(v0)
+	vec1 := simd.LoadUint32x8Slice(v1)
+	vec2 := simd.LoadUint32x8Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Uint32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x8TernaryMasked(t *testing.T, v0 []uint32, v1 []uint32, v2 []uint32, v3 []int32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x8
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x8Slice(v0)
+	vec1 := simd.LoadUint32x8Slice(v1)
+	vec2 := simd.LoadUint32x8Slice(v2)
+	vec3 := simd.LoadInt32x8Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask32x8())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask32x8())
+
+	default:
+		t.Errorf("Unknown method: Uint32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x8Unary(t *testing.T, v0 []uint32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x8
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x8Slice(v0)
+	switch which {
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Uint32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x8UnaryMasked(t *testing.T, v0 []uint32, v1 []int32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x8
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x8Slice(v0)
+	vec1 := simd.LoadInt32x8Slice(v1)
+	switch which {
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask32x8())
+
+	default:
+		t.Errorf("Unknown method: Uint32x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x16Binary(t *testing.T, v0 []uint32, v1 []uint32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x16
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x16Slice(v0)
+	vec1 := simd.LoadUint32x16Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "RotateLeft":
+		gotv = vec0.RotateLeft(vec1)
+	case "RotateRight":
+		gotv = vec0.RotateRight(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x16BinaryMasked(t *testing.T, v0 []uint32, v1 []uint32, v2 []int32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x16
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x16Slice(v0)
+	vec1 := simd.LoadUint32x16Slice(v1)
+	vec2 := simd.LoadInt32x16Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask32x16())
+	case "AndMasked":
+		gotv = vec0.AndMasked(vec1, vec2.AsMask32x16())
+	case "AndNotMasked":
+		gotv = vec0.AndNotMasked(vec1, vec2.AsMask32x16())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask32x16())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask32x16())
+	case "OrMasked":
+		gotv = vec0.OrMasked(vec1, vec2.AsMask32x16())
+	case "RotateLeftMasked":
+		gotv = vec0.RotateLeftMasked(vec1, vec2.AsMask32x16())
+	case "RotateRightMasked":
+		gotv = vec0.RotateRightMasked(vec1, vec2.AsMask32x16())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask32x16())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask32x16())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask32x16())
+	case "XorMasked":
+		gotv = vec0.XorMasked(vec1, vec2.AsMask32x16())
+
+	default:
+		t.Errorf("Unknown method: Uint32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x16Compare(t *testing.T, v0 []uint32, v1 []uint32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadUint32x16Slice(v0)
+	vec1 := simd.LoadUint32x16Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt32x16()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt32x16()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt32x16()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt32x16()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt32x16()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt32x16()
+
+	default:
+		t.Errorf("Unknown method: Uint32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x16Mask32x16Uint32x16(t *testing.T, v0 []uint32, v1 []int32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x16
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x16Slice(v0)
+	vec1 := simd.LoadInt32x16Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask32x16())
+
+	default:
+		t.Errorf("Unknown method: Uint32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x16MaskedCompare(t *testing.T, v0 []uint32, v1 []uint32, v2 []int32, want []int32, which string) {
+	t.Helper()
+	var gotv simd.Int32x16
+	got := make([]int32, len(want))
+	vec0 := simd.LoadUint32x16Slice(v0)
+	vec1 := simd.LoadUint32x16Slice(v1)
+	vec2 := simd.LoadInt32x16Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask32x16()).AsInt32x16()
+
+	default:
+		t.Errorf("Unknown method: Uint32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x16Ternary(t *testing.T, v0 []uint32, v1 []uint32, v2 []uint32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x16
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x16Slice(v0)
+	vec1 := simd.LoadUint32x16Slice(v1)
+	vec2 := simd.LoadUint32x16Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Uint32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x16TernaryMasked(t *testing.T, v0 []uint32, v1 []uint32, v2 []uint32, v3 []int32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x16
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x16Slice(v0)
+	vec1 := simd.LoadUint32x16Slice(v1)
+	vec2 := simd.LoadUint32x16Slice(v2)
+	vec3 := simd.LoadInt32x16Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask32x16())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask32x16())
+
+	default:
+		t.Errorf("Unknown method: Uint32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x16Unary(t *testing.T, v0 []uint32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x16
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x16Slice(v0)
+	switch which {
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Uint32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint32x16UnaryMasked(t *testing.T, v0 []uint32, v1 []int32, want []uint32, which string) {
+	t.Helper()
+	var gotv simd.Uint32x16
+	got := make([]uint32, len(want))
+	vec0 := simd.LoadUint32x16Slice(v0)
+	vec1 := simd.LoadInt32x16Slice(v1)
+	switch which {
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask32x16())
+
+	default:
+		t.Errorf("Unknown method: Uint32x16.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x2Binary(t *testing.T, v0 []uint64, v1 []uint64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x2
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x2Slice(v0)
+	vec1 := simd.LoadUint64x2Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulEvenWiden":
+		gotv = vec0.MulEvenWiden(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "RotateLeft":
+		gotv = vec0.RotateLeft(vec1)
+	case "RotateRight":
+		gotv = vec0.RotateRight(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x2BinaryMasked(t *testing.T, v0 []uint64, v1 []uint64, v2 []int64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x2
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x2Slice(v0)
+	vec1 := simd.LoadUint64x2Slice(v1)
+	vec2 := simd.LoadInt64x2Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask64x2())
+	case "AndMasked":
+		gotv = vec0.AndMasked(vec1, vec2.AsMask64x2())
+	case "AndNotMasked":
+		gotv = vec0.AndNotMasked(vec1, vec2.AsMask64x2())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask64x2())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask64x2())
+	case "MulEvenWidenMasked":
+		gotv = vec0.MulEvenWidenMasked(vec1, vec2.AsMask64x2())
+	case "OrMasked":
+		gotv = vec0.OrMasked(vec1, vec2.AsMask64x2())
+	case "RotateLeftMasked":
+		gotv = vec0.RotateLeftMasked(vec1, vec2.AsMask64x2())
+	case "RotateRightMasked":
+		gotv = vec0.RotateRightMasked(vec1, vec2.AsMask64x2())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask64x2())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask64x2())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask64x2())
+	case "XorMasked":
+		gotv = vec0.XorMasked(vec1, vec2.AsMask64x2())
+
+	default:
+		t.Errorf("Unknown method: Uint64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x2Compare(t *testing.T, v0 []uint64, v1 []uint64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadUint64x2Slice(v0)
+	vec1 := simd.LoadUint64x2Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt64x2()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt64x2()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt64x2()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt64x2()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt64x2()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt64x2()
+
+	default:
+		t.Errorf("Unknown method: Uint64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x2Mask64x2Uint64x2(t *testing.T, v0 []uint64, v1 []int64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x2
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x2Slice(v0)
+	vec1 := simd.LoadInt64x2Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask64x2())
+
+	default:
+		t.Errorf("Unknown method: Uint64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x2MaskedCompare(t *testing.T, v0 []uint64, v1 []uint64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x2
+	got := make([]int64, len(want))
+	vec0 := simd.LoadUint64x2Slice(v0)
+	vec1 := simd.LoadUint64x2Slice(v1)
+	vec2 := simd.LoadInt64x2Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask64x2()).AsInt64x2()
+
+	default:
+		t.Errorf("Unknown method: Uint64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x2Ternary(t *testing.T, v0 []uint64, v1 []uint64, v2 []uint64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x2
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x2Slice(v0)
+	vec1 := simd.LoadUint64x2Slice(v1)
+	vec2 := simd.LoadUint64x2Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Uint64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x2TernaryMasked(t *testing.T, v0 []uint64, v1 []uint64, v2 []uint64, v3 []int64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x2
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x2Slice(v0)
+	vec1 := simd.LoadUint64x2Slice(v1)
+	vec2 := simd.LoadUint64x2Slice(v2)
+	vec3 := simd.LoadInt64x2Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask64x2())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask64x2())
+
+	default:
+		t.Errorf("Unknown method: Uint64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x2Unary(t *testing.T, v0 []uint64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x2
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x2Slice(v0)
+	switch which {
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Uint64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x2UnaryMasked(t *testing.T, v0 []uint64, v1 []int64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x2
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x2Slice(v0)
+	vec1 := simd.LoadInt64x2Slice(v1)
+	switch which {
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask64x2())
+
+	default:
+		t.Errorf("Unknown method: Uint64x2.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x4Binary(t *testing.T, v0 []uint64, v1 []uint64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x4
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x4Slice(v0)
+	vec1 := simd.LoadUint64x4Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulEvenWiden":
+		gotv = vec0.MulEvenWiden(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "RotateLeft":
+		gotv = vec0.RotateLeft(vec1)
+	case "RotateRight":
+		gotv = vec0.RotateRight(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x4BinaryMasked(t *testing.T, v0 []uint64, v1 []uint64, v2 []int64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x4
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x4Slice(v0)
+	vec1 := simd.LoadUint64x4Slice(v1)
+	vec2 := simd.LoadInt64x4Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask64x4())
+	case "AndMasked":
+		gotv = vec0.AndMasked(vec1, vec2.AsMask64x4())
+	case "AndNotMasked":
+		gotv = vec0.AndNotMasked(vec1, vec2.AsMask64x4())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask64x4())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask64x4())
+	case "MulEvenWidenMasked":
+		gotv = vec0.MulEvenWidenMasked(vec1, vec2.AsMask64x4())
+	case "OrMasked":
+		gotv = vec0.OrMasked(vec1, vec2.AsMask64x4())
+	case "RotateLeftMasked":
+		gotv = vec0.RotateLeftMasked(vec1, vec2.AsMask64x4())
+	case "RotateRightMasked":
+		gotv = vec0.RotateRightMasked(vec1, vec2.AsMask64x4())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask64x4())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask64x4())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask64x4())
+	case "XorMasked":
+		gotv = vec0.XorMasked(vec1, vec2.AsMask64x4())
+
+	default:
+		t.Errorf("Unknown method: Uint64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x4Compare(t *testing.T, v0 []uint64, v1 []uint64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadUint64x4Slice(v0)
+	vec1 := simd.LoadUint64x4Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt64x4()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt64x4()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt64x4()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt64x4()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt64x4()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt64x4()
+
+	default:
+		t.Errorf("Unknown method: Uint64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x4Mask64x4Uint64x4(t *testing.T, v0 []uint64, v1 []int64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x4
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x4Slice(v0)
+	vec1 := simd.LoadInt64x4Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask64x4())
+
+	default:
+		t.Errorf("Unknown method: Uint64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x4MaskedCompare(t *testing.T, v0 []uint64, v1 []uint64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x4
+	got := make([]int64, len(want))
+	vec0 := simd.LoadUint64x4Slice(v0)
+	vec1 := simd.LoadUint64x4Slice(v1)
+	vec2 := simd.LoadInt64x4Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask64x4()).AsInt64x4()
+
+	default:
+		t.Errorf("Unknown method: Uint64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x4Ternary(t *testing.T, v0 []uint64, v1 []uint64, v2 []uint64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x4
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x4Slice(v0)
+	vec1 := simd.LoadUint64x4Slice(v1)
+	vec2 := simd.LoadUint64x4Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Uint64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x4TernaryMasked(t *testing.T, v0 []uint64, v1 []uint64, v2 []uint64, v3 []int64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x4
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x4Slice(v0)
+	vec1 := simd.LoadUint64x4Slice(v1)
+	vec2 := simd.LoadUint64x4Slice(v2)
+	vec3 := simd.LoadInt64x4Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask64x4())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask64x4())
+
+	default:
+		t.Errorf("Unknown method: Uint64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x4Unary(t *testing.T, v0 []uint64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x4
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x4Slice(v0)
+	switch which {
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Uint64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x4UnaryMasked(t *testing.T, v0 []uint64, v1 []int64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x4
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x4Slice(v0)
+	vec1 := simd.LoadInt64x4Slice(v1)
+	switch which {
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask64x4())
+
+	default:
+		t.Errorf("Unknown method: Uint64x4.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x8Binary(t *testing.T, v0 []uint64, v1 []uint64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x8
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x8Slice(v0)
+	vec1 := simd.LoadUint64x8Slice(v1)
+	switch which {
+	case "Add":
+		gotv = vec0.Add(vec1)
+	case "And":
+		gotv = vec0.And(vec1)
+	case "AndNot":
+		gotv = vec0.AndNot(vec1)
+	case "Max":
+		gotv = vec0.Max(vec1)
+	case "Min":
+		gotv = vec0.Min(vec1)
+	case "MulEvenWiden":
+		gotv = vec0.MulEvenWiden(vec1)
+	case "Or":
+		gotv = vec0.Or(vec1)
+	case "RotateLeft":
+		gotv = vec0.RotateLeft(vec1)
+	case "RotateRight":
+		gotv = vec0.RotateRight(vec1)
+	case "ShiftLeft":
+		gotv = vec0.ShiftLeft(vec1)
+	case "ShiftRight":
+		gotv = vec0.ShiftRight(vec1)
+	case "Sub":
+		gotv = vec0.Sub(vec1)
+	case "Xor":
+		gotv = vec0.Xor(vec1)
+
+	default:
+		t.Errorf("Unknown method: Uint64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x8BinaryMasked(t *testing.T, v0 []uint64, v1 []uint64, v2 []int64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x8
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x8Slice(v0)
+	vec1 := simd.LoadUint64x8Slice(v1)
+	vec2 := simd.LoadInt64x8Slice(v2)
+	switch which {
+	case "AddMasked":
+		gotv = vec0.AddMasked(vec1, vec2.AsMask64x8())
+	case "AndMasked":
+		gotv = vec0.AndMasked(vec1, vec2.AsMask64x8())
+	case "AndNotMasked":
+		gotv = vec0.AndNotMasked(vec1, vec2.AsMask64x8())
+	case "MaxMasked":
+		gotv = vec0.MaxMasked(vec1, vec2.AsMask64x8())
+	case "MinMasked":
+		gotv = vec0.MinMasked(vec1, vec2.AsMask64x8())
+	case "MulEvenWidenMasked":
+		gotv = vec0.MulEvenWidenMasked(vec1, vec2.AsMask64x8())
+	case "OrMasked":
+		gotv = vec0.OrMasked(vec1, vec2.AsMask64x8())
+	case "RotateLeftMasked":
+		gotv = vec0.RotateLeftMasked(vec1, vec2.AsMask64x8())
+	case "RotateRightMasked":
+		gotv = vec0.RotateRightMasked(vec1, vec2.AsMask64x8())
+	case "ShiftLeftMasked":
+		gotv = vec0.ShiftLeftMasked(vec1, vec2.AsMask64x8())
+	case "ShiftRightMasked":
+		gotv = vec0.ShiftRightMasked(vec1, vec2.AsMask64x8())
+	case "SubMasked":
+		gotv = vec0.SubMasked(vec1, vec2.AsMask64x8())
+	case "XorMasked":
+		gotv = vec0.XorMasked(vec1, vec2.AsMask64x8())
+
+	default:
+		t.Errorf("Unknown method: Uint64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x8Compare(t *testing.T, v0 []uint64, v1 []uint64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x8
+	got := make([]int64, len(want))
+	vec0 := simd.LoadUint64x8Slice(v0)
+	vec1 := simd.LoadUint64x8Slice(v1)
+	switch which {
+	case "Equal":
+		gotv = vec0.Equal(vec1).AsInt64x8()
+	case "Greater":
+		gotv = vec0.Greater(vec1).AsInt64x8()
+	case "GreaterEqual":
+		gotv = vec0.GreaterEqual(vec1).AsInt64x8()
+	case "Less":
+		gotv = vec0.Less(vec1).AsInt64x8()
+	case "LessEqual":
+		gotv = vec0.LessEqual(vec1).AsInt64x8()
+	case "NotEqual":
+		gotv = vec0.NotEqual(vec1).AsInt64x8()
+
+	default:
+		t.Errorf("Unknown method: Uint64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x8Mask64x8Uint64x8(t *testing.T, v0 []uint64, v1 []int64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x8
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x8Slice(v0)
+	vec1 := simd.LoadInt64x8Slice(v1)
+	switch which {
+	case "Compress":
+		gotv = vec0.Compress(vec1.AsMask64x8())
+
+	default:
+		t.Errorf("Unknown method: Uint64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x8MaskedCompare(t *testing.T, v0 []uint64, v1 []uint64, v2 []int64, want []int64, which string) {
+	t.Helper()
+	var gotv simd.Int64x8
+	got := make([]int64, len(want))
+	vec0 := simd.LoadUint64x8Slice(v0)
+	vec1 := simd.LoadUint64x8Slice(v1)
+	vec2 := simd.LoadInt64x8Slice(v2)
+	switch which {
+	case "EqualMasked":
+		gotv = vec0.EqualMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "GreaterEqualMasked":
+		gotv = vec0.GreaterEqualMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "GreaterMasked":
+		gotv = vec0.GreaterMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "LessEqualMasked":
+		gotv = vec0.LessEqualMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "LessMasked":
+		gotv = vec0.LessMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+	case "NotEqualMasked":
+		gotv = vec0.NotEqualMasked(vec1, vec2.AsMask64x8()).AsInt64x8()
+
+	default:
+		t.Errorf("Unknown method: Uint64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x8Ternary(t *testing.T, v0 []uint64, v1 []uint64, v2 []uint64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x8
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x8Slice(v0)
+	vec1 := simd.LoadUint64x8Slice(v1)
+	vec2 := simd.LoadUint64x8Slice(v2)
+	switch which {
+	case "ShiftLeftAndFillUpperFrom":
+		gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+	case "ShiftRightAndFillUpperFrom":
+		gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+	default:
+		t.Errorf("Unknown method: Uint64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x8TernaryMasked(t *testing.T, v0 []uint64, v1 []uint64, v2 []uint64, v3 []int64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x8
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x8Slice(v0)
+	vec1 := simd.LoadUint64x8Slice(v1)
+	vec2 := simd.LoadUint64x8Slice(v2)
+	vec3 := simd.LoadInt64x8Slice(v3)
+	switch which {
+	case "ShiftLeftAndFillUpperFromMasked":
+		gotv = vec0.ShiftLeftAndFillUpperFromMasked(vec1, vec2, vec3.AsMask64x8())
+	case "ShiftRightAndFillUpperFromMasked":
+		gotv = vec0.ShiftRightAndFillUpperFromMasked(vec1, vec2, vec3.AsMask64x8())
+
+	default:
+		t.Errorf("Unknown method: Uint64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x8Unary(t *testing.T, v0 []uint64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x8
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x8Slice(v0)
+	switch which {
+	case "PopCount":
+		gotv = vec0.PopCount()
+
+	default:
+		t.Errorf("Unknown method: Uint64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+func testUint64x8UnaryMasked(t *testing.T, v0 []uint64, v1 []int64, want []uint64, which string) {
+	t.Helper()
+	var gotv simd.Uint64x8
+	got := make([]uint64, len(want))
+	vec0 := simd.LoadUint64x8Slice(v0)
+	vec1 := simd.LoadInt64x8Slice(v1)
+	switch which {
+	case "PopCountMasked":
+		gotv = vec0.PopCountMasked(vec1.AsMask64x8())
+
+	default:
+		t.Errorf("Unknown method: Uint64x8.%s", which)
+	}
+	gotv.StoreSlice(got)
+	for i := range len(want) {
+		if got[i] != want[i] {
+			t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+		}
+	}
+}
+
+/* The operations below cannot be tested via wrappers, please test them directly */
+
+// CeilWithPrecision
+// CeilWithPrecisionMasked
+// DiffWithCeilWithPrecision
+// DiffWithCeilWithPrecisionMasked
+// DiffWithFloorWithPrecision
+// DiffWithFloorWithPrecisionMasked
+// DiffWithRoundWithPrecision
+// DiffWithRoundWithPrecisionMasked
+// DiffWithTruncWithPrecision
+// DiffWithTruncWithPrecisionMasked
+// FloorWithPrecision
+// FloorWithPrecisionMasked
+// GaloisFieldAffineTransform
+// GaloisFieldAffineTransformInverse
+// GaloisFieldAffineTransformInverseMasked
+// GaloisFieldAffineTransformMasked
+// Get128
+// GetElem
+// PairDotProdAccumulate
+// PairDotProdAccumulateMasked
+// Permute
+// Permute2
+// Permute2Masked
+// PermuteMasked
+// RotateAllLeft
+// RotateAllLeftMasked
+// RotateAllRight
+// RotateAllRightMasked
+// RoundWithPrecision
+// RoundWithPrecisionMasked
+// SaturatedPairDotProdAccumulate
+// SaturatedPairDotProdAccumulateMasked
+// SaturatedUnsignedSignedQuadDotProdAccumulate
+// SaturatedUnsignedSignedQuadDotProdAccumulateMasked
+// Set128
+// SetElem
+// ShiftAllLeft
+// ShiftAllLeftAndFillUpperFrom
+// ShiftAllLeftAndFillUpperFromMasked
+// ShiftAllLeftMasked
+// ShiftAllRight
+// ShiftAllRightAndFillUpperFrom
+// ShiftAllRightAndFillUpperFromMasked
+// ShiftAllRightMasked
+// TruncWithPrecision
+// TruncWithPrecisionMasked
+// UnsignedSignedQuadDotProdAccumulate
+// UnsignedSignedQuadDotProdAccumulateMasked
diff --git a/src/simd/slice_amd64.go b/src/simd/slice_amd64.go
new file mode 100644
index 00000000000000..10050e6b9f82a2
--- /dev/null
+++ b/src/simd/slice_amd64.go
@@ -0,0 +1,308 @@
+// Code generated by 'go run genslice.go -o slice_amd64.go'; DO NOT EDIT.
+
+//go:build goexperiment.simd
+
+// The build condition == if the experiment is not on, cmd/api TestCheck will see this and complain
+// see also go/doc/comment, where "simd" is inserted to the package list of the experiment is not on.
+
+package simd
+
+// LoadInt8x16Slice loads an Int8x16 from a slice of at least 16 int8s
+func LoadInt8x16Slice(s []int8) Int8x16 {
+	return LoadInt8x16((*[16]int8)(s))
+}
+
+// StoreSlice stores x into a slice of at least 16 int8s
+func (x Int8x16) StoreSlice(s []int8) {
+	x.Store((*[16]int8)(s))
+}
+
+// LoadUint8x16Slice loads an Uint8x16 from a slice of at least 16 uint8s
+func LoadUint8x16Slice(s []uint8) Uint8x16 {
+	return LoadUint8x16((*[16]uint8)(s))
+}
+
+// StoreSlice stores x into a slice of at least 16 uint8s
+func (x Uint8x16) StoreSlice(s []uint8) {
+	x.Store((*[16]uint8)(s))
+}
+
+// LoadInt16x8Slice loads an Int16x8 from a slice of at least 8 int16s
+func LoadInt16x8Slice(s []int16) Int16x8 {
+	return LoadInt16x8((*[8]int16)(s))
+}
+
+// StoreSlice stores x into a slice of at least 8 int16s
+func (x Int16x8) StoreSlice(s []int16) {
+	x.Store((*[8]int16)(s))
+}
+
+// LoadUint16x8Slice loads an Uint16x8 from a slice of at least 8 uint16s
+func LoadUint16x8Slice(s []uint16) Uint16x8 {
+	return LoadUint16x8((*[8]uint16)(s))
+}
+
+// StoreSlice stores x into a slice of at least 8 uint16s
+func (x Uint16x8) StoreSlice(s []uint16) {
+	x.Store((*[8]uint16)(s))
+}
+
+// LoadInt32x4Slice loads an Int32x4 from a slice of at least 4 int32s
+func LoadInt32x4Slice(s []int32) Int32x4 {
+	return LoadInt32x4((*[4]int32)(s))
+}
+
+// StoreSlice stores x into a slice of at least 4 int32s
+func (x Int32x4) StoreSlice(s []int32) {
+	x.Store((*[4]int32)(s))
+}
+
+// LoadUint32x4Slice loads an Uint32x4 from a slice of at least 4 uint32s
+func LoadUint32x4Slice(s []uint32) Uint32x4 {
+	return LoadUint32x4((*[4]uint32)(s))
+}
+
+// StoreSlice stores x into a slice of at least 4 uint32s
+func (x Uint32x4) StoreSlice(s []uint32) {
+	x.Store((*[4]uint32)(s))
+}
+
+// LoadInt64x2Slice loads an Int64x2 from a slice of at least 2 int64s
+func LoadInt64x2Slice(s []int64) Int64x2 {
+	return LoadInt64x2((*[2]int64)(s))
+}
+
+// StoreSlice stores x into a slice of at least 2 int64s
+func (x Int64x2) StoreSlice(s []int64) {
+	x.Store((*[2]int64)(s))
+}
+
+// LoadUint64x2Slice loads an Uint64x2 from a slice of at least 2 uint64s
+func LoadUint64x2Slice(s []uint64) Uint64x2 {
+	return LoadUint64x2((*[2]uint64)(s))
+}
+
+// StoreSlice stores x into a slice of at least 2 uint64s
+func (x Uint64x2) StoreSlice(s []uint64) {
+	x.Store((*[2]uint64)(s))
+}
+
+// LoadFloat32x4Slice loads a Float32x4 from a slice of at least 4 float32s
+func LoadFloat32x4Slice(s []float32) Float32x4 {
+	return LoadFloat32x4((*[4]float32)(s))
+}
+
+// StoreSlice stores x into a slice of at least 4 float32s
+func (x Float32x4) StoreSlice(s []float32) {
+	x.Store((*[4]float32)(s))
+}
+
+// LoadFloat64x2Slice loads a Float64x2 from a slice of at least 2 float64s
+func LoadFloat64x2Slice(s []float64) Float64x2 {
+	return LoadFloat64x2((*[2]float64)(s))
+}
+
+// StoreSlice stores x into a slice of at least 2 float64s
+func (x Float64x2) StoreSlice(s []float64) {
+	x.Store((*[2]float64)(s))
+}
+
+// LoadInt8x32Slice loads an Int8x32 from a slice of at least 32 int8s
+func LoadInt8x32Slice(s []int8) Int8x32 {
+	return LoadInt8x32((*[32]int8)(s))
+}
+
+// StoreSlice stores x into a slice of at least 32 int8s
+func (x Int8x32) StoreSlice(s []int8) {
+	x.Store((*[32]int8)(s))
+}
+
+// LoadUint8x32Slice loads an Uint8x32 from a slice of at least 32 uint8s
+func LoadUint8x32Slice(s []uint8) Uint8x32 {
+	return LoadUint8x32((*[32]uint8)(s))
+}
+
+// StoreSlice stores x into a slice of at least 32 uint8s
+func (x Uint8x32) StoreSlice(s []uint8) {
+	x.Store((*[32]uint8)(s))
+}
+
+// LoadInt16x16Slice loads an Int16x16 from a slice of at least 16 int16s
+func LoadInt16x16Slice(s []int16) Int16x16 {
+	return LoadInt16x16((*[16]int16)(s))
+}
+
+// StoreSlice stores x into a slice of at least 16 int16s
+func (x Int16x16) StoreSlice(s []int16) {
+	x.Store((*[16]int16)(s))
+}
+
+// LoadUint16x16Slice loads an Uint16x16 from a slice of at least 16 uint16s
+func LoadUint16x16Slice(s []uint16) Uint16x16 {
+	return LoadUint16x16((*[16]uint16)(s))
+}
+
+// StoreSlice stores x into a slice of at least 16 uint16s
+func (x Uint16x16) StoreSlice(s []uint16) {
+	x.Store((*[16]uint16)(s))
+}
+
+// LoadInt32x8Slice loads an Int32x8 from a slice of at least 8 int32s
+func LoadInt32x8Slice(s []int32) Int32x8 {
+	return LoadInt32x8((*[8]int32)(s))
+}
+
+// StoreSlice stores x into a slice of at least 8 int32s
+func (x Int32x8) StoreSlice(s []int32) {
+	x.Store((*[8]int32)(s))
+}
+
+// LoadUint32x8Slice loads an Uint32x8 from a slice of at least 8 uint32s
+func LoadUint32x8Slice(s []uint32) Uint32x8 {
+	return LoadUint32x8((*[8]uint32)(s))
+}
+
+// StoreSlice stores x into a slice of at least 8 uint32s
+func (x Uint32x8) StoreSlice(s []uint32) {
+	x.Store((*[8]uint32)(s))
+}
+
+// LoadInt64x4Slice loads an Int64x4 from a slice of at least 4 int64s
+func LoadInt64x4Slice(s []int64) Int64x4 {
+	return LoadInt64x4((*[4]int64)(s))
+}
+
+// StoreSlice stores x into a slice of at least 4 int64s
+func (x Int64x4) StoreSlice(s []int64) {
+	x.Store((*[4]int64)(s))
+}
+
+// LoadUint64x4Slice loads an Uint64x4 from a slice of at least 4 uint64s
+func LoadUint64x4Slice(s []uint64) Uint64x4 {
+	return LoadUint64x4((*[4]uint64)(s))
+}
+
+// StoreSlice stores x into a slice of at least 4 uint64s
+func (x Uint64x4) StoreSlice(s []uint64) {
+	x.Store((*[4]uint64)(s))
+}
+
+// LoadFloat32x8Slice loads a Float32x8 from a slice of at least 8 float32s
+func LoadFloat32x8Slice(s []float32) Float32x8 {
+	return LoadFloat32x8((*[8]float32)(s))
+}
+
+// StoreSlice stores x into a slice of at least 8 float32s
+func (x Float32x8) StoreSlice(s []float32) {
+	x.Store((*[8]float32)(s))
+}
+
+// LoadFloat64x4Slice loads a Float64x4 from a slice of at least 4 float64s
+func LoadFloat64x4Slice(s []float64) Float64x4 {
+	return LoadFloat64x4((*[4]float64)(s))
+}
+
+// StoreSlice stores x into a slice of at least 4 float64s
+func (x Float64x4) StoreSlice(s []float64) {
+	x.Store((*[4]float64)(s))
+}
+
+// LoadInt8x64Slice loads an Int8x64 from a slice of at least 64 int8s
+func LoadInt8x64Slice(s []int8) Int8x64 {
+	return LoadInt8x64((*[64]int8)(s))
+}
+
+// StoreSlice stores x into a slice of at least 64 int8s
+func (x Int8x64) StoreSlice(s []int8) {
+	x.Store((*[64]int8)(s))
+}
+
+// LoadUint8x64Slice loads an Uint8x64 from a slice of at least 64 uint8s
+func LoadUint8x64Slice(s []uint8) Uint8x64 {
+	return LoadUint8x64((*[64]uint8)(s))
+}
+
+// StoreSlice stores x into a slice of at least 64 uint8s
+func (x Uint8x64) StoreSlice(s []uint8) {
+	x.Store((*[64]uint8)(s))
+}
+
+// LoadInt16x32Slice loads an Int16x32 from a slice of at least 32 int16s
+func LoadInt16x32Slice(s []int16) Int16x32 {
+	return LoadInt16x32((*[32]int16)(s))
+}
+
+// StoreSlice stores x into a slice of at least 32 int16s
+func (x Int16x32) StoreSlice(s []int16) {
+	x.Store((*[32]int16)(s))
+}
+
+// LoadUint16x32Slice loads an Uint16x32 from a slice of at least 32 uint16s
+func LoadUint16x32Slice(s []uint16) Uint16x32 {
+	return LoadUint16x32((*[32]uint16)(s))
+}
+
+// StoreSlice stores x into a slice of at least 32 uint16s
+func (x Uint16x32) StoreSlice(s []uint16) {
+	x.Store((*[32]uint16)(s))
+}
+
+// LoadInt32x16Slice loads an Int32x16 from a slice of at least 16 int32s
+func LoadInt32x16Slice(s []int32) Int32x16 {
+	return LoadInt32x16((*[16]int32)(s))
+}
+
+// StoreSlice stores x into a slice of at least 16 int32s
+func (x Int32x16) StoreSlice(s []int32) {
+	x.Store((*[16]int32)(s))
+}
+
+// LoadUint32x16Slice loads an Uint32x16 from a slice of at least 16 uint32s
+func LoadUint32x16Slice(s []uint32) Uint32x16 {
+	return LoadUint32x16((*[16]uint32)(s))
+}
+
+// StoreSlice stores x into a slice of at least 16 uint32s
+func (x Uint32x16) StoreSlice(s []uint32) {
+	x.Store((*[16]uint32)(s))
+}
+
+// LoadInt64x8Slice loads an Int64x8 from a slice of at least 8 int64s
+func LoadInt64x8Slice(s []int64) Int64x8 {
+	return LoadInt64x8((*[8]int64)(s))
+}
+
+// StoreSlice stores x into a slice of at least 8 int64s
+func (x Int64x8) StoreSlice(s []int64) {
+	x.Store((*[8]int64)(s))
+}
+
+// LoadUint64x8Slice loads an Uint64x8 from a slice of at least 8 uint64s
+func LoadUint64x8Slice(s []uint64) Uint64x8 {
+	return LoadUint64x8((*[8]uint64)(s))
+}
+
+// StoreSlice stores x into a slice of at least 8 uint64s
+func (x Uint64x8) StoreSlice(s []uint64) {
+	x.Store((*[8]uint64)(s))
+}
+
+// LoadFloat32x16Slice loads a Float32x16 from a slice of at least 16 float32s
+func LoadFloat32x16Slice(s []float32) Float32x16 {
+	return LoadFloat32x16((*[16]float32)(s))
+}
+
+// StoreSlice stores x into a slice of at least 16 float32s
+func (x Float32x16) StoreSlice(s []float32) {
+	x.Store((*[16]float32)(s))
+}
+
+// LoadFloat64x8Slice loads a Float64x8 from a slice of at least 8 float64s
+func LoadFloat64x8Slice(s []float64) Float64x8 {
+	return LoadFloat64x8((*[8]float64)(s))
+}
+
+// StoreSlice stores x into a slice of at least 8 float64s
+func (x Float64x8) StoreSlice(s []float64) {
+	x.Store((*[8]float64)(s))
+}
diff --git a/src/simd/slicepart_amd64.go b/src/simd/slicepart_amd64.go
new file mode 100644
index 00000000000000..7f5247cd8c25b8
--- /dev/null
+++ b/src/simd/slicepart_amd64.go
@@ -0,0 +1,387 @@
+// Copyright 2025 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+//go:build goexperiment.simd
+
+package simd
+
+import "unsafe"
+
+// Implementation of all the {Int,Uint}{8,16} load and store slice part
+// functions and methods for 128-bit and 256-bit vectors.
+
+/* pointer-punning functions. */
+
+func int16atP8(p *int8) *int16 {
+	return (*int16)(unsafe.Pointer(p))
+}
+
+func int32atP8(p *int8) *int32 {
+	return (*int32)(unsafe.Pointer(p))
+}
+
+func int64atP8(p *int8) *int64 {
+	return (*int64)(unsafe.Pointer(p))
+}
+
+func int32atP16(p *int16) *int32 {
+	return (*int32)(unsafe.Pointer(p))
+}
+
+func int64atP16(p *int16) *int64 {
+	return (*int64)(unsafe.Pointer(p))
+}
+
+func int64atP32(p *int32) *int64 {
+	return (*int64)(unsafe.Pointer(p))
+}
+
+/* unsigned versions of integer slice part loads */
+
+// LoadUint8x16SlicePart loads a Uint8x16 from the slice s.
+// If s has fewer than 16 elements, the remaining elements of the vector are filled with zeroes.
+// If s has 16 or more elements, the function is equivalent to LoadUint8x16Slice.
+func LoadUint8x16SlicePart(s []uint8) Uint8x16 {
+	if len(s) == 0 {
+		var zero Uint8x16
+		return zero
+	}
+	t := unsafe.Slice((*int8)(unsafe.Pointer(&s[0])), len(s))
+	return LoadInt8x16SlicePart(t).AsUint8x16()
+}
+
+// LoadUint16x8SlicePart loads a Uint16x8 from the slice s.
+// If s has fewer than 8 elements, the remaining elements of the vector are filled with zeroes.
+// If s has 8 or more elements, the function is equivalent to LoadUint16x8Slice.
+func LoadUint16x8SlicePart(s []uint16) Uint16x8 {
+	if len(s) == 0 {
+		var zero Uint16x8
+		return zero
+	}
+	t := unsafe.Slice((*int16)(unsafe.Pointer(&s[0])), len(s))
+	return LoadInt16x8SlicePart(t).AsUint16x8()
+}
+
+// LoadUint8x32SlicePart loads a Uint8x32 from the slice s.
+// If s has fewer than 32 elements, the remaining elements of the vector are filled with zeroes.
+// If s has 32 or more elements, the function is equivalent to LoadUint8x32Slice.
+func LoadUint8x32SlicePart(s []uint8) Uint8x32 {
+	if len(s) == 0 {
+		var zero Uint8x32
+		return zero
+	}
+	t := unsafe.Slice((*int8)(unsafe.Pointer(&s[0])), len(s))
+	return LoadInt8x32SlicePart(t).AsUint8x32()
+}
+
+// LoadUint16x16SlicePart loads a Uint16x16 from the slice s.
+// If s has fewer than 16 elements, the remaining elements of the vector are filled with zeroes.
+// If s has 16 or more elements, the function is equivalent to LoadUint16x16Slice.
+func LoadUint16x16SlicePart(s []uint16) Uint16x16 {
+	if len(s) == 0 {
+		var zero Uint16x16
+		return zero
+	}
+	t := unsafe.Slice((*int16)(unsafe.Pointer(&s[0])), len(s))
+	return LoadInt16x16SlicePart(t).AsUint16x16()
+}
+
+/* unsigned versions of integer slice part stores*/
+
+// StoreSlicePart stores the elements of x into the slice s.
+// It stores as many elements as will fit in s.
+// If s has 16 or more elements, the method is equivalent to x.StoreSlice.
+func (x Uint8x16) StoreSlicePart(s []uint8) {
+	if len(s) == 0 {
+		return
+	}
+	t := unsafe.Slice((*int8)(unsafe.Pointer(&s[0])), len(s))
+	x.AsInt8x16().StoreSlicePart(t)
+}
+
+// StoreSlicePart stores the elements of x into the slice s.
+// It stores as many elements as will fit in s.
+// If s has 8 or more elements, the method is equivalent to x.StoreSlice.
+func (x Uint16x8) StoreSlicePart(s []uint16) {
+	if len(s) == 0 {
+		return
+	}
+	t := unsafe.Slice((*int16)(unsafe.Pointer(&s[0])), len(s))
+	x.AsInt16x8().StoreSlicePart(t)
+}
+
+// StoreSlicePart stores the elements of x into the slice s.
+// It stores as many elements as will fit in s.
+// If s has 32 or more elements, the method is equivalent to x.StoreSlice.
+func (x Uint8x32) StoreSlicePart(s []uint8) {
+	if len(s) == 0 {
+		return
+	}
+	t := unsafe.Slice((*int8)(unsafe.Pointer(&s[0])), len(s))
+	x.AsInt8x32().StoreSlicePart(t)
+}
+
+// StoreSlicePart stores the elements of x into the slice s.
+// It stores as many elements as will fit in s.
+// If s has 16 or more elements, the method is equivalent to x.StoreSlice.
+func (x Uint16x16) StoreSlicePart(s []uint16) {
+	if len(s) == 0 {
+		return
+	}
+	t := unsafe.Slice((*int16)(unsafe.Pointer(&s[0])), len(s))
+	x.AsInt16x16().StoreSlicePart(t)
+}
+
+/* 256-bit int vector loads and stores made from 128-bit parts */
+
+// LoadInt8x32SlicePart loads a Int8x32 from the slice s.
+// If s has fewer than 32 elements, the remaining elements of the vector are filled with zeroes.
+// If s has 32 or more elements, the function is equivalent to LoadInt8x32Slice.
+func LoadInt8x32SlicePart(s []int8) Int8x32 {
+	l := len(s)
+	if l >= 32 {
+		return LoadInt8x32Slice(s)
+	}
+	var x Int8x32
+	if l == 0 {
+		return x
+	}
+	if l > 16 {
+		return x.Set128(0, LoadInt8x16Slice(s)).Set128(1, LoadInt8x16SlicePart(s[16:]))
+	} else {
+		return x.Set128(0, LoadInt8x16SlicePart(s))
+	}
+}
+
+// LoadInt16x16SlicePart loads a Int16x16 from the slice s.
+// If s has fewer than 16 elements, the remaining elements of the vector are filled with zeroes.
+// If s has 16 or more elements, the function is equivalent to LoadInt16x16Slice.
+func LoadInt16x16SlicePart(s []int16) Int16x16 {
+	l := len(s)
+	if l >= 16 {
+		return LoadInt16x16Slice(s)
+	}
+	var x Int16x16
+	if l == 0 {
+		return x
+	}
+	if l > 8 {
+		return x.Set128(0, LoadInt16x8Slice(s)).Set128(1, LoadInt16x8SlicePart(s[8:]))
+	} else {
+		return x.Set128(0, LoadInt16x8SlicePart(s))
+	}
+}
+
+// StoreSlicePart stores the elements of x into the slice s.
+// It stores as many elements as will fit in s.
+// If s has 32 or more elements, the method is equivalent to x.StoreSlice.
+func (x Int8x32) StoreSlicePart(s []int8) {
+	l := len(s)
+	if l >= 32 {
+		x.StoreSlice(s)
+		return
+	}
+	if l == 0 {
+		return
+	}
+	if l > 16 {
+		x.Get128(0).StoreSlice(s)
+		x.Get128(1).StoreSlicePart(s[16:])
+	} else { // fits in one
+		x.Get128(0).StoreSlicePart(s)
+	}
+}
+
+// StoreSlicePart stores the elements of x into the slice s.
+// It stores as many elements as will fit in s.
+// If s has 16 or more elements, the method is equivalent to x.StoreSlice.
+func (x Int16x16) StoreSlicePart(s []int16) {
+	l := len(s)
+	if l >= 16 {
+		x.StoreSlice(s)
+		return
+	}
+	if l == 0 {
+		return
+	}
+	if l > 8 {
+		x.Get128(0).StoreSlice(s)
+		x.Get128(1).StoreSlicePart(s[8:])
+	} else { // fits in one
+		x.Get128(0).StoreSlicePart(s)
+	}
+}
+
+/* 128-bit vector load and store slice parts for 8 and 16-bit int elements */
+
+// LoadInt8x16SlicePart loads a Int8x16 from the slice s.
+// If s has fewer than 16 elements, the remaining elements of the vector are filled with zeroes.
+// If s has 16 or more elements, the function is equivalent to LoadInt8x16Slice.
+func LoadInt8x16SlicePart(s []int8) Int8x16 {
+	l := len(s)
+	if l >= 16 {
+		return LoadInt8x16Slice(s)
+	}
+	var x Int8x16
+	if l == 0 {
+		return x
+	}
+	if l >= 8 { // 8-15
+		x = x.AsInt64x2().SetElem(0, *int64atP8(&s[0])).AsInt8x16()
+		if l >= 12 { // 12, 13, 14, 15
+			x = x.AsInt32x4().SetElem(8/4, *int32atP8(&s[8])).AsInt8x16()
+			if l >= 14 {
+				x = x.AsInt16x8().SetElem(12/2, *int16atP8(&s[12])).AsInt8x16()
+				if l == 15 {
+					x = x.SetElem(14, s[14])
+				}
+			} else if l == 13 {
+				x = x.SetElem(12, s[12])
+			}
+		} else if l >= 10 { // 10, 11
+			x = x.AsInt16x8().SetElem(8/2, *int16atP8(&s[8])).AsInt8x16()
+			if l == 11 {
+				x = x.SetElem(10, s[10])
+			}
+		} else if l == 9 {
+			x = x.SetElem(8, s[8])
+		}
+	} else if l >= 4 { // 4-7
+		x = x.AsInt32x4().SetElem(0, *int32atP8(&s[0])).AsInt8x16()
+		if l >= 6 {
+			x = x.AsInt16x8().SetElem(4/2, *int16atP8(&s[4])).AsInt8x16()
+			if l == 7 {
+				x = x.SetElem(6, s[6])
+			}
+		} else if l == 5 {
+			x = x.SetElem(4, s[4])
+		}
+	} else if l >= 2 { // 2,3
+		x = x.AsInt16x8().SetElem(0, *int16atP8(&s[0])).AsInt8x16()
+		if l == 3 {
+			x = x.SetElem(2, s[2])
+		}
+	} else { // l == 1
+		x = x.SetElem(0, s[0])
+	}
+	return x
+}
+
+// StoreSlicePart stores the elements of x into the slice s.
+// It stores as many elements as will fit in s.
+// If s has 16 or more elements, the method is equivalent to x.StoreSlice.
+func (x Int8x16) StoreSlicePart(s []int8) {
+	l := len(s)
+	if l >= 16 {
+		x.StoreSlice(s)
+		return
+	}
+	if l == 0 {
+		return
+	}
+	if l >= 8 { // 8-15
+		*int64atP8(&s[0]) = x.AsInt64x2().GetElem(0)
+		if l >= 12 { // 12, 13, 14, 15
+			*int32atP8(&s[8]) = x.AsInt32x4().GetElem(8 / 4)
+			if l >= 14 {
+				*int16atP8(&s[12]) = x.AsInt16x8().GetElem(12 / 2)
+				if l == 15 {
+					s[14] = x.GetElem(14)
+				}
+			} else if l == 13 {
+				s[12] = x.GetElem(12)
+			}
+		} else if l >= 10 { // 10, 11
+			*int16atP8(&s[8]) = x.AsInt16x8().GetElem(8 / 2)
+			if l == 11 {
+				s[10] = x.GetElem(10)
+			}
+		} else if l == 9 {
+			s[8] = x.GetElem(8)
+		}
+	} else if l >= 4 { // 4-7
+		*int32atP8(&s[0]) = x.AsInt32x4().GetElem(0)
+		if l >= 6 {
+			*int16atP8(&s[4]) = x.AsInt16x8().GetElem(4 / 2)
+			if l == 7 {
+				s[6] = x.GetElem(6)
+			}
+		} else if l == 5 {
+			s[4] = x.GetElem(4)
+		}
+	} else if l >= 2 { // 2,3
+		*int16atP8(&s[0]) = x.AsInt16x8().GetElem(0)
+		if l == 3 {
+			s[2] = x.GetElem(2)
+		}
+	} else { // l == 1
+		s[0] = x.GetElem(0)
+	}
+}
+
+// LoadInt16x8SlicePart loads a Int16x8 from the slice s.
+// If s has fewer than 8 elements, the remaining elements of the vector are filled with zeroes.
+// If s has 8 or more elements, the function is equivalent to LoadInt16x8Slice.
+func LoadInt16x8SlicePart(s []int16) Int16x8 {
+	l := len(s)
+	if l >= 8 {
+		return LoadInt16x8Slice(s)
+	}
+	var x Int16x8
+	if l == 0 {
+		return x
+	}
+	if l >= 4 { // 4-7
+		x = x.AsInt64x2().SetElem(0, *int64atP16(&s[0])).AsInt16x8()
+		if l >= 6 {
+			x = x.AsInt32x4().SetElem(4/2, *int32atP16(&s[4])).AsInt16x8()
+			if l == 7 {
+				x = x.SetElem(6, s[6])
+			}
+		} else if l == 5 {
+			x = x.SetElem(4, s[4])
+		}
+	} else if l >= 2 { // 2,3
+		x = x.AsInt32x4().SetElem(0, *int32atP16(&s[0])).AsInt16x8()
+		if l == 3 {
+			x = x.SetElem(2, s[2])
+		}
+	} else { // l == 1
+		x = x.SetElem(0, s[0])
+	}
+	return x
+}
+
+// StoreSlicePart stores the elements of x into the slice s.
+// It stores as many elements as will fit in s.
+// If s has 8 or more elements, the method is equivalent to x.StoreSlice.
+func (x Int16x8) StoreSlicePart(s []int16) {
+	l := len(s)
+	if l >= 8 {
+		x.StoreSlice(s)
+		return
+	}
+	if l == 0 {
+		return
+	}
+	if l >= 4 { // 4-7
+		*int64atP16(&s[0]) = x.AsInt64x2().GetElem(0)
+		if l >= 6 {
+			*int32atP16(&s[4]) = x.AsInt32x4().GetElem(4 / 2)
+			if l == 7 {
+				s[6] = x.GetElem(6)
+			}
+		} else if l == 5 {
+			s[4] = x.GetElem(4)
+		}
+	} else if l >= 2 { // 2,3
+		*int32atP16(&s[0]) = x.AsInt32x4().GetElem(0)
+		if l == 3 {
+			s[2] = x.GetElem(2)
+		}
+	} else { // l == 1
+		s[0] = x.GetElem(0)
+	}
+	return
+}
diff --git a/src/simd/slicepart_test.go b/src/simd/slicepart_test.go
new file mode 100644
index 00000000000000..8f10ea630b726f
--- /dev/null
+++ b/src/simd/slicepart_test.go
@@ -0,0 +1,186 @@
+// Copyright 2025 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+//go:build goexperiment.simd && amd64
+
+package simd_test
+
+import (
+	"simd"
+	"testing"
+)
+
+func TestSlicePartInt8x16(t *testing.T) {
+	a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	b := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	for i := 16; i >= 0; i-- {
+		u := simd.LoadInt8x16SlicePart(a[:i])
+		c := make([]int8, 32, 32)
+		u.StoreSlice(c)
+		checkInt8Slices(t, c, b)
+		if i > 0 {
+			b[i-1] = 0
+		}
+	}
+}
+
+func TestSlicePartInt8x32(t *testing.T) {
+	a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	b := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	for i := 32; i >= 0; i-- {
+		u := simd.LoadInt8x32SlicePart(a[:i])
+		c := make([]int8, 32, 32)
+		u.StoreSlice(c)
+		checkInt8Slices(t, c, b)
+		if i > 0 {
+			b[i-1] = 0
+		}
+	}
+}
+
+func TestSlicePartUint8x16(t *testing.T) {
+	a := []uint8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	b := []uint8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	for i := 16; i >= 0; i-- {
+		u := simd.LoadUint8x16SlicePart(a[:i])
+		c := make([]uint8, 32, 32)
+		u.StoreSlice(c)
+		checkUint8Slices(t, c, b)
+		if i > 0 {
+			b[i-1] = 0
+		}
+	}
+}
+
+func TestSlicePartUint8x32(t *testing.T) {
+	a := []uint8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	b := []uint8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	for i := 32; i >= 0; i-- {
+		u := simd.LoadUint8x32SlicePart(a[:i])
+		c := make([]uint8, 32, 32)
+		u.StoreSlice(c)
+		checkUint8Slices(t, c, b)
+		if i > 0 {
+			b[i-1] = 0
+		}
+	}
+}
+
+func TestSlicePartInt16x8(t *testing.T) {
+	a := []int16{1, 2, 3, 4, 5, 6, 7, 8}
+	b := []int16{1, 2, 3, 4, 5, 6, 7, 8}
+	for i := 8; i >= 0; i-- {
+		u := simd.LoadInt16x8SlicePart(a[:i])
+		c := make([]int16, 16, 16)
+		u.StoreSlice(c)
+		checkInt16Slices(t, c, b)
+		if i > 0 {
+			b[i-1] = 0
+		}
+	}
+}
+
+func TestSlicePartInt16x16(t *testing.T) {
+	a := []int16{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	b := []int16{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	for i := 16; i >= 0; i-- {
+		u := simd.LoadInt16x16SlicePart(a[:i])
+		c := make([]int16, 16, 16)
+		u.StoreSlice(c)
+		checkInt16Slices(t, c, b)
+		if i > 0 {
+			b[i-1] = 0
+		}
+	}
+}
+
+func TestSlicesPartStoreInt8x16(t *testing.T) {
+	a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	b := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	for i := 16; i >= 0; i-- {
+		v := simd.LoadInt8x16Slice(a)
+		c := make([]int8, 32, 32)
+		v.StoreSlicePart(c[:i])
+		checkInt8Slices(t, c, b)
+		if i > 0 {
+			b[i-1] = 0
+		}
+	}
+}
+
+func TestSlicesPartStoreInt16x8(t *testing.T) {
+	a := []int16{1, 2, 3, 4, 5, 6, 7, 8}
+	b := []int16{1, 2, 3, 4, 5, 6, 7, 8}
+	for i := 8; i >= 0; i-- {
+		v := simd.LoadInt16x8Slice(a)
+		c := make([]int16, 32, 32)
+		v.StoreSlicePart(c[:i])
+		checkInt16Slices(t, c, b)
+		if i > 0 {
+			b[i-1] = 0
+		}
+	}
+}
+
+func TestSlicesPartStoreInt16x16(t *testing.T) {
+	a := []int16{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	b := []int16{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	for i := 16; i >= 0; i-- {
+		v := simd.LoadInt16x16Slice(a)
+		c := make([]int16, 32, 32)
+		v.StoreSlicePart(c[:i])
+		checkInt16Slices(t, c, b)
+		if i > 0 {
+			b[i-1] = 0
+		}
+	}
+}
+
+func TestSlicesPartStoreUint8x16(t *testing.T) {
+	a := []uint8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	b := []uint8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	for i := 16; i >= 0; i-- {
+		v := simd.LoadUint8x16Slice(a)
+		c := make([]uint8, 32, 32)
+		v.StoreSlicePart(c[:i])
+		checkUint8Slices(t, c, b)
+		if i > 0 {
+			b[i-1] = 0
+		}
+	}
+}
+
+func TestSlicesPartStoreUint16x16(t *testing.T) {
+	a := []uint16{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	b := []uint16{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
+	for i := 16; i >= 0; i-- {
+		v := simd.LoadUint16x16Slice(a)
+		c := make([]uint16, 32, 32)
+		v.StoreSlicePart(c[:i])
+		checkUint16Slices(t, c, b)
+		if i > 0 {
+			b[i-1] = 0
+		}
+	}
+}
+
+func TestSlicesPartStoreUint8x32(t *testing.T) {
+	a := []uint8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	b := []uint8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+		17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
+	for i := 32; i >= 0; i-- {
+		v := simd.LoadUint8x32Slice(a)
+		c := make([]uint8, 32, 32)
+		v.StoreSlicePart(c[:i])
+		checkUint8Slices(t, c, b)
+		if i > 0 {
+			b[i-1] = 0
+		}
+	}
+}
diff --git a/src/simd/testdata/sample.go b/src/simd/testdata/sample.go
new file mode 100644
index 00000000000000..b8e3697b6bf644
--- /dev/null
+++ b/src/simd/testdata/sample.go
@@ -0,0 +1,154 @@
+// Copyright 2025 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package main
+
+import (
+	"fmt"
+	"os"
+	"simd"
+	"unsafe"
+)
+
+func load(s []float64) simd.Float64x4 {
+	return simd.LoadFloat64x4((*[4]float64)(s[:4]))
+}
+
+type S1 = simd.Float64x4
+
+type S2 simd.Float64x4
+
+func (s S2) Len() int {
+	return simd.Float64x4(s).Len()
+}
+
+func (s S2) Load(a []float64) S2 {
+	return S2(load(a))
+}
+
+func (s S2) Store(a *[4]float64) {
+	simd.Float64x4(s).Store(a)
+}
+
+func (s S2) Add(a S2) S2 {
+	return S2(simd.Float64x4(s).Add(simd.Float64x4(a)))
+}
+
+func (s S2) Mul(a S2) S2 {
+	return S2(simd.Float64x4(s).Mul(simd.Float64x4(a)))
+}
+
+type S3 struct {
+	simd.Float64x4
+}
+
+func ip64_0(a, b []float64) float64 {
+	s := 0.0
+	for i := range a {
+		s += a[i] * b[i]
+	}
+	return s
+}
+
+func ip64_1(a, b []float64) float64 {
+	var z S1
+	sum := z
+	var i int
+	stride := z.Len()
+	for ; i <= len(a)-stride; i += stride {
+		va := load(a[i:])
+		vb := load(b[i:])
+		sum = sum.Add(va.Mul(vb))
+	}
+	var tmp [4]float64
+	sum.Store(&tmp)
+	return tmp[0] + tmp[1] + tmp[2] + tmp[3]
+}
+
+func ip64_1a(a, b []float64) float64 {
+	var z S1
+	sum := z
+	var i int
+	stride := z.Len()
+	for ; i <= len(a)-stride; i += stride {
+		va := load(a[i:])
+		vb := load(b[i:])
+		sum = FMA(sum, va, vb)
+	}
+	var tmp [4]float64
+	sum.Store(&tmp)
+	return tmp[0] + tmp[1] + tmp[2] + tmp[3]
+}
+
+//go:noinline
+func FMA(a, b, c simd.Float64x4) simd.Float64x4 {
+	return a.Add(b.Mul(c))
+}
+
+func ip64_2(a, b []float64) float64 {
+	var z S2
+	sum := z
+	var i int
+	stride := z.Len()
+	for ; i <= len(a)-stride; i += stride {
+		va := z.Load(a[i:])
+		vb := z.Load(b[i:])
+		sum = sum.Add(va.Mul(vb))
+	}
+	var tmp [4]float64
+	sum.Store(&tmp)
+	return tmp[0] + tmp[1] + tmp[2] + tmp[3]
+}
+
+func ip64_3(a, b []float64) float64 {
+	var z S3
+	sum := z
+	var i int
+	stride := z.Len()
+	for ; i <= len(a)-stride; i += stride {
+		va := load(a[i:])
+		vb := load(b[i:])
+		sum = S3{sum.Add(va.Mul(vb))}
+	}
+	var tmp [4]float64
+	sum.Store(&tmp)
+	return tmp[0] + tmp[1] + tmp[2] + tmp[3]
+}
+
+func main() {
+	a := []float64{1, 2, 3, 4, 5, 6, 7, 8}
+	ip0 := ip64_0(a, a)
+	ip1 := ip64_1(a, a)
+	ip1a := ip64_1a(a, a)
+	ip2 := ip64_2(a, a)
+	ip3 := ip64_3(a, a)
+	fmt.Printf("Test IP    = %f\n", ip0)
+	fmt.Printf("SIMD IP 1  = %f\n", ip1)
+	fmt.Printf("SIMD IP 1a = %f\n", ip1a)
+	fmt.Printf("SIMD IP 2  = %f\n", ip2)
+	fmt.Printf("SIMD IP 3 = %f\n", ip3)
+	var z1 S1
+	var z2 S2
+	var z3 S2
+
+	s1, s2, s3 := unsafe.Sizeof(z1), unsafe.Sizeof(z2), unsafe.Sizeof(z3)
+
+	fmt.Printf("unsafe.Sizeof(z1, z2, z3)=%d, %d, %d\n", s1, s2, s3)
+
+	fail := false
+
+	if s1 != 32 || s2 != 32 || s3 != 32 {
+		fmt.Println("Failed a sizeof check, should all be 32")
+		fail = true
+	}
+
+	if ip1 != ip0 || ip1a != ip0 || ip2 != ip0 || ip3 != ip0 {
+		fmt.Println("Failed an inner product check, should all be", ip0)
+		fail = true
+	}
+
+	if fail {
+		os.Exit(1)
+	}
+}
diff --git a/src/simd/types_amd64.go b/src/simd/types_amd64.go
new file mode 100644
index 00000000000000..6cc79275767c4c
--- /dev/null
+++ b/src/simd/types_amd64.go
@@ -0,0 +1,662 @@
+// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT.
+
+//go:build goexperiment.simd
+
+package simd
+
+// v128 is a tag type that tells the compiler that this is really 128-bit SIMD
+type v128 struct {
+	_128 struct{}
+}
+
+// Float32x4 is a 128-bit SIMD vector of 4 float32
+type Float32x4 struct {
+	float32x4 v128
+	vals      [4]float32
+}
+
+// Len returns the number of elements in a Float32x4
+func (x Float32x4) Len() int { return 4 }
+
+// LoadFloat32x4 loads a Float32x4 from an array
+//
+//go:noescape
+func LoadFloat32x4(y *[4]float32) Float32x4
+
+// Store stores a Float32x4 to an array
+//
+//go:noescape
+func (x Float32x4) Store(y *[4]float32)
+
+// Float64x2 is a 128-bit SIMD vector of 2 float64
+type Float64x2 struct {
+	float64x2 v128
+	vals      [2]float64
+}
+
+// Len returns the number of elements in a Float64x2
+func (x Float64x2) Len() int { return 2 }
+
+// LoadFloat64x2 loads a Float64x2 from an array
+//
+//go:noescape
+func LoadFloat64x2(y *[2]float64) Float64x2
+
+// Store stores a Float64x2 to an array
+//
+//go:noescape
+func (x Float64x2) Store(y *[2]float64)
+
+// Int8x16 is a 128-bit SIMD vector of 16 int8
+type Int8x16 struct {
+	int8x16 v128
+	vals    [16]int8
+}
+
+// Len returns the number of elements in a Int8x16
+func (x Int8x16) Len() int { return 16 }
+
+// LoadInt8x16 loads a Int8x16 from an array
+//
+//go:noescape
+func LoadInt8x16(y *[16]int8) Int8x16
+
+// Store stores a Int8x16 to an array
+//
+//go:noescape
+func (x Int8x16) Store(y *[16]int8)
+
+// Int16x8 is a 128-bit SIMD vector of 8 int16
+type Int16x8 struct {
+	int16x8 v128
+	vals    [8]int16
+}
+
+// Len returns the number of elements in a Int16x8
+func (x Int16x8) Len() int { return 8 }
+
+// LoadInt16x8 loads a Int16x8 from an array
+//
+//go:noescape
+func LoadInt16x8(y *[8]int16) Int16x8
+
+// Store stores a Int16x8 to an array
+//
+//go:noescape
+func (x Int16x8) Store(y *[8]int16)
+
+// Int32x4 is a 128-bit SIMD vector of 4 int32
+type Int32x4 struct {
+	int32x4 v128
+	vals    [4]int32
+}
+
+// Len returns the number of elements in a Int32x4
+func (x Int32x4) Len() int { return 4 }
+
+// LoadInt32x4 loads a Int32x4 from an array
+//
+//go:noescape
+func LoadInt32x4(y *[4]int32) Int32x4
+
+// Store stores a Int32x4 to an array
+//
+//go:noescape
+func (x Int32x4) Store(y *[4]int32)
+
+// Int64x2 is a 128-bit SIMD vector of 2 int64
+type Int64x2 struct {
+	int64x2 v128
+	vals    [2]int64
+}
+
+// Len returns the number of elements in a Int64x2
+func (x Int64x2) Len() int { return 2 }
+
+// LoadInt64x2 loads a Int64x2 from an array
+//
+//go:noescape
+func LoadInt64x2(y *[2]int64) Int64x2
+
+// Store stores a Int64x2 to an array
+//
+//go:noescape
+func (x Int64x2) Store(y *[2]int64)
+
+// Uint8x16 is a 128-bit SIMD vector of 16 uint8
+type Uint8x16 struct {
+	uint8x16 v128
+	vals     [16]uint8
+}
+
+// Len returns the number of elements in a Uint8x16
+func (x Uint8x16) Len() int { return 16 }
+
+// LoadUint8x16 loads a Uint8x16 from an array
+//
+//go:noescape
+func LoadUint8x16(y *[16]uint8) Uint8x16
+
+// Store stores a Uint8x16 to an array
+//
+//go:noescape
+func (x Uint8x16) Store(y *[16]uint8)
+
+// Uint16x8 is a 128-bit SIMD vector of 8 uint16
+type Uint16x8 struct {
+	uint16x8 v128
+	vals     [8]uint16
+}
+
+// Len returns the number of elements in a Uint16x8
+func (x Uint16x8) Len() int { return 8 }
+
+// LoadUint16x8 loads a Uint16x8 from an array
+//
+//go:noescape
+func LoadUint16x8(y *[8]uint16) Uint16x8
+
+// Store stores a Uint16x8 to an array
+//
+//go:noescape
+func (x Uint16x8) Store(y *[8]uint16)
+
+// Uint32x4 is a 128-bit SIMD vector of 4 uint32
+type Uint32x4 struct {
+	uint32x4 v128
+	vals     [4]uint32
+}
+
+// Len returns the number of elements in a Uint32x4
+func (x Uint32x4) Len() int { return 4 }
+
+// LoadUint32x4 loads a Uint32x4 from an array
+//
+//go:noescape
+func LoadUint32x4(y *[4]uint32) Uint32x4
+
+// Store stores a Uint32x4 to an array
+//
+//go:noescape
+func (x Uint32x4) Store(y *[4]uint32)
+
+// Uint64x2 is a 128-bit SIMD vector of 2 uint64
+type Uint64x2 struct {
+	uint64x2 v128
+	vals     [2]uint64
+}
+
+// Len returns the number of elements in a Uint64x2
+func (x Uint64x2) Len() int { return 2 }
+
+// LoadUint64x2 loads a Uint64x2 from an array
+//
+//go:noescape
+func LoadUint64x2(y *[2]uint64) Uint64x2
+
+// Store stores a Uint64x2 to an array
+//
+//go:noescape
+func (x Uint64x2) Store(y *[2]uint64)
+
+// Mask8x16 is a 128-bit SIMD vector of 16 int8
+type Mask8x16 struct {
+	int8x16 v128
+	vals    [16]int8
+}
+
+// Mask16x8 is a 128-bit SIMD vector of 8 int16
+type Mask16x8 struct {
+	int16x8 v128
+	vals    [8]int16
+}
+
+// Mask32x4 is a 128-bit SIMD vector of 4 int32
+type Mask32x4 struct {
+	int32x4 v128
+	vals    [4]int32
+}
+
+// Mask64x2 is a 128-bit SIMD vector of 2 int64
+type Mask64x2 struct {
+	int64x2 v128
+	vals    [2]int64
+}
+
+// v256 is a tag type that tells the compiler that this is really 256-bit SIMD
+type v256 struct {
+	_256 struct{}
+}
+
+// Float32x8 is a 256-bit SIMD vector of 8 float32
+type Float32x8 struct {
+	float32x8 v256
+	vals      [8]float32
+}
+
+// Len returns the number of elements in a Float32x8
+func (x Float32x8) Len() int { return 8 }
+
+// LoadFloat32x8 loads a Float32x8 from an array
+//
+//go:noescape
+func LoadFloat32x8(y *[8]float32) Float32x8
+
+// Store stores a Float32x8 to an array
+//
+//go:noescape
+func (x Float32x8) Store(y *[8]float32)
+
+// Float64x4 is a 256-bit SIMD vector of 4 float64
+type Float64x4 struct {
+	float64x4 v256
+	vals      [4]float64
+}
+
+// Len returns the number of elements in a Float64x4
+func (x Float64x4) Len() int { return 4 }
+
+// LoadFloat64x4 loads a Float64x4 from an array
+//
+//go:noescape
+func LoadFloat64x4(y *[4]float64) Float64x4
+
+// Store stores a Float64x4 to an array
+//
+//go:noescape
+func (x Float64x4) Store(y *[4]float64)
+
+// Int8x32 is a 256-bit SIMD vector of 32 int8
+type Int8x32 struct {
+	int8x32 v256
+	vals    [32]int8
+}
+
+// Len returns the number of elements in a Int8x32
+func (x Int8x32) Len() int { return 32 }
+
+// LoadInt8x32 loads a Int8x32 from an array
+//
+//go:noescape
+func LoadInt8x32(y *[32]int8) Int8x32
+
+// Store stores a Int8x32 to an array
+//
+//go:noescape
+func (x Int8x32) Store(y *[32]int8)
+
+// Int16x16 is a 256-bit SIMD vector of 16 int16
+type Int16x16 struct {
+	int16x16 v256
+	vals     [16]int16
+}
+
+// Len returns the number of elements in a Int16x16
+func (x Int16x16) Len() int { return 16 }
+
+// LoadInt16x16 loads a Int16x16 from an array
+//
+//go:noescape
+func LoadInt16x16(y *[16]int16) Int16x16
+
+// Store stores a Int16x16 to an array
+//
+//go:noescape
+func (x Int16x16) Store(y *[16]int16)
+
+// Int32x8 is a 256-bit SIMD vector of 8 int32
+type Int32x8 struct {
+	int32x8 v256
+	vals    [8]int32
+}
+
+// Len returns the number of elements in a Int32x8
+func (x Int32x8) Len() int { return 8 }
+
+// LoadInt32x8 loads a Int32x8 from an array
+//
+//go:noescape
+func LoadInt32x8(y *[8]int32) Int32x8
+
+// Store stores a Int32x8 to an array
+//
+//go:noescape
+func (x Int32x8) Store(y *[8]int32)
+
+// Int64x4 is a 256-bit SIMD vector of 4 int64
+type Int64x4 struct {
+	int64x4 v256
+	vals    [4]int64
+}
+
+// Len returns the number of elements in a Int64x4
+func (x Int64x4) Len() int { return 4 }
+
+// LoadInt64x4 loads a Int64x4 from an array
+//
+//go:noescape
+func LoadInt64x4(y *[4]int64) Int64x4
+
+// Store stores a Int64x4 to an array
+//
+//go:noescape
+func (x Int64x4) Store(y *[4]int64)
+
+// Uint8x32 is a 256-bit SIMD vector of 32 uint8
+type Uint8x32 struct {
+	uint8x32 v256
+	vals     [32]uint8
+}
+
+// Len returns the number of elements in a Uint8x32
+func (x Uint8x32) Len() int { return 32 }
+
+// LoadUint8x32 loads a Uint8x32 from an array
+//
+//go:noescape
+func LoadUint8x32(y *[32]uint8) Uint8x32
+
+// Store stores a Uint8x32 to an array
+//
+//go:noescape
+func (x Uint8x32) Store(y *[32]uint8)
+
+// Uint16x16 is a 256-bit SIMD vector of 16 uint16
+type Uint16x16 struct {
+	uint16x16 v256
+	vals      [16]uint16
+}
+
+// Len returns the number of elements in a Uint16x16
+func (x Uint16x16) Len() int { return 16 }
+
+// LoadUint16x16 loads a Uint16x16 from an array
+//
+//go:noescape
+func LoadUint16x16(y *[16]uint16) Uint16x16
+
+// Store stores a Uint16x16 to an array
+//
+//go:noescape
+func (x Uint16x16) Store(y *[16]uint16)
+
+// Uint32x8 is a 256-bit SIMD vector of 8 uint32
+type Uint32x8 struct {
+	uint32x8 v256
+	vals     [8]uint32
+}
+
+// Len returns the number of elements in a Uint32x8
+func (x Uint32x8) Len() int { return 8 }
+
+// LoadUint32x8 loads a Uint32x8 from an array
+//
+//go:noescape
+func LoadUint32x8(y *[8]uint32) Uint32x8
+
+// Store stores a Uint32x8 to an array
+//
+//go:noescape
+func (x Uint32x8) Store(y *[8]uint32)
+
+// Uint64x4 is a 256-bit SIMD vector of 4 uint64
+type Uint64x4 struct {
+	uint64x4 v256
+	vals     [4]uint64
+}
+
+// Len returns the number of elements in a Uint64x4
+func (x Uint64x4) Len() int { return 4 }
+
+// LoadUint64x4 loads a Uint64x4 from an array
+//
+//go:noescape
+func LoadUint64x4(y *[4]uint64) Uint64x4
+
+// Store stores a Uint64x4 to an array
+//
+//go:noescape
+func (x Uint64x4) Store(y *[4]uint64)
+
+// Mask8x32 is a 256-bit SIMD vector of 32 int8
+type Mask8x32 struct {
+	int8x32 v256
+	vals    [32]int8
+}
+
+// Mask16x16 is a 256-bit SIMD vector of 16 int16
+type Mask16x16 struct {
+	int16x16 v256
+	vals     [16]int16
+}
+
+// Mask32x8 is a 256-bit SIMD vector of 8 int32
+type Mask32x8 struct {
+	int32x8 v256
+	vals    [8]int32
+}
+
+// Mask64x4 is a 256-bit SIMD vector of 4 int64
+type Mask64x4 struct {
+	int64x4 v256
+	vals    [4]int64
+}
+
+// v512 is a tag type that tells the compiler that this is really 512-bit SIMD
+type v512 struct {
+	_512 struct{}
+}
+
+// Float32x16 is a 512-bit SIMD vector of 16 float32
+type Float32x16 struct {
+	float32x16 v512
+	vals       [16]float32
+}
+
+// Len returns the number of elements in a Float32x16
+func (x Float32x16) Len() int { return 16 }
+
+// LoadFloat32x16 loads a Float32x16 from an array
+//
+//go:noescape
+func LoadFloat32x16(y *[16]float32) Float32x16
+
+// Store stores a Float32x16 to an array
+//
+//go:noescape
+func (x Float32x16) Store(y *[16]float32)
+
+// Float64x8 is a 512-bit SIMD vector of 8 float64
+type Float64x8 struct {
+	float64x8 v512
+	vals      [8]float64
+}
+
+// Len returns the number of elements in a Float64x8
+func (x Float64x8) Len() int { return 8 }
+
+// LoadFloat64x8 loads a Float64x8 from an array
+//
+//go:noescape
+func LoadFloat64x8(y *[8]float64) Float64x8
+
+// Store stores a Float64x8 to an array
+//
+//go:noescape
+func (x Float64x8) Store(y *[8]float64)
+
+// Int8x64 is a 512-bit SIMD vector of 64 int8
+type Int8x64 struct {
+	int8x64 v512
+	vals    [64]int8
+}
+
+// Len returns the number of elements in a Int8x64
+func (x Int8x64) Len() int { return 64 }
+
+// LoadInt8x64 loads a Int8x64 from an array
+//
+//go:noescape
+func LoadInt8x64(y *[64]int8) Int8x64
+
+// Store stores a Int8x64 to an array
+//
+//go:noescape
+func (x Int8x64) Store(y *[64]int8)
+
+// Int16x32 is a 512-bit SIMD vector of 32 int16
+type Int16x32 struct {
+	int16x32 v512
+	vals     [32]int16
+}
+
+// Len returns the number of elements in a Int16x32
+func (x Int16x32) Len() int { return 32 }
+
+// LoadInt16x32 loads a Int16x32 from an array
+//
+//go:noescape
+func LoadInt16x32(y *[32]int16) Int16x32
+
+// Store stores a Int16x32 to an array
+//
+//go:noescape
+func (x Int16x32) Store(y *[32]int16)
+
+// Int32x16 is a 512-bit SIMD vector of 16 int32
+type Int32x16 struct {
+	int32x16 v512
+	vals     [16]int32
+}
+
+// Len returns the number of elements in a Int32x16
+func (x Int32x16) Len() int { return 16 }
+
+// LoadInt32x16 loads a Int32x16 from an array
+//
+//go:noescape
+func LoadInt32x16(y *[16]int32) Int32x16
+
+// Store stores a Int32x16 to an array
+//
+//go:noescape
+func (x Int32x16) Store(y *[16]int32)
+
+// Int64x8 is a 512-bit SIMD vector of 8 int64
+type Int64x8 struct {
+	int64x8 v512
+	vals    [8]int64
+}
+
+// Len returns the number of elements in a Int64x8
+func (x Int64x8) Len() int { return 8 }
+
+// LoadInt64x8 loads a Int64x8 from an array
+//
+//go:noescape
+func LoadInt64x8(y *[8]int64) Int64x8
+
+// Store stores a Int64x8 to an array
+//
+//go:noescape
+func (x Int64x8) Store(y *[8]int64)
+
+// Uint8x64 is a 512-bit SIMD vector of 64 uint8
+type Uint8x64 struct {
+	uint8x64 v512
+	vals     [64]uint8
+}
+
+// Len returns the number of elements in a Uint8x64
+func (x Uint8x64) Len() int { return 64 }
+
+// LoadUint8x64 loads a Uint8x64 from an array
+//
+//go:noescape
+func LoadUint8x64(y *[64]uint8) Uint8x64
+
+// Store stores a Uint8x64 to an array
+//
+//go:noescape
+func (x Uint8x64) Store(y *[64]uint8)
+
+// Uint16x32 is a 512-bit SIMD vector of 32 uint16
+type Uint16x32 struct {
+	uint16x32 v512
+	vals      [32]uint16
+}
+
+// Len returns the number of elements in a Uint16x32
+func (x Uint16x32) Len() int { return 32 }
+
+// LoadUint16x32 loads a Uint16x32 from an array
+//
+//go:noescape
+func LoadUint16x32(y *[32]uint16) Uint16x32
+
+// Store stores a Uint16x32 to an array
+//
+//go:noescape
+func (x Uint16x32) Store(y *[32]uint16)
+
+// Uint32x16 is a 512-bit SIMD vector of 16 uint32
+type Uint32x16 struct {
+	uint32x16 v512
+	vals      [16]uint32
+}
+
+// Len returns the number of elements in a Uint32x16
+func (x Uint32x16) Len() int { return 16 }
+
+// LoadUint32x16 loads a Uint32x16 from an array
+//
+//go:noescape
+func LoadUint32x16(y *[16]uint32) Uint32x16
+
+// Store stores a Uint32x16 to an array
+//
+//go:noescape
+func (x Uint32x16) Store(y *[16]uint32)
+
+// Uint64x8 is a 512-bit SIMD vector of 8 uint64
+type Uint64x8 struct {
+	uint64x8 v512
+	vals     [8]uint64
+}
+
+// Len returns the number of elements in a Uint64x8
+func (x Uint64x8) Len() int { return 8 }
+
+// LoadUint64x8 loads a Uint64x8 from an array
+//
+//go:noescape
+func LoadUint64x8(y *[8]uint64) Uint64x8
+
+// Store stores a Uint64x8 to an array
+//
+//go:noescape
+func (x Uint64x8) Store(y *[8]uint64)
+
+// Mask8x64 is a 512-bit SIMD vector of 64 int8
+type Mask8x64 struct {
+	int8x64 v512
+	vals    [64]int8
+}
+
+// Mask16x32 is a 512-bit SIMD vector of 32 int16
+type Mask16x32 struct {
+	int16x32 v512
+	vals     [32]int16
+}
+
+// Mask32x16 is a 512-bit SIMD vector of 16 int32
+type Mask32x16 struct {
+	int32x16 v512
+	vals     [16]int32
+}
+
+// Mask64x8 is a 512-bit SIMD vector of 8 int64
+type Mask64x8 struct {
+	int64x8 v512
+	vals    [8]int64
+}
diff --git a/src/sync/pool.go b/src/sync/pool.go
index 0fa8f8cdaa028d..f9a8405b791736 100644
--- a/src/sync/pool.go
+++ b/src/sync/pool.go
@@ -315,4 +315,4 @@ func runtime_procUnpin()
 func runtime_LoadAcquintptr(ptr *uintptr) uintptr
 
 //go:linkname runtime_StoreReluintptr internal/runtime/atomic.StoreReluintptr
-func runtime_StoreReluintptr(ptr *uintptr, val uintptr) uintptr
+func runtime_StoreReluintptr(ptr *uintptr, val uintptr)

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