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added support for SX1276 LoRa module
issue fossasia#62
1 parent 2c41fe7 commit 7df2c3f

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2 files changed

+303
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‎PSL/SENSORS/Sx1276.py

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# This library allows P2P connections for LoRa modules that are built with the SX1276 chip from Semtech
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# It does not implement the LoRaWAN stack, and is only meant for standalone long range communications
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# Register definitions adapted from sample code for SEMTECH SX1276
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import time
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def connect(SPI):
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return SX1276(SPI)
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class SX1276():
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name = 'SX1276'
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#********************LoRA mode***************************/
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LR_RegFifo = 0x00
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#Common settings
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LR_RegOpMode = 0x01
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LR_RegFrMsb = 0x06
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LR_RegFrMid = 0x07
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LR_RegFrLsb = 0x08
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#Tx settings
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LR_RegPaConfig = 0x09
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LR_RegPaRamp = 0x0A
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LR_RegOcp = 0x0B
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#Rx settings
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LR_RegLna = 0x0C
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#LoRa registers
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LR_RegFifoAddrPtr = 0x0D
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LR_RegFifoTxBaseAddr = 0x0E
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LR_RegFifoRxBaseAddr = 0x0F
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LR_RegFifoRxCurrentaddr = 0x10
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LR_RegIrqFlagsMask = 0x11
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LR_RegIrqFlags = 0x12
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LR_RegRxNbBytes = 0x13
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LR_RegRxHeaderCntValueMsb = 0x14
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LR_RegRxHeaderCntValueLsb = 0x15
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LR_RegRxPacketCntValueMsb = 0x16
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LR_RegRxPacketCntValueLsb = 0x17
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LR_RegModemStat = 0x18
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LR_RegPktSnrValue = 0x19
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LR_RegPktRssiValue = 0x1A
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LR_RegRssiValue = 0x1B
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LR_RegHopChannel = 0x1C
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LR_RegModemConfig1 = 0x1D
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LR_RegModemConfig2 = 0x1E
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LR_RegSymbTimeoutLsb = 0x1F
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LR_RegPreambleMsb = 0x20
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LR_RegPreambleLsb = 0x21
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LR_RegPayloadLength = 0x22
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LR_RegMaxPayloadLength = 0x23
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LR_RegHopPeriod = 0x24
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LR_RegFifoRxByteAddr = 0x25
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#I/O settings
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REG_LR_DIOMAPPING1 = 0x40
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REG_LR_DIOMAPPING2 = 0x41
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#Version
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REG_LR_VERSION = 0x42
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#Additional settings
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REG_LR_PLLHOP = 0x44
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REG_LR_TCXO = 0x4B
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REG_LR_PADAC = 0x4D
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REG_LR_FORMERTEMP = 0x5B
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REG_LR_AGCREF = 0x61
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REG_LR_AGCTHRESH1 = 0x62
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REG_LR_AGCTHRESH2 = 0x63
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REG_LR_AGCTHRESH3 = 0x64
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#/********************FSK/ook mode***************************/
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RegFIFO = 0x00 #FIFO
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RegOpMode = 0x01 #Operation mode
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RegBitRateMsb = 0x02 #BR MSB
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RegBitRateLsb = 0x03 #BR LSB
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RegFdevMsb = 0x04 #FD MSB
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RegFdevLsb = 0x05 #FD LSB
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RegFreqMsb = 0x06 #Freq MSB
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RegFreqMid = 0x07 #Freq Middle byte
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RegFreqLsb = 0x08 #Freq LSB
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RegPaConfig = 0x09
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RegPaRamp = 0x0a
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RegOcp = 0x0b
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RegLna = 0x0c
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RegRxConfig = 0x0d
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RegRssiConfig = 0x0e
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RegRssiCollision = 0x0f
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RegRssiThresh = 0x10
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RegRssiValue = 0x11
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RegRxBw = 0x12
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RegAfcBw = 0x13
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RegOokPeak = 0x14
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RegOokFix = 0x15
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RegOokAvg = 0x16
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RegAfcFei = 0x1a
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RegAfcMsb = 0x1b
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RegAfcLsb = 0x1c
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RegFeiMsb = 0x1d
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RegFeiLsb = 0x1e
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RegPreambleDetect = 0x1f
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RegRxTimeout1 = 0x20
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RegRxTimeout2 = 0x21
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RegRxTimeout3 = 0x22
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RegRxDelay = 0x23
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RegOsc = 0x24 #Set OSC
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RegPreambleMsb = 0x25
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RegPreambleLsb = 0x26
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RegSyncConfig = 0x27
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RegSyncValue1 = 0x28
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RegSyncValue2 = 0x29
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RegSyncValue3 = 0x2a
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RegSyncValue4 = 0x2b
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RegSyncValue5 = 0x2c
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RegSyncValue6 = 0x2d
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RegSyncValue7 = 0x2e
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RegSyncValue8 = 0x2f
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RegPacketConfig1 = 0x30
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RegPacketConfig2 = 0x31
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RegPayloadLength = 0x32
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RegNodeAdrs = 0x33
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RegBroadcastAdrs = 0x34
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RegFifoThresh = 0x35
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RegSeqConfig1 = 0x36
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RegSeqConfig2 = 0x37
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RegTimerResol = 0x38
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RegTimer1Coef = 0x39
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RegTimer2Coef = 0x3a
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RegImageCal = 0x3b
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RegTemp = 0x3c
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RegLowBat = 0x3d
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RegIrqFlags1 = 0x3e
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RegIrqFlags2 = 0x3f
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RegDioMapping1 = 0x40
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RegDioMapping2 = 0x41
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RegVersion = 0x42
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RegPllHop = 0x44
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RegPaDac = 0x4d
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RegBitRateFrac = 0x5d
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CR_SETTINGS = {'4_5': 0x01,'4_6': 0x02,'4_7': 0x03,'4_8': 0x04}
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sx1276_7_8FreqTbl = [[0x6C,0x80,0x00]] #434MHz
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sx1276_7_8PowerTbl = [0xFF,0xFC,0xF9,0xF6] #20dbm,17dbm,14dbm,11dbm
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sx1276_7_8SpreadFactorTbl = [6,7,8,9,10,11,12]
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#7.8KHz,10.4KHz,15.6KHz,20.8KHz,31.2KHz,41.7KHz,62.5KHz,125KHz,250KHz,500KHz
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sx1276_7_8LoRaBwTbl = [0,1,2,3,4,5,6,7,8,9]
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sampleData = [ord(a) for a in "Mark1 Lora sx1276_7_8"]
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mode = 0x01 #lora mode
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Freq_Sel = 0x00 #433M
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Power_Sel = 0x00
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Lora_Rate_Sel = 0x06
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BandWide_Sel = 0x07
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Fsk_Rate_Sel = 0x00
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def __init__(self,SPI,**args):
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self.SPI = SPI
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self.SPI.set_parameters(2,6,1,0)
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self.CR = self.CR_SETTINGS['4_5']
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self.CRC = 1
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self.name = 'SX1276'
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self.config()
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self.LoRaEntryRX();
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def standby(self):
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self.SPIWrite(self.LR_RegOpMode,[0x09]) #Low freq mode
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#self.SPIWrite(self.LR_RegOpMode,[0x01]) #High freq mode
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def sleep(self):
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self.SPIWrite(self.LR_RegOpMode,[0x08])
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def EntryLoRa(self):
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self.SPIWrite(self.LR_RegOpMode,[0x88]) #Low freq mode
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#self.SPIWrite(self.LR_RegOpMode,[0x80]) #High freq mode
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def LoRaClearIRQ(self):
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self.SPIWrite(self.LR_RegIrqFlags,[0xFF])
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def LoRaEntryRX(self):
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self.config() #setting base parameter
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self.SPIWrite(self.REG_LR_PADAC,[0x84]) #Normal and Rx
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self.SPIWrite(self.LR_RegHopPeriod,[0xFF]) #RegHopPeriod NO FHSS
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self.SPIWrite(self.REG_LR_DIOMAPPING1,[0x01]) #DIO0=00, DIO1=00, DIO2=00, DIO3=01
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self.SPIWrite(self.LR_RegIrqFlagsMask,[0x3F]) #Open RxDone interrupt & Timeout
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self.LoRaClearIRQ()
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self.SPIWrite(self.RegPayloadLength,[21]) #RegPayloadLength 21byte(this register must difine when the data long of one byte in SF is 6)
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addr = self.SPIRead(self.LR_RegFifoRxBaseAddr,1)[0] #Read RxBaseAddr
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print ('rx address',addr, self.SPIRead(self.LR_RegFifoRxCurrentaddr,1)[0])
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self.SPIWrite(self.LR_RegFifoAddrPtr,[addr]) #RxBaseAddr -> FiFoAddrPtr
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self.SPIWrite(self.LR_RegOpMode,[0x8D]) #Continuous Rx Mode//Low Frequency Mode
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#self.SPIWrite(self.LR_RegOpMode,[0x05]) #High freq mode
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while 1:
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if self.SPIRead(self.LR_RegModemStat,1)[0]&0x04 == 0x04: #Rx-on going RegModemStat
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print ('done')
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break
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print ('waiting :',time.ctime(),self.SPIRead(self.LR_RegModemStat,1))
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def LoRaReadRSSI(self):
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tmp = self.SPIRead(self.LR_RegRssiValue,1)[0]
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tmp = tmp+127-137 #127:Max RSSI, 137:RSSI offset
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return tmp
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def LoRaRxPacket(self):
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#if get_state('ID1'): #IRQ is high
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time.sleep(0.01)
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addr = self.SPIRead(self.LR_RegFifoRxCurrentaddr,1)[0] #last packet addr
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self.SPIWrite(self.LR_RegFifoAddrPtr,[addr])
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if self.sx1276_7_8SpreadFactorTbl[self.Lora_Rate_Sel] == 6: #Spread Factor = 6
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packet_size = 21
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else:
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packet_size = self.SPIRead(self.LR_RegRxNbBytes,1)[0]
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RxData = self.SPIRead(0x00,packet_size)
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self.LoRaClearIRQ()
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return RxData
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def LoRaEntryTX(self):
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length = 21
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self.config() #setting base parameter
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self.SPIWrite(self.REG_LR_PADAC,[0x87]) #Tx at 20dbm
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self.SPIWrite(self.LR_RegHopPeriod,[0x00]) #RegHopPeriod NO FHSS
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self.SPIWrite(self.REG_LR_DIOMAPPING1,[0x41]) #DIO0=01, DIO1=00, DIO2=00, DIO3=01
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self.LoRaClearIRQ()
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self.SPIWrite(self.LR_RegIrqFlagsMask,[0xF7]) #Open TxDone interrupt
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self.SPIWrite(self.RegPayloadLength,[length]) #RegPayloadLength 21byte
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addr = self.SPIRead(self.LR_RegFifoTxBaseAddr,1)[0] #Read TxBaseAddr
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print ('tx address',addr)
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self.SPIWrite(self.LR_RegFifoAddrPtr,[addr]) #TxBaseAddr -> FiFoAddrPtr
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while 1:
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if self.SPIRead(self.LR_RegPayloadLength,1)[0] == length: #Rx-on going RegModemStat
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print ('done')
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break
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print ('waiting :',time.ctime(),self.SPIRead(self.LR_RegPayloadLength,1))
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time.sleep(0.1)
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def LoRaTxPacket(self,dataArray):
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self.SPIWrite(0x00,dataArray)
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self.SPIWrite(self.LR_RegOpMode,[0x8B]) #TX Mode
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#while not self.get_state('ID1'):
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time.sleep(0.1)
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self.SPIRead(self.LR_RegIrqFlags,1)
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self.LoRaClearIRQ()
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self.standby()
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print (len(lora.sampleData),lora.sampleData)
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def ReadRSSI(self):
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tmp = self.SPIRead(self.LR_RegIrqFlagsMask,1)[0]
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tmp >>=1
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return 127-tmp
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def config(self):
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self.sleep()
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time.sleep(0.015)
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self.EntryLoRa()
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self.SPIWrite(self.LR_RegFrMsb,self.sx1276_7_8FreqTbl[self.Freq_Sel])
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self.SPIWrite(self.LR_RegPaConfig,[self.sx1276_7_8PowerTbl[self.Power_Sel]])
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self.SPIWrite(self.LR_RegOcp,[0x0B]) #Close ocp
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self.SPIWrite(self.LR_RegLna,[0x23]) #RegLNA , HIGH, LNA enable
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if self.sx1276_7_8SpreadFactorTbl[self.Lora_Rate_Sel]==6:
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self.SPIWrite(self.LR_RegModemConfig1,[(self.sx1276_7_8LoRaBwTbl[self.BandWide_Sel]<<4)+(self.CR<<1)+0x01]) # Enable CRC Enable(0x02) & Error Coding rate 4/5(0x01), 4/6(0x02), 4/7
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self.SPIWrite(self.LR_RegModemConfig2,[(self.sx1276_7_8SpreadFactorTbl[self.Lora_Rate_Sel]<<4)+(self.CRC<<2)+0x03]) # SFactor & LNA gain set by the internal AGC loop
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tmp = self.SPIRead(0x31)[0]
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tmp&=0xF8;tmp|=0x05
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self.SPIWrite(0x31,[tmp])
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self.SPIWrite(0x37,[0x0C])
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else:
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self.SPIWrite(self.LR_RegModemConfig1,[(self.sx1276_7_8LoRaBwTbl[self.BandWide_Sel]<<4)+(self.CR<<1)+0x00])
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self.SPIWrite(self.LR_RegModemConfig2,[(self.sx1276_7_8SpreadFactorTbl[self.Lora_Rate_Sel]<<4)+(self.CRC<<2)+0x03])
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self.SPIWrite(self.LR_RegSymbTimeoutLsb,[0xFF]) #Max timeout
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self.SPIWrite(self.LR_RegPreambleMsb,[0x00])
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self.SPIWrite(self.LR_RegPreambleLsb,[12]) #RegPreambleLsb 8+4=12byte Preamble
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self.SPIWrite(self.REG_LR_DIOMAPPING2,[0x01]) #RegDioMapping2 DIO5=00, DIO4=01
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self.standby()
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def SPIWrite(self,adr,byteArray):
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return self.SPI.xfer('CS1',[0x80|adr]+byteArray)[1:]
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def SPIRead(self,adr,total_bytes):
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return self.SPI.xfer('CS1',[adr]+[0]*total_bytes)[1:]
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def getRaw(self):
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val = self.SPIRead(0x02,1)
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return val
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‎PSL/sciencelab.py

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4143,12 +4143,15 @@ def raiseException(self, ex, msg):
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41444144

41454145
if __name__ == "__main__":
4146-
print("""this is not an executable file
4146+
print("""this is not an executable file
41474147
from PSL import sciencelab
41484148
I=sciencelab.connect()
41494149
eg.
41504150
I.get_average_voltage('CH1')
41514151
""")
4152-
# I=connect(verbose = True)
4153-
# for a in range(20):print (I.get_capacitance())
4154-
# I=connect(verbose=True,load_calibration=False)
4152+
I=connect(verbose = True)
4153+
t = time.time()
4154+
for a in range(100):
4155+
s = I.read_flash(3,a)
4156+
#print(s.replace('\n','.'),len(s))
4157+
print (time.time()-t)

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