diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 139fa7ba35625..3d46e68e06950 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21062,7 +21062,7 @@ RISCVTargetLowering::getTargetConstantFromLoad(LoadSDNode *Ld) const {
// Simple case, LLA.
if (Ptr.getOpcode() == RISCVISD::LLA) {
- auto *CNode = GetSupportedConstantPool(Ptr);
+ auto *CNode = GetSupportedConstantPool(Ptr.getOperand(0));
if (!CNode || CNode->getTargetFlags() != 0)
return nullptr;
diff --git a/llvm/test/CodeGen/RISCV/constpool-known-bits.ll b/llvm/test/CodeGen/RISCV/constpool-known-bits.ll
new file mode 100644
index 0000000000000..85a6de1095a03
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/constpool-known-bits.ll
@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -O0 -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=NOPIC
+; RUN: llc < %s -O0 -mtriple=riscv64 -mattr=+m -relocation-model=pic | FileCheck %s --check-prefix=PIC
+
+define i64 @test(i32 noundef signext %c, i32 noundef signext %d) {
+; NOPIC-LABEL: test:
+; NOPIC: # %bb.0: # %entry
+; NOPIC-NEXT: # kill: def $x11 killed $x10
+; NOPIC-NEXT: slli a0, a0, 32
+; NOPIC-NEXT: srli a1, a0, 32
+; NOPIC-NEXT: lui a0, %hi(.LCPI0_0)
+; NOPIC-NEXT: ld a0, %lo(.LCPI0_0)(a0)
+; NOPIC-NEXT: mul a0, a1, a0
+; NOPIC-NEXT: addi a0, a0, 127
+; NOPIC-NEXT: mul a0, a1, a0
+; NOPIC-NEXT: lui a2, %hi(.LCPI0_1)
+; NOPIC-NEXT: ld a2, %lo(.LCPI0_1)(a2)
+; NOPIC-NEXT: mul a0, a0, a2
+; NOPIC-NEXT: add a0, a0, a1
+; NOPIC-NEXT: lui a1, 1015920
+; NOPIC-NEXT: addi a1, a1, 1541
+; NOPIC-NEXT: slli a1, a1, 16
+; NOPIC-NEXT: addi a1, a1, 1027
+; NOPIC-NEXT: slli a1, a1, 20
+; NOPIC-NEXT: add a0, a0, a1
+; NOPIC-NEXT: ret
+;
+; PIC-LABEL: test:
+; PIC: # %bb.0: # %entry
+; PIC-NEXT: # kill: def $x11 killed $x10
+; PIC-NEXT: slli a0, a0, 32
+; PIC-NEXT: srli a1, a0, 32
+; PIC-NEXT: .Lpcrel_hi0:
+; PIC-NEXT: auipc a0, %pcrel_hi(.LCPI0_0)
+; PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi0)
+; PIC-NEXT: ld a0, 0(a0)
+; PIC-NEXT: mul a0, a1, a0
+; PIC-NEXT: addi a0, a0, 127
+; PIC-NEXT: mul a0, a1, a0
+; PIC-NEXT: .Lpcrel_hi1:
+; PIC-NEXT: auipc a2, %pcrel_hi(.LCPI0_1)
+; PIC-NEXT: addi a2, a2, %pcrel_lo(.Lpcrel_hi1)
+; PIC-NEXT: ld a2, 0(a2)
+; PIC-NEXT: mul a0, a0, a2
+; PIC-NEXT: add a0, a0, a1
+; PIC-NEXT: lui a1, 1015920
+; PIC-NEXT: addi a1, a1, 1541
+; PIC-NEXT: slli a1, a1, 16
+; PIC-NEXT: addi a1, a1, 1027
+; PIC-NEXT: slli a1, a1, 20
+; PIC-NEXT: add a0, a0, a1
+; PIC-NEXT: ret
+entry:
+ %or1 = or i64 -9191740941672644608, 4096
+ %or2 = or i64 -9191740941672644608, 8192
+ %or3 = or i64 -9191740941672644608, 16384
+ %conv = zext i32 %c to i64
+ %donv = zext i32 %d to i64
+ %3 = mul i64 %or1, %conv
+ %4 = mul i64 %or2, %donv
+ %5 = mul i64 %or3, %conv
+ %6 = add i64 %3, %4
+ %7 = add i64 %6, %5
+ %8 = or i64 %5, 127
+ %9 = mul i64 %3, %8
+ %add = add i64 -9191740941672644608, %9
+ %add2 = add i64 %add, %conv
+ ret i64 %add2
+}
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