py/nlrriscv32: Add floating-point support.

esmil · esmil · commit 2260074c424f · 2020-09-30T19:39:23.000+02:00
This should work, but for now it has only been compile-tested
diff --git a/py/nlr.h b/py/nlr.h
@@ -78,7 +78,15 @@
     #define MICROPY_NLR_NUM_REGS (128)
 #elif defined(__riscv_xlen) && __riscv_xlen == 32
     #define MICROPY_NLR_RISCV32 (1)
+    #ifndef __riscv_flen
     #define MICROPY_NLR_NUM_REGS (14)
+    #elif __riscv_flen == 32
+    #define MICROPY_NLR_NUM_REGS (14 + 12)
+    #elif __riscv_flen == 64
+    #define MICROPY_NLR_NUM_REGS (14 + 24)
+    #else
+    #error Unimplemented __riscv_flen
+    #endif
 #else
     #define MICROPY_NLR_SETJMP (1)
     //#warning "No native NLR support for this arch, using setjmp implementation"
diff --git a/py/nlrriscv32.c b/py/nlrriscv32.c
@@ -31,7 +31,7 @@
 #undef nlr_push
 
 // For reference, riscv callee save regs are:
-//      s0-s11, ra and sp
+//      s0-s11, ra, sp and fs0-fs11
 
 __attribute__((naked)) unsigned int nlr_push(nlr_buf_t *nlr) {
 
@@ -50,6 +50,34 @@ __attribute__((naked)) unsigned int nlr_push(nlr_buf_t *nlr) {
         "sw    s11,   44+%0    \n" // store s11 into nlr->regs
         "sw    ra,    48+%0    \n" // store ra into nlr->regs
         "sw    sp,    52+%0    \n" // store sp into nlr->regs
+        #ifndef __riscv_flen
+        #elif __riscv_flen == 32
+        "fsw   fs0,   56+%0    \n" // store fs0 into nlr->regs
+        "fsw   fs1,   60+%0    \n" // store fs1 into nlr->regs
+        "fsw   fs2,   64+%0    \n" // store fs2 into nlr->regs
+        "fsw   fs3,   68+%0    \n" // store fs3 into nlr->regs
+        "fsw   fs4,   72+%0    \n" // store fs4 into nlr->regs
+        "fsw   fs5,   76+%0    \n" // store fs5 into nlr->regs
+        "fsw   fs6,   80+%0    \n" // store fs6 into nlr->regs
+        "fsw   fs7,   84+%0    \n" // store fs7 into nlr->regs
+        "fsw   fs8,   88+%0    \n" // store fs8 into nlr->regs
+        "fsw   fs9,   92+%0    \n" // store fs9 into nlr->regs
+        "fsw   fs10,  96+%0    \n" // store fs10 into nlr->regs
+        "fsw   fs11, 100+%0    \n" // store fs11 into nlr->regs
+        #elif __riscv_flen == 64
+        "fsd   fs0,   56+%0    \n" // store fs0 into nlr->regs
+        "fsd   fs1,   64+%0    \n" // store fs1 into nlr->regs
+        "fsd   fs2,   72+%0    \n" // store fs2 into nlr->regs
+        "fsd   fs3,   80+%0    \n" // store fs3 into nlr->regs
+        "fsd   fs4,   88+%0    \n" // store fs4 into nlr->regs
+        "fsd   fs5,   96+%0    \n" // store fs5 into nlr->regs
+        "fsd   fs6,  104+%0    \n" // store fs6 into nlr->regs
+        "fsd   fs7,  112+%0    \n" // store fs7 into nlr->regs
+        "fsd   fs8,  120+%0    \n" // store fs8 into nlr->regs
+        "fsd   fs9,  128+%0    \n" // store fs9 into nlr->regs
+        "fsd   fs10, 136+%0    \n" // store fs10 into nlr->regs
+        "fsd   fs11, 144+%0    \n" // store fs11 into nlr->regs
+        #endif
         "tail  nlr_push_tail   \n" // do the rest in C
         : "=o" (nlr->regs)
         );
@@ -77,6 +105,34 @@ NORETURN void nlr_jump(void *val) {
         "lw    s10,   40+%0    \n" // load s10 from top->regs
         "lw    s11,   44+%0    \n" // load s11 from top->regs
         "lw    ra,    48+%0    \n" // load ra from top->regs
+        #ifndef __riscv_flen
+        #elif __riscv_flen == 32
+        "flw   fs0,   56+%0    \n" // load fs0 from top->regs
+        "flw   fs1,   60+%0    \n" // load fs1 from top->regs
+        "flw   fs2,   64+%0    \n" // load fs2 from top->regs
+        "flw   fs3,   68+%0    \n" // load fs3 from top->regs
+        "flw   fs4,   72+%0    \n" // load fs4 from top->regs
+        "flw   fs5,   76+%0    \n" // load fs5 from top->regs
+        "flw   fs6,   80+%0    \n" // load fs6 from top->regs
+        "flw   fs7,   84+%0    \n" // load fs7 from top->regs
+        "flw   fs8,   88+%0    \n" // load fs8 from top->regs
+        "flw   fs9,   92+%0    \n" // load fs9 from top->regs
+        "flw   fs10,  96+%0    \n" // load fs10 from top->regs
+        "flw   fs11, 100+%0    \n" // load fs11 from top->regs
+        #elif __riscv_flen == 64
+        "fld   fs0,   56+%0    \n" // load fs0 from top->regs
+        "fld   fs1,   64+%0    \n" // load fs1 from top->regs
+        "fld   fs2,   72+%0    \n" // load fs2 from top->regs
+        "fld   fs3,   80+%0    \n" // load fs3 from top->regs
+        "fld   fs4,   88+%0    \n" // load fs4 from top->regs
+        "fld   fs5,   96+%0    \n" // load fs5 from top->regs
+        "fld   fs6,  104+%0    \n" // load fs6 from top->regs
+        "fld   fs7,  112+%0    \n" // load fs7 from top->regs
+        "fld   fs8,  120+%0    \n" // load fs8 from top->regs
+        "fld   fs9,  128+%0    \n" // load fs9 from top->regs
+        "fld   fs10, 136+%0    \n" // load fs10 from top->regs
+        "fld   fs11, 144+%0    \n" // load fs11 from top->regs
+        #endif
         "lw    sp,    52+%0    \n" // load sp from top->regs
         "li    a0,   1         \n" // return 1, non-local return
         "ret                   \n" // return
