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tests/run-tests, ports/qemu-riscv, README: Add QEMU RV32 port.
This adds a QEMU-based bare metal RISC-V 32 bits port. For the time being only QEMU's "virt" 32 bits board is supported, using the ilp32 ABI and the RV32IMC architecture. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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‎README.md

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@@ -114,7 +114,8 @@ In addition, the following ports are provided in this repository:
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- [nrf](ports/nrf) -- Nordic Semiconductor nRF51 and nRF52.
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- [pic16bit](ports/pic16bit) -- Microchip PIC 16-bit.
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- [powerpc](ports/powerpc) -- IBM PowerPC (including Microwatt)
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- [qemu-arm](ports/qemu-arm) -- QEMU-based emulated target, for testing)
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- [qemu-arm](ports/qemu-arm) -- QEMU-based Arm emulated target (for testing)
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- [qemu-riscv](ports/qemu-riscv) -- QEMU-based RISC-V emulated target (for testing)
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- [renesas-ra](ports/renesas-ra) -- Renesas RA family.
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- [rp2](ports/rp2) -- Raspberry Pi RP2040 (including Pico and Pico W).
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- [samd](ports/samd) -- Microchip (formerly Atmel) SAMD21 and SAMD51.

‎ports/qemu-riscv/Makefile

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include ../../py/mkenv.mk
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-include mpconfigport.mk
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# qstr definitions (must come before including py.mk)
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QSTR_DEFS = qstrdefsport.h
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# MicroPython feature configurations
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MICROPY_ROM_TEXT_COMPRESSION ?= 1
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# include py core make definitions
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include $(TOP)/py/py.mk
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include $(TOP)/extmod/extmod.mk
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BOARD ?= virt
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CROSS_COMPILE ?= riscv64-unknown-elf-
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GCC_VERSION = $(word 1, $(subst ., , $(shell $(CC) -dumpversion)))
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# If Picolibc is available then select it explicitly. Ubuntu 22.04 ships its
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# bare metal RISC-V toolchain with Picolibc rather than Newlib, and the default
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# is "nosys" so a value must be provided. To avoid having per-distro
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# workarounds, always select Picolibc if available.
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PICOLIBC_SPECS = $(shell $(CC) --print-file-name=picolibc.specs)
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ifeq ($(PICOLIBC_SPECS),picolibc.specs)
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# Picolibc was not found.
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SPECS_FRAGMENT =
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else
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SPECS_FRAGMENT = --specs=$(PICOLIBC_SPECS)
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CFLAGS += $(SPECS_FRAGMENT)
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endif
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ifeq ($(BOARD),virt)
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ABI = ilp32
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# GCC 10 and lower do not recognise the Zicsr extension in the
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# architecture name. "Make" unfortunately does not provide any simple way
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# to perform numeric comparisons, so to keep things simple we assume that
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# GCC is at least version 10 for the time being.
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ifeq ($(GCC_VERSION),10)
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ARCH ?= rv32imac
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else
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# Recent GCC versions explicitly require to declare extensions.
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ARCH ?= rv32imac_zicsr
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ARCH_LD ?= rv32imac_zicsr
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endif
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AFLAGS = -mabi=$(ABI) -march=$(ARCH)
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CFLAGS += $(AFLAGS)
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CFLAGS += -DQEMU_SOC_VIRT
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ARCH_LD ?= $(ARCH)
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LDSCRIPT = virt.ld
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LDFLAGS += -mabi=$(ABI) -march=$(ARCH_LD) -T $(LDSCRIPT) -Wl,-EL
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SRC_BOARD_O = shared/runtime/gchelper_native.o shared/runtime/gchelper_rv32i.o
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SRC_BOARD_O += entrypoint.o
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endif
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INC += -I.
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INC += -I$(TOP)
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INC += -I$(BUILD)
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CFLAGS += $(INC) -Wall -Wpointer-arith -Wdouble-promotion -Wfloat-conversion -Werror -std=gnu99 $(COPT) \
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-ffunction-sections -fdata-sections
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CFLAGS += $(CFLAGS_EXTRA)
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LD = $(CC)
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# Debugging/Optimization
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ifeq ($(DEBUG), 1)
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CFLAGS += -g
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COPT = -O0
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else
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COPT += -Os -DNDEBUG
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endif
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LDFLAGS += $(SPECS_FRAGMENT) -Wl,--gc-sections -Wl,-Map=$(@:.elf=.map)
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SRC_COMMON_C = \
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interrupts.c \
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startup.c \
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uart.c \
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shared/libc/string0.c \
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shared/runtime/sys_stdio_mphal.c \
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SRC_RUN_C = \
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ports/qemu-arm/main.c \
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SRC_TEST_C = \
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test_main.c \
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lib/tinytest/tinytest.c \
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LIB_SRC_C += $(SRC_LIB_LIBM_C)
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LIB_SRC_C += $(SRC_LIB_LIBM_SQRT_SW_C)
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OBJ_COMMON =
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OBJ_COMMON += $(PY_O)
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OBJ_COMMON += $(addprefix $(BUILD)/, $(SRC_COMMON_C:.c=.o))
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OBJ_COMMON += $(addprefix $(BUILD)/, $(SRC_BOARD_O))
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OBJ_COMMON += $(addprefix $(BUILD)/, $(LIB_SRC_C:.c=.o))
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OBJ_RUN =
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OBJ_RUN += $(addprefix $(BUILD)/, $(SRC_RUN_C:.c=.o))
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ALL_OBJ_RUN = $(OBJ_COMMON) $(OBJ_RUN)
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OBJ_TEST =
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OBJ_TEST += $(addprefix $(BUILD)/, $(SRC_TEST_C:.c=.o))
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ALL_OBJ_TEST = $(OBJ_COMMON) $(OBJ_TEST)
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# All object files, needed to get dependencies correct
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OBJ = $(OBJ_COMMON) $(OBJ_RUN) $(OBJ_TEST)
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# List of sources for qstr extraction
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SRC_QSTR += $(SRC_COMMON_C) $(SRC_RUN_C) $(LIB_SRC_C)
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all: run
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# `make debug` will block QEMU until a debugger is connected to port 1234.
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debug: $(BUILD)/firmware.elf
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qemu-system-riscv32 -machine $(BOARD) -bios none $(QEMU_EXTRA) -nographic -monitor null -semihosting -serial mon:stdio -S -s -kernel $<
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run: $(BUILD)/firmware.elf
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qemu-system-riscv32 -machine $(BOARD) -bios none $(QEMU_EXTRA) -nographic -monitor null -semihosting -kernel $<
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$(BUILD)/firmware.elf: $(LDSCRIPT) $(ALL_OBJ_RUN)
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$(Q)$(LD) $(LDFLAGS) -o $@ $(ALL_OBJ_RUN) $(LIBS)
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$(Q)$(SIZE) $@
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include $(TOP)/py/mkrules.mk

‎ports/qemu-riscv/Makefile.test

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LIB_SRC_C = shared/upytesthelper/upytesthelper.c
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include Makefile
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CFLAGS += -DTEST
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.PHONY: $(BUILD)/genhdr/tests.h
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TESTS_PROFILE = $(dir $(abspath $(firstword $(MAKEFILE_LIST))))/tests_profile.txt
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$(BUILD)/test_main.o: $(BUILD)/genhdr/tests.h
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$(BUILD)/genhdr/tests.h:
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(cd $(TOP)/tests; ./run-tests.py --target=qemu-riscv --write-exp)
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$(Q)echo "Generating $@";(cd $(TOP)/tests; ../tools/tinytest-codegen.py --profile $(TESTS_PROFILE) $(addprefix --exclude ,$(TESTS_EXCLUDE))) > $@
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$(BUILD)/lib/tinytest/tinytest.o: CFLAGS += -DNO_FORKING
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$(BUILD)/firmware-test.elf: $(LDSCRIPT) $(ALL_OBJ_TEST)
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$(Q)$(LD) $(LDFLAGS) -o $@ $(ALL_OBJ_TEST) $(LIBS)
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$(Q)$(SIZE) $@
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# Note: Using timeout(1) to handle cases where qemu hangs (e.g. this can happen with alignment errors).
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test: $(BUILD)/firmware-test.elf
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timeout --foreground -k 5s 60s qemu-system-riscv32 -machine $(BOARD) -bios none $(QEMU_EXTRA) -nographic -monitor null -semihosting -kernel $< > $(BUILD)/console.out
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$(Q)tail -n2 $(BUILD)/console.out
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$(Q)tail -n1 $(BUILD)/console.out | grep -q "status: 0"
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# `make debugtest` will block QEMU until a debugger is connected to port 1234.
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debugtest: $(BUILD)/firmware-test.elf
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qemu-system-riscv32 -machine $(BOARD) -bios none $(QEMU_EXTRA) -nographic -monitor null -semihosting -serial mon:stdio -S -s -kernel $<

‎ports/qemu-riscv/README.md

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This is an experimental, community-supported port for RISC-V RV32IMC emulation
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as provided by QEMU (http://qemu.org).
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The purposes of this port are to enable:
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1. Continuous integration
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- run tests against architecture-specific parts of code base
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2. Experimentation
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- simulation & prototyping of anything that has architecture-specific
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code
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- exploring instruction set in terms of optimising some part of
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MicroPython or a module
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3. Streamlined debugging
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- no need for JTAG or even an MCU chip itself
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- no need to use OpenOCD or anything else that might slow down the
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process in terms of plugging things together, pressing buttons, etc.
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This port requires a bare metal RISC-V toolchain with GCC 10 or later, either
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with multilib support or 32 bits specific (M, C, and Zicsr extensions must be
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supported, along with ilp32 ABI). Both newlib and picolibc are supported,
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with the latter having precedence if found.
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Most pre-built toolchains should work out of the box, either coming from your
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Linux distribution's package manager, or independently packaged ones like
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[xPack](https://xpack.github.io/dev-tools/riscv-none-elf-gcc/).
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To build and run the image with builtin testsuite:
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make -f Makefile.test test

‎ports/qemu-riscv/entrypoint.s

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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2023 Alessandro Gatti
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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.section .start
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.option norvc /* Do not emit compressed instructions. */
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.type start, @function
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.global start
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start:
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.cfi_startproc
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.option push
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.option norelax
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la gp, _global_pointer /* Load global pointer register. */
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.option pop
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csrw satp, zero /* Disable supervisor mode. */
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/* Fill stack with a canary value. */
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li t0, 0xBBBBBBBB /* Load canary value. */
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la t1, _sstack /* Load stack area start address. */
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la t2, _estack /* Load stack area end address. */
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1:
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sw t0, (t1) /* Write canary. */
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addi t1, t1, 4 /* Next word. */
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bltu t1, t2, 1b /* Loop until stack is filled. */
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la sp, _estack /* Load stack pointer. */
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/* Clear BSS area. */
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la t1, _sbss /* Load BSS area start address. */
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la t2, _ebss /* Load BSS area end address. */
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1:
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sw zero, (t1) /* Clear word. */
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addi t1, t1, 4 /* Next word. */
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bltu t1, t2, 1b /* Loop until BSS is cleared. */
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/* Set program counter. */
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la t0, _entry_point /* Load program counter address. */
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csrw mepc, t0 /* Store it into machine exception PC. */
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tail _entry_point /* Jump to entry point. */
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.cfi_endproc
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.end

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