mimxrt/flexspi_nor_c: Set the flash CLK frequency on boot.

robert-hh · robert-hh · commit b40abbcf4b92 · 2025-02-05T20:06:23.000+01:00
The flash clock frequency may have been set to a different value by
a bootloader. Set the frequency according to the configured value.
Use a table of pre-calculated dividers for PFD_480 and the flespi
PODF to get the closest value for the flash frequency, achieving:

  30 -&gt; 30.85 MHz
  50 -&gt; 49.65 MHz
  60 -&gt; 60 MHz
  75 -&gt; 75.13 MHz
  80 -&gt; 80 MHz
  100 -&gt; 99.31 Mhz
  133 -&gt; 132.92 MHz
  166  -&gt; 166.15 MHz

Signed-off-by: robert-hh &lt;robert@hammelrath.com&gt;
diff --git a/ports/mimxrt/flash.c b/ports/mimxrt/flash.c
@@ -29,7 +29,8 @@
 void flash_init(void) {
     // Upload the custom flash configuration
     // And fix the entry for PAGEPROGRAM_QUAD
-    flexspi_nor_update_lut();
+    // Update the flash CLK
+    flexspi_nor_update_lut_clk();
 
     // Configure FLEXSPI IP FIFO access.
     BOARD_FLEX_SPI->MCR0 &= ~(FLEXSPI_MCR0_ARDFEN_MASK);
diff --git a/ports/mimxrt/hal/flexspi_hyper_flash.c b/ports/mimxrt/hal/flexspi_hyper_flash.c
@@ -9,7 +9,7 @@
 #include "fsl_clock.h"
 #include "flexspi_hyper_flash.h"
 
-void flexspi_nor_update_lut(void) {
+void flexspi_nor_update_lut_clk(void) {
 }
 
 // Copy of a few (pseudo-)functions from fsl_clock.h, which were nor reliably
diff --git a/ports/mimxrt/hal/flexspi_nor_flash.c b/ports/mimxrt/hal/flexspi_nor_flash.c
@@ -38,6 +38,9 @@
 #include "flexspi_nor_flash.h"
 #include "flexspi_flash_config.h"
 
+bool flash_busy_status_pol = 0;
+bool flash_busy_status_offset = 0;
+
 uint32_t LUT_pageprogram_quad[4] = {
     // 10 Page Program - quad mode
     FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32, RADDR_SDR, FLEXSPI_1PAD, 24),
@@ -54,16 +57,69 @@ uint32_t LUT_write_status[4] = {
     FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),         // Filler
 };
 
-void flexspi_nor_update_lut(void) {
+#if !defined(MIMXRT117x_SERIES)
+typedef struct _ps_div_t {
+    uint8_t pfd480_div;
+    uint8_t podf_div;
+} ps_div_t;
+
+static ps_div_t div_table_mhz[] = {
+    { 35, 8 }, // Entry 0 is out of range
+    { 35, 8 }, // 30 -> 30.85 MHz
+    { 29, 6 }, // 50 -> 49.65 MHz
+    { 18, 8 }, // 60 -> 60 MHz
+    { 23, 5 }, // 75 -> 75.13 MHz
+    { 18, 6 }, // 80 -> 80 MHz
+    { 29, 3 }, // 100 -> 99.31 Mhz
+    { 13, 5 }, // 133 -> 132.92 MHz
+    { 26, 2 }  // 166  -> 166.15 MHz
+};
+#endif
+
+__attribute__((section(".ram_functions"))) void flexspi_nor_update_lut_clk(void) {
+    // Create a local copy of the LookupTable. Modify the entry for WRITESTATUSREG
+    // Add an entry for PAGEPROGRAM_QUAD.
     uint32_t lookuptable_copy[64];
     memcpy(lookuptable_copy, (const uint32_t *)&qspiflash_config.memConfig.lookupTable, 64 * sizeof(uint32_t));
-    // write WRITESTATUSREG code to entry 10
+    // write local WRITESTATUSREG code to index 4
     memcpy(&lookuptable_copy[NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG * 4],
         LUT_write_status, 4 * sizeof(uint32_t));
-    // write PAGEPROGRAM_QUAD code to entry 10
+    // write local PAGEPROGRAM_QUAD code to index 10
     memcpy(&lookuptable_copy[NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD * 4],
         LUT_pageprogram_quad, 4 * sizeof(uint32_t));
+    // Update the LookupTable.
     FLEXSPI_UpdateLUT(BOARD_FLEX_SPI, 0, lookuptable_copy, 64);
+
+    #if !defined(MIMXRT117x_SERIES)
+    volatile uint8_t pfd480_div = div_table_mhz[MICROPY_HW_FLASH_CLK].pfd480_div;
+    volatile uint8_t podf_div = div_table_mhz[MICROPY_HW_FLASH_CLK].podf_div - 1;
+
+    __DSB();
+    __ISB();
+    __disable_irq();
+    SCB_DisableDCache();
+    while (!FLEXSPI_GetBusIdleStatus(BOARD_FLEX_SPI)) {
+    }
+    FLEXSPI_Enable(BOARD_FLEX_SPI, false);
+
+    // Disable FlexSPI clock
+    CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK;
+    // Changing the clock is OK now.
+    // Change the PFD
+    CCM_ANALOG->PFD_480 = (CCM_ANALOG->PFD_480 & ~CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) | CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(pfd480_div);
+    // Change the flexspi divider
+    CCM->CSCMR1 = (CCM->CSCMR1 & ~CCM_CSCMR1_FLEXSPI_PODF_MASK) | CCM_CSCMR1_FLEXSPI_PODF(podf_div);
+    // Re-enable FlexSPI
+    CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
+
+    FLEXSPI_Enable(BOARD_FLEX_SPI, true);
+    FLEXSPI_SoftwareReset(BOARD_FLEX_SPI);
+    while (!FLEXSPI_GetBusIdleStatus(BOARD_FLEX_SPI)) {
+    }
+
+    SCB_EnableDCache();
+    __enable_irq();
+    #endif
 }
 
 void flexspi_nor_reset(FLEXSPI_Type *base) __attribute__((section(".ram_functions")));
diff --git a/ports/mimxrt/hal/flexspi_nor_flash.h b/ports/mimxrt/hal/flexspi_nor_flash.h
@@ -46,7 +46,7 @@ extern flexspi_nor_config_t qspiflash_config;
 
 status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId);
 status_t flexspi_nor_init(void);
-void flexspi_nor_update_lut(void);
+void flexspi_nor_update_lut_clk(void);
 status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base);
 status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address);
 status_t flexspi_nor_flash_erase_block(FLEXSPI_Type *base, uint32_t address);

Original file line number	Diff line number	Diff line change
`@@ -9,7 +9,7 @@`
`9`	`9`	`#include "fsl_clock.h"`
`10`	`10`	`#include "flexspi_hyper_flash.h"`
`11`	`11`
`12`		`-void flexspi_nor_update_lut(void) {`
	`12`	`+void flexspi_nor_update_lut_clk(void) {`
`13`	`13`	`}`
`14`	`14`
`15`	`15`	`// Copy of a few (pseudo-)functions from fsl_clock.h, which were nor reliably`