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tests/run-tests, ports/qemu-riscv: Add QEMU RV32 port.
This adds a QEMU-based bare metal RISC-V 32 bits port. For the time being only QEMU's "virt" 32 bits board is supported, using the ilp32 ABI and the RV32IMC architecture. Tests run and pass, and the test generator framework was modified to remove hardcoded references to the "qemu-arm" port. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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‎ports/qemu-riscv/Makefile

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include ../../py/mkenv.mk
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-include mpconfigport.mk
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# qstr definitions (must come before including py.mk)
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QSTR_DEFS = qstrdefsport.h
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# MicroPython feature configurations
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MICROPY_ROM_TEXT_COMPRESSION ?= 1
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# include py core make definitions
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include $(TOP)/py/py.mk
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include $(TOP)/extmod/extmod.mk
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CROSS_COMPILE ?= riscv64-unknown-elf-
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BOARD ?= virt
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LDFLAGS = --gc-sections -Map=$(@:.elf=.map)
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LIBS = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
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ifeq ($(BOARD),virt)
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ABI=ilp32
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ARCH=rv32imc_zicsr
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AFLAGS = -mabi=$(ABI) -march=$(ARCH)
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CFLAGS += -mabi=$(ABI) -fPIC -mlittle-endian -march=$(ARCH) -mcmodel=medany
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CFLAGS += -DQEMU_SOC_VIRT
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LDSCRIPT = virt.ld
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LDFLAGS += -T $(LDSCRIPT) -m elf32lriscv
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SRC_BOARD_O = shared/runtime/gchelper_generic.o setjmp.o
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SRC_BOARD_O += entry.o
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endif
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INC += -I.
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INC += -I$(TOP)
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INC += -I$(BUILD)
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CFLAGS += $(INC) -Wall -Wpointer-arith -Wdouble-promotion -Wfloat-conversion -Werror -std=gnu99 $(COPT) \
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-ffunction-sections -fdata-sections
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CFLAGS += $(CFLAGS_EXTRA)
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# Debugging/Optimization
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ifeq ($(DEBUG), 1)
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CFLAGS += -g
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COPT = -O0
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else
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COPT += -Os -DNDEBUG
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endif
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SRC_COMMON_C = \
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interrupts.c \
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startup.c \
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uart.c \
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modmachine.c \
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shared/libc/string0.c \
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shared/runtime/sys_stdio_mphal.c \
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SRC_RUN_C = \
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main.c \
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SRC_TEST_C = \
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test_main.c \
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lib/tinytest/tinytest.c \
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LIB_SRC_C += $(addprefix lib/,\
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libm/math.c \
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libm/fmodf.c \
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libm/nearbyintf.c \
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libm/ef_sqrt.c \
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libm/kf_rem_pio2.c \
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libm/kf_sin.c \
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libm/kf_cos.c \
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libm/kf_tan.c \
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libm/ef_rem_pio2.c \
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libm/sf_sin.c \
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libm/sf_cos.c \
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libm/sf_tan.c \
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libm/sf_frexp.c \
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libm/sf_modf.c \
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libm/sf_ldexp.c \
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libm/asinfacosf.c \
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libm/atanf.c \
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libm/atan2f.c \
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libm/roundf.c \
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)
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OBJ_COMMON =
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OBJ_COMMON += $(PY_O)
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OBJ_COMMON += $(addprefix $(BUILD)/, $(SRC_COMMON_C:.c=.o))
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OBJ_COMMON += $(addprefix $(BUILD)/, $(SRC_BOARD_O))
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OBJ_COMMON += $(addprefix $(BUILD)/, $(LIB_SRC_C:.c=.o))
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OBJ_RUN =
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OBJ_RUN += $(addprefix $(BUILD)/, $(SRC_RUN_C:.c=.o))
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ALL_OBJ_RUN = $(OBJ_COMMON) $(OBJ_RUN)
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OBJ_TEST =
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OBJ_TEST += $(addprefix $(BUILD)/, $(SRC_TEST_C:.c=.o))
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ALL_OBJ_TEST = $(OBJ_COMMON) $(OBJ_TEST)
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# All object files, needed to get dependencies correct
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OBJ = $(OBJ_COMMON) $(OBJ_RUN) $(OBJ_TEST)
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# List of sources for qstr extraction
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SRC_QSTR += $(SRC_COMMON_C) $(SRC_RUN_C) $(LIB_SRC_C)
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all: run
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debug: $(BUILD)/firmware.elf
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qemu-system-riscv32 -machine $(BOARD) -bios none $(QEMU_EXTRA) -nographic -monitor null -semihosting -serial mon:stdio -S -s -kernel $<
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run: $(BUILD)/firmware.elf
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qemu-system-riscv32 -machine $(BOARD) -bios none $(QEMU_EXTRA) -nographic -monitor null -semihosting -kernel $<
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## `$(LD)` doesn't seem to like `--specs` for some reason, but we can just use `$(CC)` here.
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$(BUILD)/firmware.elf: $(LDSCRIPT) $(ALL_OBJ_RUN)
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$(Q)$(LD) $(LDFLAGS) -o $@ $(ALL_OBJ_RUN) $(LIBS)
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$(Q)$(SIZE) $@
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include $(TOP)/py/mkrules.mk

‎ports/qemu-riscv/Makefile.test

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LIB_SRC_C = shared/upytesthelper/upytesthelper.c
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include Makefile
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ifeq ($(BOARD),virt)
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TESTS_EXCLUDE = extmod/deflate_decompress.py
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endif
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CFLAGS += -DTEST
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.PHONY: $(BUILD)/genhdr/tests.h
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TESTS_PROFILE = $(dir $(abspath $(firstword $(MAKEFILE_LIST))))/tests_profile.txt
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$(BUILD)/test_main.o: $(BUILD)/genhdr/tests.h
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$(BUILD)/genhdr/tests.h:
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(cd $(TOP)/tests; ./run-tests.py --target=qemu-riscv --write-exp)
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$(Q)echo "Generating $@";(cd $(TOP)/tests; ../tools/tinytest-codegen.py --profile $(TESTS_PROFILE) $(addprefix --exclude ,$(TESTS_EXCLUDE))) > $@
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$(BUILD)/lib/tinytest/tinytest.o: CFLAGS += -DNO_FORKING
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$(BUILD)/firmware-test.elf: $(LDSCRIPT) $(ALL_OBJ_TEST)
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$(Q)$(LD) $(LDFLAGS) -o $@ $(ALL_OBJ_TEST) $(LIBS)
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$(Q)$(SIZE) $@
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# Note: Using timeout(1) to handle cases where qemu hangs (e.g. this can happen with alignment errors).
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test: $(BUILD)/firmware-test.elf
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timeout --foreground -k 5s 60s qemu-system-riscv32 -machine $(BOARD) -bios none $(QEMU_EXTRA) -nographic -monitor null -semihosting -kernel $< > $(BUILD)/console.out
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$(Q)tail -n2 $(BUILD)/console.out
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$(Q)tail -n1 $(BUILD)/console.out | grep -q "status: 0"
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debugtest: $(BUILD)/firmware-test.elf
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qemu-system-riscv32 -machine $(BOARD) -bios none $(QEMU_EXTRA) -nographic -monitor null -semihosting -serial mon:stdio -S -s -kernel $<
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‎ports/qemu-riscv/README.md

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This is experimental, community-supported port for RISC-V RV32IM emulation as
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provided by QEMU (http://qemu.org).
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The purposes of this port are to enable:
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1. Continuous integration
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- run tests against architecture-specific parts of code base
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2. Experimentation
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- simulation & prototyping of anything that has architecture-specific
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code
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- exploring instruction set in terms of optimising some part of
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MicroPython or a module
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3. Streamlined debugging
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- no need for JTAG or even an MCU chip itself
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- no need to use OpenOCD or anything else that might slow down the
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process in terms of plugging things together, pressing buttons, etc.
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This port requires a newlib based bare metal/ELF RISC-V toolchain, either
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with multilib support or 32 bits specific (M, C, and Zicsr extensions must
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be supported, along with ilp32 ABI). Either musl-based or glibc-based
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toolchains are not tested or known to work.
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If your toolchain does not support the above requirements, either download
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a pre-built toolchain (and that's a hit or miss situation in its own right)
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or follow the instructions on [RISC-V's reference toolchain Github repo](https://github.com/riscv-collab/riscv-gnu-toolchain)
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to get a newlib-based multilib toolchain (the target will be
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`riscv64-unknown-elf` but said toolchain will be able to generate 32 bits
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code as well).
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That said, when in doubt, build your own toolchain - it's the fastest way to
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get things going for sure.
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To build and run image with builtin testsuite:
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make -f Makefile.test test

‎ports/qemu-riscv/entry.s

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/*
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Adapted from https://wiki.osdev.org/RISC-V_Bare_Bones#entry.S
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According to the page history, this content was added after 20110703, and
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following the text found at https://wiki.osdev.org/OSDev_Wiki:License the
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overall licence for this code is as follows:
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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.section .init
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.option norvc
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.type start, @function
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.global start
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start:
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.cfi_startproc
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.option push
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.option norelax
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la gp, global_pointer
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.option pop
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csrw satp, zero
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la sp, stack_top
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la t5, bss_start
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la t6, bss_end
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bss_clear:
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sw zero, (t5)
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addi t5, t5, 4
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bltu t5, t6, bss_clear
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la t0, _entry_point
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csrw mepc, t0
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tail _entry_point
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.cfi_endproc
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.end
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