+
+void ra_gpt_timer_start(uint32_t ch);
+void ra_gpt_timer_stop(uint32_t ch);
+void ra_gpt_timer_set_freq(uint32_t ch, float freq);
+float ra_gpt_timer_get_freq(uint32_t ch);
+void ra_gpt_timer_set_period(uint32_t ch, uint32_t ns);
+uint32_t ra_gpt_timer_get_period(uint32_t ch);
+void ra_gpt_timer_set_duty(uint32_t ch, uint8_t id, uint32_t duty);
+uint32_t ra_gpt_timer_get_duty(uint32_t ch, uint8_t id);
+void ra_gpt_timer_init(uint32_t pwm_pin, uint32_t ch, uint8_t id, uint32_t duty, float freq);
+void ra_gpt_timer_deinit(uint32_t pwm_pin, uint32_t ch, uint8_t id);
+bool ra_gpt_timer_is_pwm_pin(uint32_t pin);
+
+#endif /* RA_RA_GPT_H_ */
diff --git a/ports/renesas-ra/ra/ra_i2c.c b/ports/renesas-ra/ra/ra_i2c.c
index ad1e3a74e0de3..46b1ed7c30ee4 100644
--- a/ports/renesas-ra/ra/ra_i2c.c
+++ b/ports/renesas-ra/ra/ra_i2c.c
@@ -305,11 +305,16 @@ static void ra_i2c_clock_calc(uint32_t baudrate, uint8_t *cks, uint8_t *brh, uin
*cks = 1;
*brh = 9;
*brl = 20;
- } else {
+ } else if (baudrate >= 100000) {
// assume clock is 100000Hz (PCLKB 32MHz)
*cks = 3;
*brh = 15;
*brl = 18;
+ } else {
+ // assume clock is 50000Hz (PCLKB 32MHz)
+ *cks = 4;
+ *brh = 15;
+ *brl = 18;
}
#elif defined(RA6M1)
// PCLKB 60MHz SCLE=0
@@ -458,7 +463,9 @@ static void ra_i2c_iceri_isr(R_IIC0_Type *i2c_inst) {
}
// Check Start
if (i2c_inst->ICSR2_b.START != 0) {
- action->m_status = RA_I2C_STATUS_Started;
+ if (action->m_status == RA_I2C_STATUS_Idle) {
+ action->m_status = RA_I2C_STATUS_Started;
+ }
i2c_inst->ICSR2_b.START = 0;
}
// Check Stop
@@ -504,8 +511,8 @@ static void ra_i2c_icrxi_isr(R_IIC0_Type *i2c_inst) {
static void ra_i2c_ictxi_isr(R_IIC0_Type *i2c_inst) {
xaction_t *action = current_xaction;
xaction_unit_t *unit = current_xaction_unit;
-
- if (action->m_status == RA_I2C_STATUS_Started) {
+ // When STIE is already checked. When TIE occurs before STIE
+ if (action->m_status == RA_I2C_STATUS_Started || action->m_status == RA_I2C_STATUS_Idle) {
i2c_inst->ICDRT = action->m_address; // I2C send slave address
action->m_status = RA_I2C_STATUS_AddrWriteCompleted;
return;
diff --git a/ports/renesas-ra/ra/ra_spi.c b/ports/renesas-ra/ra/ra_spi.c
index 096519ffd6402..b41503d3179c7 100644
--- a/ports/renesas-ra/ra/ra_spi.c
+++ b/ports/renesas-ra/ra/ra_spi.c
@@ -141,6 +141,102 @@ static const ra_af_pin_t sck_pins[] = {
};
#define SCK_PINS_SIZE sizeof(sck_pins) / sizeof(ra_af_pin_t)
+typedef struct ra_ssl_pin {
+ uint8_t ssln;
+ uint32_t pin;
+} ra_ssl_pin_t;
+
+static const ra_ssl_pin_t ssl_pins[] = {
+ #if defined(RA4M1)
+
+ { 0, P103 }, /* SSLA0 */
+ { 1, P104 }, /* SSLA1 */
+ { 2, P105 }, /* SSLA2 */
+ { 3, P106 }, /* SSLA3 */
+ { 0, P108 }, /* SSLB0 */
+ { 0, P112 }, /* SSLB0 */
+
+ { 0, P205 }, /* SSLB0 */
+ { 1, P206 }, /* SSLB1 */
+
+ { 1, P300 }, /* SSLB1 */
+ { 2, P301 }, /* SSLB2 */
+ { 3, P302 }, /* SSLB3 */
+
+ { 3, P407 }, /* SSLB3 */
+ { 0, P413 }, /* SSLA0 */
+ { 1, P414 }, /* SSLA1 */
+ { 2, P415 }, /* SSLA2 */
+
+ #elif defined(RA4W1)
+
+ { 0, P103 }, /* SSLA0 */
+ { 1, P104 }, /* SSLA1 */
+ { 2, P105 }, /* SSLA2 */
+ { 3, P106 }, /* SSLA3 */
+ { 0, P108 }, /* SSLB0 */
+
+ { 0, P205 }, /* SSLB0 */
+ { 1, P206 }, /* SSLB1 */
+
+ { 1, P300 }, /* SSLB1 */
+
+ { 3, P407 }, /* SSLB3 */
+ { 1, P414 }, /* SSLA1 */
+
+ #elif defined(RA6M1)
+
+ { 0, P103 }, /* SSLA0_A */
+ { 1, P104 }, /* SSLA1_A */
+ { 2, P105 }, /* SSLA2_A */
+ { 3, P106 }, /* SSLA3_A */
+ { 0, P108 }, /* SSLB0_B */
+ { 0, P112 }, /* SSLB0_B */
+
+ { 1, P300 }, /* SSLB1_B */
+ { 2, P301 }, /* SSLB2_B */
+ { 3, P302 }, /* SSLB3_B */
+
+ { 0, P413 }, /* SSLA0_B */
+ { 1, P414 }, /* SSLA1_B */
+ { 2, P415 }, /* SSLA2_B */
+
+ { 3, P708 }, /* SSLA3_B */
+
+ #elif defined(RA6M2) || defined(RA6M3)
+
+ { 0, P103 }, /* SSLA0_A */
+ { 1, P104 }, /* SSLA1_A */
+ { 2, P105 }, /* SSLA2_A */
+ { 3, P106 }, /* SSLA3_A */
+ { 0, P108 }, /* SSLB0_B */
+ { 0, P112 }, /* SSLB0_B */
+
+ { 0, P205 }, /* SSLB0_A */
+ { 1, P206 }, /* SSLB1_A */
+ { 2, P207 }, /* SSLB2_A */
+
+ { 1, P300 }, /* SSLB1_B */
+ { 2, P301 }, /* SSLB2_B */
+ { 3, P302 }, /* SSLB3_B */
+
+ { 3, P406 }, /* SSLB3_C */
+ { 3, P407 }, /* SSLB3_A */
+ { 0, P413 }, /* SSLA0_B */
+ { 1, P414 }, /* SSLA1_B */
+ { 2, P415 }, /* SSLA2_B */
+
+ { 0, P703 }, /* SSLB0_C */
+ { 1, P704 }, /* SSLB1_C */
+ { 2, P705 }, /* SSLB2_C */
+ { 3, P708 }, /* SSLA3_B */
+
+ #else
+ #error "CMSIS MCU Series is not specified."
+ #endif
+};
+#define SSL_PINS_SIZE sizeof(ssl_pins) / sizeof(ra_ssl_pin_t)
+
bool ra_af_find_ch(ra_af_pin_t *af_pin, uint32_t size, uint32_t pin, uint8_t *ch) {
bool find = false;
uint32_t i;
@@ -178,6 +274,25 @@ bool ra_spi_find_af_ch(uint32_t mosi, uint32_t miso, uint32_t sck, uint8_t *ch)
return find;
}
+static bool ra_spi_pin_to_ssln(uint32_t pin, uint8_t *ssln) {
+ ra_ssl_pin_t *ssl_pin = (ra_ssl_pin_t *)&ssl_pins;
+ bool find = false;
+ uint32_t i;
+ for (i = 0; i < SSL_PINS_SIZE; i++) {
+ if (ssl_pin->pin == pin) {
+ find = true;
+ if (find) {
+ *ssln = ssl_pin->ssln;
+ } else {
+ *ssln = 0;
+ }
+ break;
+ }
+ ssl_pin++;
+ }
+ return find;
+}
+
static void ra_spi_module_start(uint32_t ch) {
if (ch == 0) {
ra_mstpcrb_start(R_MSTP_MSTPCRB_MSTPB19_Msk);
@@ -202,7 +317,7 @@ static void ra_spi_set_pin(uint32_t pin, bool miso) {
}
}
-void ra_spi_set_bits(uint32_t ch, uint32_t bits) {
+static void ra_spi_set_bits(uint32_t ch, uint32_t bits) {
R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
if (bits == 8) {
spi_reg->SPDCR_b.SPBYT = 1;
@@ -219,17 +334,7 @@ void ra_spi_set_bits(uint32_t ch, uint32_t bits) {
}
}
-void ra_spi_set_clk(uint32_t ch, uint32_t baud) {
- R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
- if (baud == 0) {
- return;
- }
- spi_reg->SPCR_b.SPE = 0;
- spi_reg->SPBR = (PCLK / 2 / baud) - 1;
- spi_reg->SPCR_b.SPE = 1;
-}
-
-void ra_spi_set_lsb_first(uint32_t ch, uint32_t lsb_first) {
+static void ra_spi_set_lsb_first(uint32_t ch, uint32_t lsb_first) {
R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
if (lsb_first) {
spi_reg->SPCMD_b[0].LSBF = 1; // LSB first
@@ -238,7 +343,7 @@ void ra_spi_set_lsb_first(uint32_t ch, uint32_t lsb_first) {
}
}
-void ra_spi_set_mode(uint32_t ch, uint32_t polarity, uint32_t phase) {
+static void ra_spi_set_mode(uint32_t ch, uint32_t polarity, uint32_t phase) {
R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
if (polarity != 0) {
// CPOL(Clock Polarity)
@@ -254,18 +359,6 @@ void ra_spi_set_mode(uint32_t ch, uint32_t polarity, uint32_t phase) {
}
}
-void ra_spi_set_ch(uint32_t ch) {
- R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
- spi_reg->SPCR = 0x00; // disable SPI
- spi_reg->SPSR = 0xa0;
- spi_reg->SPPCR = 0x00; // fixed idle value, disable loop-back mode
- spi_reg->SPSCR = 0x00; // Disable sequence control
- spi_reg->SPDCR = 0x40; // SPBYT=1, SPLW=0 byte access
- spi_reg->SPCMD[0] = 0xe700; // LSBF=0, SPB=7, BRDV=0, CPOL=0, CPHA=0
- spi_reg->SPCR2 = 0x10;
- spi_reg->SPCR = 0x48; // Start SPI in master mode
-}
-
uint8_t ra_spi_write_byte(uint32_t ch, uint8_t b) {
R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
while (spi_reg->SPSR_b.SPTEF == 0) {
@@ -280,7 +373,6 @@ uint8_t ra_spi_write_byte(uint32_t ch, uint8_t b) {
void ra_spi_write_bytes8(uint32_t ch, uint8_t *buf, uint32_t count) {
R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
- ra_spi_set_bits(ch, 8);
while (count-- > 0) {
while (spi_reg->SPSR_b.SPTEF == 0) {
;
@@ -295,7 +387,6 @@ void ra_spi_write_bytes8(uint32_t ch, uint8_t *buf, uint32_t count) {
void ra_spi_read_bytes8(uint32_t ch, uint8_t *buf, uint32_t count) {
R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
- ra_spi_set_bits(ch, 8);
while (count-- > 0) {
while (spi_reg->SPSR_b.SPTEF == 0) {
;
@@ -310,7 +401,6 @@ void ra_spi_read_bytes8(uint32_t ch, uint8_t *buf, uint32_t count) {
void ra_spi_write_bytes16(uint32_t ch, uint16_t *buf, uint32_t count) {
R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
- ra_spi_set_bits(ch, 16);
while (count-- > 0) {
while (spi_reg->SPSR_b.SPTEF == 0) {
;
@@ -325,7 +415,6 @@ void ra_spi_write_bytes16(uint32_t ch, uint16_t *buf, uint32_t count) {
void ra_spi_write_bytes32(uint32_t ch, uint32_t *buf, uint32_t count) {
R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
- ra_spi_set_bits(ch, 32);
while (count-- > 0) {
while (spi_reg->SPSR_b.SPTEF == 0) {
;
@@ -350,7 +439,6 @@ void ra_spi_write_bytes(uint32_t ch, uint32_t bits, uint8_t *buf, uint32_t count
void ra_spi_transfer8(uint32_t ch, uint8_t *dst, uint8_t *src, uint32_t count) {
R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
- ra_spi_set_bits(ch, 8);
while (count-- > 0) {
while (spi_reg->SPSR_b.SPTEF == 0) {
;
@@ -359,13 +447,16 @@ void ra_spi_transfer8(uint32_t ch, uint8_t *dst, uint8_t *src, uint32_t count) {
while (spi_reg->SPSR_b.SPRF == 0) {
;
}
- *dst++ = (uint8_t)(spi_reg->SPDR_BY);
+ if (dst) {
+ *dst++ = (uint8_t)(spi_reg->SPDR_BY);
+ } else {
+ spi_reg->SPDR_BY;
+ }
}
}
void ra_spi_transfer16(uint32_t ch, uint16_t *dst, uint16_t *src, uint32_t count) {
R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
- ra_spi_set_bits(ch, 16);
while (count-- > 0) {
while (spi_reg->SPSR_b.SPTEF == 0) {
;
@@ -374,13 +465,16 @@ void ra_spi_transfer16(uint32_t ch, uint16_t *dst, uint16_t *src, uint32_t count
while (spi_reg->SPSR_b.SPRF == 0) {
;
}
- *dst++ = (uint16_t)(spi_reg->SPDR_HA);
+ if (dst) {
+ *dst++ = (uint16_t)(spi_reg->SPDR_HA);
+ } else {
+ spi_reg->SPDR_HA;
+ }
}
}
void ra_spi_transfer32(uint32_t ch, uint32_t *dst, uint32_t *src, uint32_t count) {
R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
- ra_spi_set_bits(ch, 32);
while (count-- > 0) {
while (spi_reg->SPSR_b.SPTEF == 0) {
;
@@ -389,7 +483,11 @@ void ra_spi_transfer32(uint32_t ch, uint32_t *dst, uint32_t *src, uint32_t count
while (spi_reg->SPSR_b.SPRF == 0) {
;
}
- *dst++ = (uint32_t)(spi_reg->SPDR);
+ if (dst) {
+ *dst++ = (uint32_t)(spi_reg->SPDR);
+ } else {
+ spi_reg->SPDR;
+ }
}
}
@@ -421,18 +519,50 @@ void ra_spi_get_conf(uint32_t ch, uint16_t *spcmd, uint8_t *spbr) {
*spbr = spi_reg->SPBR;
}
-void ra_spi_init(uint32_t ch, uint32_t mosi, uint32_t miso, uint32_t sck, uint32_t cs, uint32_t baud, uint32_t bits, uint32_t polarity, uint32_t phase) {
- ra_gpio_mode_output(cs);
- ra_gpio_write(cs, 1);
+void ra_spi_init(uint32_t ch, uint32_t mosi, uint32_t miso, uint32_t sck, uint32_t cs, uint32_t baud, uint32_t bits, uint32_t polarity, uint32_t phase, uint32_t firstbit) {
+ R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
+ uint8_t ssln = 0;
+ uint8_t sslp = 0;
+
+ ra_spi_pin_to_ssln(cs, &ssln);
+ sslp &= ~0x0fU;
+ sslp |= (uint8_t)polarity << ssln;
+
ra_spi_module_start(ch);
+
+ spi_reg->SPSR; // dummy read to clear OVRF
+ spi_reg->SPSR = 0xa0; // clear all status
+
+ spi_reg->SPCR = 0x00; // disable SPI
+ spi_reg->SSLP = sslp; // select slave active polarity
+ spi_reg->SPPCR = 0x00; // fixed idle value, disable loop-back mode
+ spi_reg->SPBR = (PCLK / 2 / baud) - 1; // Set baudrate
+ spi_reg->SPDCR = 0x40; // SPBYT=1, SPLW=0 byte access
+ spi_reg->SPCKD = 0x00; // 1RSPCK
+ spi_reg->SPDCR = 0x00; // 1RSPCK
+ spi_reg->SPND = 0x00; // 1RSPCK + 2PCLKA
+ spi_reg->SPCR2 = 0x10; // SCKASE=1
+ spi_reg->SPSCR = 0x00; // Disable sequence control
+ spi_reg->SPCMD[0] = (0xe700 | (ssln << 4)); // LSBF=0, SPB=7, SSLA:ssln, BRDV=0, CPOL=0, CPHA=0
+ spi_reg->SPDCR2 = 0x00; // BYSW=0, SINV=0(RA6M5)
+
+ /* set other setting */
+ ra_spi_set_mode(ch, polarity, phase);
+ ra_spi_set_bits(ch, bits);
+ ra_spi_set_lsb_first(ch, firstbit);
+
+ /* NIVC, DMAC setting */
+
+ /* I/O port setting */
ra_spi_set_pin(mosi, false);
ra_spi_set_pin(miso, true);
ra_spi_set_pin(sck, false);
- ra_spi_set_mode(ch, polarity, phase);
- ra_spi_set_ch(ch);
- ra_spi_set_clk(ch, baud);
- ra_spi_set_bits(ch, bits);
- ra_spi_set_lsb_first(ch, 0); // MSB first
+ ra_spi_set_pin(cs, false);
+
+
+ spi_reg->SPCR = 0x48; // Start SPI in master mode
+ spi_reg->SPCR; // wait for completion
+
return;
}
diff --git a/ports/renesas-ra/ra/ra_spi.h b/ports/renesas-ra/ra/ra_spi.h
index e75acf8701bb9..c33120a863d28 100644
--- a/ports/renesas-ra/ra/ra_spi.h
+++ b/ports/renesas-ra/ra/ra_spi.h
@@ -34,16 +34,6 @@
bool ra_af_find_ch(ra_af_pin_t *af_pin, uint32_t size, uint32_t pin, uint8_t *ch);
bool ra_spi_find_af_ch(uint32_t mosi, uint32_t miso, uint32_t sck, uint8_t *ch);
-// static void ra_spi_module_start(uint32_t ch);
-// static void ra_spi_module_stop(uint32_t ch);
-// static void ra_spi_set_pin(uint8_t pin);
-
-void ra_spi_set_bits(uint32_t ch, uint32_t bits);
-void ra_spi_set_clk(uint32_t ch, uint32_t baud);
-void ra_spi_set_lsb_first(uint32_t ch, uint32_t lsb_first);
-void ra_spi_set_mode(uint32_t ch, uint32_t polarity, uint32_t phase);
-void ra_spi_set_ch(uint32_t ch);
-
uint8_t ra_spi_write_byte(uint32_t ch, uint8_t b);
void ra_spi_read_bytes8(uint32_t ch, uint8_t *buf, uint32_t count);
void ra_spi_write_bytes8(uint32_t ch, uint8_t *buf, uint32_t count);
@@ -57,7 +47,7 @@ void ra_spi_transfer(uint32_t ch, uint32_t bits, uint8_t *dst, uint8_t *src, uin
void ra_spi_start_xfer(uint32_t ch, uint16_t spcmd, uint8_t spbr);
void ra_spi_end_xfer(uint32_t ch);
void ra_spi_get_conf(uint32_t ch, uint16_t *spcmd, uint8_t *spbr);
-void ra_spi_init(uint32_t ch, uint32_t mosi, uint32_t miso, uint32_t sck, uint32_t cs, uint32_t baud, uint32_t bits, uint32_t polarity, uint32_t phase);
+void ra_spi_init(uint32_t ch, uint32_t mosi, uint32_t miso, uint32_t sck, uint32_t cs, uint32_t baud, uint32_t bits, uint32_t polarity, uint32_t phase, uint32_t firstbit);
void ra_spi_deinit(uint32_t ch, uint32_t cs);
#endif /* RA_RA_SPI_H_ */
diff --git a/ports/renesas-ra/spi.h b/ports/renesas-ra/spi.h
index 47d9c13567e36..04be9f9b64e2b 100644
--- a/ports/renesas-ra/spi.h
+++ b/ports/renesas-ra/spi.h
@@ -34,11 +34,8 @@
#define SPI_TRANSFER_TIMEOUT(len) ((len) + 100)
void spi_init0(void);
-void spi_init(uint32_t ch);
void spi_deinit(uint32_t ch);
int spi_find_index(mp_obj_t id);
-void spi_set_params(uint32_t ch, int32_t baudrate,
- int32_t polarity, int32_t phase, int32_t bits, int32_t firstbit);
void spi_transfer(uint32_t ch, uint32_t bits, size_t len, const uint8_t *src, uint8_t *dest, uint32_t timeout);
#endif // MICROPY_INCLUDED_RA_SPI_H
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