diff --git a/ports/stm32/boards/WEACT_STM32H743/bdev.c b/ports/stm32/boards/WEACT_STM32H743/bdev.c
new file mode 100644
index 0000000000000..c55326d5e199a
--- /dev/null
+++ b/ports/stm32/boards/WEACT_STM32H743/bdev.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Matt Trentini
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "storage.h"
+#include "qspi.h"
+
+#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
+// Shared cache for first and second SPI block devices
+static mp_spiflash_cache_t spi_bdev_cache;
+#endif
+
+// First external SPI flash uses hardware QSPI interface
+const mp_spiflash_config_t spiflash_config = {
+ .bus_kind = MP_SPIFLASH_BUS_QSPI,
+ .bus.u_qspi.data = NULL,
+ .bus.u_qspi.proto = &qspi_proto,
+ #if MICROPY_HW_SPIFLASH_ENABLE_CACHE
+ .cache = &spi_bdev_cache,
+ #endif
+};
+
+spi_bdev_t spi_bdev;
diff --git a/ports/stm32/boards/WEACT_STM32H743/board.json b/ports/stm32/boards/WEACT_STM32H743/board.json
new file mode 100644
index 0000000000000..c87863e39c715
--- /dev/null
+++ b/ports/stm32/boards/WEACT_STM32H743/board.json
@@ -0,0 +1,13 @@
+{
+ "deploy": [
+ "deploy.md"
+ ],
+ "features": ["External Flash", "DAC", "Display","microSD", "USB", "USB-C"],
+ "images": [
+ "weact_stm32h743.jpg"
+ ],
+ "mcu": "STM32H743VIT6",
+ "product": "WeAct Studio STM32H743",
+ "url": "https://github.com/WeActStudio/MiniSTM32H7xx",
+ "vendor": "WeAct Studio"
+}
diff --git a/ports/stm32/boards/WEACT_STM32H743/deploy.md b/ports/stm32/boards/WEACT_STM32H743/deploy.md
new file mode 100644
index 0000000000000..a4572bfe30617
--- /dev/null
+++ b/ports/stm32/boards/WEACT_STM32H743/deploy.md
@@ -0,0 +1,19 @@
+### WeAct Studio STM32H7xx
+
+WeAct Studio make a number of STM32H7xx-based boards, they can all be updated
+using
+[DFU](https://en.wikipedia.org/wiki/USB?useskin=vector#Device_Firmware_Upgrade_mechanism).
+
+### DFU update
+
+Hold the Boot button - the middle of the cluster of three buttons - while the
+board is reset (either by connecting USB or by pressing reset). Release the Boot
+button shortly after the board has reset. The board ought to now be in DFU mode
+and detectable as such from a connected computer.
+
+Use a tool like [`dfu-util`](https://dfu-util.sourceforge.net/) to update the
+firmware:
+
+```bash
+dfu-util --alt 0 -D firmware.dfu
+```
diff --git a/ports/stm32/boards/WEACT_STM32H743/manifest.py b/ports/stm32/boards/WEACT_STM32H743/manifest.py
new file mode 100644
index 0000000000000..7d163e1847964
--- /dev/null
+++ b/ports/stm32/boards/WEACT_STM32H743/manifest.py
@@ -0,0 +1,4 @@
+include("$(PORT_DIR)/boards/manifest.py")
+
+# Currently this file is a placeholder.
+# It would be good to extend to add an LCD driver.
diff --git a/ports/stm32/boards/WEACT_STM32H743/mpconfigboard.h b/ports/stm32/boards/WEACT_STM32H743/mpconfigboard.h
new file mode 100644
index 0000000000000..ebbbc0bbf0827
--- /dev/null
+++ b/ports/stm32/boards/WEACT_STM32H743/mpconfigboard.h
@@ -0,0 +1,146 @@
+/*
+ * The MIT License (MIT)
+ * Copyright (c) 2023 Matt Trentini
+ */
+
+#define MICROPY_HW_BOARD_NAME "WEACT_STM32H743"
+#define MICROPY_HW_MCU_NAME "STM32H743VIT6"
+#define MICROPY_HW_FLASH_FS_LABEL "WEACT_STM32H743"
+
+#define MICROPY_FATFS_EXFAT (1)
+#define MICROPY_HW_ENABLE_RTC (1)
+#define MICROPY_HW_ENABLE_RNG (1)
+#define MICROPY_HW_ENABLE_ADC (1)
+#define MICROPY_HW_ENABLE_DAC (1)
+#define MICROPY_HW_ENABLE_USB (1)
+#define MICROPY_HW_HAS_SWITCH (1)
+#define MICROPY_HW_HAS_FLASH (1)
+#define MICROPY_HW_ENABLE_SERVO (1)
+#define MICROPY_HW_ENABLE_TIMER (1)
+#define MICROPY_HW_ENABLE_SDCARD (1)
+#define MICROPY_HW_ENABLE_MMCARD (0)
+
+// Flash storage config
+#define MICROPY_HW_SPIFLASH_ENABLE_CACHE (1)
+#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0)
+
+// Clock config
+#define MICROPY_HW_CLK_PLLM (5)
+#define MICROPY_HW_CLK_PLLN (160)
+#define MICROPY_HW_CLK_PLLP (2)
+#define MICROPY_HW_CLK_PLLQ (4)
+#define MICROPY_HW_CLK_PLLR (2)
+#define MICROPY_HW_CLK_PLLVCI (RCC_PLL1VCIRANGE_1)
+#define MICROPY_HW_CLK_PLLVCO (RCC_PLL1VCOWIDE)
+#define MICROPY_HW_CLK_PLLFRAC (0)
+
+#define MICROPY_HW_CLK_PLL3M (25)
+#define MICROPY_HW_CLK_PLL3N (240)
+#define MICROPY_HW_CLK_PLL3P (2)
+#define MICROPY_HW_CLK_PLL3Q (5)
+#define MICROPY_HW_CLK_PLL3R (2)
+#define MICROPY_HW_CLK_PLL3VCI (RCC_PLL3VCIRANGE_1)
+#define MICROPY_HW_CLK_PLL3VCO (RCC_PLL3VCOWIDE)
+#define MICROPY_HW_CLK_PLL3FRAC (0)
+
+// 32kHz crystal for RTC
+#define MICROPY_HW_RTC_USE_LSE (1)
+#define MICROPY_HW_RTC_USE_US (0)
+
+#if (MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE == 0)
+// W25Q64 for storage
+#define MICROPY_HW_QSPI_PRESCALER (2) // 100 MHz
+#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (26)
+#define MICROPY_HW_SPIFLASH_SIZE_BITS (64 * 1024 * 1024)
+#define MICROPY_HW_QSPIFLASH_CS (pin_B6)
+#define MICROPY_HW_QSPIFLASH_SCK (pin_B2)
+#define MICROPY_HW_QSPIFLASH_IO0 (pin_D11)
+#define MICROPY_HW_QSPIFLASH_IO1 (pin_D12)
+#define MICROPY_HW_QSPIFLASH_IO2 (pin_E2)
+#define MICROPY_HW_QSPIFLASH_IO3 (pin_D13)
+
+// SPI flash, block device config
+extern const struct _mp_spiflash_config_t spiflash_config;
+extern struct _spi_bdev_t spi_bdev;
+#define MICROPY_HW_BDEV_IOCTL(op, arg) ( \
+ (op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \
+ (op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \
+ spi_bdev_ioctl(&spi_bdev, (op), (arg)) \
+ )
+#define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n))
+#define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n))
+#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev)
+#endif
+
+// 4 wait states
+#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_2
+
+// UART
+#define MICROPY_HW_UART1_TX (pin_A9)
+#define MICROPY_HW_UART1_RX (pin_A10)
+
+#define MICROPY_HW_UART2_TX (pin_A2)
+#define MICROPY_HW_UART2_RX (pin_A3)
+
+// I2C buses
+#define MICROPY_HW_I2C1_SCL (pin_B8)
+#define MICROPY_HW_I2C1_SDA (pin_B9)
+
+#define MICROPY_HW_I2C2_SCL (pin_B10)
+#define MICROPY_HW_I2C2_SDA (pin_B11)
+
+// SPI buses
+// NOTE: SPI3 is used for the QSPI flash.
+#define MICROPY_HW_SPI1_NSS (pin_A4)
+#define MICROPY_HW_SPI1_SCK (pin_A5)
+#define MICROPY_HW_SPI1_MISO (pin_A6)
+#define MICROPY_HW_SPI1_MOSI (pin_A7)
+
+#define MICROPY_HW_SPI2_NSS (pin_B12)
+#define MICROPY_HW_SPI2_SCK (pin_B13)
+#define MICROPY_HW_SPI2_MISO (pin_B14)
+#define MICROPY_HW_SPI2_MOSI (pin_B15)
+
+#define MICROPY_HW_SPI4_NSS (pin_E11)
+#define MICROPY_HW_SPI4_SCK (pin_E12)
+#define MICROPY_HW_SPI4_MOSI (pin_E14)
+#define MICROPY_HW_SPI4_MISO (pin_E13)
+// https://community.st.com/t5/embedded-software-mcus/issue-with-bootloader-on-stm32h743-using-boot0-and-inline/td-p/73183
+
+// CAN buses
+#define MICROPY_HW_CAN1_TX (pin_B9)
+#define MICROPY_HW_CAN1_RX (pin_B8)
+
+// USRSW
+#define MICROPY_HW_USRSW_PIN (pin_C13) // K1 on the board.
+#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL)
+#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING)
+#define MICROPY_HW_USRSW_PRESSED (0)
+
+// LEDs
+#define MICROPY_HW_LED1 (pin_E3) // the only controllable LED on the board.
+#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
+#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin))
+
+// SD Card SDMMC
+#define MICROPY_HW_SDCARD_SDMMC (1)
+#define MICROPY_HW_SDCARD_CK (pin_C12)
+#define MICROPY_HW_SDCARD_CMD (pin_D2)
+#define MICROPY_HW_SDCARD_D0 (pin_C8)
+#define MICROPY_HW_SDCARD_D1 (pin_C9)
+#define MICROPY_HW_SDCARD_D2 (pin_C10)
+#define MICROPY_HW_SDCARD_D3 (pin_C11)
+
+// USB config
+#define MICROPY_HW_USB_FS (1)
+
+// Ethernet via RMII
+#define MICROPY_HW_ETH_MDC (pin_C1)
+#define MICROPY_HW_ETH_MDIO (pin_A2)
+#define MICROPY_HW_ETH_RMII_REF_CLK (pin_A1)
+#define MICROPY_HW_ETH_RMII_CRS_DV (pin_A7)
+#define MICROPY_HW_ETH_RMII_RXD0 (pin_C4)
+#define MICROPY_HW_ETH_RMII_RXD1 (pin_C5)
+#define MICROPY_HW_ETH_RMII_TX_EN (pin_B11)
+#define MICROPY_HW_ETH_RMII_TXD0 (pin_B12)
+#define MICROPY_HW_ETH_RMII_TXD1 (pin_B13)
diff --git a/ports/stm32/boards/WEACT_STM32H743/mpconfigboard.mk b/ports/stm32/boards/WEACT_STM32H743/mpconfigboard.mk
new file mode 100644
index 0000000000000..2a10d7018bdf1
--- /dev/null
+++ b/ports/stm32/boards/WEACT_STM32H743/mpconfigboard.mk
@@ -0,0 +1,14 @@
+# MCU settings
+MCU_SERIES = h7
+CMSIS_MCU = STM32H743xx
+MICROPY_FLOAT_IMPL = double
+AF_FILE = boards/stm32h743_af.csv
+LD_FILES = boards/WEACT_STM32H743/weact_stm32h743.ld boards/common_basic.ld
+TEXT0_ADDR = 0x08000000
+
+# MicroPython settings
+MICROPY_PY_SSL = 1
+MICROPY_SSL_MBEDTLS = 1
+MICROPY_PY_LWIP = 1
+MICROPY_PY_USSL = 1
+MICROPY_VFS_LFS2 = 1
diff --git a/ports/stm32/boards/WEACT_STM32H743/pins.csv b/ports/stm32/boards/WEACT_STM32H743/pins.csv
new file mode 100644
index 0000000000000..c046fc67d1f19
--- /dev/null
+++ b/ports/stm32/boards/WEACT_STM32H743/pins.csv
@@ -0,0 +1,115 @@
+A0,PA0
+A1,PA1
+A2,PA2
+A3,PA3
+A4,PA4
+A5,PA5
+A6,PA6
+A7,PA7
+A8,PA8
+A9,PA9
+A10,PA10
+A11,PA11
+A12,PA12
+A13,PA13
+A14,PA14
+A15,PA15
+B0,PB0
+B1,PB1
+B2,PB2
+B3,PB3
+B4,PB4
+B5,PB5
+B6,PB6
+B7,PB7
+B8,PB8
+B9,PB9
+B10,PB10
+B11,PB11
+B12,PB12
+B13,PB13
+B14,PB14
+B15,PB15
+C0,PC0
+C1,PC1
+C2,PC2
+C3,PC3
+C4,PC4
+C5,PC5
+C6,PC6
+C7,PC7
+C8,PC8
+C9,PC9
+C10,PC10
+C11,PC11
+C12,PC12
+C13,PC13
+C14,PC14
+C15,PC15
+D0,PD0
+D1,PD1
+D2,PD2
+D3,PD3
+D4,PD4
+D5,PD5
+D6,PD6
+D7,PD7
+D8,PD8
+D9,PD9
+D10,PD10
+D11,PD11
+D12,PD12
+D13,PD13
+D14,PD14
+D15,PD15
+E0,PE0
+E1,PE1
+E2,PE2
+E3,PE3
+E4,PE4
+E5,PE5
+E6,PE6
+E7,PE7
+E8,PE8
+E9,PE9
+E10,PE10
+E11,PE11
+E12,PE12
+E13,PE13
+E14,PE14
+E15,PE15
+LED_BLUE,PE3
+KEY_1,PC13
+QSPI_CS,PB6
+QSPI_CLK,PB2
+QSPI_D0,PD11
+QSPI_D1,PD12
+QSPI_D2,PE2
+QSPI_D3,PD13
+USB_DM,PA11
+USB_DP,PA12
+DCMI_SDA,PB11
+DCMI_SCL,PB10
+DCMI_RESET,PC4
+DCMI_CH1,PA4
+DCMI_PWDN,PA7
+DCMI_HREF,PA4
+DCMI_VSYNC,PB7
+DCMI_D0,PC6
+DCMI_D1,PC7
+DCMI_D2,PE0
+DCMI_D3,PE1
+DCMI_D4,PE4
+DCMI_D5,PD3
+DCMI_D6,PE5
+DCMI_D7,PE6
+DCMI_PCLK,PA6
+DCMI_XCLK,PA8
+OSC32_IN,PC14
+OSC32_OUT,PC15
+SDIO_CK,PC12
+SDIO_CMD,PD2
+SDIO_D0,PC8
+SDIO_D1,PC9
+SDIO_D2,PC10
+SDIO_D3,PC11
diff --git a/ports/stm32/boards/WEACT_STM32H743/stm32h7xx_hal_conf.h b/ports/stm32/boards/WEACT_STM32H743/stm32h7xx_hal_conf.h
new file mode 100644
index 0000000000000..05d6a2fecbaa0
--- /dev/null
+++ b/ports/stm32/boards/WEACT_STM32H743/stm32h7xx_hal_conf.h
@@ -0,0 +1,14 @@
+/* This file is part of the MicroPython project, http://micropython.org/
+ * The MIT License (MIT)
+ * Copyright (c) 2019 Damien P. George
+ */
+#ifndef MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H
+#define MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H
+
+#include "boards/stm32h7xx_hal_conf_base.h"
+
+// Oscillator timeouts in ms
+#define HSE_STARTUP_TIMEOUT (5000)
+#define LSE_STARTUP_TIMEOUT (5000)
+
+#endif // MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H
diff --git a/ports/stm32/boards/WEACT_STM32H743/weact_stm32h743.ld b/ports/stm32/boards/WEACT_STM32H743/weact_stm32h743.ld
new file mode 100644
index 0000000000000..de8c93cb289ec
--- /dev/null
+++ b/ports/stm32/boards/WEACT_STM32H743/weact_stm32h743.ld
@@ -0,0 +1,38 @@
+/*
+ GNU linker script for WeAct Studio STM32H743
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1536K /* sectors (0-7) + (0-3) */
+ FLASH_APP (rx) : ORIGIN = 0x08020000, LENGTH = 1408K /* sectors (1-7) + (0-3) */
+ FLASH_FS (r) : ORIGIN = 0x08180000, LENGTH = 512K /* sectors (4-7) */
+ FLASH_EXT (rx) : ORIGIN = 0x90000000, LENGTH = 8192K /* external QSPI */
+ DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for storage cache */
+ RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K /* AXI SRAM */
+ RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
+}
+
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 16K;
+
+/* Define the stack. The stack is full descending so begins just above last byte
+ of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */
+_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;
+_sstack = _estack - 16K; /* tunable */
+
+/* RAM extents for the garbage collector */
+_ram_start = ORIGIN(RAM);
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_start = _ebss; /* heap starts just after statically allocated memory */
+_heap_end = _sstack;
+
+/* Location of filesystem RAM cache */
+_micropy_hw_internal_flash_storage_ram_cache_start = ORIGIN(DTCM);
+_micropy_hw_internal_flash_storage_ram_cache_end = ORIGIN(DTCM) + LENGTH(DTCM);
+
+/* Location of filesystem flash storage */
+_micropy_hw_internal_flash_storage_start = ORIGIN(FLASH_FS);
+_micropy_hw_internal_flash_storage_end = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS);
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