From 22804fccf312030104adf48f836dd8667411cad1 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Tue, 13 Aug 2024 10:54:36 +1000 Subject: [PATCH 1/2] stm32/boards/WEACT_F411_BLACKPILL: Add WeAct F411 'blackpill' boards. Adds board profile for the WeAct F411 'blackpill' which is a quite popular low cost ST dev board. This board also has optional spiflash so can be purchased in a few different configurations. Builds for v3.1 with no SPI Flash by default. Includes variants for different board versions and spi flash sizes. Signed-off-by: Andrew Leech --- .../boards/WEACT_F411_BLACKPILL/README.md | 55 +++++++++ .../stm32/boards/WEACT_F411_BLACKPILL/bdev.c | 45 +++++++ .../boards/WEACT_F411_BLACKPILL/board.json | 22 ++++ .../WEACT_F411_BLACKPILL/mpconfigboard.h | 112 ++++++++++++++++++ .../WEACT_F411_BLACKPILL/mpconfigboard.mk | 38 ++++++ .../mpconfigvariant_V13.mk | 1 + .../mpconfigvariant_V13_FLASH_4M.mk | 2 + .../mpconfigvariant_V20_FLASH_4M.mk | 2 + .../mpconfigvariant_V31_FLASH_8M.mk | 2 + .../mpconfigvariant_V31_XTAL_8M.mk | 2 + .../boards/WEACT_F411_BLACKPILL/pins.csv | 45 +++++++ .../WEACT_F411_BLACKPILL/stm32f4xx_hal_conf.h | 19 +++ 12 files changed, 345 insertions(+) create mode 100644 ports/stm32/boards/WEACT_F411_BLACKPILL/README.md create mode 100644 ports/stm32/boards/WEACT_F411_BLACKPILL/bdev.c create mode 100644 ports/stm32/boards/WEACT_F411_BLACKPILL/board.json create mode 100644 ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigboard.h create mode 100644 ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigboard.mk create mode 100644 ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V13.mk create mode 100644 ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V13_FLASH_4M.mk create mode 100644 ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V20_FLASH_4M.mk create mode 100644 ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V31_FLASH_8M.mk create mode 100644 ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V31_XTAL_8M.mk create mode 100644 ports/stm32/boards/WEACT_F411_BLACKPILL/pins.csv create mode 100644 ports/stm32/boards/WEACT_F411_BLACKPILL/stm32f4xx_hal_conf.h diff --git a/ports/stm32/boards/WEACT_F411_BLACKPILL/README.md b/ports/stm32/boards/WEACT_F411_BLACKPILL/README.md new file mode 100644 index 0000000000000..9af29e6b1e4ad --- /dev/null +++ b/ports/stm32/boards/WEACT_F411_BLACKPILL/README.md @@ -0,0 +1,55 @@ +WeAct F411 'blackpill' +====================== + +The WeAct F411 blackpill board comes in a number of versions and variants. +All have a footprint for a SPI flash chip on the back, though the board is +often sold without any flash chip loaded. + +At the time of writing (Sep 2024) v3.1 is the current version. +This version is sold with both 25Mhz HSE crystal (same as previous versions) and also +with a 8Mhz crystal. The end user should be careful to confirm which variant is +purchased and/or read the markings on the crystal to know which variant build to load. + +The previous v2.0 boards had changed the MCU pinout for the spi flash chip so requires +soft-spi support enabled in the variant settings, unlike v3.1 or v1.3 which is +compatible with the hardware spi peripheral. + +The original v1.3 boards did not include a user switch on the top, it only has +"BOOT0" and "NRST" switches to load bootloader and reset the board respectively. + +For more information see: https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 + +Note: The pins used by features like spiflash and USB are also broken out to the +gpio headers on the sides of the board. +If these peripherals / features are enabled then these external pins must be avoided to ensure +there are no conflicts. [pins.csv](pins.csv) should be consulted to check all pins assigned +to alternate functions on the board. + +Customising the build +--------------------- + +After purchasing a board without any spiflash chip loaded the user can solder on +their own of any desired size. Most brands of spiflash in SO8 pinout are compatible +however some do have a slightly different protocol so may not work out of the box +with micropython. Brand compatibility is outide the scope of this doc. + +Once a custom spiflash chip has been loaded onto the board micropython should +be built with the flash size specified. After doing so the spiflash chip will +be used for the FAT/LFS main filesystem. + +Examples: + +For a v3.1 / 25Mhz (default version) board with 16MiB flash chip loaded: +``` bash +make -C ports/stm32 BOARD=WEACT_F411_BLACKPILL SPI_FLASH_SIZE_MB=16 +``` + +For a v3.1 / 8Mhz board with 4MiB flash chip loaded: +``` bash +make -C ports/stm32 BOARD=WEACT_F411_BLACKPILL BOARD_VARIANT=V31_XTAL_8M SPI_FLASH_SIZE_MB=4 +``` + +For a v1.3 board with 2MiB flash chip loaded and XTAL manually replaced with 8Mhz: +``` bash +make -C ports/stm32 BOARD=WEACT_F411_BLACKPILL BOARD_VARIANT=V13 SPI_FLASH_SIZE_MB=2 XTAL_FREQ_MHZ=8 +``` diff --git a/ports/stm32/boards/WEACT_F411_BLACKPILL/bdev.c b/ports/stm32/boards/WEACT_F411_BLACKPILL/bdev.c new file mode 100644 index 0000000000000..fe349e0c8a4ed --- /dev/null +++ b/ports/stm32/boards/WEACT_F411_BLACKPILL/bdev.c @@ -0,0 +1,45 @@ +#include "storage.h" +#include "spi.h" +#include "py/mpconfig.h" + +#if !MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE + +#if WEACT_F411_V20 +// External SPI flash uses SPI interface, but not on all HW spi pins. +static const mp_soft_spi_obj_t spi_bus = { + .delay_half = MICROPY_HW_SOFTSPI_MIN_DELAY, + .polarity = 0, + .phase = 0, + .sck = MICROPY_HW_SPIFLASH_SCK, + .mosi = MICROPY_HW_SPIFLASH_MOSI, + .miso = MICROPY_HW_SPIFLASH_MISO, +}; + +#else // WEACT_F411_V1.3 or WEACT_F411_V3.1 +static const spi_proto_cfg_t spi_bus = { + .spi = &spi_obj[0], // SPI1 + .baudrate = 25000000, + .polarity = 0, + .phase = 0, + .bits = 8, + .firstbit = SPI_FIRSTBIT_MSB, +}; +#endif + +#if MICROPY_HW_SPIFLASH_ENABLE_CACHE +static mp_spiflash_cache_t spi_bdev_cache; +#endif + +const mp_spiflash_config_t spiflash_config = { + .bus_kind = MP_SPIFLASH_BUS_SPI, + .bus.u_spi.cs = MICROPY_HW_SPIFLASH_CS, + .bus.u_spi.data = (void *)&spi_bus, + .bus.u_spi.proto = &spi_proto, + #if MICROPY_HW_SPIFLASH_ENABLE_CACHE + .cache = &spi_bdev_cache, + #endif +}; + +spi_bdev_t spi_bdev; + +#endif diff --git a/ports/stm32/boards/WEACT_F411_BLACKPILL/board.json b/ports/stm32/boards/WEACT_F411_BLACKPILL/board.json new file mode 100644 index 0000000000000..5b10787216995 --- /dev/null +++ b/ports/stm32/boards/WEACT_F411_BLACKPILL/board.json @@ -0,0 +1,22 @@ +{ + "deploy": [ + "../PYBV10/deploy.md" + ], + "docs": "", + "features": [], + "images": [ + "WEACTV20_F411.jpg" + ], + "mcu": "stm32f411", + "product": "WeAct F411 'blackpill'. Default variant is v3.1 with no SPI Flash.", + "thumbnail": "", + "url": "https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1", + "variants": { + "V13": "v1.3 board with no SPI Flash", + "V13_FLASH_4M": "v1.3 board with 4MB SPI Flash", + "V20_FLASH_4M": "v2.0 board with 4MB SPI Flash", + "V31_FLASH_8M": "v3.1 board with 8MB SPI Flash", + "V31_XTAL_8M": "v3.1 board with 8MHz crystal" + }, + "vendor": "WeAct Studio" +} diff --git a/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigboard.h b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigboard.h new file mode 100644 index 0000000000000..561c1a9f1516e --- /dev/null +++ b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigboard.h @@ -0,0 +1,112 @@ +// based off the following two repositories: +// * https://github.com/mcauser/WEACT_F411CEU6 +// * https://github.com/YXZhu/micropython + +#define MICROPY_HW_BOARD_NAME "WEACT_F411_BLACKPILL" +#define MICROPY_HW_MCU_NAME "STM32F411CE" +#define MICROPY_HW_FLASH_FS_LABEL "WEACT_F411_BLACKPILL" + +// some users having issues with FLASH_LATENCY_2, so set to 3 +// from https://forum.micropython.org/viewtopic.php?t=7154 +#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_3 + +#define MICROPY_HW_HAS_FLASH (1) +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_ENABLE_USB (1) +#define MICROPY_HW_USB_FS (1) + +// Switch +#if WEACT_F411_V13 +#define MICROPY_HW_HAS_SWITCH (0) +#else +#define MICROPY_HW_HAS_SWITCH (1) +#define MICROPY_HW_USRSW_PIN (pyb_pin_SW) +#define MICROPY_HW_USRSW_PULL (GPIO_PULLUP) +#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING) +#define MICROPY_HW_USRSW_PRESSED (0) +#endif + +// LEDs +#define MICROPY_HW_LED1 (pyb_pin_LED_BLUE) +#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin)) +#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) + +// RTC +#define MICROPY_HW_RTC_USE_LSE (1) +#define MICROPY_HW_RTC_USE_US (0) +#define MICROPY_HW_RTC_USE_CALOUT (1) + +// Set PLLM same as HSE in MHZ. +#define MICROPY_HW_CLK_PLLM (MICROPY_HW_HSE_SPEED_MHZ) +// Configure PLL for final CPU freq of 96MHz +#define MICROPY_HW_CLK_PLLN (192) +#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2) +#define MICROPY_HW_CLK_PLLQ (4) + +// UART config +#define MICROPY_HW_UART1_TX (pin_A9) +#define MICROPY_HW_UART1_RX (pin_A10) + +#define MICROPY_HW_UART2_TX (pin_A2) +#define MICROPY_HW_UART2_RX (pin_A3) + +#define MICROPY_HW_UART_REPL (PYB_UART_1) +#define MICROPY_HW_UART_REPL_BAUD (115200) + +// I2C bus +#define MICROPY_HW_I2C1_SCL (pin_B6) +#define MICROPY_HW_I2C1_SDA (pin_B7) +#define MICROPY_HW_I2C2_SCL (pin_B10) +#define MICROPY_HW_I2C2_SDA (pin_B9) +#define MICROPY_HW_I2C3_SCL (pin_A8) +#define MICROPY_HW_I2C3_SDA (pin_B8) + +// SPI bus +// SPI 1 is generally used for the SPI flash if enabled below. +#define MICROPY_HW_SPI1_NSS (pin_A4) +#define MICROPY_HW_SPI1_SCK (pin_A5) +#define MICROPY_HW_SPI1_MISO (pin_A6) +#define MICROPY_HW_SPI1_MOSI (pin_A7) + +#define MICROPY_HW_SPI2_NSS (pin_B12) +#define MICROPY_HW_SPI2_SCK (pin_B13) +#define MICROPY_HW_SPI2_MISO (pin_B14) +#define MICROPY_HW_SPI2_MOSI (pin_B15) + +// SPI 3 is not accessible if SPI flash module is used on V2.0 (PB4 conflict) +#define MICROPY_HW_SPI3_NSS (pin_A15) +#define MICROPY_HW_SPI3_SCK (pin_B3) +#define MICROPY_HW_SPI3_MISO (pin_B4) +#define MICROPY_HW_SPI3_MOSI (pin_B5) + +// External SPI Flash configuration + +#if !MICROPY_HW_SPIFLASH_SIZE_BYTES +// Use internal filesystem if spiflash not enabled. +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1) + +#else +// Disable internal filesystem to use spiflash. +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0) + +// SPI flash pins +#define MICROPY_HW_SPIFLASH_CS (pyb_pin_FLASH_CS) +#define MICROPY_HW_SPIFLASH_SCK (pyb_pin_FLASH_SCK) +#define MICROPY_HW_SPIFLASH_MOSI (pyb_pin_FLASH_MOSI) +#if WEACT_F411_V13 +#define MICROPY_HW_SPIFLASH_MISO (pyb_pin_FLASH_MISO_V13) +#elif WEACT_F411_V20 +#define MICROPY_HW_SPIFLASH_MISO (pyb_pin_FLASH_MISO_V20) +#else +#define MICROPY_HW_SPIFLASH_MISO (pyb_pin_FLASH_MISO_V31) +#endif + +extern const struct _mp_spiflash_config_t spiflash_config; +extern struct _spi_bdev_t spi_bdev; +#define MICROPY_HW_SPIFLASH_ENABLE_CACHE (1) +#define MICROPY_HW_BDEV_SPIFLASH (&spi_bdev) +#define MICROPY_HW_BDEV_SPIFLASH_CONFIG (&spiflash_config) +#define MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES (MICROPY_HW_SPIFLASH_SIZE_BITS / 8) +#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol +#define MICROPY_HW_SPIFLASH_SIZE_BITS (MICROPY_HW_SPIFLASH_SIZE_BYTES * 8) +#endif diff --git a/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigboard.mk b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigboard.mk new file mode 100644 index 0000000000000..3ae152294d27c --- /dev/null +++ b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigboard.mk @@ -0,0 +1,38 @@ +MCU_SERIES = f4 +CMSIS_MCU = STM32F411xE +AF_FILE = boards/stm32f411_af.csv +LD_FILES = boards/stm32f411.ld boards/common_ifs.ld +TEXT0_ADDR = 0x08000000 +TEXT1_ADDR = 0x08020000 + +MICROPY_VFS_LFS2 = 1 + +# Settings for version, spi flash and HSE xtal. +# These are used in variant configs and/or on make command line. +# If provided on make command line the build folder name will be updated to match +# When set in variant they're included after this file so the following ifdef blocks are ignored. + +ifdef BOARD_VERSION +BUILD := $(BUILD)_V$(BOARD_VERSION) +endif + +ifdef SPI_FLASH_SIZE_MB +BUILD := $(BUILD)_FLASH_$(SPI_FLASH_SIZE_MB)M +endif + +ifdef XTAL_FREQ_MHZ +BUILD := $(BUILD)_XTAL_$(XTAL_FREQ_MHZ)M +endif + +# Blackpill v3.1 board by default +BOARD_VERSION ?= 31 + +# No flash chip in default build - use internal flash +SPI_FLASH_SIZE_MB ?= 0 + +# 25Mhz HSE crystal by default. +XTAL_FREQ_MHZ ?= 25 + +CFLAGS += -DWEACT_F411_V$(BOARD_VERSION)=1 +CFLAGS += -DMICROPY_HW_SPIFLASH_SIZE_BYTES="($(SPI_FLASH_SIZE_MB) * 1024 * 1024)" +CFLAGS += -DMICROPY_HW_HSE_SPEED_MHZ="($(XTAL_FREQ_MHZ))" diff --git a/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V13.mk b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V13.mk new file mode 100644 index 0000000000000..47c94faee4012 --- /dev/null +++ b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V13.mk @@ -0,0 +1 @@ +BOARD_VERSION = 13 diff --git a/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V13_FLASH_4M.mk b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V13_FLASH_4M.mk new file mode 100644 index 0000000000000..ae7aeaaf52d13 --- /dev/null +++ b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V13_FLASH_4M.mk @@ -0,0 +1,2 @@ +BOARD_VERSION = 13 +SPI_FLASH_SIZE_MB = 4 diff --git a/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V20_FLASH_4M.mk b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V20_FLASH_4M.mk new file mode 100644 index 0000000000000..21ce84ceaff85 --- /dev/null +++ b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V20_FLASH_4M.mk @@ -0,0 +1,2 @@ +BOARD_VERSION = 20 +SPI_FLASH_SIZE_MB = 4 diff --git a/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V31_FLASH_8M.mk b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V31_FLASH_8M.mk new file mode 100644 index 0000000000000..87867b1fedf45 --- /dev/null +++ b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V31_FLASH_8M.mk @@ -0,0 +1,2 @@ +BOARD_VERSION = 31 +SPI_FLASH_SIZE_MB = 8 diff --git a/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V31_XTAL_8M.mk b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V31_XTAL_8M.mk new file mode 100644 index 0000000000000..5eb05e49fe926 --- /dev/null +++ b/ports/stm32/boards/WEACT_F411_BLACKPILL/mpconfigvariant_V31_XTAL_8M.mk @@ -0,0 +1,2 @@ +BOARD_VERSION = 31 +XTAL_FREQ_MHZ = 8 diff --git a/ports/stm32/boards/WEACT_F411_BLACKPILL/pins.csv b/ports/stm32/boards/WEACT_F411_BLACKPILL/pins.csv new file mode 100644 index 0000000000000..eabf753de852b --- /dev/null +++ b/ports/stm32/boards/WEACT_F411_BLACKPILL/pins.csv @@ -0,0 +1,45 @@ +,PA0 +,PA1 +,PA2 +,PA3 +,PA4 +,PA5 +,PA6 +,PA7 +,PA8 +,PA9 +,PA10 +,PA11 +,PA12 +,PA15 +,PB0 +,PB1 +,PB2 +,PB3 +,PB4 +,PB5 +,PB6 +,PB7 +,PB8 +,PB9 +,PB10 +,PB12 +,PB13 +,PB14 +,PB15 +,PC14 +,PC15 +LED_BLUE,PC13 +SW,PA0 +-SWDIO,PA13 +-SWCLK,PA14 +-OSC32_IN,PH0 +-OSC32_OUT,PH1 +-USB_DM,PA11 +-USB_DP,PA12 +-FLASH_CS,PA4 +-FLASH_SCK,PA5 +-FLASH_MOSI,PA7 +-FLASH_MISO_V13,PA6 +-FLASH_MISO_V20,PB4 +-FLASH_MISO_V31,PA6 diff --git a/ports/stm32/boards/WEACT_F411_BLACKPILL/stm32f4xx_hal_conf.h b/ports/stm32/boards/WEACT_F411_BLACKPILL/stm32f4xx_hal_conf.h new file mode 100644 index 0000000000000..c11d72a213ff6 --- /dev/null +++ b/ports/stm32/boards/WEACT_F411_BLACKPILL/stm32f4xx_hal_conf.h @@ -0,0 +1,19 @@ +/* This file is part of the MicroPython project, http://micropython.org/ + * The MIT License (MIT) + * Copyright (c) 2024 Andrew Leech + */ +#ifndef MICROPY_INCLUDED_STM32F4XX_HAL_CONF_H +#define MICROPY_INCLUDED_STM32F4XX_HAL_CONF_H + +#include "boards/stm32f4xx_hal_conf_base.h" + +// Oscillator values in Hz +#define HSE_VALUE (MICROPY_HW_HSE_SPEED_MHZ * 1000000) +#define LSE_VALUE (32768) +#define EXTERNAL_CLOCK_VALUE (12288000) + +// Oscillator timeouts in ms +#define HSE_STARTUP_TIMEOUT (100) +#define LSE_STARTUP_TIMEOUT (5000) + +#endif // MICROPY_INCLUDED_STM32F4XX_HAL_CONF_H From 7924b31050271c76ff6cf26c6fda5fe3ba615d08 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Tue, 3 Sep 2024 10:41:25 +1000 Subject: [PATCH 2/2] stm32: Generate PLL tables from pre-processed headers. Allows boards to configure their HSE and PLL values in variants. Signed-off-by: Andrew Leech --- ports/stm32/Makefile | 12 +++---- ports/stm32/boards/plli2svalues.py | 55 +++++++++++++++--------------- ports/stm32/boards/pllvalues.py | 30 ++++++++-------- ports/stm32/machine_i2s.c | 2 ++ ports/stm32/powerctrl.c | 17 ++++++++- 5 files changed, 67 insertions(+), 49 deletions(-) diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile index 806added49e9a..a9612f1a5792e 100644 --- a/ports/stm32/Makefile +++ b/ports/stm32/Makefile @@ -640,15 +640,15 @@ $(BUILD)/%_$(BOARD).c $(HEADER_BUILD)/%.h $(HEADER_BUILD)/%_af_const.h $(HEADER_ --output-source $(GEN_PINS_SRC) --output-header $(GEN_PINS_HDR) \ --output-af-const $(GEN_PINS_AF_CONST) --output-af-defs $(GEN_PINS_AF_DEFS) -powerctrl.c: $(GEN_PLLFREQTABLE_HDR) -$(GEN_PLLFREQTABLE_HDR): $(PLLVALUES) | $(HEADER_BUILD) +$(BUILD)/powerctrl.o: $(GEN_PLLFREQTABLE_HDR) +$(GEN_PLLFREQTABLE_HDR): $(PLLVALUES) | $(HEADER_BUILD)/qstr.i.last $(ECHO) "GEN $@" - $(Q)$(PYTHON) $(PLLVALUES) -c -m $(CMSIS_MCU_LOWER) file:$(BOARD_DIR)/stm32$(MCU_SERIES)xx_hal_conf.h > $@ + $(Q)$(PYTHON) $(PLLVALUES) -c -m $(CMSIS_MCU_LOWER) file:$(HEADER_BUILD)/qstr.i.last > $@ -$(TOP)/extmod/machine_i2s.c: $(GEN_PLLI2STABLE_HDR) -$(GEN_PLLI2STABLE_HDR): $(PLLI2SVALUES) | $(HEADER_BUILD) +$(BUILD)/extmod/machine_i2s.o: $(GEN_PLLI2STABLE_HDR) +$(GEN_PLLI2STABLE_HDR): $(PLLI2SVALUES) | $(HEADER_BUILD)/qstr.i.last $(ECHO) "GEN $@" - $(Q)$(PYTHON) $(PLLI2SVALUES) -c -m $(CMSIS_MCU_LOWER) hse:$(BOARD_DIR)/stm32$(MCU_SERIES)xx_hal_conf.h pllm:$(BOARD_DIR)/mpconfigboard.h > $@ + $(Q)$(PYTHON) $(PLLI2SVALUES) -c -m $(CMSIS_MCU_LOWER) file:$(HEADER_BUILD)/qstr.i.last > $@ $(BUILD)/modstm.o: $(GEN_STMCONST_HDR) $(HEADER_BUILD)/modstm_const.h: $(CMSIS_MCU_HDR) make-stmconst.py | $(HEADER_BUILD) diff --git a/ports/stm32/boards/plli2svalues.py b/ports/stm32/boards/plli2svalues.py index 8ff7f0ff8fcdf..436dcee7444a7 100644 --- a/ports/stm32/boards/plli2svalues.py +++ b/ports/stm32/boards/plli2svalues.py @@ -123,22 +123,21 @@ def generate_c_table(plli2s_table, hse, pllm): print("}") -def search_header(filename, re_include, re_define, lookup, val): - regex_include = re.compile(re_include) +def search_header(filename, re_define, lookup): regex_define = re.compile(re_define) + val = None with open(filename) as f: for line in f: line = line.strip() - m = regex_include.match(line) - if m: - # Search included file - search_header(m.group(1), re_include, re_define, lookup, val) - continue m = regex_define.match(line) if m: # found lookup value + found = m.group(3) + if "*" in found or "/" in found: + # process define using multiply or divide to calculate value + found = eval(found) if m.group(1) == lookup: - val[0] = int(m.group(3)) + val = int(found) return val @@ -166,35 +165,37 @@ def main(): break if mcu_series in mcu_support_plli2s: - if len(argv) != 2: + if len(argv) not in (1, 2): print("usage: pllvalues.py [-c] [-m ] ") sys.exit(1) if argv[0].startswith("hse:"): - # extract HSE_VALUE from header file - (hse,) = search_header( - argv[0][len("hse:") :], - r'#include "(boards/[A-Za-z0-9_./]+)"', - r"#define +(HSE_VALUE) +\((\(uint32_t\))?([0-9]+)\)", - "HSE_VALUE", - [None], + hse = int(argv[0][len("hse:") :]) + + if argv[0].startswith("pllm:"): + pllm = int(argv[0][len("pllm:") :]) + + if argv[0].startswith("file:"): + # extract hse value from processed header files + hse = search_header( + argv[0][len("file:") :], + r"static.* (micropy_hw_hse_value) = +\(*(\(uint32_t\))?([0-9 +-/\*]+)\)*;", + "micropy_hw_hse_value", ) if hse is None: - raise ValueError("%s does not contain a definition of HSE_VALUE" % argv[0]) - argv.pop(0) + raise ValueError( + "%s does not contain a definition of micropy_hw_hse_value" % argv[0] + ) - if argv[0].startswith("pllm:"): - # extract MICROPY_HW_CLK_PLLM from header file - (pllm,) = search_header( - argv[0][len("pllm:") :], - r'#include "(boards/[A-Za-z0-9_./]+)"', - r"#define +(MICROPY_HW_CLK_PLLM) +\((\(uint32_t\))?([0-9]+)\)", - "MICROPY_HW_CLK_PLLM", - [None], + # extract pllm value from processed header files + pllm = search_header( + argv[0][len("file:") :], + r"static.* (micropy_hw_clk_pllm) = +\(*(\(uint32_t\))?([0-9 +-/\*]+)\)*;", + "micropy_hw_clk_pllm", ) if pllm is None: raise ValueError( - "%s does not contain a definition of MICROPY_HW_CLK_PLLM" % argv[0] + "%s does not contain a definition of micropy_hw_clk_pllm" % argv[0] ) argv.pop(0) diff --git a/ports/stm32/boards/pllvalues.py b/ports/stm32/boards/pllvalues.py index 2db6b5f257044..5edc1d51fd6bc 100644 --- a/ports/stm32/boards/pllvalues.py +++ b/ports/stm32/boards/pllvalues.py @@ -228,26 +228,26 @@ def print_table(hse, valid_plls): print("found %u valid configurations" % len(valid_plls)) -def search_header_for_hsx_values(filename, vals): - regex_inc = re.compile(r'#include "(boards/[A-Za-z0-9_./]+)"') - regex_def = re.compile(r"#define +(HSE_VALUE|HSI_VALUE) +\((\(uint32_t\))?([0-9]+)\)") +def search_header_for_hsx_values(filename): + hse = hsi = None + regex_def = re.compile( + r"static.* +(micropy_hw_hs[ei]_value) = +\(*(\(uint32_t\))?([0-9 +-/\*]+)\)*;", + ) with open(filename) as f: for line in f: line = line.strip() - m = regex_inc.match(line) - if m: - # Search included file - search_header_for_hsx_values(m.group(1), vals) - continue m = regex_def.match(line) if m: # Found HSE_VALUE or HSI_VALUE - val = int(m.group(3)) // 1000000 - if m.group(1) == "HSE_VALUE": - vals[0] = val + found = m.group(3) + if "*" in found or "/" in found: + found = eval(found) + val = int(found) // 1000000 + if m.group(1) == "micropy_hw_hse_value": + hse = val else: - vals[1] = val - return vals + hsi = val + return hse, hsi def main(): @@ -280,9 +280,9 @@ def main(): if argv[0].startswith("file:"): # extract HSE_VALUE, and optionally HSI_VALUE, from header file - hse, hsi = search_header_for_hsx_values(argv[0][5:], [None, None]) + hse, hsi = search_header_for_hsx_values(argv[0][5:]) if hse is None: - raise ValueError("%s does not contain a definition of HSE_VALUE" % argv[0]) + raise ValueError("%s does not contain a definition of micropy_hw_hse_value" % argv[0]) else: # HSE given directly as an integer hse = int(argv[0]) diff --git a/ports/stm32/machine_i2s.c b/ports/stm32/machine_i2s.c index a2a0a8291008c..d7d4dc14b988b 100644 --- a/ports/stm32/machine_i2s.c +++ b/ports/stm32/machine_i2s.c @@ -33,7 +33,9 @@ #include "py/mphal.h" #include "pin.h" #include "dma.h" +#ifndef NO_QSTR #include "genhdr/plli2stable.h" +#endif // Notes on this port's specific implementation of I2S: // - the DMA callbacks (1/2 complete and complete) are used to implement the asynchronous background operations diff --git a/ports/stm32/powerctrl.c b/ports/stm32/powerctrl.c index 9d3f374f93757..eea009e2d782b 100644 --- a/ports/stm32/powerctrl.c +++ b/ports/stm32/powerctrl.c @@ -28,8 +28,23 @@ #include "py/mphal.h" #include "powerctrl.h" #include "rtc.h" -#include "genhdr/pllfreqtable.h" #include "extmod/modbluetooth.h" +#include "py/mpconfig.h" +#ifndef NO_QSTR +#include "genhdr/pllfreqtable.h" +#endif + +// These will be defined / expanded in pre-processor output for use in the +// boards/pllvalues.py script, then generally stripped from final firmware. +#ifdef HSI_VALUE +static uint32_t __attribute__((unused)) micropy_hw_hsi_value = HSI_VALUE; +#endif +#ifdef HSE_VALUE +static uint32_t __attribute__((unused)) micropy_hw_hse_value = HSE_VALUE; +#endif +#ifdef MICROPY_HW_CLK_PLLM +static uint32_t __attribute__((unused)) micropy_hw_clk_pllm = MICROPY_HW_CLK_PLLM; +#endif #if defined(STM32H5) || defined(STM32H7) #define RCC_SR RSR pFad - Phonifier reborn

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