diff --git a/.gitmodules b/.gitmodules index d2d8dd2783271..9b57248562773 100644 --- a/.gitmodules +++ b/.gitmodules @@ -15,3 +15,6 @@ path = lib/stm32lib url = https://github.com/micropython/stm32lib branch = work-F4-1.13.1+F7-1.5.0+L4-1.3.0 +[submodule "lib/lpc43xxlib"] + path = lib/lpc43xxlib + url = https://github.com/martinribelotta/lpc43xxlib.git diff --git a/lib/lpc43xxlib b/lib/lpc43xxlib new file mode 160000 index 0000000000000..222099585e40c --- /dev/null +++ b/lib/lpc43xxlib @@ -0,0 +1 @@ +Subproject commit 222099585e40c22d83b1b706621feb026a9ca7d3 diff --git a/ports/lpc/Makefile b/ports/lpc/Makefile new file mode 100644 index 0000000000000..15a3df5b394b6 --- /dev/null +++ b/ports/lpc/Makefile @@ -0,0 +1,114 @@ +include ../../py/mkenv.mk + +BOARD=lpc_board_ciaa_edu_4337 + +MPY_CROSS=$(TOP)/mpy-cross/mpy-cross + +-include boards/$(BOARD)/board.mk + +# qstr definitions (must come before including py.mk) +QSTR_DEFS = qstrdefsport.h + +# include py core make definitions +include $(TOP)/py/py.mk + +CHIP_LIB=$(TOP)/lib/$(CHIP)lib + +CROSS_COMPILE = arm-none-eabi- + +INC += -I. +INC += -I$(TOP) +INC += -I$(BUILD) +INC += -I$(TOP)/lib/cmsis/inc +INC += -I$(CMSIS_DIR)/ +INC += -Iboards/$(BOARD)/inc +INC += -I$(CHIP_LIB)/inc + +include $(CHIP_LIB)/chip.mk + +OPENOCD = openocd +OPENOCD_CONFIG = boards/$(BOARD)/openocd.cfg +DFU = dfu-util +DFUHDR = $(TOP)/tools/dfuheader.py +CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -mabi=aapcs -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant -Wdouble-promotion +CFLAGS = $(INC) -Wall -Werror -std=gnu99 -nostdlib $(CFLAGS_CORTEX_M4) $(COPT) +LDFLAGS = -nostdlib -Lboards/$(BOARD) -L$(CHIP_LIB)/lib -Tlinker.lds -Map=$@.map --cref --gc-sections + +# Tune for Debugging or Optimization +ifeq ($(DEBUG), 1) +CFLAGS += -O0 -ggdb +else +CFLAGS += -Os -DNDEBUG +CFLAGS += -fdata-sections -ffunction-sections +endif + +CFLAGS += $(BOARD_CFLAGS) $(CHIP_CFLAGS) + +LIBS = $(shell $(CROSS_COMPILE)gcc $(CFLAGS_CORTEX_M4) --print-libgcc-file-name) + +SRC_LIBM = $(addprefix lib/libm/,\ + math.c \ + thumb_vfp_sqrtf.c \ + acoshf.c \ + asinfacosf.c \ + asinhf.c \ + atan2f.c \ + atanf.c \ + atanhf.c \ + ef_rem_pio2.c \ + erf_lgamma.c \ + fmodf.c \ + kf_cos.c \ + kf_rem_pio2.c \ + kf_sin.c \ + kf_tan.c \ + log1pf.c \ + nearbyintf.c \ + sf_cos.c \ + sf_erf.c \ + sf_frexp.c \ + sf_ldexp.c \ + sf_modf.c \ + sf_sin.c \ + sf_tan.c \ + wf_lgamma.c \ + wf_tgamma.c \ + ) + +SRC_C = \ + main.c \ + mphalport.c \ + $(wildcard boards/$(BOARD)/src/*.c) \ + $(CHIP_LIB_SRC_C) \ + lib/utils/stdout_helpers.c \ + lib/utils/pyexec.c \ + lib/libc/string0.c \ + lib/mp-readline/readline.c \ + $(SRC_LIBM) + +OBJ = $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o)) + +all: $(BUILD)/firmware.bin + +$(BUILD)/firmware.elf: $(OBJ) + $(ECHO) "LINK $@" + $(Q)$(LD) $(LDFLAGS) -o $@ $^ $(LIBS) + $(Q)$(SIZE) $@ + +$(BUILD)/firmware.bin: $(BUILD)/firmware.elf + $(ECHO) "Create $@" + $(Q)$(OBJCOPY) -O binary -j .isr_vector -j .text -j .data $^ $(BUILD)/firmware.bin + +$(BUILD)/firmware.dfu: $(BUILD)/firmware.bin + $(ECHO) "Create $@" + $(Q)$(DFUHDR) $^ $@ + +deploy-dfu: $(BUILD)/firmware.dfu + $(ECHO) "Writing $< to the board via DFU" + $(Q)$(DFU) -R -D $^ + +deploy-openocd: $(BUILD)/firmware.bin + $(ECHO) "Writing $< to the board via OpenOCD" + $(Q)$(OPENOCD) -f $(OPENOCD_CONFIG) -c "lpc_flash $<" + +include $(TOP)/py/mkrules.mk diff --git a/ports/lpc/board.h b/ports/lpc/board.h new file mode 100644 index 0000000000000..fb94a76b125ca --- /dev/null +++ b/ports/lpc/board.h @@ -0,0 +1,20 @@ +#ifndef _LPC_BOARD_H_ +#define _LPC_BOARD_H_ + +#include + +#define CONSOLE_UART LPC_USART2 +#define BOARD_CIAA_EDU_NXP_4337 + +#ifdef __cplusplus +extern "C" { +#endif + +void Board_SystemInit(void); +void Board_Init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _LPC_BOARD_H_ */ diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/README b/ports/lpc/boards/lpc_board_ciaa_edu_4337/README new file mode 100644 index 0000000000000..fe41408c63698 --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/README @@ -0,0 +1,3 @@ +LPCOpen v3.01 + +Release Date: 03/24/2017 diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/board.mk b/ports/lpc/boards/lpc_board_ciaa_edu_4337/board.mk new file mode 100644 index 0000000000000..7ae2da8265529 --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/board.mk @@ -0,0 +1,2 @@ +CHIP=lpc43xx +BOARD_CFLAGS=-D__USE_LPCOPEN diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/inc/mpconfigboard.h b/ports/lpc/boards/lpc_board_ciaa_edu_4337/inc/mpconfigboard.h new file mode 100644 index 0000000000000..de38645fc4dcd --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/inc/mpconfigboard.h @@ -0,0 +1,2 @@ +#define MICROPY_HW_BOARD_NAME "EDU-CIAA" +#define MICROPY_HW_MCU_NAME "LPC4337" diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/memory.lds b/ports/lpc/boards/lpc_board_ciaa_edu_4337/memory.lds new file mode 100644 index 0000000000000..c2284be89f16f --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/memory.lds @@ -0,0 +1,14 @@ +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x1a000000, LENGTH = 512K + RAM (xrw) : ORIGIN = 0x10000000, LENGTH = 32k + + FLASHB (rx) : ORIGIN = 0x1b000000, LENGTH = 512K + RAMB (rwx) : ORIGIN = 0x10080000, LENGTH = 32K + RAMC (rwx) : ORIGIN = 0x10088000, LENGTH = 8K + RAMD (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +_py_heap_start = ORIGIN(RAMD); +_py_heap_end = ORIGIN(RAMD) + LENGTH(RAMD); diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/openocd.cfg b/ports/lpc/boards/lpc_board_ciaa_edu_4337/openocd.cfg new file mode 100644 index 0000000000000..c5941312ee4b1 --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/openocd.cfg @@ -0,0 +1,79 @@ +############################################################################### +# +# Copyright 2014, Juan Cecconi (UTN-FRBA, Numetron) +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from this +# software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################### + +interface ftdi + +ftdi_vid_pid 0x0403 0x6010 +ftdi_channel 0 +ftdi_layout_init 0x0708 0xFFFB +ftdi_layout_signal nTRST -data 0x0100 +ftdi_layout_signal nSRST -data 0x0200 + +transport select jtag +adapter_khz 2000 + +set _CHIPNAME lpc4337 + +set _M4_JTAG_TAPID 0x4ba00477 +set _M0_JTAG_TAPID 0x0ba01477 + +jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M4_JTAG_TAPID +jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M0_JTAG_TAPID + +target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4 +target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0 + +set _WORKAREASIZE 0x8000 +$_CHIPNAME.m4 configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME lpc2000 0x1a000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 96000 calc_checksum + +reset_config none +cortex_m reset_config vectreset + +targets $_CHIPNAME.m4 + +$_CHIPNAME.m4 configure -event gdb-attach { + echo "Reset Halt, due to gdb attached...!" + reset halt +} + +init + +proc lpc_flash { BIN } { + init + halt 0 + flash write_image erase unlock $BIN 0x1a000000 bin + reset run + shutdown +} diff --git a/ports/lpc/boards/lpc_board_ciaa_edu_4337/src/board.c b/ports/lpc/boards/lpc_board_ciaa_edu_4337/src/board.c new file mode 100644 index 0000000000000..d57637afd399f --- /dev/null +++ b/ports/lpc/boards/lpc_board_ciaa_edu_4337/src/board.c @@ -0,0 +1,159 @@ +#include "board.h" + +#include + +/* System configuration variables used by chip driver */ +const uint32_t ExtRateIn = 0; +const uint32_t OscRateIn = 12000000; + +/* Structure for initial base clock states */ +struct CLK_BASE_STATES { + CHIP_CGU_BASE_CLK_T clk; /* Base clock */ + CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */ + bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */ + bool powerdn; /* Set to true if the base clock is initially powered down */ +}; + +/* Initial base clock states are mostly on */ +static const struct CLK_BASE_STATES InitClkStates[] = { + /* Ethernet Clock base */ + {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false}, + {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false}, + + /* Clocks derived from dividers */ + {CLK_BASE_USB0, CLKIN_IDIVD, true, true} +}; + +static const PINMUX_GRP_T pinmuxing[] = { + /* Board LEDs */ + {2, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)}, + {2, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)}, + {2, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0)}, + {2, 0, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4)}, + {2, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4)}, + {2, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4)}, + + /* UART 3 */ + {2, 3, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC2)}, + {2, 4, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC2)}, + + /* UART 2 */ + {7, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC6)}, + {7, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC6)}, + + /* CAN1 */ + {3, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC2)}, + {3, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC2)}, + + /* GPIO2 */ + {4, 0, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + {4, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + {4, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + {4, 3, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + {4, 5, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + {4, 6, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + {4, 7, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)}, + + /* GPIO5 */ + {4, 8, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)}, + {4, 9, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)}, + {4, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)}, + + /* ENET Pin mux (RMII Pins) */ + {1, 15, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, /* RXD0 */ + {1, 16, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)}, /* CRS_DV */ + {1, 17, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, /* MDIO */ + {1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, /* TXD0 */ + {1, 19, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)}, /* REFCLK */ + {1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, /* TXD1 */ + {7, 7, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)}, /* MDC */ + {0, 0, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)}, /* RXD1 */ + {0, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)}, /* TXEN */ +}; + +void Board_UART_Init(LPC_USART_T *pUART) +{ + Chip_SCU_PinMuxSet(0x7, 1, (SCU_MODE_INACT | SCU_MODE_FUNC6)); /* P7.1 : UART2_TXD */ + Chip_SCU_PinMuxSet(0x7, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6));/* P7.2 : UART2_RXD */ +} + +/* Initialize debug output via UART for board */ +void Board_Debug_Init(void) +{ + Board_UART_Init(CONSOLE_UART); + + Chip_UART_Init(CONSOLE_UART); + Chip_UART_SetBaudFDR(CONSOLE_UART, 115200); + Chip_UART_ConfigData(CONSOLE_UART, UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS); + /* Enable UART Transmit */ + Chip_UART_TXEnable(CONSOLE_UART); +} + +/* Set up and initialize all required blocks and functions related to the + board hardware */ +void Board_Init(void) +{ + /* Sets up DEBUG UART */ + Board_Debug_Init(); + + /* Initializes GPIO */ + Chip_GPIO_Init(LPC_GPIO_PORT); +} + +/* Sets up system pin muxing */ +void Board_SetupMuxing(void) +{ + /* Setup system level pin muxing */ + Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); + /* Off all leds */ +#define X(port, pin) do { \ + Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, port, pin); \ + Chip_GPIO_SetPinState(LPC_GPIO_PORT, port, pin, false); \ +} while(0) + X(5, 0); + X(5, 1); + X(5, 2); + X(0, 14); + X(1, 11); + X(1, 12); +#undef X +} + +/* Set up and initialize clocking prior to call to main */ +void Board_SetupClocking(void) +{ + int i; + + /* Enable Flash acceleration and setup wait states */ + Chip_CREG_SetFlashAcceleration(MAX_CLOCK_FREQ); + + /* Setup System core frequency to MAX_CLOCK_FREQ */ + Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true); + + /* Setup system base clocks and initial states. This won't enable and + disable individual clocks, but sets up the base clock sources for + each individual peripheral clock. */ + for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { + Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, + InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); + } + + /* Reset and enable 32Khz oscillator */ + LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2)); + LPC_CREG->CREG0 |= (1 << 1) | (1 << 0); + + /* Wait until stable */ + volatile unsigned int delay = 10000; + while (delay--); +} + +/* Set up and initialize hardware prior to call to main */ +void Board_SystemInit(void) +{ + /* Setup system clocking and memory. This is done early to allow the + application and tools to clear memory and use scatter loading to + external memory. */ + fpuInit(); + Board_SetupMuxing(); + Board_SetupClocking(); +} diff --git a/ports/lpc/main.c b/ports/lpc/main.c new file mode 100644 index 0000000000000..e583e15eaec77 --- /dev/null +++ b/ports/lpc/main.c @@ -0,0 +1,95 @@ +#include +#include +#include + +#include "py/nlr.h" +#include "py/compile.h" +#include "py/runtime.h" +#include "py/repl.h" +#include "py/gc.h" +#include "py/mperrno.h" +#include "lib/utils/pyexec.h" + +#include "board.h" + +void do_str(const char *src, mp_parse_input_kind_t input_kind) { + nlr_buf_t nlr; + if (nlr_push(&nlr) == 0) { + mp_lexer_t *lex = mp_lexer_new_from_str_len(MP_QSTR__lt_stdin_gt_, src, strlen(src), 0); + qstr source_name = lex->source_name; + mp_parse_tree_t parse_tree = mp_parse(lex, input_kind); + mp_obj_t module_fun = mp_compile(&parse_tree, source_name, MP_EMIT_OPT_NONE, true); + mp_call_function_0(module_fun); + nlr_pop(); + } else { + // uncaught exception + mp_obj_print_exception(&mp_plat_print, (mp_obj_t)nlr.ret_val); + } +} + +static char *stack_top; +extern int _py_heap_start, _py_heap_end; + +int main(void) { + + while(1) { + int stack_dummy; + stack_top = (char*)&stack_dummy; + + Board_SystemInit(); + SystemCoreClockUpdate(); + SysTick_Config(SystemCoreClock/1000); + Board_Init(); + + gc_init(&_py_heap_start, &_py_heap_end); + + mp_init(); + mp_obj_list_init(mp_sys_path, 0); + mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_)); // current dir (or base dir of the script) + mp_obj_list_init(mp_sys_argv, 0); + + pyexec_friendly_repl(); + + mp_deinit(); + } + + return 0; +} + +void gc_collect(void) { + // WARNING: This gc_collect implementation doesn't try to get root + // pointers from CPU registers, and thus may function incorrectly. + void *dummy; + gc_collect_start(); + gc_collect_root(&dummy, ((mp_uint_t)stack_top - (mp_uint_t)&dummy) / sizeof(mp_uint_t)); + gc_collect_end(); + gc_dump_info(); +} + +mp_lexer_t *mp_lexer_new_from_file(const char *filename) { + mp_raise_OSError(MP_ENOENT); +} + +mp_import_stat_t mp_import_stat(const char *path) { + return MP_IMPORT_STAT_NO_EXIST; +} + +mp_obj_t mp_builtin_open(size_t n_args, const mp_obj_t *args, mp_map_t *kwargs) { + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, mp_builtin_open); + +void nlr_jump_fail(void *val) { + while (1); +} + +void NORETURN __fatal_error(const char *msg) { + while (1); +} + +#ifndef NDEBUG +void MP_WEAK __assert_func(const char *file, int line, const char *func, const char *expr) { + printf("Assertion '%s' failed, at file %s:%d\n", expr, file, line); + __fatal_error("Assertion failed"); +} +#endif diff --git a/ports/lpc/mpconfigport.h b/ports/lpc/mpconfigport.h new file mode 100644 index 0000000000000..886d4cc7cb7c1 --- /dev/null +++ b/ports/lpc/mpconfigport.h @@ -0,0 +1,190 @@ +#include +#include "mpconfigboard.h" + +// options to control how MicroPython is built + +#define MICROPY_ENABLE_COMPILER (1) +#define MICROPY_QSTR_BYTES_IN_HASH (1) +#define MICROPY_ALLOC_PATH_MAX (256) +#define MICROPY_ALLOC_PARSE_CHUNK_INIT (16) +#define MICROPY_EMIT_X64 (0) +#define MICROPY_EMIT_THUMB (0) +#define MICROPY_EMIT_INLINE_THUMB (0) +#define MICROPY_COMP_MODULE_CONST (1) +#define MICROPY_COMP_CONST (1) +#define MICROPY_COMP_DOUBLE_TUPLE_ASSIGN (0) +#define MICROPY_COMP_TRIPLE_TUPLE_ASSIGN (0) +#define MICROPY_MEM_STATS (0) +#define MICROPY_DEBUG_PRINTERS (0) +#define MICROPY_ENABLE_GC (1) +#define MICROPY_GC_ALLOC_THRESHOLD (0) +#define MICROPY_REPL_EVENT_DRIVEN (0) +#define MICROPY_HELPER_REPL (1) +#define MICROPY_HELPER_LEXER_UNIX (0) +#define MICROPY_ENABLE_SOURCE_LINE (0) +#define MICROPY_ENABLE_DOC_STRING (0) +#define MICROPY_ERROR_REPORTING (MICROPY_ERROR_REPORTING_TERSE) +#define MICROPY_BUILTIN_METHOD_CHECK_SELF_ARG (0) +#define MICROPY_PY_ASYNC_AWAIT (0) +#define MICROPY_PY_BUILTINS_BYTEARRAY (1) +#define MICROPY_PY_BUILTINS_MEMORYVIEW (1) +#define MICROPY_PY_BUILTINS_ENUMERATE (1) +#define MICROPY_PY_BUILTINS_FILTER (1) +#define MICROPY_PY_BUILTINS_FROZENSET (1) +#define MICROPY_PY_BUILTINS_REVERSED (1) +#define MICROPY_PY_BUILTINS_SET (1) +#define MICROPY_PY_BUILTINS_SLICE (1) +#define MICROPY_PY_BUILTINS_PROPERTY (1) +#define MICROPY_PY_BUILTINS_MIN_MAX (1) +#define MICROPY_PY_BUILTINS_HELP (1) +#define MICROPY_PY_BUILTINS_HELP_MODULES (1) +#define MICROPY_PY___FILE__ (1) +#define MICROPY_PY_GC (1) +#define MICROPY_PY_ARRAY (1) +#define MICROPY_PY_ATTRTUPLE (1) +#define MICROPY_PY_COLLECTIONS (1) +#define MICROPY_PY_MATH (1) +#define MICROPY_PY_CMATH (1) +#define MICROPY_PY_IO (1) +#define MICROPY_PY_STRUCT (1) +#define MICROPY_PY_SYS (1) +#define MICROPY_MODULE_FROZEN_MPY (0) +#define MICROPY_MODULE_WEAK_LINKS (1) +#define MICROPY_CPYTHON_COMPAT (0) +#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_MPZ) +#define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_FLOAT) + +// extended modules +#define MICROPY_PY_UCTYPES (1) +#define MICROPY_PY_UZLIB (1) +#define MICROPY_PY_UJSON (1) +#define MICROPY_PY_URE (1) +#define MICROPY_PY_UHEAPQ (1) +#define MICROPY_PY_UHASHLIB (1) +#define MICROPY_PY_UBINASCII (1) +#define MICROPY_PY_URANDOM (1) +#define MICROPY_PY_URANDOM_EXTRA_FUNCS (1) +#define MICROPY_PY_USELECT (1) +#define MICROPY_PY_UTIMEQ (0) +#define MICROPY_PY_UTIME_MP_HAL (0) +#define MICROPY_PY_MACHINE (0) +#define MICROPY_PY_MACHINE_PULSE (0) +#define MICROPY_PY_MACHINE_PIN_MAKE_NEW mp_pin_make_new +#define MICROPY_PY_MACHINE_I2C (0) +#define MICROPY_PY_MACHINE_I2C_MAKE_NEW machine_hard_i2c_make_new +#define MICROPY_PY_MACHINE_SPI (0) +#define MICROPY_PY_MACHINE_SPI_MSB (SPI_FIRSTBIT_MSB) +#define MICROPY_PY_MACHINE_SPI_LSB (SPI_FIRSTBIT_LSB) +#define MICROPY_PY_MACHINE_SPI_MAKE_NEW machine_hard_spi_make_new +#define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0) +#define MICROPY_PY_MACHINE_SPI_MAX_BAUDRATE (HAL_RCC_GetSysClockFreq() / 48) +#define MICROPY_PY_FRAMEBUF (0) +#define MICROPY_PY_USOCKET (0) +#define MICROPY_PY_NETWORK (0) + +// type definitions for the specific machine + +#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void*)((mp_uint_t)(p) | 1)) + +// This port is intended to be 32-bit, but unfortunately, int32_t for +// different targets may be defined in different ways - either as int +// or as long. This requires different printf formatting specifiers +// to print such value. So, we avoid int32_t and use int directly. +#define UINT_FMT "%u" +#define INT_FMT "%d" +typedef int mp_int_t; // must be pointer size +typedef unsigned mp_uint_t; // must be pointer size + +typedef long mp_off_t; + +#define MP_PLAT_PRINT_STRN(str, len) mp_hal_stdout_tx_strn_cooked(str, len) + +// extra built in names to add to the global namespace +#define MICROPY_PORT_BUILTINS \ + { MP_ROM_QSTR(MP_QSTR_open), MP_ROM_PTR(&mp_builtin_open_obj) }, + +extern const struct _mp_obj_module_t machine_module; // TODO: Implement me +extern const struct _mp_obj_module_t pyb_module; // TODO: Implement me +extern const struct _mp_obj_module_t lpc_module; // TODO: Implement me +extern const struct _mp_obj_module_t mp_module_ubinascii; +extern const struct _mp_obj_module_t mp_module_ure; +extern const struct _mp_obj_module_t mp_module_uzlib; +extern const struct _mp_obj_module_t mp_module_ujson; +extern const struct _mp_obj_module_t mp_module_uheapq; +extern const struct _mp_obj_module_t mp_module_uhashlib; +extern const struct _mp_obj_module_t mp_module_uos; // TODO: Implement me +extern const struct _mp_obj_module_t mp_module_utime; // TODO: Implement me +extern const struct _mp_obj_module_t mp_module_usocket; // TODO: Implement me +extern const struct _mp_obj_module_t mp_module_network; // TODO: Implement me +extern const struct _mp_obj_module_t mp_module_onewire; // TODO: Implement me + +/* TODO: Implement me +#define MICROPY_PORT_BUILTIN_MODULES \ + { MP_ROM_QSTR(MP_QSTR_umachine), MP_ROM_PTR(&machine_module) }, \ + { MP_ROM_QSTR(MP_QSTR_pyb), MP_ROM_PTR(&pyb_module) }, \ + { MP_ROM_QSTR(MP_QSTR_stm), MP_ROM_PTR(&lpc_module) }, \ + { MP_ROM_QSTR(MP_QSTR_uos), MP_ROM_PTR(&mp_module_uos) }, \ + { MP_ROM_QSTR(MP_QSTR_utime), MP_ROM_PTR(&mp_module_utime) }, \ + SOCKET_BUILTIN_MODULE \ + NETWORK_BUILTIN_MODULE \ + { MP_ROM_QSTR(MP_QSTR__onewire), MP_ROM_PTR(&mp_module_onewire) }, \ + */ + +#define SOCKET_BUILTIN_MODULE_WEAK_LINKS + +#define MICROPY_PORT_BUILTIN_MODULE_WEAK_LINKS \ + { MP_ROM_QSTR(MP_QSTR_binascii), MP_ROM_PTR(&mp_module_ubinascii) }, \ + { MP_ROM_QSTR(MP_QSTR_collections), MP_ROM_PTR(&mp_module_collections) }, \ + { MP_ROM_QSTR(MP_QSTR_re), MP_ROM_PTR(&mp_module_ure) }, \ + { MP_ROM_QSTR(MP_QSTR_zlib), MP_ROM_PTR(&mp_module_uzlib) }, \ + { MP_ROM_QSTR(MP_QSTR_json), MP_ROM_PTR(&mp_module_ujson) }, \ + { MP_ROM_QSTR(MP_QSTR_heapq), MP_ROM_PTR(&mp_module_uheapq) }, \ + { MP_ROM_QSTR(MP_QSTR_hashlib), MP_ROM_PTR(&mp_module_uhashlib) }, \ + /*{ MP_ROM_QSTR(MP_QSTR_io), MP_ROM_PTR(&mp_module_io) },*/ \ + /*{ MP_ROM_QSTR(MP_QSTR_os), MP_ROM_PTR(&mp_module_uos) },*/ \ + { MP_ROM_QSTR(MP_QSTR_random), MP_ROM_PTR(&mp_module_urandom) }, \ + /*{ MP_ROM_QSTR(MP_QSTR_time), MP_ROM_PTR(&mp_module_utime) },*/ \ + { MP_ROM_QSTR(MP_QSTR_select), MP_ROM_PTR(&mp_module_uselect) }, \ + SOCKET_BUILTIN_MODULE_WEAK_LINKS \ + { MP_ROM_QSTR(MP_QSTR_struct), MP_ROM_PTR(&mp_module_ustruct) }, \ + /*{ MP_ROM_QSTR(MP_QSTR_machine), MP_ROM_PTR(&machine_module) },*/ \ + /*{ MP_ROM_QSTR(MP_QSTR_errno), MP_ROM_PTR(&mp_module_uerrno) },*/ \ + +/* TODO Implement me +// extra constants +#define MICROPY_PORT_CONSTANTS \ + { MP_ROM_QSTR(MP_QSTR_umachine), MP_ROM_PTR(&machine_module) }, \ + { MP_ROM_QSTR(MP_QSTR_machine), MP_ROM_PTR(&machine_module) }, \ + { MP_ROM_QSTR(MP_QSTR_pyb), MP_ROM_PTR(&pyb_module) }, \ + { MP_ROM_QSTR(MP_QSTR_lpc), MP_ROM_PTR(&lpc_module) }, \ +*/ + +// We need to provide a declaration/definition of alloca() +#include + +#if MICROPY_PY_THREAD +#define MICROPY_EVENT_POLL_HOOK \ + do { \ + extern void mp_handle_pending(void); \ + mp_handle_pending(); \ + if (pyb_thread_enabled) { \ + MP_THREAD_GIL_EXIT(); \ + pyb_thread_yield(); \ + MP_THREAD_GIL_ENTER(); \ + } else { \ + __asm volatile("wfi"); \ + } \ + } while (0); +#else +#define MICROPY_EVENT_POLL_HOOK \ + do { \ + extern void mp_handle_pending(void); \ + mp_handle_pending(); \ + __asm volatile("wfi"); \ + } while (0); +#endif + +#define MP_STATE_PORT MP_STATE_VM + +#define MICROPY_PORT_ROOT_POINTERS \ + const char *readline_hist[8]; diff --git a/ports/lpc/mphalport.c b/ports/lpc/mphalport.c new file mode 100644 index 0000000000000..a3d1b402b5c56 --- /dev/null +++ b/ports/lpc/mphalport.c @@ -0,0 +1,19 @@ +#include "py/mphal.h" +#include "board.h" + +int mp_hal_stdin_rx_chr(void) { + for (;;) { + if (Chip_UART_ReadLineStatus(CONSOLE_UART) & UART_LSR_RDR) { + return (int) Chip_UART_ReadByte(CONSOLE_UART); + } + } + return -1; +} + +void mp_hal_stdout_tx_strn(const char *str, size_t len) { + for (; len > 0; --len) { + uint8_t ch = (uint8_t) *str++; + while ((Chip_UART_ReadLineStatus(CONSOLE_UART) & UART_LSR_THRE) == 0) {} + Chip_UART_SendByte(CONSOLE_UART, ch); + } +} diff --git a/ports/lpc/mphalport.h b/ports/lpc/mphalport.h new file mode 100644 index 0000000000000..60d68bd2d6d50 --- /dev/null +++ b/ports/lpc/mphalport.h @@ -0,0 +1,2 @@ +static inline mp_uint_t mp_hal_ticks_ms(void) { return 0; } +static inline void mp_hal_set_interrupt_char(char c) {} diff --git a/ports/lpc/qstrdefsport.h b/ports/lpc/qstrdefsport.h new file mode 100644 index 0000000000000..3ba897069bf73 --- /dev/null +++ b/ports/lpc/qstrdefsport.h @@ -0,0 +1 @@ +// qstrs specific to this port pFad - Phonifier reborn

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