diff --git a/ports/stm32/modmachine.c b/ports/stm32/modmachine.c
index ac4d8712397e4..a34a569730902 100644
--- a/ports/stm32/modmachine.c
+++ b/ports/stm32/modmachine.c
@@ -89,6 +89,10 @@
#define PYB_RESET_HARD (2)
#define PYB_RESET_WDT (3)
#define PYB_RESET_DEEPSLEEP (4)
+#if defined(STM32F7)
+#define PYB_RESET_DEEPSLEEP_X1 (5)
+#define PYB_RESET_DEEPSLEEP_X18 (6)
+#endif
STATIC uint32_t reset_cause;
@@ -104,6 +108,14 @@ void machine_init(void) {
// came out of standby
reset_cause = PYB_RESET_DEEPSLEEP;
PWR->CR1 |= PWR_CR1_CSBF;
+ if (PWR->CSR2 & PWR_CSR2_WUPF1) {
+ reset_cause = PYB_RESET_DEEPSLEEP_X1;
+ PWR->CR2 |= PWR_CR2_CWUPF1;
+ } else if (PWR->CSR2 & PWR_CSR2_WUPF4) {
+ reset_cause = PYB_RESET_DEEPSLEEP_X18;
+ PWR->CR2 |= PWR_CR2_CWUPF4;
+ }
+
} else
#elif defined(STM32H7)
if (PWR->CPUCR & PWR_CPUCR_SBF || PWR->CPUCR & PWR_CPUCR_STOPF) {
@@ -373,6 +385,7 @@ STATIC mp_obj_t machine_deepsleep(size_t n_args, const mp_obj_t *args) {
powerctrl_enter_standby_mode();
return mp_const_none;
}
+
MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_deepsleep_obj, 0, 1, machine_deepsleep);
STATIC mp_obj_t machine_reset_cause(void) {
@@ -435,6 +448,10 @@ STATIC const mp_rom_map_elem_t machine_module_globals_table[] = {
{ MP_ROM_QSTR(MP_QSTR_WDT_RESET), MP_ROM_INT(PYB_RESET_WDT) },
{ MP_ROM_QSTR(MP_QSTR_DEEPSLEEP_RESET), MP_ROM_INT(PYB_RESET_DEEPSLEEP) },
{ MP_ROM_QSTR(MP_QSTR_SOFT_RESET), MP_ROM_INT(PYB_RESET_SOFT) },
+ #if defined(STM32F7)
+ { MP_ROM_QSTR(MP_QSTR_DEEPSLEEP_X1_RESET), MP_ROM_INT(PYB_RESET_DEEPSLEEP_X1) },
+ { MP_ROM_QSTR(MP_QSTR_DEEPSLEEP_X18_RESET), MP_ROM_INT(PYB_RESET_DEEPSLEEP_X18) },
+ #endif
#if 0
{ MP_ROM_QSTR(MP_QSTR_WLAN_WAKE), MP_ROM_INT(PYB_SLP_WAKED_BY_WLAN) },
{ MP_ROM_QSTR(MP_QSTR_PIN_WAKE), MP_ROM_INT(PYB_SLP_WAKED_BY_GPIO) },
diff --git a/ports/stm32/modpyb.c b/ports/stm32/modpyb.c
index c92090699108e..68d81cd715293 100644
--- a/ports/stm32/modpyb.c
+++ b/ports/stm32/modpyb.c
@@ -56,8 +56,54 @@
#include "extmod/vfs.h"
#include "extmod/utime_mphal.h"
+#if defined(STM32F7)
+#include "powerctrl.h"
+#define PYB_PWR_WKUP_X1 (PWR_CSR2_EWUP1)
+#define PYB_PWR_WKUP_X1_FALLING (PWR_CSR2_EWUP1)
+#define PYB_PWR_WKUP_X1_RISING (0)
+#define PYB_PWR_WKUP_X18 (PWR_CSR2_EWUP4)
+#define PYB_PWR_WKUP_X18_FALLING (PWR_CSR2_EWUP4)
+#define PYB_PWR_WKUP_X18_RISING (0)
+#endif
+
char pyb_country_code[2];
+STATIC mp_obj_t pyb_standby(size_t n_args, const mp_obj_t *args) {
+ char has_args = false;
+ int ms_value = 0;
+
+ #if defined(STM32F7)
+ // make sure all pins are cleared
+ PWR->CSR2 &= ~(PWR_CSR2_EWUP6 | PWR_CSR2_EWUP5 | PWR_CSR2_EWUP4 | PWR_CSR2_EWUP3 | PWR_CSR2_EWUP2 | PWR_CSR2_EWUP1);
+ if (n_args != 0) {
+ has_args = true;
+ ms_value = mp_obj_get_int(args[0]);
+
+ if (n_args == 3) {
+ uint32_t pins = mp_obj_get_int(args[1]);
+ uint32_t falling = mp_obj_get_int(args[2]);
+
+ if ((pins | (PYB_PWR_WKUP_X1 | PYB_PWR_WKUP_X18)) != 0) {
+ PWR->CSR2 |= pins;
+ }
+ if ((falling | (PYB_PWR_WKUP_X1_FALLING | PYB_PWR_WKUP_X18_FALLING)) != 0) {
+ PWR->CR2 |= falling;
+ }
+ }
+ }
+ #endif
+ if (has_args == true && ms_value != 0) {
+ mp_obj_t args2[2] = {MP_OBJ_NULL, args[0]};
+
+ pyb_rtc_wakeup(2, args2);
+ }
+ powerctrl_enter_standby_mode();
+
+ return mp_const_none;
+}
+
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_standby_obj, 0, 3, pyb_standby);
+
STATIC mp_obj_t pyb_fault_debug(mp_obj_t value) {
pyb_hard_fault_debug = mp_obj_is_true(value);
return mp_const_none;
@@ -155,7 +201,7 @@ STATIC const mp_rom_map_elem_t pyb_module_globals_table[] = {
#if MICROPY_PY_PYB_LEGACY
{ MP_ROM_QSTR(MP_QSTR_stop), MP_ROM_PTR(&machine_lightsleep_obj) },
- { MP_ROM_QSTR(MP_QSTR_standby), MP_ROM_PTR(&machine_deepsleep_obj) },
+ { MP_ROM_QSTR(MP_QSTR_standby), MP_ROM_PTR(&pyb_standby_obj) },
#endif
{ MP_ROM_QSTR(MP_QSTR_main), MP_ROM_PTR(&pyb_main_obj) },
{ MP_ROM_QSTR(MP_QSTR_repl_uart), MP_ROM_PTR(&pyb_repl_uart_obj) },
@@ -257,6 +303,14 @@ STATIC const mp_rom_map_elem_t pyb_module_globals_table[] = {
#if MICROPY_HW_HAS_LCD
{ MP_ROM_QSTR(MP_QSTR_LCD), MP_ROM_PTR(&pyb_lcd_type) },
#endif
+ #if defined(STM32F7)
+ { MP_ROM_QSTR(MP_QSTR_WKUP_X1), MP_ROM_INT(PYB_PWR_WKUP_X1) },
+ { MP_ROM_QSTR(MP_QSTR_WKUP_X1_FALLING), MP_ROM_INT(PYB_PWR_WKUP_X1_FALLING) },
+ { MP_ROM_QSTR(MP_QSTR_WKUP_X1_RISING), MP_ROM_INT(PYB_PWR_WKUP_X1_RISING) },
+ { MP_ROM_QSTR(MP_QSTR_WKUP_X18), MP_ROM_INT(PYB_PWR_WKUP_X18) },
+ { MP_ROM_QSTR(MP_QSTR_WKUP_X18_FALLING), MP_ROM_INT(PYB_PWR_WKUP_X18_FALLING) },
+ { MP_ROM_QSTR(MP_QSTR_WKUP_X18_RISING), MP_ROM_INT(PYB_PWR_WKUP_X18_RISING) },
+ #endif
};
STATIC MP_DEFINE_CONST_DICT(pyb_module_globals, pyb_module_globals_table);
diff --git a/ports/stm32/powerctrl.c b/ports/stm32/powerctrl.c
index 946185fba09d3..4011061395ca8 100644
--- a/ports/stm32/powerctrl.c
+++ b/ports/stm32/powerctrl.c
@@ -629,10 +629,14 @@ void powerctrl_enter_standby_mode(void) {
RTC->ISR &= ~ISR_BITS;
#if defined(STM32F7)
+ // Save user EWUP state
+ uint32_t csr2_ewup = PWR->CSR2 & (PWR_CSR2_EWUP6 | PWR_CSR2_EWUP5 | PWR_CSR2_EWUP4 | PWR_CSR2_EWUP3 | PWR_CSR2_EWUP2 | PWR_CSR2_EWUP1);
// disable wake-up flags
PWR->CSR2 &= ~(PWR_CSR2_EWUP6 | PWR_CSR2_EWUP5 | PWR_CSR2_EWUP4 | PWR_CSR2_EWUP3 | PWR_CSR2_EWUP2 | PWR_CSR2_EWUP1);
// clear global wake-up flag
PWR->CR2 |= PWR_CR2_CWUPF6 | PWR_CR2_CWUPF5 | PWR_CR2_CWUPF4 | PWR_CR2_CWUPF3 | PWR_CR2_CWUPF2 | PWR_CR2_CWUPF1;
+ // Restore state
+ PWR->CSR2 |= csr2_ewup;
#elif defined(STM32H7)
// TODO
#elif defined(STM32L4) || defined(STM32WB)
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