diff --git a/ports/stm32/boards/AEMICS_PYglet/bdev.c b/ports/stm32/boards/AEMICS_PYglet/bdev.c
new file mode 100644
index 0000000000000..286b686ac10d0
--- /dev/null
+++ b/ports/stm32/boards/AEMICS_PYglet/bdev.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018-2019 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "storage.h"
+#include "qspi.h"
+#include "py/mphal.h"
+
+#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
+// Shared cache for first and second SPI block devices
+STATIC mp_spiflash_cache_t spi_bdev_cache;
+#endif
+
+// First external SPI flash uses software QSPI interface
+
+STATIC const mp_soft_qspi_obj_t soft_qspi_bus = {
+ .cs = MICROPY_HW_QSPIFLASH_CS,
+ .clk = MICROPY_HW_QSPIFLASH_SCK,
+ .io0 = MICROPY_HW_QSPIFLASH_IO0,
+ .io1 = MICROPY_HW_QSPIFLASH_IO1,
+ .io2 = MICROPY_HW_QSPIFLASH_IO2,
+ .io3 = MICROPY_HW_QSPIFLASH_IO3,
+};
+
+const mp_spiflash_config_t spiflash_config = {
+ .bus_kind = MP_SPIFLASH_BUS_QSPI,
+ .bus.u_qspi.data = (void *)&soft_qspi_bus,
+ .bus.u_qspi.proto = &mp_soft_qspi_proto,
+ #if MICROPY_HW_SPIFLASH_ENABLE_CACHE
+ .cache = &spi_bdev_cache,
+ #endif
+};
+
+spi_bdev_t spi_bdev;
+
+void board_early_init(void) {
+ qspi_init();
+ qspi_memory_map();
+}
diff --git a/ports/stm32/boards/AEMICS_PYglet/board.json b/ports/stm32/boards/AEMICS_PYglet/board.json
new file mode 100644
index 0000000000000..ac28e1e89fd40
--- /dev/null
+++ b/ports/stm32/boards/AEMICS_PYglet/board.json
@@ -0,0 +1,16 @@
+{
+ "deploy": [
+ "./deploy.md"
+ ],
+ "docs": "",
+ "features": [],
+ "id": "AEMICS_PYglet",
+ "images": [
+ "aemics_pyglet_1.png"
+ ],
+ "mcu": "stm32g4",
+ "product": "AEMICS PYglet",
+ "thumbnail": "",
+ "url": "https://www.aemics.nl/pyg/",
+ "vendor": "AEMICS"
+}
diff --git a/ports/stm32/boards/AEMICS_PYglet/deploy.md b/ports/stm32/boards/AEMICS_PYglet/deploy.md
new file mode 100644
index 0000000000000..3c97bc2a381c8
--- /dev/null
+++ b/ports/stm32/boards/AEMICS_PYglet/deploy.md
@@ -0,0 +1,17 @@
+### AEMICS PYglet via DFU
+
+One you have downloaded or made the appropriate DFU file it can be flashed directly to your PYglet
+using a DFU programmer (Like STM32 Cube Programmer, see[here](https://www.st.com/en/development-tools/stm32cubeprog.html)).
+
+The board can also be programmed via the ST DFU bootloader, using e.g. [dfu-util](http://dfu-util.sourceforge.net/) or [pydfu.py](https://github.com/micropython/micropython/blob/master/tools/pydfu.py).
+
+To enter the bootloader the `BOOT0` pin can be connected to `3V3` during reset, or you can use `machine.bootloader()` from the MicroPython REPL.
+
+```bash
+dfu-util --alt 0 -D build-AEMICS_PYglet/firmware.dfu
+```
+
+`3V3` is on Pin 1 of the PYglet module.
+`BOOT0` is on Pin 16 of the PYglet module.
+
+Check the [AEMICS PYg page](https://www.aemics.nl/pyg/) for more information.
diff --git a/ports/stm32/boards/AEMICS_PYglet/mpconfigboard.h b/ports/stm32/boards/AEMICS_PYglet/mpconfigboard.h
new file mode 100644
index 0000000000000..ceb1893cf3252
--- /dev/null
+++ b/ports/stm32/boards/AEMICS_PYglet/mpconfigboard.h
@@ -0,0 +1,107 @@
+#define MICROPY_HW_BOARD_NAME "AEMICS PYglet"
+#define MICROPY_HW_MCU_NAME "STM32G473"
+#define MICROPY_HW_FLASH_FS_LABEL "PYglet"
+
+#define MICROPY_HW_USB_FS (1)
+#define MICROPY_HW_ENABLE_RTC (0)
+#define MICROPY_HW_ENABLE_RNG (1)
+#define MICROPY_HW_ENABLE_ADC (1)
+#define MICROPY_HW_ENABLE_DAC (1) // A4, A5
+#define MICROPY_HW_ENABLE_USB (1) // A12 (dp), A11 (dm)
+#define MICROPY_HW_HAS_SWITCH (1)
+#define MICROPY_HW_HAS_LED (1)
+#define MICROPY_HW_HAS_FLASH (1) // QSPI extflash mounted
+// #define MICROPY_HW_UART_REPL (1)
+// #define MICROPY_HW_UART_REPL_BAUD (115200)
+
+#define MICROPY_BOARD_EARLY_INIT board_early_init
+void board_early_init(void);
+
+#if MICROPY_HW_USB_FS == 1
+#define MICROPY_HW_USB_MANUFACTURER_STRING "AEMICS"
+#endif
+#define MICROPY_HW_USB_PRODUCT_FS_STRING MICROPY_HW_BOARD_NAME
+
+
+// // ports/stm32/mpconfigport.h
+// #define MICROPY_PY_LWIP (0) // Geen ETH
+// #define MICROPY_PY_USSL (0)
+// #define MICROPY_SSL_MBEDTLS (0)
+// #define MICROPY_PY_UASYNCIO (0)
+// #define MICROPY_PY_UZLIB (0)
+// #define MICROPY_PY_UJSON (1)
+// #define MICROPY_PY_URE (0)
+// #define MICROPY_PY_FRAMEBUF (0)
+// #define MICROPY_PY_USOCKET (0)
+// #define MICROPY_PY_NETWORK (0)
+// #define MICROPY_PERSISTENT_CODE_LOAD (1)
+
+// The board has an 16MHz HSI, the following gives 170MHz CPU speed and 48MHz for USB
+#define MICROPY_HW_CLK_USE_HSE (0)
+#define MICROPY_HW_CLK_USE_HSI (1)
+#define MICROPY_HW_CLK_PLLM (4)
+#define MICROPY_HW_CLK_PLLN (85)
+#define MICROPY_HW_CLK_PLLP (2)
+#define MICROPY_HW_CLK_PLLQ (2)
+#define MICROPY_HW_CLK_PLLR (2)
+
+#define MICROPY_HW_CLK_USE_HSI48 (1)
+
+// 4 wait states
+#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_8
+
+// UART config
+#define MICROPY_HW_UART4_TX (pin_C10)
+#define MICROPY_HW_UART4_RX (pin_C11)
+
+// xSPI
+// SPI1
+#define MICROPY_HW_SPI1_NSS (pin_A3)
+#define MICROPY_HW_SPI1_SCK (pin_A5)
+#define MICROPY_HW_SPI1_MISO (pin_B4)
+#define MICROPY_HW_SPI1_MOSI (pin_B5)
+// SPI2
+#define MICROPY_HW_SPI2_NSS (pin_B12)
+#define MICROPY_HW_SPI2_SCK (pin_B13)
+#define MICROPY_HW_SPI2_MISO (pin_B14)
+#define MICROPY_HW_SPI2_MOSI (pin_B15)
+// //SPI3
+// #define MICROPY_HW_SPI3_NSS (pin_A15)
+// #define MICROPY_HW_SPI3_SCK (pin_C10)
+// #define MICROPY_HW_SPI3_MISO (pin_C11)
+// #define MICROPY_HW_SPI3_MOSI (pin_C12)
+
+// QSPI1
+// 8MBit external QSPI flash, used for either the filesystem or XIP memory mapped
+#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (23)
+#define MICROPY_HW_QSPIFLASH_CS (pin_A2)
+#define MICROPY_HW_QSPIFLASH_SCK (pin_A3)
+#define MICROPY_HW_QSPIFLASH_IO0 (pin_B1)
+#define MICROPY_HW_QSPIFLASH_IO1 (pin_B0)
+#define MICROPY_HW_QSPIFLASH_IO2 (pin_A7)
+#define MICROPY_HW_QSPIFLASH_IO3 (pin_A6)
+extern const struct _mp_spiflash_config_t spiflash_config;
+extern struct _spi_bdev_t spi_bdev;
+#if !USE_QSPI_XIP
+#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0)
+#define MICROPY_HW_SPIFLASH_ENABLE_CACHE (1)
+#define MICROPY_HW_BDEV_IOCTL(op, arg) ( \
+ (op) == BDEV_IOCTL_NUM_BLOCKS ? ((1 << MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2) / 8 / FLASH_BLOCK_SIZE) : \
+ (op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \
+ spi_bdev_ioctl(&spi_bdev, (op), (arg)) \
+ )
+#define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n))
+#define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n))
+#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) // for extended block protocol
+#endif
+
+// USRSW has pullup, pressing the switch makes the input go low
+#define MICROPY_HW_USRSW_PIN (pin_B9)
+#define MICROPY_HW_USRSW_PULL (GPIO_PULLDOWN)
+#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_RISING)
+#define MICROPY_HW_USRSW_PRESSED (1)
+
+// LED
+#define MICROPY_HW_LED1 (pin_B7) // Red
+#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
+#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin))
diff --git a/ports/stm32/boards/AEMICS_PYglet/mpconfigboard.mk b/ports/stm32/boards/AEMICS_PYglet/mpconfigboard.mk
new file mode 100644
index 0000000000000..af03633ff1d12
--- /dev/null
+++ b/ports/stm32/boards/AEMICS_PYglet/mpconfigboard.mk
@@ -0,0 +1,8 @@
+DEBUG = 0
+
+# MCU settings
+MCU_SERIES = g4
+CMSIS_MCU = STM32G473xx
+MICROPY_FLOAT_IMPL = double
+AF_FILE = boards/stm32g473_af.csv
+LD_FILES = boards/stm32g474.ld boards/common_basic.ld
diff --git a/ports/stm32/boards/AEMICS_PYglet/pins.csv b/ports/stm32/boards/AEMICS_PYglet/pins.csv
new file mode 100644
index 0000000000000..ba004c2d90c68
--- /dev/null
+++ b/ports/stm32/boards/AEMICS_PYglet/pins.csv
@@ -0,0 +1,95 @@
+LED_RED,PB7
+SW,PB9
+PA0,PA0
+PA1,PA1
+QSPI_CSN,PA2
+QSPI_CLK,PA3
+PA4,PA4
+PA5,PA5
+QSPI_IO3,PA6
+QSPI_IO2,PA7
+PA8,PA8
+PA9,PA9
+PA10,PA10
+USB_DN,PA11
+USB_DP,PA12
+PA13,PA13
+PA14,PA14
+PA15,PA15
+QSPI_IO1,PB0
+QSPI_IO0,PB1
+PB2,PB2
+PB3,PB3
+PB4,PB4
+PB5,PB5
+PB6,PB6
+PB7,PB7
+BOOT0,PB8
+PB9,PB9
+PB10,PB10
+PB11,PB11
+SPI2_NSS,PB12
+SPI2_SCK,PB13
+SPI2_MISO,PB14
+SPI2_MOSI,PB15
+PC0,PC0
+PC1,PC1
+PC2,PC2
+PC3,PC3
+PC4,PC4
+PC5,PC5
+I2C4_SCL,PC6
+I2C4_SDA,PC7
+PC8,PC8
+PC9,PC9
+UART4_TX,PC10
+UART4_RX,PC11
+PC12,PC12
+PC13,PC13
+OSC32_IN,PC14
+OSC32_OUT,PC15
+PD2,PD2
+OSC_IN,PF0
+OSC_OUT,PF1
+RSTN,PG10
+P2,PC13
+P3,PB10
+P4,PC8
+P5,PC9
+P6,PA10
+P7,PA13
+P8,PA14
+P9,PA15
+P10,PC12
+P11,PD2
+P12,PB3
+P13,PB4
+P14,PB5
+P15,PB6
+P16,PB8
+P17,PC6
+P18,PC7
+P23,PB9
+P25,PA11
+P26,PA12
+P27,PB14
+P28,PB15
+P29,PB13
+P30,PB12
+P31,PC0
+P32,PC1
+P33,PC2
+P34,PC3
+P35,PA0
+P36,PA1
+P37,PA9
+P38,PA8
+P39,PA4
+P40,PA5
+P41,PC4
+P42,PC5
+P43,PB2
+P44,PB11
+P45,PG10
+P46,PC11
+P47,PC10
diff --git a/ports/stm32/boards/AEMICS_PYglet/stm32g4xx_hal_conf.h b/ports/stm32/boards/AEMICS_PYglet/stm32g4xx_hal_conf.h
new file mode 100644
index 0000000000000..55ea1f8025ba3
--- /dev/null
+++ b/ports/stm32/boards/AEMICS_PYglet/stm32g4xx_hal_conf.h
@@ -0,0 +1,13 @@
+#ifndef MICROPY_INCLUDED_STM32G4xx_HAL_CONF_H
+#define MICROPY_INCLUDED_STM32G4xx_HAL_CONF_H
+
+#include "boards/stm32g4xx_hal_conf_base.h"
+
+#define HSE_VALUE (8000000)
+#define LSE_VALUE (32768) /*!< Value of the External oscillator in Hz*/
+#define EXTERNAL_CLOCK_VALUE (0) /*!< Value of the External clock source in Hz*/
+
+#define HSE_STARTUP_TIMEOUT (100) /*!< Time out for HSE start up, in ms */
+#define LSE_STARTUP_TIMEOUT (5000) /*!< Time out for LSE start up, in ms */
+
+#endif /* MICROPY_INCLUDED_STM32G4xx_HAL_CONF_H */
diff --git a/ports/stm32/boards/stm32g473_af.csv b/ports/stm32/boards/stm32g473_af.csv
new file mode 100644
index 0000000000000..758ab427ae80a
--- /dev/null
+++ b/ports/stm32/boards/stm32g473_af.csv
@@ -0,0 +1,109 @@
+Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,
+,,SYS_AF,LPTIM1/TIM2/5/15/16/17,I2C3/TIM1/2/3/4/5/8/15/20/GPCOMP1,QUADSPI/I2C3/4/SAI1/USB/TIM8/15/20/GPCOMP3/TSC,I2C1/2/3/4/TIM1/8/16/17,QUADSPI/SPI1/2/3/4/I2S2/3/I2C4/UART4/5/TIM8/Infrared,QUADSPI/SPI2/3/I2S2/3/TIM1/5/8/20/Infrared,USART1/2/3/CAN/GPCOMP5/6/7,I2C3/4/UART4/5/LPUART1/GPCOMP1/2/3/4/5/6/7,CAN/TIM1/8/15/CAN1/2,QUADSPI/TIM2/3/4/8/17,LPTIM1/TIM1/8/CAN1/3,SDIO/FMC/LPUART1/SAI1TIM1,SAI1/OPAMP2,UART4/5/SAI1/TIM2/15/UCPD,EVENT,
+PortA,PA0,,TIM2_CH1,TIM5_CH1,,,,,USART2_CTS,COMP1_OUT,TIM8_BKIN,TIM8_ETR,,,,TIM2_ETR,EVENTOUT
+PortA,PA1,RTC_REFIN,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS_DE,,TIM15_CH1N,,,,,,EVENTOUT
+PortA,PA2,,TIM2_CH3,TIM5_CH3,,,,,USART2_TX,COMP2_OUT,TIM15_CH1,QUADSPI_BK1_NCS,,LPUART1_TX,,UCPD1_FRSTX,EVENTOUT
+PortA,PA3,,TIM2_CH4,TIM5_CH4,SAI1_CK1,,,,USART2_RX,,TIM15_CH2,QUADSPI_CLK,,LPUART1_RX,SAI1_MCLK_A,,EVENTOUT
+PortA,PA4,,,TIM3_CH2,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,SAI1_FS_B,,EVENTOUT
+PortA,PA5,,TIM2_CH1,TIM2_ETR,,,SPI1_SCK,,,,,,,,,UCPD1_FRSTX,EVENTOUT
+PortA,PA6,,TIM16_CH1,TIM3_CH1,,TIM8_BKIN,SPI1_MISO,TIM1_BKIN,,COMP1_OUT,,QUADSPI_BK1_IO3,,LPUART1_CTS,,,EVENTOUT
+PortA,PA7,,TIM17_CH1,TIM3_CH2,,TIM8_CH1N,SPI1_MOSI,TIM1_CH1N,,COMP2_OUT,,QUADSPI_BK1_IO2,,,,UCPD1_FRSTX,EVENTOUT
+PortA,PA8,MCO,,,,I2C2_SMBA,I2S2_MCK,TIM1_CH1,USART1_CK,COMP7_OUT,,TIM4_ETR,CAN3_RX,SAI1_CK2,,SAI1_SCK_A,EVENTOUT
+PortA,PA9,,,I2C3_SMBA,,I2C2_SCL,I2S3_MCK,TIM1_CH2,USART1_TX,COMP5_OUT,TIM15_BKIN,TIM2_CH3,CAN1_RXFD,,,SAI1_FS_A,EVENTOUT
+PortA,PA10,,TIM17_BKIN,I2C3_SCL,USB_CRS_SYNC,I2C2_SDA,SPI2_MISO,TIM1_CH3,USART1_RX,COMP6_OUT,CAN1_TXFD,TIM2_CH4,TIM8_BKIN,SAI1_D1,,SAI1_SD_A,EVENTOUT
+PortA,PA11,,,,,,SPI2_MOSI/I2S2_SD,TIM1_CH1N,USART1_CTS,COMP1_OUT,CAN1_RX,TIM4_CH1,TIM1_CH4,TIM1_BKIN2,,,EVENTOUT
+PortA,PA12,,TIM16_CH1,,,,I2SCKIN,TIM1_CH2N,USART1_RTS_DE,COMP2_OUT,CAN1_TX,TIM4_CH2,TIM1_ETR,,,,EVENTOUT
+PortA,PA13,SWDIO/JTMS,TIM16_CH1N,,,,IR_OUT,,USART3_CTS,,,TIM4_CH3,,,SAI1_SD_B,,EVENTOUT
+PortA,PA14,SWCLK/JTCK,LPTIM1_OUT,,I2C4_SMBA,I2C1_SDA,TIM8_CH2,TIM1_BKIN,USART2_TX,,,,CAN3_TXFD,,SAI1_FS_B,,EVENTOUT
+PortA,PA15,JTDI,TIM2_CH1,TIM8_CH1,,I2C1_SCL,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_RX,UART4_RTS_DE,TIM1_BKIN,,CAN3_TX,,,TIM2_ETR,EVENTOUT
+PortB,PB0,,,TIM3_CH3,,TIM8_CH2N,,TIM1_CH2N,,,,QUADSPI_BK1_IO1,,,,UCPD1_FRSTX,EVENTOUT
+PortB,PB1,,,TIM3_CH4,,TIM8_CH3N,,TIM1_CH3N,,COMP4_OUT,,QUADSPI_BK1_IO0,,LPUART1_RTS_DE,,,EVENTOUT
+PortB,PB2,,LPTIM1_OUT,TIM5_CH1,TIM20_CH1,I2C3_SMBA,,,,,,QUADSPI_BK2_IO1,,,,,EVENTOUT
+PortB,PB3,JTDO/TRACESWO,TIM2_CH2,TIM4_ETR,USB_CRS_SYNC,TIM8_CH1N,SPI1_SCK,SPI3_SCK/I2S3_CK,USART2_TX,,,TIM3_ETR,CAN3_RX,,,SAI1_SCK_B,EVENTOUT
+PortB,PB4,JTRST,TIM16_CH1,TIM3_CH1,,TIM8_CH2N,SPI1_MISO,SPI3_MISO,USART2_RX,UART5_RTS_DE,,TIM17_BKIN,CAN3_TX,,,SAI1_MCLK_B,EVENTOUT
+PortB,PB5,,TIM16_BKIN,TIM3_CH2,TIM8_CH3N,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,USART2_CK,I2C3_SDA,CAN2_RX,TIM17_CH1,LPTIM1_IN1,SAI1_SD_B,,UART5_CTS,EVENTOUT
+PortB,PB6,,TIM16_CH1N,TIM4_CH1,I2C4_SCL,I2C1_SCL,TIM8_CH1,TIM8_ETR,USART1_TX,COMP4_OUT,CAN2_TX,TIM8_BKIN2,LPTIM1_ETR,,,SAI1_FS_B,EVENTOUT
+PortB,PB7,,TIM17_CH1N,TIM4_CH2,I2C4_SDA,I2C1_SDA,TIM8_BKIN,,USART1_RX,COMP3_OUT,CAN2_TXFD,TIM3_CH4,LPTIM1_IN2,FMC_NL,,UART4_CTS,EVENTOUT
+PortB,PB8,,TIM16_CH1,TIM4_CH3,SAI1_CK1,I2C1_SCL,,,USART3_RX,COMP1_OUT,CAN1_RX,TIM8_CH2,,TIM1_BKIN,,SAI1_MCLK_A,EVENTOUT
+PortB,PB9,,TIM17_CH1,TIM4_CH4,SAI1_D2,I2C1_SDA,,IR_OUT,USART3_TX,COMP2_OUT,CAN1_TX,TIM8_CH3,,TIM1_CH3N,,SAI1_FS_A,EVENTOUT
+PortB,PB10,,TIM2_CH3,,,,,,USART3_TX,LPUART1_RX,,QUADSPI_CLK,CAN3_TXFD,TIM1_BKIN,,SAI1_SCK_A,EVENTOUT
+PortB,PB11,,TIM2_CH4,,,,,,USART3_RX,LPUART1_TX,,QUADSPI_BK1_NCS,CAN3_RXFD,,,,EVENTOUT
+PortB,PB12,,,TIM5_ETR,,I2C2_SMBA,SPI2_NSS/I2S2_WS,TIM1_BKIN,USART3_CKLP,UART1_RTS_DE,CAN2_RX,,,,,,EVENTOUT
+PortB,PB13,,,,,,SPI2_SCK/I2S2_CK,TIM1_CH1N,USART3_CTS,LPUART1_CTS,CAN2_TX,,,,,,EVENTOUT
+PortB,PB14,,TIM15_CH1,,,,SPI2_MISO,TIM1_CH2N,USART3_RTS_DE,COMP4_OUT,,,,,,,EVENTOUT
+PortB,PB15,RTC_REFIN,TIM15_CH2,TIM15_CH1N,COMP3_OUT,TIM1_CH3N,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT
+PortC,PC0,,LPTIM1_IN1,TIM1_CH1,,,,,,LPUART1_RX,,,,,,,EVENTOUT
+PortC,PC1,,LPTIM1_OUT,TIM1_CH2,,,,,,LPUART1_TX,,QUADSPI_BK2_IO0,,,SAI1_SD_A,,EVENTOUT
+PortC,PC2,,LPTIM1_IN2,TIM1_CH3,COMP3_OUT,,,TIM20_CH2,,,,QUADSPI_BK2_IO1,,,,,EVENTOUT
+PortC,PC3,,LPTIM1_ETR,TIM1_CH4,SAI1_D1,,,TIM1_BKIN2,,,,QUADSPI_BK2_IO2,,,SAI1_SD_A,,EVENTOUT
+PortC,PC4,,,TIM1_ETR,,I2C2_SCL,,,USART1_TX,,,QUADSPI_BK2_IO3,,,,,EVENTOUT
+PortC,PC5,,,TIM15_BKIN,SAI1_D3,,,TIM1_CH4N,USART1_RX,,,,,,,,EVENTOUT
+PortC,PC6,,,TIM3_CH1,,TIM8_CH1,,I2S2_MCK,COMP6_OUT,I2C4_SCL,,,,,,,EVENTOUT
+PortC,PC7,,,TIM3_CH2,,TIM8_CH2,,I2S3_MCK,COMP5_OUT,I2C4_SDA,,,,,,,EVENTOUT
+PortC,PC8,,,TIM3_CH3,,TIM8_CH3,,TIM20_CH3,COMP7_OUT,I2C3_SCL,,,,,,,EVENTOUT
+PortC,PC9,,,TIM3_CH4,,TIM8_CH4,I2SCKIN,TIM8_BKIN2,,I2C3_SDA,,,,,,,EVENTOUT
+PortC,PC10,,,,,TIM8_CH1N,UART4_TX,SPI3_SCK/I2S3_CK,USART3_TX,,,,,,,,EVENTOUT
+PortC,PC11,,,,,TIM8_CH2N,UART4_RX,SPI3_MISO,USART3_RX,I2C3_SDA,,,,,,,EVENTOUT
+PortC,PC12,,TIM5_CH2,,,TIM8_CH3N,UART5_TX,SPI3_MOSI/I2S3_SD,USART3_CK,,,,,,,UCPD1_FRSTX,EVENTOUT
+PortC,PC13,,,TIM1_BKIN,,TIM1_CH1N,,TIM8_CH4N,,,,,,,,,EVENTOUT
+PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT
+PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT
+PortD,PD0,,,,,,,TIM8_CH4N,,,CAN1_RX,,,FMC_D2,,,EVENTOUT
+PortD,PD1,,,,,TIM8_CH4,,TIM8_BKIN2,,,CAN1_TX,,,FMC_D3,,,EVENTOUT
+PortD,PD2,,,TIM3_ETR,,TIM8_BKIN,UART5_RX,,,,,,,,,,EVENTOUT
+PortD,PD3,,,TIM2_CH1/TIM2_ETR,,,,,USART2_CTS,,,QUADSPI_BK2_NCS,,FMC_CLK,,,EVENTOUT
+PortD,PD4,,,TIM2_CH2,,,,,USART2_RTS_DE,,CAN1_RXFD,QUADSPI_BK2_IO0,,FMC_NOE,,,EVENTOUT
+PortD,PD5,,,,,,,,USART2_TX,,CAN1_TXFD,QUADSPI_BK2_IO1,,FMC_NWE,,,EVENTOUT
+PortD,PD6,,,TIM2_CH4,SAI1_D1,,,,USART2_RX,,CAN2_RXFD,QUADSPI_BK2_IO2,,FMC_NWAIT,SAI1_SD_A,,EVENTOUT
+PortD,PD7,,,TIM2_CH3,,,,,USART2_CK,,,QUADSPI_BK2_IO3,,FMC_NCE/FMC_NE1,,,EVENTOUT
+PortD,PD8,,,,,,,,USART3_TX,,,,,FMC_D13,,,EVENTOUT
+PortD,PD9,,,,,,,,USART3_RX,,CAN2_RXFD,,,FMC_D14,,,EVENTOUT
+PortD,PD10,,,,,,,,USART3_CK,,CAN2_TXFD,,,FMC_D15,,,EVENTOUT
+PortD,PD11,,TIM5_ETR,,,I2C4_SMBA,,,USART3_CTS,,,,,FMC_A16,,,EVENTOUT
+PortD,PD12,,,TIM4_CH1,,,,,USART3_RTS_DE,,,,,FMC_A17,,,EVENTOUT
+PortD,PD13,,,TIM4_CH2,,,,,,,,,,FMC_A18,,,EVENTOUT
+PortD,PD14,,,TIM4_CH3,,,,,,,,,,FMC_D0,,,EVENTOUT
+PortD,PD15,,,TIM4_CH4,,,,SPI2_NSS,,,,,,FMC_D1,,,EVENTOUT
+PortE,PE0,,,TIM4_ETR,TIM20_CH4N,TIM16_CH1,,TIM20_ETR,USART1_TX,,CAN1_RXFD,,,FMC_NBL0,,,EVENTOUT
+PortE,PE1,,,,,TIM17_CH1,,TIM20_CH4,USART1_RX,,CAN1_TXFD,,,FMC_NBL1,,,EVENTOUT
+PortE,PE2,TRACECK,,TIM3_CH1,SAI1_CK1,,SPI4_SCK,TIM20_CH1,,,,,,FMC_A23,SAI1_MCLK_A,,EVENTOUT
+PortE,PE3,TRACED0,,TIM3_CH2,,,SPI4_NSS,TIM20_CH2,,,,,,FMC_A19,SAI1_SD_B,,EVENTOUT
+PortE,PE4,TRACED1,,TIM3_CH3,SAI1_D2,,SPI4_NSS,TIM20_CH1N,,,,,,FMC_A20,SAI1_FS_A,,EVENTOUT
+PortE,PE5,TRACED2,,TIM3_CH4,SAI1_CK2,,SPI4_MISO,TIM20_CH2N,,,,,,FMC_A21,SAI1_SCK_A,,EVENTOUT
+PortE,PE6,TRACED3,,,SAI1_D1,,SPI4_MOSI,TIM20_CH3N,,,,,,FMC_A22,SAI1_SD_A,,EVENTOUT
+PortE,PE7,,,TIM1_ETR,,,,,,,,,,FMC_D4,SAI1_SD_B,,EVENTOUT
+PortE,PE8,,TIM5_CH3,TIM1_CH1N,,,,,,,,,,FMC_D5,SAI1_SCK_B,,EVENTOUT
+PortE,PE9,,TIM5_CH4,TIM1_CH1,,,,,,,,,,FMC_D6,SAI1_FS_B,,EVENTOUT
+PortE,PE10,,,TIM1_CH2N,,,,,,,,QUADSPI_CLK,,FMC_D7,SAI1_MCLK_B,,EVENTOUT
+PortE,PE11,,,TIM1_CH2,,,SPI4_NSS,,,,,QUADSPI_BK1_NCS,,FMC_D8,,,EVENTOUT
+PortE,PE12,,,TIM1_CH3N,,,SPI4_SCK,,,,,QUADSPI_BK1_IO0,,FMC_D9,,,EVENTOUT
+PortE,PE13,,,TIM1_CH3,,,SPI4_MISO,,,,,QUADSPI_BK1_IO1,,FMC_D10,,,EVENTOUT
+PortE,PE14,,,TIM1_CH4,,,SPI4_MOSI,TIM1_BKIN2,,,,QUADSPI_BK1_IO2,,FMC_D11,,,EVENTOUT
+PortE,PE15,,,TIM1_BKIN,,,,TIM1_CH4N,USART3_RX,,,QUADSPI_BK1_IO3,,FMC_D12,,,EVENTOUT
+PortF,PF0,,,,,I2C2_SDA,SPI2_NSS/I2S2_WS,TIM1_CH3N,,,,,,,,,EVENTOUT
+PortF,PF1,,,,,,SPI2_SCK/I2S2_CK,,,,,,,,,,EVENTOUT
+PortF,PF2,,,TIM20_CH3,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT
+PortF,PF3,,,TIM20_CH4,,I2C3_SCL,,,,,,,,FMC_A3,,,EVENTOUT
+PortF,PF4,,,COMP1_OUT,TIM20_CH1N,I2C3_SDA,,,,,,,,FMC_A4,,,EVENTOUT
+PortF,PF5,,,TIM20_CH2N,,,,,,,,,,FMC_A5,,,EVENTOUT
+PortF,PF6,,TIM5_ETR,TIM4_CH4,SAI1_SD_B,I2C2_SCL,,TIM5_CH1,USART3_RTS,,,QUADSPI_BK1_IO3,,,,,EVENTOUT
+PortF,PF7,,,TIM20_BKIN,,,,TIM5_CH2,,,,QUADSPI_BK1_IO2,,FMC_A1,SAI1_MCLK_B,,EVENTOUT
+PortF,PF8,,,TIM20_BKIN2,,,,TIM5_CH3,,,,QUADSPI_BK1_IO0,,FMC_A24,SAI1_SCK_B,,EVENTOUT
+PortF,PF9,,,TIM20_BKIN,TIM15_CH1,,SPI2_SCK,TIM5_CH4,,,,QUADSPI_BK1_IO1,,FMC_A25,SAI1_FS_B,,EVENTOUT
+PortF,PF10,,,TIM20_BKIN2,TIM15_CH2,,SPI2_SCK,,,,,QUADSPI_CLK,,FMC_A0,SAI1_D3,,EVENTOUT
+PortF,PF11,,,TIM20_ETR,,,,,,,,,,FMC_NE4,,,EVENTOUT
+PortF,PF12,,,TIM20_CH1,,,,,,,,,,FMC_A6,,,EVENTOUT
+PortF,PF13,,,TIM20_CH2,,I2C4_SMBA,,,,,,,,FMC_A7,,,EVENTOUT
+PortF,PF14,,,TIM20_CH3,,I2C4_SCL,,,,,,,,FMC_A8,,,EVENTOUT
+PortF,PF15,,,TIM20_CH4,,I2C4_SDA,,,,,,,,FMC_A9,,,EVENTOUT
+PortG,PG0,,,TIM20_CH1N,,,,,,,,,,FMC_A10,,,EVENTOUT
+PortG,PG1,,,TIM20_CH2N,,,,,,,,,,FMC_A11,,,EVENTOUT
+PortG,PG2,,,TIM20_CH3N,,,SPI1_SCK,,,,,,,FMC_A12,,,EVENTOUT
+PortG,PG3,,,TIM20_BKIN,,I2C4_SCL,SPI1_MISO,TIM20_CH4N,,,,,,FMC_A13,,,EVENTOUT
+PortG,PG4,,,TIM20_BKIN2,,I2C4_SDA,SPI1_MOSI,,,,,,,FMC_A14,,,EVENTOUT
+PortG,PG5,,,TIM20_ETR,,,SPI1_NSS,,,LPUART1_CTS,,,,FMC_A15,,,EVENTOUT
+PortG,PG6,,,TIM20_BKIN,,I2C3_SMBA,,,,LPUART1_RTS_DE,,,,FMC_INT,,,EVENTOUT
+PortG,PG7,,,,SAI1_CK1,I2C3_SCL,,,,LPUART1_TX,,,,FMC_INT,SAI1_MCLK_A,,EVENTOUT
+PortG,PG8,,,,,I2C3_SDA,,,,LPUART1_RX,,,,FMC_NE3,,,EVENTOUT
+PortG,PG9,,,,,,,SPI3_SCK,USART1_TX,,,,,FMC_NCE/FMC_NE2,,TIM15_CH1N,EVENTOUT
+PortG,PG10,MCO,,,,,,,,,,,,,,,
diff --git a/ports/stm32/boards/stm32g474_af.csv b/ports/stm32/boards/stm32g474_af.csv
index 0108ee90138ae..513210e04d2be 100644
--- a/ports/stm32/boards/stm32g474_af.csv
+++ b/ports/stm32/boards/stm32g474_af.csv
@@ -16,8 +16,8 @@ PortA,PA12,,TIM16_CH1,,,,I2SCKIN,TIM1_CH2N,USART1_RTS_DE,COMP2_OUT,CAN1_TX,TIM4_
PortA,PA13,SWDIOJTMS,TIM16_CH1N,,I2C4_SCL,I2C1_SCL,IR_OUT,,USART3_CTS,,,TIM4_CH3,,,SAI1_SD_B,,EVENTOUT,,,,
PortA,PA14,SWCLKJTCK,LPTIM1_OUT,,I2C4_SMBA,I2C1_SDA,TIM8_CH2,TIM1_BKIN,USART2_TX,,,,,,SAI1_FS_B,,EVENTOUT,,,,
PortA,PA15,JTDI,TIM2_CH1,TIM8_CH1,,I2C1_SCL,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_RX,UART4_RTS_DE,TIM1_BKIN,,CAN3_TX,,HRTIM1_FLT2,TIM2_ETR,EVENTOUT,,,,
-PortB,PB0,,,TIM3_CH3,,TIM8_CH2N,,TIM1_CH2N,,,,QUADSPI1_BK1_IO1,,,HRTIM1_FLT5,UCPD1_FRSTX,EVENTOUT,ADC3_IN12/ADC1_IN15,COMP4_INP,,OPAMP2_VINP/OPAMP3_VINP
-PortB,PB1,,,TIM3_CH4,,TIM8_CH3N,,TIM1_CH3N,,COMP4_OUT,,QUADSPI1_BK1_IO0,,LPUART1_RTS_DE,HRTIM1_SCOUT,,EVENTOUT,ADC3_IN1/ADC1_IN12,COMP1_INP,,OPAMP3_VOUT/OPAMP6_VINM
+PortB,PB0,,,TIM3_CH3,,TIM8_CH2N,,TIM1_CH2N,,,,QUADSPI1_BK1_IO1,,,HRTIM1_FLT5,UCPD1_FRSTX,EVENTOUT,ADC1_IN15/ADC3_IN12,COMP4_INP,,OPAMP2_VINP/OPAMP3_VINP
+PortB,PB1,,,TIM3_CH4,,TIM8_CH3N,,TIM1_CH3N,,COMP4_OUT,,QUADSPI1_BK1_IO0,,LPUART1_RTS_DE,HRTIM1_SCOUT,,EVENTOUT,ADC1_IN12/ADC3_IN1,COMP1_INP,,OPAMP3_VOUT/OPAMP6_VINM
PortB,PB2,RTC_OUT2,LPTIM1_OUT,TIM5_CH1,TIM20_CH1,I2C3_SMBA,,,,,,QUADSPI1_BK2_IO1,,,HRTIM1_SCIN,,EVENTOUT,ADC2_IN12,COMP4_INM,,OPAMP3_VINM
PortB,PB3,JTDOTRACESWO,TIM2_CH2,TIM4_ETR,USB_CRS_SYNC,TIM8_CH1N,SPI1_SCK,SPI3_SCK/I2S3_CK,USART2_TX,,,TIM3_ETR,CAN3_RX,HRTIM1_SCOUT,HRTIM1_EEV9,SAI1_SCK_B,EVENTOUT,,,,
PortB,PB4,JTRST,TIM16_CH1,TIM3_CH1,,TIM8_CH2N,SPI1_MISO,SPI3_MISO,USART2_RX,UART5_RTS_DE,,TIM17_BKIN,CAN3_TX,,HRTIM1_EEV7,SAI1_MCLK_B,EVENTOUT,,,,
@@ -28,9 +28,9 @@ PortB,PB8,,TIM16_CH1,TIM4_CH3,SAI1_CK1,I2C1_SCL,,,USART3_RX,COMP1_OUT,CAN1_RX,TI
PortB,PB9,,TIM17_CH1,TIM4_CH4,SAI1_D2,I2C1_SDA,,IR_OUT,USART3_TX,COMP2_OUT,CAN1_TX,TIM8_CH3,,TIM1_CH3N,HRTIM1_EEV5,SAI1_FS_A,EVENTOUT,,,,
PortB,PB10,,TIM2_CH3,,,,,,USART3_TX,LPUART1_RX,,QUADSPI1_CLK,,TIM1_BKIN,HRTIM1_FLT3,SAI1_SCK_A,EVENTOUT,,COMP5_INM,,OPAMP3_VINM/OPAMP4_VINM
PortB,PB11,,TIM2_CH4,,,,,,USART3_RX,LPUART1_TX,,QUADSPI1_BK1_NCS,,,HRTIM1_FLT4,,EVENTOUT,ADC12_IN14,COMP6_INP,,OPAMP4_VINP/OPAMP6_VOUT
-PortB,PB12,,,TIM5_ETR,,I2C2_SMBA,SPI2_NSS/I2S2_WS,TIM1_BKIN,USART3_CK,LPUART1_RTS_DE,CAN2_RX,,,,HRTIM1_CHC1,,EVENTOUT,ADC4_IN3/ADC1_IN11,COMP7_INM,,OPAMP4_VOUT/OPAMP6_VINP
+PortB,PB12,,,TIM5_ETR,,I2C2_SMBA,SPI2_NSS/I2S2_WS,TIM1_BKIN,USART3_CK,LPUART1_RTS_DE,CAN2_RX,,,,HRTIM1_CHC1,,EVENTOUT,ADC1_IN11/ADC4_IN3,COMP7_INM,,OPAMP4_VOUT/OPAMP6_VINP
PortB,PB13,,,,,,SPI2_SCK/I2S2_CK,TIM1_CH1N,USART3_CTS,LPUART1_CTS,CAN2_TX,,,,HRTIM1_CHC2,,EVENTOUT,ADC3_IN5,COMP5_INP,,OPAMP3_VINP/OPAMP4_VINP/OPAMP6_VINP
-PortB,PB14,,TIM15_CH1,,,,SPI2_MISO,TIM1_CH2N,USART3_RTS_DE,COMP4_OUT,,,,,HRTIM1_CHD1,,EVENTOUT,ADC4_IN4/ADC1_IN5,COMP7_INP,,OPAMP2_VINP/OPAMP5_VINP
+PortB,PB14,,TIM15_CH1,,,,SPI2_MISO,TIM1_CH2N,USART3_RTS_DE,COMP4_OUT,,,,,HRTIM1_CHD1,,EVENTOUT,ADC1_IN5/ADC4_IN4,COMP7_INP,,OPAMP2_VINP/OPAMP5_VINP
PortB,PB15,RTC_REFIN,TIM15_CH2,TIM15_CH1N,COMP3_OUT,TIM1_CH3N,SPI2_MOSI/I2S2_SD,,,,,,,,HRTIM1_CHD2,,EVENTOUT,ADC4_IN5/ADC2_IN15,COMP6_INM,,OPAMP5_VINM
PortC,PC0,,LPTIM1_IN1,TIM1_CH1,,,,,,LPUART1_RX,,,,,,,EVENTOUT,ADC12_IN6,COMP3_INM,
PortC,PC1,,LPTIM1_OUT,TIM1_CH2,,,,,,LPUART1_TX,,QUADSPI1_BK2_IO0,,,SAI1_SD_A,,EVENTOUT,ADC12_IN7,COMP3_INP,,
diff --git a/ports/stm32/dma.c b/ports/stm32/dma.c
index 29306f1b271cc..0f926a102c46e 100644
--- a/ports/stm32/dma.c
+++ b/ports/stm32/dma.c
@@ -626,6 +626,8 @@ const dma_descr_t dma_SPI_1_RX = { DMA1_Channel1, DMA_REQUEST_SPI1_RX, dma_id_0,
const dma_descr_t dma_SPI_1_TX = { DMA1_Channel2, DMA_REQUEST_SPI1_TX, dma_id_1, &dma_init_struct_spi_i2c };
const dma_descr_t dma_SPI_2_RX = { DMA1_Channel1, DMA_REQUEST_SPI2_RX, dma_id_0, &dma_init_struct_spi_i2c };
const dma_descr_t dma_SPI_2_TX = { DMA1_Channel2, DMA_REQUEST_SPI2_TX, dma_id_1, &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_3_RX = { DMA1_Channel1, DMA_REQUEST_SPI3_RX, dma_id_0, &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_3_TX = { DMA1_Channel2, DMA_REQUEST_SPI3_TX, dma_id_1, &dma_init_struct_spi_i2c };
const dma_descr_t dma_I2C_1_RX = { DMA1_Channel3, DMA_REQUEST_I2C1_RX, dma_id_2, &dma_init_struct_spi_i2c };
const dma_descr_t dma_I2C_1_TX = { DMA1_Channel4, DMA_REQUEST_I2C1_TX, dma_id_3, &dma_init_struct_spi_i2c };
diff --git a/ports/stm32/dma.h b/ports/stm32/dma.h
index 37b8710c214c1..7b32c21547ac0 100644
--- a/ports/stm32/dma.h
+++ b/ports/stm32/dma.h
@@ -68,6 +68,8 @@ extern const dma_descr_t dma_SPI_1_RX;
extern const dma_descr_t dma_SPI_1_TX;
extern const dma_descr_t dma_SPI_2_RX;
extern const dma_descr_t dma_SPI_2_TX;
+extern const dma_descr_t dma_SPI_3_RX;
+extern const dma_descr_t dma_SPI_3_TX;
extern const dma_descr_t dma_I2C_1_RX;
extern const dma_descr_t dma_I2C_1_TX;
extern const dma_descr_t dma_I2C_2_RX;
diff --git a/ports/stm32/mpconfigboard_common.h b/ports/stm32/mpconfigboard_common.h
index b538f78235487..0bb80f215ee8c 100644
--- a/ports/stm32/mpconfigboard_common.h
+++ b/ports/stm32/mpconfigboard_common.h
@@ -559,7 +559,7 @@
#endif
// Whether the USB peripheral is device-only, or multiple OTG
-#if defined(STM32L0) || defined(STM32L432xx) || defined(STM32WB)
+#if defined(STM32G4) || defined(STM32L0) || defined(STM32L432xx) || defined(STM32WB)
#define MICROPY_HW_USB_IS_MULTI_OTG (0)
#else
#define MICROPY_HW_USB_IS_MULTI_OTG (1)
diff --git a/ports/stm32/mpu.h b/ports/stm32/mpu.h
index ff51f382eeec0..df4a7c222057e 100644
--- a/ports/stm32/mpu.h
+++ b/ports/stm32/mpu.h
@@ -26,7 +26,7 @@
#ifndef MICROPY_INCLUDED_STM32_MPU_H
#define MICROPY_INCLUDED_STM32_MPU_H
-#if defined(STM32F7) || defined(STM32H7) || defined(MICROPY_HW_ETH_MDC)
+#if defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(MICROPY_HW_ETH_MDC)
#define MPU_REGION_ETH (MPU_REGION_NUMBER0)
#define MPU_REGION_QSPI1 (MPU_REGION_NUMBER1)
diff --git a/ports/stm32/stm32_it.c b/ports/stm32/stm32_it.c
index c2604992186f9..a489c0b37baf2 100644
--- a/ports/stm32/stm32_it.c
+++ b/ports/stm32/stm32_it.c
@@ -304,7 +304,7 @@ void USB_IRQHandler(void) {
}
#endif
-#elif defined(STM32WB)
+#elif defined(STM32G4) || defined(STM32WB)
#if MICROPY_HW_USB_FS
void USB_LP_IRQHandler(void) {
@@ -670,6 +670,12 @@ void TIM2_IRQHandler(void) {
IRQ_EXIT(TIM2_IRQn);
}
+void TIM20_UP_IRQHandler(void) {
+ IRQ_ENTER(TIM20_UP_IRQn);
+ timer_irq_handler(20);
+ IRQ_EXIT(TIM20_UP_IRQn);
+}
+
#if defined(STM32G0)
void TIM3_TIM4_IRQHandler(void) {
IRQ_ENTER(TIM3_TIM4_IRQn);
diff --git a/ports/stm32/timer.c b/ports/stm32/timer.c
index 8816c218f5e32..e78dd230f694c 100644
--- a/ports/stm32/timer.c
+++ b/ports/stm32/timer.c
@@ -234,7 +234,7 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
// respective APB clock. See DM00031020 Rev 4, page 115.
uint32_t timer_get_source_freq(uint32_t tim_id) {
uint32_t source, clk_div;
- if (tim_id == 1 || (8 <= tim_id && tim_id <= 11)) {
+ if (tim_id == 1 || (8 <= tim_id && tim_id <= 11) || tim_id == 20) {
// TIM{1,8,9,10,11} are on APB2
#if defined(STM32F0) || defined(STM32G0)
source = HAL_RCC_GetPCLK1Freq();
diff --git a/ports/stm32/usb.c b/ports/stm32/usb.c
index 12c5e497de84e..f5fc9b7a1990f 100644
--- a/ports/stm32/usb.c
+++ b/ports/stm32/usb.c
@@ -67,7 +67,7 @@
#define MAX_ENDPOINT(dev_id) ((dev_id) == USB_PHY_FS_ID ? 3 : 5)
#elif defined(STM32F7)
#define MAX_ENDPOINT(dev_id) ((dev_id) == USB_PHY_FS_ID ? 5 : 8)
-#elif defined(STM32H7)
+#elif defined(STM32G4) || defined(STM32H7)
#define MAX_ENDPOINT(dev_id) (8)
#endif
diff --git a/ports/stm32/usbd_conf.c b/ports/stm32/usbd_conf.c
index d0f519d456701..cb059978832e9 100644
--- a/ports/stm32/usbd_conf.c
+++ b/ports/stm32/usbd_conf.c
@@ -69,14 +69,18 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) {
const uint32_t otg_alt = GPIO_AF10_USB_FS;
#elif defined(STM32WB)
const uint32_t otg_alt = GPIO_AF10_USB;
+ #elif defined(STM32G4)
+ // no alt pin function
#else
const uint32_t otg_alt = GPIO_AF10_OTG_FS;
#endif
+ #if !defined(STM32G4)
mp_hal_pin_config(pin_A11, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, otg_alt);
mp_hal_pin_config_speed(pin_A11, GPIO_SPEED_FREQ_VERY_HIGH);
mp_hal_pin_config(pin_A12, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, otg_alt);
mp_hal_pin_config_speed(pin_A12, GPIO_SPEED_FREQ_VERY_HIGH);
+ #endif
#if defined(MICROPY_HW_USB_VBUS_DETECT_PIN)
// USB VBUS detect pin is always A9
@@ -95,7 +99,7 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) {
#endif
// Enable USB FS Clocks
- #if !MICROPY_HW_USB_IS_MULTI_OTG
+ #if !MICROPY_HW_USB_IS_MULTI_OTG || defined(STM32G4)
__HAL_RCC_USB_CLK_ENABLE();
#else
__USB_OTG_FS_CLK_ENABLE();
@@ -113,7 +117,11 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) {
#endif
// Configure and enable USB FS interrupt
- #if defined(STM32L0)
+ #if defined(STM32G4)
+ uint32_t prioritygroup = NVIC_GetPriorityGrouping();
+ NVIC_SetPriority(USB_LP_IRQn, NVIC_EncodePriority(prioritygroup, 0, 0));
+ HAL_NVIC_EnableIRQ(USB_LP_IRQn);
+ #elif defined(STM32L0)
NVIC_SetPriority(USB_IRQn, IRQ_PRI_OTG_FS);
HAL_NVIC_EnableIRQ(USB_IRQn);
#elif defined(STM32L432xx)
diff --git a/shared/runtime/pyexec.c b/shared/runtime/pyexec.c
index 40491650e4213..75c95f8442840 100644
--- a/shared/runtime/pyexec.c
+++ b/shared/runtime/pyexec.c
@@ -504,6 +504,7 @@ int pyexec_raw_repl(void) {
mp_hal_stdout_tx_str(">");
for (;;) {
int c = mp_hal_stdin_rx_chr();
+ NVIC->STIR = FLASH_IRQn;
if (c == CHAR_CTRL_A) {
// reset raw REPL
if (vstr_len(&line) == 2 && vstr_str(&line)[0] == CHAR_CTRL_E) {
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