stmhal: Adjust computation of SYSCLK to retain precision.

dpgeorge · dpgeorge · commit c568a2b44387 · 2014-10-04T01:54:02.000+01:00
diff --git a/stmhal/hal/src/stm32f4xx_hal_rcc.c b/stmhal/hal/src/stm32f4xx_hal_rcc.c
@@ -972,7 +972,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
       if (__RCC_PLLSRC() != 0)
       {
         /* HSE used as PLL clock source */
-        pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+        //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+        // dpgeorge: Adjust the way the arithmetic is done so it retains
+        // precision for the case that pllm doesn't evenly divide HSE_VALUE.
+        // Must be sure not to overflow, so divide by 4 first.  HSE_VALUE
+        // should be a multiple of 4 (being a multiple of 100 is enough).
+        pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;
       }
       else
       {

Original file line number	Diff line number	Diff line change
`@@ -972,7 +972,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void)`
`972`	`972`	`if (__RCC_PLLSRC() != 0)`
`973`	`973`	`{`
`974`	`974`	`/* HSE used as PLL clock source */`
`975`		`- pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));`
	`975`	`+ //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));`
	`976`	`+ // dpgeorge: Adjust the way the arithmetic is done so it retains`
	`977`	`+ // precision for the case that pllm doesn't evenly divide HSE_VALUE.`
	`978`	`+ // Must be sure not to overflow, so divide by 4 first. HSE_VALUE`
	`979`	`+ // should be a multiple of 4 (being a multiple of 100 is enough).`
	`980`	`+ pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;`
`976`	`981`	`}`
`977`	`982`	`else`
`978`	`983`	`{`