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Import STM32Cube_FW_L4_V1.8.1 on 16-Jun-2017
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‎CMSIS/STM32L4xx/Include/stm32l431xx.h

Lines changed: 6 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32l431xx.h
44
* @author MCD Application Team
5-
* @version V1.3.1
6-
* @date 21-April-2017
5+
* @version V1.3.2
6+
* @date 16-June-2017
77
* @brief CMSIS STM32L431xx Device Peripheral Access Layer Header File.
88
*
99
* This file contains:
@@ -945,7 +945,6 @@ typedef struct
945945

946946
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
947947
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
948-
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
949948
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
950949

951950
/* Legacy defines */
@@ -6787,11 +6786,8 @@ typedef struct
67876786
#define EXTI_IMR2_IM38_Pos (6U)
67886787
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
67896788
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
6790-
#define EXTI_IMR2_IM39_Pos (7U)
6791-
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
6792-
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
67936789
#define EXTI_IMR2_IM_Pos (0U)
6794-
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
6790+
#define EXTI_IMR2_IM_Msk (0x7FU << EXTI_IMR2_IM_Pos) /*!< 0x0000007F */
67956791
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
67966792

67976793
/******************* Bit definition for EXTI_EMR2 register ******************/
@@ -6816,9 +6812,9 @@ typedef struct
68166812
#define EXTI_EMR2_EM38_Pos (6U)
68176813
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
68186814
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
6819-
#define EXTI_EMR2_EM39_Pos (7U)
6820-
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
6821-
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
6815+
#define EXTI_EMR2_EM_Pos (0U)
6816+
#define EXTI_EMR2_EM_Msk (0x7FU << EXTI_EMR2_EM_Pos) /*!< 0x0000007F */
6817+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
68226818

68236819
/****************** Bit definition for EXTI_RTSR2 register ******************/
68246820
#define EXTI_RTSR2_RT35_Pos (3U)

‎CMSIS/STM32L4xx/Include/stm32l432xx.h

Lines changed: 6 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32l432xx.h
44
* @author MCD Application Team
5-
* @version V1.3.1
6-
* @date 21-April-2017
5+
* @version V1.3.2
6+
* @date 16-June-2017
77
* @brief CMSIS STM32L432xx Device Peripheral Access Layer Header File.
88
*
99
* This file contains:
@@ -941,7 +941,6 @@ typedef struct
941941

942942
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
943943
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
944-
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
945944
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
946945

947946
/* Legacy defines */
@@ -6763,20 +6762,14 @@ typedef struct
67636762
#define EXTI_IMR2_IM35_Pos (3U)
67646763
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
67656764
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
6766-
#define EXTI_IMR2_IM36_Pos (4U)
6767-
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
6768-
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
67696765
#define EXTI_IMR2_IM37_Pos (5U)
67706766
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
67716767
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
67726768
#define EXTI_IMR2_IM38_Pos (6U)
67736769
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
67746770
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
6775-
#define EXTI_IMR2_IM39_Pos (7U)
6776-
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
6777-
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
67786771
#define EXTI_IMR2_IM_Pos (0U)
6779-
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
6772+
#define EXTI_IMR2_IM_Msk (0x6FU << EXTI_IMR2_IM_Pos) /*!< 0x0000006F */
67806773
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
67816774

67826775
/******************* Bit definition for EXTI_EMR2 register ******************/
@@ -6792,18 +6785,15 @@ typedef struct
67926785
#define EXTI_EMR2_EM35_Pos (3U)
67936786
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
67946787
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
6795-
#define EXTI_EMR2_EM36_Pos (4U)
6796-
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
6797-
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
67986788
#define EXTI_EMR2_EM37_Pos (5U)
67996789
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
68006790
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
68016791
#define EXTI_EMR2_EM38_Pos (6U)
68026792
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
68036793
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
6804-
#define EXTI_EMR2_EM39_Pos (7U)
6805-
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
6806-
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
6794+
#define EXTI_EMR2_EM_Pos (0U)
6795+
#define EXTI_EMR2_EM_Msk (0x6FU << EXTI_EMR2_EM_Pos) /*!< 0x0000006F */
6796+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
68076797

68086798
/****************** Bit definition for EXTI_RTSR2 register ******************/
68096799
#define EXTI_RTSR2_RT35_Pos (3U)

‎CMSIS/STM32L4xx/Include/stm32l433xx.h

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32l433xx.h
44
* @author MCD Application Team
5-
* @version V1.3.1
6-
* @date 21-April-2017
5+
* @version V1.3.2
6+
* @date 16-June-2017
77
* @brief CMSIS STM32L433xx Device Peripheral Access Layer Header File.
88
*
99
* This file contains:
@@ -999,7 +999,6 @@ typedef struct
999999

10001000
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
10011001
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
1002-
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
10031002
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
10041003

10051004
/* Legacy defines */
@@ -6878,6 +6877,9 @@ typedef struct
68786877
#define EXTI_EMR2_EM39_Pos (7U)
68796878
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
68806879
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
6880+
#define EXTI_EMR2_EM_Pos (0U)
6881+
#define EXTI_EMR2_EM_Msk (0xFFU << EXTI_EMR2_EM_Pos) /*!< 0x000000FF */
6882+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
68816883

68826884
/****************** Bit definition for EXTI_RTSR2 register ******************/
68836885
#define EXTI_RTSR2_RT35_Pos (3U)

‎CMSIS/STM32L4xx/Include/stm32l442xx.h

Lines changed: 6 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32l442xx.h
44
* @author MCD Application Team
5-
* @version V1.3.1
6-
* @date 21-April-2017
5+
* @version V1.3.2
6+
* @date 16-June-2017
77
* @brief CMSIS STM32L442xx Device Peripheral Access Layer Header File.
88
*
99
* This file contains:
@@ -974,7 +974,6 @@ typedef struct
974974

975975
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
976976
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
977-
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
978977
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
979978

980979
/* Legacy defines */
@@ -6979,20 +6978,14 @@ typedef struct
69796978
#define EXTI_IMR2_IM35_Pos (3U)
69806979
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
69816980
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
6982-
#define EXTI_IMR2_IM36_Pos (4U)
6983-
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
6984-
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
69856981
#define EXTI_IMR2_IM37_Pos (5U)
69866982
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
69876983
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
69886984
#define EXTI_IMR2_IM38_Pos (6U)
69896985
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
69906986
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
6991-
#define EXTI_IMR2_IM39_Pos (7U)
6992-
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
6993-
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
69946987
#define EXTI_IMR2_IM_Pos (0U)
6995-
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
6988+
#define EXTI_IMR2_IM_Msk (0x6FU << EXTI_IMR2_IM_Pos) /*!< 0x0000006F */
69966989
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
69976990

69986991
/******************* Bit definition for EXTI_EMR2 register ******************/
@@ -7017,9 +7010,9 @@ typedef struct
70177010
#define EXTI_EMR2_EM38_Pos (6U)
70187011
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
70197012
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
7020-
#define EXTI_EMR2_EM39_Pos (7U)
7021-
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
7022-
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
7013+
#define EXTI_EMR2_EM_Pos (0U)
7014+
#define EXTI_EMR2_EM_Msk (0x7FU << EXTI_EMR2_EM_Pos) /*!< 0x0000007F */
7015+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
70237016

70247017
/****************** Bit definition for EXTI_RTSR2 register ******************/
70257018
#define EXTI_RTSR2_RT35_Pos (3U)

‎CMSIS/STM32L4xx/Include/stm32l443xx.h

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32l443xx.h
44
* @author MCD Application Team
5-
* @version V1.3.1
6-
* @date 21-April-2017
5+
* @version V1.3.2
6+
* @date 16-June-2017
77
* @brief CMSIS STM32L443xx Device Peripheral Access Layer Header File.
88
*
99
* This file contains:
@@ -1032,7 +1032,6 @@ typedef struct
10321032

10331033
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
10341034
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
1035-
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
10361035
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
10371036

10381037
/* Legacy defines */
@@ -7094,6 +7093,9 @@ typedef struct
70947093
#define EXTI_EMR2_EM39_Pos (7U)
70957094
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
70967095
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
7096+
#define EXTI_EMR2_EM_Pos (0U)
7097+
#define EXTI_EMR2_EM_Msk (0xFFU << EXTI_EMR2_EM_Pos) /*!< 0x000000FF */
7098+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
70977099

70987100
/****************** Bit definition for EXTI_RTSR2 register ******************/
70997101
#define EXTI_RTSR2_RT35_Pos (3U)

‎CMSIS/STM32L4xx/Include/stm32l451xx.h

Lines changed: 9 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32l451xx.h
44
* @author MCD Application Team
5-
* @version V1.3.1
6-
* @date 21-April-2017
5+
* @version V1.3.2
6+
* @date 16-June-2017
77
* @brief CMSIS STM32L451xx Device Peripheral Access Layer Header File.
88
*
99
* This file contains:
@@ -965,7 +965,6 @@ typedef struct
965965

966966
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
967967
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
968-
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
969968
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
970969

971970
/* Legacy defines */
@@ -7029,9 +7028,6 @@ typedef struct
70297028
#define EXTI_IMR2_IM33_Pos (1U)
70307029
#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
70317030
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
7032-
#define EXTI_IMR2_IM34_Pos (2U)
7033-
#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
7034-
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
70357031
#define EXTI_IMR2_IM35_Pos (3U)
70367032
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
70377033
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
@@ -7044,14 +7040,11 @@ typedef struct
70447040
#define EXTI_IMR2_IM38_Pos (6U)
70457041
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
70467042
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
7047-
#define EXTI_IMR2_IM39_Pos (7U)
7048-
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
7049-
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
70507043
#define EXTI_IMR2_IM40_Pos (8U)
70517044
#define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
70527045
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
70537046
#define EXTI_IMR2_IM_Pos (0U)
7054-
#define EXTI_IMR2_IM_Msk (0x1FFU << EXTI_IMR2_IM_Pos) /*!< 0x000001FF */
7047+
#define EXTI_IMR2_IM_Msk (0x16BU << EXTI_IMR2_IM_Pos) /*!< 0x0000016B */
70557048
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
70567049

70577050
/******************* Bit definition for EXTI_EMR2 register ******************/
@@ -7061,9 +7054,6 @@ typedef struct
70617054
#define EXTI_EMR2_EM33_Pos (1U)
70627055
#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
70637056
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
7064-
#define EXTI_EMR2_EM34_Pos (2U)
7065-
#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
7066-
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
70677057
#define EXTI_EMR2_EM35_Pos (3U)
70687058
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
70697059
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
@@ -7076,12 +7066,12 @@ typedef struct
70767066
#define EXTI_EMR2_EM38_Pos (6U)
70777067
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
70787068
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
7079-
#define EXTI_EMR2_EM39_Pos (7U)
7080-
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
7081-
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
7082-
#define EXTI_EMR2_IM40_Pos (8U)
7083-
#define EXTI_EMR2_IM40_Msk (0x1U << EXTI_EMR2_IM40_Pos) /*!< 0x00000100 */
7084-
#define EXTI_EMR2_IM40 EXTI_EMR2_IM40_Msk /*!< Event Mask on line 40 */
7069+
#define EXTI_EMR2_EM40_Pos (8U)
7070+
#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
7071+
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
7072+
#define EXTI_EMR2_EM_Pos (0U)
7073+
#define EXTI_EMR2_EM_Msk (0x17BU << EXTI_EMR2_EM_Pos) /*!< 0x0000017B */
7074+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
70857075

70867076
/****************** Bit definition for EXTI_RTSR2 register ******************/
70877077
#define EXTI_RTSR2_RT35_Pos (3U)

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