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Add comments explaining why our Itanium spinlock implementation is safe.
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src/include/storage/s_lock.h

Lines changed: 30 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -234,7 +234,23 @@ spin_delay(void)
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#endif /* __x86_64__ */
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#if defined(__ia64__) || defined(__ia64) /* Intel Itanium */
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#if defined(__ia64__) || defined(__ia64)
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/*
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* Intel Itanium, gcc or Intel's compiler.
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*
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* Itanium has weak memory ordering, but we rely on the compiler to enforce
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* strict ordering of accesses to volatile data. In particular, while the
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* xchg instruction implicitly acts as a memory barrier with 'acquire'
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* semantics, we do not have an explicit memory fence instruction in the
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* S_UNLOCK macro. We use a regular assignment to clear the spinlock, and
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* trust that the compiler marks the generated store instruction with the
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* ".rel" opcode.
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*
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* Testing shows that assumption to hold on gcc, although I could not find
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* any explicit statement on that in the gcc manual. In Intel's compiler,
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* the -m[no-]serialize-volatile option controls that, and testing shows that
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* it is enabled by default.
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*/
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#define HAS_TEST_AND_SET
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typedef unsigned int slock_t;
@@ -785,7 +801,19 @@ tas(volatile slock_t *lock)
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#if defined(__hpux) && defined(__ia64) && !defined(__GNUC__)
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/*
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* HP-UX on Itanium, non-gcc compiler
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*
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* We assume that the compiler enforces strict ordering of loads/stores on
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* volatile data (see comments on the gcc-version earlier in this file).
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* Note that this assumption does *not* hold if you use the
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* +Ovolatile=__unordered option on the HP-UX compiler, so don't do that.
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*
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* See also Implementing Spinlocks on the Intel Itanium Architecture and
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* PA-RISC, by Tor Ekqvist and David Graves, for more information. As of
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* this writing, version 1.0 of the manual is available at:
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* http://h21007.www2.hp.com/portal/download/files/unprot/itanium/spinlocks.pdf
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*/
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#define HAS_TEST_AND_SET
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typedef unsigned int slock_t;

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