Fix atomic ops inline x86 inline assembly for older 32bit gccs.

anarazel · anarazel · commit f18cad944911 · 2014-09-26T02:44:44.000+02:00
Some x86 32bit versions of gcc apparently generate references to the
nonexistant %sil register when using when using the r input
constraint, but not with the =q constraint. The latter restricts
allocations to a/b/c/d which should all work.
diff --git a/src/include/port/atomics/arch-x86.h b/src/include/port/atomics/arch-x86.h
@@ -175,7 +175,7 @@ pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
 		"	lock				\n"
 		"	cmpxchgl	%4,%5	\n"
 		"   setz		%2		\n"
-:		"=a" (*expected), "=m"(ptr->value), "=r" (ret)
+:		"=a" (*expected), "=m"(ptr->value), "=q" (ret)
 :		"a" (*expected), "r" (newval), "m"(ptr->value)
 :		"memory", "cc");
 	return (bool) ret;
@@ -212,7 +212,7 @@ pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr,
 		"	lock				\n"
 		"	cmpxchgq	%4,%5	\n"
 		"   setz		%2		\n"
-:		"=a" (*expected), "=m"(ptr->value), "=r" (ret)
+:		"=a" (*expected), "=m"(ptr->value), "=q" (ret)
 :		"a" (*expected), "r" (newval), "m"(ptr->value)
 :		"memory", "cc");
 	return (bool) ret;
