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| 1 | +"""Tests for pslab.bus.uart. |
| 2 | +
|
| 3 | +When integration testing, the PSLab's logic analyzer is used to verify the |
| 4 | +function of the I2C bus. Before running the integration tests, connect: |
| 5 | + TxD2->LA1 |
| 6 | + RxD2->SQ1 |
| 7 | +""" |
| 8 | + |
| 9 | +import pytest |
| 10 | + |
| 11 | +from pslab.bus.uart import UART |
| 12 | +from pslab.instrument.logic_analyzer import LogicAnalyzer |
| 13 | +from pslab.instrument.waveform_generator import PWMGenerator |
| 14 | +from pslab.serial_handler import SerialHandler, MockHandler |
| 15 | + |
| 16 | +SPI_SUPPORTED_DEVICES = [ |
| 17 | + # "PSLab vMOCK", # Uncomment after adding recording json files. |
| 18 | + "PSLab V6", |
| 19 | +] |
| 20 | + |
| 21 | +WRITE_DATA = 0x55 |
| 22 | +TXD2 = "LA1" |
| 23 | +RXD2 = "SQ1" |
| 24 | +PWM_FERQUENCY = UART._baudrate |
| 25 | +MICROSECONDS = 1e-6 |
| 26 | +RELTOL = 0.05 |
| 27 | +# Number of expected logic level changes. |
| 28 | +TXD_START = 1 |
| 29 | +TXD_WRITE_DATA = 8 # if LSB is 1 |
| 30 | +TXD_STOP = 1 # if data MSB is 0 |
| 31 | + |
| 32 | + |
| 33 | +@pytest.fixture |
| 34 | +def uart(handler: SerialHandler) -> UART: |
| 35 | + if handler.version not in SPI_SUPPORTED_DEVICES: |
| 36 | + pytest.skip("UART2 not supported by this device.") |
| 37 | + handler._logging = True |
| 38 | + return UART(device=handler) |
| 39 | + |
| 40 | + |
| 41 | +@pytest.fixture |
| 42 | +def la(handler: SerialHandler) -> LogicAnalyzer: |
| 43 | + handler._logging = True |
| 44 | + return LogicAnalyzer(handler) |
| 45 | + |
| 46 | + |
| 47 | +@pytest.fixture |
| 48 | +def pwm(handler: SerialHandler) -> PWMGenerator: |
| 49 | + if not isinstance(handler, MockHandler): |
| 50 | + pwm = PWMGenerator(handler) |
| 51 | + pwm.generate(RXD2, PWM_FERQUENCY, 0.5) |
| 52 | + handler._logging = True |
| 53 | + |
| 54 | + |
| 55 | +def test_configure(la: LogicAnalyzer, uart: UART): |
| 56 | + baudrate = 1000000 |
| 57 | + uart.configure(baudrate) |
| 58 | + la.capture(1, block=False) |
| 59 | + uart.write_byte(WRITE_DATA) |
| 60 | + la.stop() |
| 61 | + (txd2,) = la.fetch_data() |
| 62 | + start_to_stop = 1 + 8 + 1 |
| 63 | + period = (txd2[-1] - txd2[0]) / start_to_stop |
| 64 | + assert (period * MICROSECONDS) ** -1 == pytest.approx(baudrate, rel=RELTOL) |
| 65 | + |
| 66 | + |
| 67 | +def test_write_byte(la: LogicAnalyzer, uart: UART): |
| 68 | + la.capture(3, block=False) |
| 69 | + uart.write_byte(WRITE_DATA) |
| 70 | + la.stop() |
| 71 | + (txd2,) = la.fetch_data() |
| 72 | + |
| 73 | + assert len(txd2) == (TXD_START + TXD_WRITE_DATA + TXD_STOP) |
| 74 | + |
| 75 | + |
| 76 | +def test_write_int(la: LogicAnalyzer, uart: UART): |
| 77 | + la.capture(3, block=False) |
| 78 | + uart.write_int((WRITE_DATA << 8) | WRITE_DATA) |
| 79 | + la.stop() |
| 80 | + (txd2,) = la.fetch_data() |
| 81 | + |
| 82 | + assert len(txd2) == 2 * (TXD_START + TXD_WRITE_DATA + TXD_STOP) |
| 83 | + |
| 84 | + |
| 85 | +def test_read_byte(pwm: PWMGenerator, uart: UART): |
| 86 | + value = uart.read_byte() |
| 87 | + |
| 88 | + assert value in (0, 0xFF) |
| 89 | + |
| 90 | + |
| 91 | +def test_read_int(pwm: PWMGenerator, uart: UART): |
| 92 | + value = uart.read_int() |
| 93 | + |
| 94 | + assert value in (0, 0xFFFF) |
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