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Merge pull request #1161 from vinchatl/reorganise_f2_f4_f7_flash
F2-F4-F7 FLASH: Fix several issues, add definitions and reorganise yamls
2 parents 33cee3b + 2fa47fb commit 3cd2bb8

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‎CHANGELOG.md

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‎devices/collect/flash/optcr_nwrp.yaml renamed to ‎devices/collect/flash/optcr/nwrp.yaml

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‎devices/collect/flash/optcr1_nwrp.yaml renamed to ‎devices/collect/flash/optcr1/nwrp.yaml

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‎devices/collect/flash/optcr2_pcrop.yaml renamed to ‎devices/collect/flash/optcr2/pcrop.yaml

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‎devices/fields/flash/acr/common_f2_f4.yaml

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ACR:
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DCRST:
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NoReset: [0, Data cache is not reset]
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Reset: [1, Data cache is reset]
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ICRST:
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NoReset: [0, Instruction cache is not reset]
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Reset: [1, Instruction cache is reset]
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DCEN:
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Disabled: [0, Data cache is disabled]
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Enabled: [1, Data cache is enabled]
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ICEN:
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Disabled: [0, Instruction cache is disabled]
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Enabled: [1, Instruction cache is enabled]
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PRFTEN:
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Disabled: [0, Prefetch is disabled]
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Enabled: [1, Prefetch is enabled]

‎devices/fields/flash/acr/common_f7.yaml

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ACR:
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ARTRST:
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NoReset: [0, Accelerator is not reset]
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Reset: [1, Accelerator is reset]
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ARTEN:
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Disabled: [0, ART Accelerator is disabled]
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Enabled: [1, ART Accelerator is enabled]
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PRFTEN:
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Disabled: [0, Prefetch is disabled]
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Enabled: [1, Prefetch is enabled]

‎devices/fields/flash/flash_f3_acr_hlfcya.yaml renamed to ‎devices/fields/flash/acr/hlfcya.yaml

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‎devices/fields/flash/flash_latency16.yaml renamed to ‎devices/fields/flash/acr/latency_16_states.yaml

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‎devices/fields/flash/acr/latency_2_states.yaml

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ACR:
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LATENCY:
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WS0: [0, 0 wait states]
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WS1: [1, 1 wait states]

‎devices/fields/flash/acr/latency_3_states.yaml

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ACR:
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LATENCY:
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WS0: [0, 0 wait states]
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WS1: [1, 1 wait states]
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WS2: [2, 2 wait states]

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