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RTC for C0
1 parent 47dbbdb commit 401386a

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14 files changed

+282
-279
lines changed

14 files changed

+282
-279
lines changed

‎devices/collect/rtc/alarm.yaml

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,9 @@
11
CR:
22
_array:
3-
ALR[AB]E: {}
4-
ALR[AB]IE: {}
3+
ALR[AB]E:
4+
description: Alarm %s enable
5+
ALR[AB]IE:
6+
description: Alarm %s interrupt enable
57

68
"?~ISR":
79
_array:

‎devices/fields/rtc/v1/f1.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,4 +46,4 @@ DIVL:
4646
CNT[HL]:
4747
CNT[HL]: [0, 0xFFFF]
4848
ALR[HL]:
49-
ALR[HL]: [0, 0xFFFF]
49+
ALR[HL]: [0, 0xFFFF]

‎devices/fields/rtc/v2/common.yaml

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
# Real Time Clock
22

3-
_include: basic_wakeup.yaml
3+
_include:
4+
- basic.yaml
5+
- wakeup.yaml
46

57
CR:
68
COSEL:

‎devices/fields/rtc/v2/basic_wakeup.yaml renamed to ‎devices/fields/rtc/v2/wakeup.yaml

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,5 @@
11
# Real Time Clock
22

3-
_include: basic.yaml
4-
53
CR:
64
WUTIE:
75
Disabled: [0, Wakeup timer interrupt disabled]

‎devices/fields/rtc/v3/basic.yaml

Lines changed: 208 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,208 @@
1+
TR:
2+
PM:
3+
AM: [0, AM or 24-hour format]
4+
PM: [1, PM]
5+
HT: [0, 3]
6+
HU: [0, 15]
7+
MNT: [0, 7]
8+
MNU: [0, 15]
9+
ST: [0, 7]
10+
SU: [0, 15]
11+
DR:
12+
YT: [0, 15]
13+
YU: [0, 15]
14+
WDU: [1, 7]
15+
MT: [0, 1]
16+
MU: [0, 15]
17+
DT: [0, 3]
18+
DU: [0, 15]
19+
20+
SSR:
21+
SS: [0, 65535]
22+
23+
ICSR:
24+
RECALPF:
25+
_read:
26+
Pending:
27+
[
28+
1,
29+
"The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0",
30+
]
31+
INIT:
32+
FreeRunningMode: [0, Free running mode]
33+
InitMode:
34+
[
35+
1,
36+
"Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.",
37+
]
38+
INITF:
39+
_read:
40+
NotAllowed: [0, Calendar registers update is not allowed]
41+
Allowed: [1, Calendar registers update is allowed]
42+
RSF:
43+
_read:
44+
NotSynced: [0, Calendar shadow registers not yet synchronized]
45+
Synced: [1, Calendar shadow registers synchronized]
46+
_W0C:
47+
Clear: [0, This flag is cleared by software by writing 0]
48+
INITS:
49+
_read:
50+
NotInitalized: [0, Calendar has not been initialized]
51+
Initalized: [1, Calendar has been initialized]
52+
SHPF:
53+
_read:
54+
NoShiftPending: [0, No shift operation is pending]
55+
ShiftPending: [1, A shift operation is pending]
56+
57+
PRER:
58+
PREDIV_A: [0, 0x7F]
59+
PREDIV_S: [0, 0x7FFF]
60+
61+
CR:
62+
OUT2EN:
63+
Disabled: [0, RTC output 2 disable]
64+
Enabled: [1, RTC output 2 enable]
65+
TAMPALRM_TYPE:
66+
PushPull: [0, TAMPALRM is push-pull output]
67+
OpenDrain: [1, TAMPALRM is open-drain output]
68+
TAMPALRM_PU:
69+
NoPullUp: [0, No pull-up is applied on TAMPALRM output]
70+
PullUp: [1, A pull-up is applied on TAMPALRM output]
71+
COE:
72+
Disabled: [0, Calibration output disabled]
73+
Enabled: [1, Calibration output enabled]
74+
OSEL:
75+
Disabled: [0, Output disabled]
76+
AlarmA: [1, Alarm A output enabled]
77+
AlarmB: [2, Alarm B output enabled]
78+
Wakeup: [3, Wakeup output enabled]
79+
POL:
80+
High: [0, "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"]
81+
Low: [1, "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"]
82+
COSEL:
83+
CalFreq_512Hz: [0, Calibration output is 512 Hz (with default prescaler setting)]
84+
CalFreq_1Hz: [1, Calibration output is 1 Hz (with default prescaler setting)]
85+
BKP:
86+
DSTNotChanged: [0, Daylight Saving Time change has not been performed]
87+
DSTChanged: [1, Daylight Saving Time change has been performed]
88+
SUB1H:
89+
_write:
90+
Sub1:
91+
[1, Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode]
92+
ADD1H:
93+
_write:
94+
Add1: [1, Adds 1 hour to the current time. This can be used for summer time change outside initialization mode]
95+
TSIE:
96+
Disabled: [0, Time-stamp Interrupt disabled]
97+
Enabled: [1, Time-stamp Interrupt enabled]
98+
ALR[AB]IE:
99+
Disabled: [0, Alarm Interrupt disabled]
100+
Enabled: [1, Alarm Interrupt enabled]
101+
TSE:
102+
Disabled: [0, Timestamp disabled]
103+
Enabled: [1, Timestamp enabled]
104+
ALR[AB]E:
105+
Disabled: [0, Alarm disabled]
106+
Enabled: [1, Alarm enabled]
107+
FMT:
108+
TwentyFourHour: [0, 24 hour/day format]
109+
AmPm: [1, AM/PM hour format]
110+
BYPSHAD:
111+
ShadowReg:
112+
[
113+
0,
114+
"Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles",
115+
]
116+
BypassShadowReg:
117+
[
118+
1,
119+
"Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters",
120+
]
121+
REFCKON:
122+
Disabled: [0, RTC_REFIN detection disabled]
123+
Enabled: [1, RTC_REFIN detection enabled]
124+
TSEDGE:
125+
RisingEdge: [0, RTC_TS input rising edge generates a time-stamp event]
126+
FallingEdge: [1, RTC_TS input falling edge generates a time-stamp event]
127+
128+
WPR:
129+
KEY:
130+
Deactivate1: [0xCA, Key 1]
131+
Deactivate2: [0x53, Key 2]
132+
Activate: [0x0, Activate write protection (any value that is not the keys)]
133+
134+
CALR:
135+
CALP:
136+
NoChange: [0, No RTCCLK pulses are added]
137+
IncreaseFreq: [1, "One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)"]
138+
CALW8:
139+
EightSeconds: [1, "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected"]
140+
CALW16:
141+
SixteenSeconds:
142+
[
143+
1,
144+
"When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1",
145+
]
146+
147+
CALM: [0, 511]
148+
149+
SHIFTR:
150+
ADD1S:
151+
_write:
152+
Add1: [1, Add one second to the clock/calendar]
153+
SUBFS: [0, 32767]
154+
155+
TSTR:
156+
PM:
157+
AM: [0, AM or 24-hour format]
158+
PM: [1, PM]
159+
160+
ALRM[AB]R:
161+
MSK*:
162+
Mask: [0, Alarm set if the date/day match]
163+
NotMask: [1, "Date/day don’t care in Alarm comparison"]
164+
WDSEL:
165+
DateUnits: [0, "DU[3:0] represents the date units"]
166+
WeekDay: [1, "DU[3:0] represents the week day. DT[1:0] is don’t care."]
167+
DT: [0, 3]
168+
DU: [0, 15]
169+
PM:
170+
AM: [0, AM or 24-hour format]
171+
PM: [1, PM]
172+
HT: [0, 3]
173+
HU: [0, 15]
174+
MNT: [0, 7]
175+
MNU: [0, 15]
176+
ST: [0, 7]
177+
SU: [0, 15]
178+
179+
ALRM?SSR:
180+
SS: [0, 0x7FFF]
181+
182+
SR:
183+
TSOVF:
184+
Overflow: [1, This flag is set by hardware when a time-stamp event occurs while TSF is already set]
185+
TSF:
186+
TimestampEvent: [1, This flag is set by hardware when a time-stamp event occurs]
187+
ALR[AB]F:
188+
Match:
189+
[
190+
1,
191+
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR),
192+
]
193+
194+
MISR:
195+
TSOVMF:
196+
Overflow: [1, This flag is set by hardware when a time-stamp event occurs while TSF is already set]
197+
TSMF:
198+
TimestampEvent: [1, This flag is set by hardware when a time-stamp event occurs]
199+
ALR[AB]MF:
200+
Match:
201+
[
202+
1,
203+
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR),
204+
]
205+
206+
SCR:
207+
"*":
208+
Clear: [1, Clear interrupt flag]

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