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Merge pull request #1163 from z-av/structures
Add placeholders for all peripherals
2 parents 488944d + 69b2a55 commit 8b9cde4

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‎CHANGELOG.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
* USART: refactor and add missing enums
66
* STM32H503: Add missing RNG_NSCR register
77
* Refactor timers, add enums
8+
* Add placeholders for all peripherals
89
* STM32H5xx: Add H533 (#1129)
910
* G4: Fix swapped reset values for SPI4 CR1 and CR2 by deriving SPI4 from SPI1 (#957)
1011
* STM32H5xx: Update SVD to version 1.7 and add H523 (#1124)

‎devices/collect/gtzc/h5_u5.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,6 @@ _array:
88
_array:
99
PRIV*: {}
1010

11-
CFGLOCK?,CFGLOCKR?:
11+
CFGLOCK,CFGLOCK?,CFGLOCKR?:
1212
_array:
1313
SPLCK*: {}

‎devices/fields/crs/crs.yaml

Lines changed: 49 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -1,53 +1,52 @@
1-
CRS:
2-
CR:
3-
TRIM: [0, 0x3F]
4-
SWSYNC:
5-
Sync: [1, A software sync is generated]
6-
AUTOTRIMEN:
7-
Disabled: [0, Automatic trimming disabled]
8-
Enabled: [1, Automatic trimming enabled]
9-
CEN:
10-
Disabled: [0, Frequency error counter disabled]
11-
Enabled: [1, Frequency error counter enabled]
12-
"*IE":
13-
Disabled: [0, Interrupt disabled]
14-
Enabled: [1, Interrupt enabled]
1+
CR:
2+
TRIM: [0, 0x3F]
3+
SWSYNC:
4+
Sync: [1, A software sync is generated]
5+
AUTOTRIMEN:
6+
Disabled: [0, Automatic trimming disabled]
7+
Enabled: [1, Automatic trimming enabled]
8+
CEN:
9+
Disabled: [0, Frequency error counter disabled]
10+
Enabled: [1, Frequency error counter enabled]
11+
"*IE":
12+
Disabled: [0, Interrupt disabled]
13+
Enabled: [1, Interrupt enabled]
1514

16-
CFGR:
17-
SYNCPOL:
18-
RisingEdge: [0, SYNC active on rising edge]
19-
FallingEdge: [1, SYNC active on falling edge]
20-
SYNCSRC:
21-
GPIO_AF: [0, GPIO AF (crs_sync_in_1) selected as SYNC signal source]
22-
LSE: [1, LSE (crs_sync_in_2) selected as SYNC signal source]
23-
USB_SOF: [2, USB SOF (crs_sync_in_3) selected as SYNC signal source]
24-
SYNCDIV:
25-
NotDivided: [0, SYNC not divided]
26-
DivideBy2: [1, SYNC divided by 2]
27-
DivideBy4: [2, SYNC divided by 4]
28-
DivideBy8: [3, SYNC divided by 8]
29-
DivideBy16: [4, SYNC divided by 16]
30-
DivideBy32: [5, SYNC divided by 32]
31-
DivideBy64: [6, SYNC divided by 64]
32-
DivideBy128: [7, SYNC divided by 128]
33-
FELIM: [0, 0xFF]
34-
RELOAD: [0, 0xFFFF]
15+
CFGR:
16+
SYNCPOL:
17+
RisingEdge: [0, SYNC active on rising edge]
18+
FallingEdge: [1, SYNC active on falling edge]
19+
SYNCSRC:
20+
GPIO_AF: [0, GPIO AF (crs_sync_in_1) selected as SYNC signal source]
21+
LSE: [1, LSE (crs_sync_in_2) selected as SYNC signal source]
22+
USB_SOF: [2, USB SOF (crs_sync_in_3) selected as SYNC signal source]
23+
SYNCDIV:
24+
NotDivided: [0, SYNC not divided]
25+
DivideBy2: [1, SYNC divided by 2]
26+
DivideBy4: [2, SYNC divided by 4]
27+
DivideBy8: [3, SYNC divided by 8]
28+
DivideBy16: [4, SYNC divided by 16]
29+
DivideBy32: [5, SYNC divided by 32]
30+
DivideBy64: [6, SYNC divided by 64]
31+
DivideBy128: [7, SYNC divided by 128]
32+
FELIM: [0, 0xFF]
33+
RELOAD: [0, 0xFFFF]
3534

36-
ISR:
37-
FECAP: [0, 0xFFFF]
38-
FEDIR:
39-
UpCounting: [0, Error in up-counting direction]
40-
DownCounting: [1, Error in down-counting direction]
41-
SYNCMISS:
42-
NotSignaled: [0, Signal not set]
43-
Signaled: [1, Signal set]
44-
SYNCERR:
45-
NotSignaled: [0, Signal not set]
46-
Signaled: [1, Signal set]
47-
"*F":
48-
NotSignaled: [0, Signal not set]
49-
Signaled: [1, Signal set]
35+
ISR:
36+
FECAP: [0, 0xFFFF]
37+
FEDIR:
38+
UpCounting: [0, Error in up-counting direction]
39+
DownCounting: [1, Error in down-counting direction]
40+
SYNCMISS:
41+
NotSignaled: [0, Signal not set]
42+
Signaled: [1, Signal set]
43+
SYNCERR:
44+
NotSignaled: [0, Signal not set]
45+
Signaled: [1, Signal set]
46+
"*F":
47+
NotSignaled: [0, Signal not set]
48+
Signaled: [1, Signal set]
5049

51-
ICR:
52-
"*C":
53-
Clear: [1, Clear flag]
50+
ICR:
51+
"*C":
52+
Clear: [1, Clear flag]

‎devices/fields/dbg/dbg_l0.yaml

Lines changed: 33 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1,36 +1,35 @@
11
# Debug registers for L0
22

3-
DBG:
4-
CR:
5-
DBG_STANDBY:
6-
Disabled: [0, Debug Standby Mode Disabled]
7-
Enabled: [1, Debug Standby Mode Enabled]
8-
DBG_STOP:
9-
Disabled: [0, Debug Stop Mode Disabled]
10-
Enabled: [1, Debug Stop Mode Enabled]
11-
DBG_SLEEP:
12-
Disabled: [0, Debug Sleep Mode Disabled]
13-
Enabled: [1, Debug Sleep Mode Enabled]
14-
APB1_FZ:
15-
DBG_LPTIMER_STOP:
16-
Continue: [0, LPTIM1 counter clock is fed even if the core is halted]
17-
Stop: [1, LPTIM1 counter clock is stopped when the core is halted]
18-
DBG_I2C*_STOP:
19-
NormalMode: [0, Same behavior as in normal mode]
20-
SMBusTimeoutFrozen: [1, I2C3 SMBUS timeout is frozen]
21-
DBG_IWDG_STOP:
22-
Continue: [0, The independent watchdog counter clock continues even if the core is halted]
23-
Stop: [1, The independent watchdog counter clock is stopped when the core is halted]
24-
DBG_WWDG_STOP:
25-
Continue: [0, The window watchdog counter clock continues even if the core is halted]
26-
Stop: [1, The window watchdog counter clock is stopped when the core is halted]
27-
DBG_RTC_STOP:
28-
Continue: [0, The clock of the RTC counter is fed even if the core is halted]
29-
Stop: [1, The clock of the RTC counter is stopped when the core is halted]
30-
DBG_TIM*_STOP:
31-
Continue: [0, The counter clock of TIMx is fed even if the core is halted]
32-
Stop: [1, The counter clock of TIMx is stopped when the core is halted]
33-
APB2_FZ:
34-
DBG_TIM*_STOP:
35-
Continue: [0, The counter clock of TIMx is fed even if the core is halted]
36-
Stop: [1, The counter clock of TIMx is stopped when the core is halted]
3+
CR:
4+
DBG_STANDBY:
5+
Disabled: [0, Debug Standby Mode Disabled]
6+
Enabled: [1, Debug Standby Mode Enabled]
7+
DBG_STOP:
8+
Disabled: [0, Debug Stop Mode Disabled]
9+
Enabled: [1, Debug Stop Mode Enabled]
10+
DBG_SLEEP:
11+
Disabled: [0, Debug Sleep Mode Disabled]
12+
Enabled: [1, Debug Sleep Mode Enabled]
13+
APB1_FZ:
14+
DBG_LPTIMER_STOP:
15+
Continue: [0, LPTIM1 counter clock is fed even if the core is halted]
16+
Stop: [1, LPTIM1 counter clock is stopped when the core is halted]
17+
DBG_I2C*_STOP:
18+
NormalMode: [0, Same behavior as in normal mode]
19+
SMBusTimeoutFrozen: [1, I2C3 SMBUS timeout is frozen]
20+
DBG_IWDG_STOP:
21+
Continue: [0, The independent watchdog counter clock continues even if the core is halted]
22+
Stop: [1, The independent watchdog counter clock is stopped when the core is halted]
23+
DBG_WWDG_STOP:
24+
Continue: [0, The window watchdog counter clock continues even if the core is halted]
25+
Stop: [1, The window watchdog counter clock is stopped when the core is halted]
26+
DBG_RTC_STOP:
27+
Continue: [0, The clock of the RTC counter is fed even if the core is halted]
28+
Stop: [1, The clock of the RTC counter is stopped when the core is halted]
29+
DBG_TIM*_STOP:
30+
Continue: [0, The counter clock of TIMx is fed even if the core is halted]
31+
Stop: [1, The counter clock of TIMx is stopped when the core is halted]
32+
APB2_FZ:
33+
DBG_TIM*_STOP:
34+
Continue: [0, The counter clock of TIMx is fed even if the core is halted]
35+
Stop: [1, The counter clock of TIMx is stopped when the core is halted]

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