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Merge branch 'master' into h7-hi-mem-flash
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‎CHANGELOG.md

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## [Unreleased]
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* Updated to `svd2rust` 0.36.1, `svdtools` 0.4.6, `form` 0.12.1, use tools binaries for CI (#1174)
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* bump `defmt` dependency to 1.0
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* Updated to `svd2rust` 0.36.1, `svdtools` 0.4.6, `form` 0.13.0, use tools binaries for CI (#1174)
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* bump `defmt` dependency to 1.0 (#1209)
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* Use `svd2rust.toml` config, use custom ident suffixes (#948)
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* Replace `makehtml.py` with `svdtools html` (#881)
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* Remove workaround for bug in duckscript's `mv` (#981)
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* F2, F4, F7: Add definitions for OPTCR, OPTCR1 and OPTCR2 registers of FLASH peripheral (#1157)
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* F2, F4, F7: Fix several fields of FLASH peripheral and reorganise 'patches', 'fields' and 'collect' according to impacted registers (#1161)
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* F1, F2, F4: Derive identical UART registers from USART1, add GPTR.PSC (#1179)
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* CCMR3_Output fix
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* CRC enums and fixes
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* Add DAC enums
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* DCMI enums
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* DFSDM enums and fixes
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* RNG enums
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* SDIO/SDMMC v1
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* TSC enums and arrays
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* USB v2
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* Use arrays for DAC channels
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* Derive TIM registers
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* CCMR3_Output fix (#1184)
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* CRC enums and fixes (#1206)
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* Add DAC enums (#1196)
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* DCMI enums (#1205)
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* DFSDM enums and fixes (#1218)
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* RNG enums (#1220)
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* SDIO/SDMMC v1 (#1204)
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* OCTOSPI, TAMP, LTDC enums (#1226)
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* TSC enums and arrays (#1221)
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* USB v2 (#1202)
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* Use arrays for DAC channels (#1197)
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* Derive TIM registers (#1184)
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* Update README.md (#1152)
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* Add SPI enums for G4, U5, H7+
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* FMC/FSMC enums, arrays & derives
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* CRS enums
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* Add SPI enums for G4, U5, H7+ (#1199)
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* FMC/FSMC enums, arrays & derives (#1200)
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* CRS enums (#1208)
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* HRTIM:
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* H7 & G4 fixes and enums (#1021) (#1022)
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* Remove timer block suffixes from register/field names (#1023)

‎README.md

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* On x86-64 Linux, run `make install` to download pre-built binaries at the
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current version used by stm32-rs
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* Otherwise, build using `cargo` (double check versions against `scripts/tool_install.sh`):
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* `cargo install form --version 0.12.1`
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* `cargo install form --version 0.13.0`
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* `cargo install svdtools --version 0.4.6`
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* `cargo install svd2rust --version 0.36.1`
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* Install rustfmt: `rustup component add rustfmt`

‎devices/collect/lpgpio/lp.yaml

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MODER:
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_array:
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MODE*: {}
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IDR:
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_array:
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ID*: {}
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ODR:
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_array:
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OD*: {}
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BSRR:
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_array:
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BS*: {}
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BR*: {}
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BRR:
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_array:
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BR*: {}

‎devices/collect/tamp/bkp.yaml

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‎devices/fields/octospi/common.yaml

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"HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or Indirect read/write modes must be used",
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]
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DEVSIZE: [0, 0x1F]
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CSHT: [0, 0x3F]
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DLYBYP:
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DelayBlockEnabled:
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[
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DCR3:
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CSBOUND: [0, 0x1F]
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MAXTRAN: [0, 0xFF]
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"?~MAXTRAN": [0, 0xFF]
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DCR4:
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REFRESH: [0, 0xFFFFFFFF]
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INTERVAL: [0, 0xFFFF]
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CCR:
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SIOO:
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"?~SIOO":
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SendEveryTransaction: [0, Send instruction on every transaction]
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SendOnlyFirstCmd: [1, Send instruction only for the first command]
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DQSE:

‎devices/fields/octospi/l4.yaml

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DMM:
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Disabled: [0, Dual-quad configuration disabled]
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Enabled: [1, Dual-quad configuration enabled]
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DCR1:
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CSHT: [0, 0x3F]

‎devices/fields/octospi/l5.yaml

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_include:
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- common.yaml
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CR:
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FSEL:
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FLASH1: [0, "FLASH 1 selected (data exchanged over IO[3:0])"]
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FLASH2: [1, "FLASH 2 selected (data exchanged over IO[7:4])"]
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DMM:
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Disabled: [0, Dual-quad configuration disabled]
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Enabled: [1, Dual-quad configuration enabled]
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DCR1:
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CSHT: [0, 7]

‎devices/fields/octospi/u5.yaml

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DMM:
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Disabled: [0, Dual-memory configuration disabled]
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Enabled: [1, Dual-memory configuration enabled]
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DCR1:
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CSHT: [0, 0x3F]

‎devices/fields/tamp/tamp_wl.yaml

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COUNTR:
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COUNT: [0, 0xFFFFFFFF]
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BKP?R:
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BKP: [0, 0xFFFFFFFF]
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BKP1?R:
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BKP?*R:
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BKP: [0, 0xFFFFFFFF]

‎devices/patches/octospi/add_wrap.yaml

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_add:
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WPCCR:
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description: wrap communication configuration register
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addressOffset: 0x140
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resetValue: 0x00000000
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fields:
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DQSE:
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description: DQS enable
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bitOffset: 29
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bitWidth: 1
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DDTR:
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description: Data double transfer rate
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bitOffset: 27
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bitWidth: 1
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DMODE:
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description: Data mode
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bitOffset: 24
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bitWidth: 3
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ABSIZE:
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description: Alternate bytes size
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bitOffset: 20
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bitWidth: 2
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ABDTR:
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description: Alternate bytes double transfer rate
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bitOffset: 19
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bitWidth: 1
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ABMODE:
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description: Alternate-byte mode
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bitOffset: 16
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bitWidth: 3
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ADSIZE:
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description: Address size
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bitOffset: 12
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bitWidth: 2
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ADDTR:
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description: Address double transfer rate
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bitOffset: 11
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bitWidth: 1
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ADMODE:
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description: Address mode
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bitOffset: 8
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bitWidth: 3
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ISIZE:
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description: Instruction size
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bitOffset: 4
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bitWidth: 2
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IDTR:
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description: Instruction double transfer rate
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bitOffset: 3
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bitWidth: 1
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IMODE:
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description: Instruction mode
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bitOffset: 0
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bitWidth: 3
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WPTCR:
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description: Wrap timing configuration register
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addressOffset: 0x148
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resetValue: 0x00000000
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fields:
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SSHIFT:
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description: Sample shift
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bitOffset: 30
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bitWidth: 1
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DHQC:
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description: Delay hold quarter cycle
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bitOffset: 28
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bitWidth: 1
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DCYC:
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description: Number of dummy cycles
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bitOffset: 0
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bitWidth: 5
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WPIR:
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description: Wrap instruction register
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addressOffset: 0x150
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resetValue: 0x00000000
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fields:
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INSTRUCTION:
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description: Instruction
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bitOffset: 0
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bitWidth: 32
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WPABR:
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description: Wrap alternate bytes register
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addressOffset: 0x160
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resetValue: 0x00000000
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fields:
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ALTERNATE:
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description: Alternate bytes
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bitOffset: 0
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bitWidth: 32

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