|
1 | 1 | # Base for `i2c_v2.yaml`. |
2 | 2 |
|
3 | | -CR1: |
4 | | - PECEN: |
5 | | - Disabled: [0, PEC calculation disabled] |
6 | | - Enabled: [1, PEC calculation enabled] |
7 | | - ALERTEN: |
8 | | - Disabled: |
9 | | - [ |
10 | | - 0, |
11 | | - "In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported", |
12 | | - ] |
13 | | - Enabled: |
14 | | - [ |
15 | | - 1, |
16 | | - "In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported", |
17 | | - ] |
18 | | - SMBDEN: |
19 | | - Disabled: [0, Device default address disabled. Address 0b1100001x is NACKed] |
20 | | - Enabled: [1, Device default address enabled. Address 0b1100001x is ACKed] |
21 | | - SMBHEN: |
22 | | - Disabled: [0, Host address disabled. Address 0b0001000x is NACKed] |
23 | | - Enabled: [1, Host address enabled. Address 0b0001000x is ACKed] |
24 | | - GCEN: |
25 | | - Disabled: [0, General call disabled. Address 0b00000000 is NACKed] |
26 | | - Enabled: [1, General call enabled. Address 0b00000000 is ACKed] |
27 | | - NOSTRETCH: |
28 | | - Enabled: [0, Clock stretching enabled] |
29 | | - Disabled: [1, Clock stretching disabled] |
30 | | - SBC: |
31 | | - Disabled: [0, Slave byte control disabled] |
32 | | - Enabled: [1, Slave byte control enabled] |
33 | | - RXDMAEN: |
34 | | - Disabled: [0, DMA mode disabled for reception] |
35 | | - Enabled: [1, DMA mode enabled for reception] |
36 | | - TXDMAEN: |
37 | | - Disabled: [0, DMA mode disabled for transmission] |
38 | | - Enabled: [1, DMA mode enabled for transmission] |
39 | | - ANFOFF: |
40 | | - Enabled: [0, Analog noise filter enabled] |
41 | | - Disabled: [1, Analog noise filter disabled] |
42 | | - DNF: |
43 | | - NoFilter: [0, Digital filter disabled] |
44 | | - Filter1: [1, Digital filter enabled and filtering capability up to 1 tI2CCLK] |
45 | | - Filter2: [2, Digital filter enabled and filtering capability up to 2 tI2CCLK] |
46 | | - Filter3: [3, Digital filter enabled and filtering capability up to 3 tI2CCLK] |
47 | | - Filter4: [4, Digital filter enabled and filtering capability up to 4 tI2CCLK] |
48 | | - Filter5: [5, Digital filter enabled and filtering capability up to 5 tI2CCLK] |
49 | | - Filter6: [6, Digital filter enabled and filtering capability up to 6 tI2CCLK] |
50 | | - Filter7: [7, Digital filter enabled and filtering capability up to 7 tI2CCLK] |
51 | | - Filter8: [8, Digital filter enabled and filtering capability up to 8 tI2CCLK] |
52 | | - Filter9: [9, Digital filter enabled and filtering capability up to 9 tI2CCLK] |
53 | | - Filter10: [10, Digital filter enabled and filtering capability up to 10 tI2CCLK] |
54 | | - Filter11: [11, Digital filter enabled and filtering capability up to 11 tI2CCLK] |
55 | | - Filter12: [12, Digital filter enabled and filtering capability up to 12 tI2CCLK] |
56 | | - Filter13: [13, Digital filter enabled and filtering capability up to 13 tI2CCLK] |
57 | | - Filter14: [14, Digital filter enabled and filtering capability up to 14 tI2CCLK] |
58 | | - Filter15: [15, Digital filter enabled and filtering capability up to 15 tI2CCLK] |
59 | | - ERRIE: |
60 | | - Disabled: [0, Error detection interrupts disabled] |
61 | | - Enabled: [1, Error detection interrupts enabled] |
62 | | - TCIE: |
63 | | - Disabled: [0, Transfer Complete interrupt disabled] |
64 | | - Enabled: [1, Transfer Complete interrupt enabled] |
65 | | - STOPIE: |
66 | | - Disabled: [0, Stop detection (STOPF) interrupt disabled] |
67 | | - Enabled: [1, Stop detection (STOPF) interrupt enabled] |
68 | | - NACKIE: |
69 | | - Disabled: [0, Not acknowledge (NACKF) received interrupts disabled] |
70 | | - Enabled: [1, Not acknowledge (NACKF) received interrupts enabled] |
71 | | - ADDRIE: |
72 | | - Disabled: [0, Address match (ADDR) interrupts disabled] |
73 | | - Enabled: [1, Address match (ADDR) interrupts enabled] |
74 | | - RXIE: |
75 | | - Disabled: [0, Receive (RXNE) interrupt disabled] |
76 | | - Enabled: [1, Receive (RXNE) interrupt enabled] |
77 | | - TXIE: |
78 | | - Disabled: [0, Transmit (TXIS) interrupt disabled] |
79 | | - Enabled: [1, Transmit (TXIS) interrupt enabled] |
80 | | - PE: |
81 | | - Disabled: [0, Peripheral disabled] |
82 | | - Enabled: [1, Peripheral enabled] |
83 | | - "?~WUPEN": |
84 | | - Disabled: [0, Wakeup from Stop mode disabled] |
85 | | - Enabled: [1, Wakeup from Stop mode enabled] |
86 | | - |
87 | | -CR2: |
88 | | - PECBYTE: |
89 | | - _read: |
90 | | - NoPec: [0, No PEC transfer] |
91 | | - Pec: [1, PEC transmission/reception is requested] |
92 | | - _W1S: |
93 | | - Pec: [1, PEC transmission/reception is requested] |
94 | | - AUTOEND: |
95 | | - Software: [0, "Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low"] |
96 | | - Automatic: [1, "Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred"] |
97 | | - RELOAD: |
98 | | - Completed: [0, The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)] |
99 | | - NotCompleted: [1, The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)] |
100 | | - NACK: |
101 | | - _read: |
102 | | - Ack: [0, an ACK is sent after current received byte] |
103 | | - Nack: [1, a NACK is sent after current received byte] |
104 | | - _W1S: |
105 | | - Nack: [1, a NACK is sent after current received byte] |
106 | | - STOP: |
107 | | - _read: |
108 | | - NoStop: [0, No Stop generation] |
109 | | - Stop: [1, Stop generation after current byte transfer] |
110 | | - _W1S: |
111 | | - Stop: [1, Stop generation after current byte transfer] |
112 | | - START: |
113 | | - _read: |
114 | | - NoStart: [0, No Start generation] |
115 | | - Start: [1, Restart/Start generation] |
116 | | - _W1S: |
117 | | - Start: [1, Restart/Start generation] |
118 | | - HEAD10R: |
119 | | - Complete: [0, The master sends the complete 10 bit slave address read sequence] |
120 | | - Partial: [1, "The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction"] |
121 | | - ADD10: |
122 | | - Bit7: [0, The master operates in 7-bit addressing mode] |
123 | | - Bit10: [1, The master operates in 10-bit addressing mode] |
124 | | - RD_WRN: |
125 | | - Write: [0, Master requests a write transfer] |
126 | | - Read: [1, Master requests a read transfer] |
127 | | - NBYTES: [0, 255] |
128 | | - SADD: [0, 1023] |
129 | | -OAR1: |
130 | | - OA1EN: |
131 | | - Disabled: [0, Own address 1 disabled. The received slave address OA1 is NACKed] |
132 | | - Enabled: [1, Own address 1 enabled. The received slave address OA1 is ACKed] |
133 | | - OA1MODE: |
134 | | - Bit7: [0, Own address 1 is a 7-bit address] |
135 | | - Bit10: [1, Own address 1 is a 10-bit address] |
136 | | - OA1: [0, 1023] |
137 | | -OAR2: |
138 | | - OA2EN: |
139 | | - Disabled: [0, Own address 2 disabled. The received slave address OA2 is NACKed] |
140 | | - Enabled: [1, Own address 2 enabled. The received slave address OA2 is ACKed] |
141 | | - OA2MSK: |
142 | | - NoMask: [0, No mask] |
143 | | - Mask1: [1, "OA2[1] is masked and don’t care. Only OA2[7:2] are compared"] |
144 | | - Mask2: [2, "OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared"] |
145 | | - Mask3: [3, "OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared"] |
146 | | - Mask4: [4, "OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared"] |
147 | | - Mask5: [5, "OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared"] |
148 | | - Mask6: [6, "OA2[6:1] are masked and don’t care. Only OA2[7] is compared."] |
149 | | - Mask7: |
150 | | - [ |
151 | | - 7, |
152 | | - "OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged", |
153 | | - ] |
154 | | - OA2: [0, 127] |
155 | | -TIMINGR: |
156 | | - PRESC: [0, 15] |
157 | | - SCLDEL: [0, 15] |
158 | | - SDADEL: [0, 15] |
159 | | - SCLH: [0, 255] |
160 | | - SCLL: [0, 255] |
161 | | -TIMEOUTR: |
162 | | - TEXTEN: |
163 | | - Disabled: [0, Extended clock timeout detection is disabled] |
164 | | - Enabled: [1, Extended clock timeout detection is enabled] |
165 | | - TIMEOUTB: [0, 4095] |
166 | | - TIMOUTEN: |
167 | | - Disabled: [0, SCL timeout detection is disabled] |
168 | | - Enabled: [1, SCL timeout detection is enabled] |
169 | | - TIDLE: |
170 | | - Disabled: [0, TIMEOUTA is used to detect SCL low timeout] |
171 | | - Enabled: [1, TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)] |
172 | | - TIMEOUTA: [0, 4095] |
173 | | -ISR: |
174 | | - ADDCODE: [0, 127] |
175 | | - DIR: |
176 | | - Write: [0, "Write transfer, slave enters receiver mode"] |
177 | | - Read: [1, "Read transfer, slave enters transmitter mode"] |
178 | | - BUSY: |
179 | | - NotBusy: [0, No communication is in progress on the bus] |
180 | | - Busy: [1, A communication is in progress on the bus] |
181 | | - ALERT: |
182 | | - NoAlert: [0, SMBA alert is not detected] |
183 | | - Alert: [1, SMBA alert event is detected on SMBA pin] |
184 | | - TIMEOUT: |
185 | | - NoTimeout: [0, No timeout occured] |
186 | | - Timeout: [1, Timeout occured] |
187 | | - PECERR: |
188 | | - Match: [0, Received PEC does match with PEC register] |
189 | | - NoMatch: [1, Received PEC does not match with PEC register] |
190 | | - OVR: |
191 | | - NoOverrun: [0, No overrun/underrun error occurs] |
192 | | - Overrun: [1, "slave mode with NOSTRETCH=1, when an overrun/underrun error occurs"] |
193 | | - ARLO: |
194 | | - NotLost: [0, No arbitration lost] |
195 | | - Lost: [1, Arbitration lost] |
196 | | - BERR: |
197 | | - NoError: [0, No bus error] |
198 | | - Error: [1, Misplaced Start and Stop condition is detected] |
199 | | - TCR: |
200 | | - NotComplete: [0, Transfer is not complete] |
201 | | - Complete: [1, NBYTES has been transfered] |
202 | | - TC: |
203 | | - NotComplete: [0, Transfer is not complete] |
204 | | - Complete: [1, NBYTES has been transfered] |
205 | | - STOPF: |
206 | | - NoStop: [0, No Stop condition detected] |
207 | | - Stop: [1, Stop condition detected] |
208 | | - NACKF: |
209 | | - NoNack: [0, No NACK has been received] |
210 | | - Nack: [1, NACK has been received] |
211 | | - ADDR: |
212 | | - NotMatch: [0, Adress mismatched or not received] |
213 | | - Match: [1, Received slave address matched with one of the enabled slave addresses] |
214 | | - RXNE: |
215 | | - Empty: [0, The RXDR register is empty] |
216 | | - NotEmpty: [1, "Received data is copied into the RXDR register, and is ready to be read"] |
217 | | - TXIS: |
218 | | - _read: |
219 | | - NotEmpty: [0, The TXDR register is not empty] |
220 | | - Empty: [1, The TXDR register is empty and the data to be transmitted must be written in the TXDR register] |
221 | | - _W1S: |
222 | | - Trigger: [1, Generate a TXIS event] |
223 | | - TXE: |
224 | | - _read: |
225 | | - NotEmpty: [0, TXDR register not empty] |
226 | | - Empty: [1, TXDR register empty] |
227 | | - _W1S: |
228 | | - Flush: [1, Flush the transmit data register] |
229 | | - |
230 | | -ICR: |
231 | | - ALERTCF: |
232 | | - Clear: [1, Clears the ALERT flag in ISR register] |
233 | | - TIMOUTCF: |
234 | | - Clear: [1, Clears the TIMOUT flag in ISR register] |
235 | | - PECCF: |
236 | | - Clear: [1, Clears the PEC flag in ISR register] |
237 | | - OVRCF: |
238 | | - Clear: [1, Clears the OVR flag in ISR register] |
239 | | - ARLOCF: |
240 | | - Clear: [1, Clears the ARLO flag in ISR register] |
241 | | - BERRCF: |
242 | | - Clear: [1, Clears the BERR flag in ISR register] |
243 | | - STOPCF: |
244 | | - Clear: [1, Clears the STOP flag in ISR register] |
245 | | - NACKCF: |
246 | | - Clear: [1, Clears the NACK flag in ISR register] |
247 | | - ADDRCF: |
248 | | - Clear: [1, Clears the ADDR flag in ISR register] |
249 | | -PECR: |
250 | | - PEC: [0, 255] |
251 | | -RXDR: |
252 | | - RXDATA: [0, 255] |
253 | | -TXDR: |
254 | | - TXDATA: [0, 255] |
| 3 | +_include: |
| 4 | + - v2/common.yaml |
| 5 | + - v2/smbus.yaml |
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