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ADC refactor
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lines changed

‎devices/collect/adc/pcsel.yaml

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
PCSEL:
2+
_array:
3+
PCSEL*:
4+
description: Channel %s (VINP[i]) pre selection

‎devices/collect/adc/v3.yaml

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2,16 +2,6 @@ _array:
22
OFR?: {}
33
JDR?: {}
44

5-
# H7 only
6-
"?~CFGR2":
7-
_array:
8-
"?~RSHIFT?":
9-
description: Right-shift data after Offset %s correction
10-
CR:
11-
_array:
12-
"?~LINCALRDYW?":
13-
description: Linearity calibration ready Word %s
14-
155
ISR:
166
_array:
177
AWD?:

‎devices/collect/adc/v4.yaml

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
# ADC as used on the H7 family
2+
3+
_include: v3.yaml
4+
5+
CFGR2:
6+
_array:
7+
RSHIFT?:
8+
description: Right-shift data after Offset %s correction
9+
CR:
10+
_array:
11+
LINCALRDYW?:
12+
description: Linearity calibration ready Word %s

‎devices/collect/adc/c0_g0_wl.yaml renamed to ‎devices/collect/adc/v5.yaml

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
# ADC as used on the C0/G0/WL family
2+
13
CHSELR0:
24
_array:
35
CHSEL*:

‎devices/fields/adc/adc_v3_f3.yaml

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,8 @@ CFGR:
3232
Bits8: [2, 8-bit]
3333
Bits6: [3, 6-bit]
3434
DMACFG:
35-
OneShot: [0, DMA One Shot Mode selected]
36-
Circular: [1, DMA circular mode selected]
35+
OneShot: [0, DMA One Shot mode selected]
36+
Circular: [1, DMA Circular mode selected]
3737
DMAEN:
3838
Disabled: [0, DMA disabled]
3939
Enabled: [1, DMA enabled]
@@ -67,11 +67,19 @@ TR1:
6767
"[HL]T1": [0, 0xFFF]
6868
"TR[23]":
6969
"[HL]T?": [0, 0xFF]
70+
71+
DR:
72+
RDATA: [0, 0xFFFF]
73+
7074
OFR?:
7175
OFFSET_EN:
7276
Disabled: [0, Offset disabled]
7377
Enabled: [1, Offset enabled]
7478
OFFSET_CH: [0, 31]
7579
OFFSET: [0, 0xFFF]
80+
81+
JDR?:
82+
JDATA: [0, 0xFFFF]
83+
7684
CALFACT:
77-
CALFACT_?: [0, 0x7F]
85+
CALFACT_[DS]: [0, 0x7F]

‎devices/fields/adc/adc_v3_g4.yaml

Lines changed: 4 additions & 118 deletions
Original file line numberDiff line numberDiff line change
@@ -1,131 +1,17 @@
11
# ADC v3 with G4 specific fields
22

33
_include:
4-
- ../../patches/adc/split.yaml
5-
- adc_v3.yaml
4+
- v3+.yaml
5+
- sampling.yaml
6+
67
DIFSEL:
78
_merge:
89
DIFSEL: DIFSEL*
9-
CR:
10-
ADVREGEN:
11-
Disabled: [0, ADC voltage regulator disabled]
12-
Enabled: [1, ADC voltage regulator enabled]
13-
DEEPPWD:
14-
Disabled: [0, ADC not in Deep-power down]
15-
Enabled: [1, ADC in Deep-power-down (default reset state)]
1610

1711
CFGR:
18-
JQDIS:
19-
Enabled: [0, Injected Queue enabled]
20-
Disabled: [1, Injected Queue disabled]
2112
AWD1CH: [0, 18]
22-
EXTSEL:
23-
TIM1_CC1: [0, Timer 1 CC1 event]
24-
TIM1_CC2: [1, Timer 1 CC2 event]
25-
TIM1_CC3: [2, Timer 1 CC3 event]
26-
TIM2_CC2: [3, Timer 2 CC2 event]
27-
TIM3_TRGO: [4, Timer 3 TRGO event]
28-
EXTI11: [6, EXTI line 11]
29-
HRTIM_ADCTRG1: [7, HRTIM_ADCTRG1 event]
30-
HRTIM_ADCTRG3: [8, HRTIM_ADCTRG3 event]
31-
TIM1_TRGO: [9, Timer 1 TRGO event]
32-
TIM1_TRGO2: [10, Timer 1 TRGO2 event]
33-
TIM2_TRGO: [11, Timer 2 TRGO event]
34-
TIM6_TRGO: [13, Timer 6 TRGO event]
35-
TIM15_TRGO: [14, Timer 15 TRGO event]
36-
TIM3_CC4: [15, Timer 3 CC4 event]
37-
ALIGN:
38-
Right: [0, Right alignment]
39-
Left: [1, Left alignment]
40-
RES:
41-
Bits12: [0, 12-bit]
42-
Bits10: [1, 10-bit]
43-
Bits8: [2, 8-bit]
44-
Bits6: [3, 6-bit]
45-
DMACFG:
46-
OneShot: [0, DMA One Shot Mode selected]
47-
Circular: [1, DMA circular mode selected]
48-
DMAEN:
49-
Disabled: [0, DMA disabled]
50-
Enabled: [1, DMA enabled]
13+
5114
CFGR2:
52-
SMPTRIG:
53-
Disabled: [0, Sampling time control trigger mode disabled]
54-
Enabled: [1, Sampling time control trigger mode enabled]
55-
BULB:
56-
Disabled: [0, Bulb sampling mode disabled]
57-
Enabled: [1, Bulb sampling mode enabled. Immediately start sampling after last conversion finishes.]
58-
SWTRIG:
59-
Disabled: [0, End sampling period and start conversion]
60-
Enabled: [1, Start sampling period]
6115
GCOMP:
6216
Disabled: [0, Regular ADC operating mode]
6317
Enabled: [1, Gain compensation enabled and applies to all channels]
64-
ROVSM:
65-
Continued: [0, Oversampling is temporary stopped and continued after injection sequence]
66-
Resumed: [1, Oversampling is aborted and resumed from start after injection sequence]
67-
TROVS:
68-
Automatic: [0, All oversampled conversions for a channel are run following a trigger]
69-
Triggered: [1, Each oversampled conversion for a channel needs a new trigger]
70-
OVSS:
71-
NoShift: [0, No right shift applied to oversampling result]
72-
Shift1: [1, Shift oversampling result right by 1 bit]
73-
Shift2: [2, Shift oversampling result right by 2 bits]
74-
Shift3: [3, Shift oversampling result right by 3 bits]
75-
Shift4: [4, Shift oversampling result right by 4 bits]
76-
Shift5: [5, Shift oversampling result right by 5 bits]
77-
Shift6: [6, Shift oversampling result right by 6 bits]
78-
Shift7: [7, Shift oversampling result right by 7 bits]
79-
Shift8: [8, Shift oversampling result right by 8 bits]
80-
OVSR:
81-
OS2: [0, Oversampling ratio of 2]
82-
OS4: [1, Oversampling ratio of 4]
83-
OS8: [2, Oversampling ratio of 8]
84-
OS16: [3, Oversampling ratio of 16]
85-
OS32: [4, Oversampling ratio of 32]
86-
OS64: [5, Oversampling ratio of 64]
87-
OS128: [6, Oversampling ratio of 128]
88-
OS256: [7, Oversampling ratio of 256]
89-
JOVSE:
90-
Disabled: [0, Injected oversampling disabled]
91-
Enabled: [1, Injected oversampling enabled]
92-
ROVSE:
93-
Disabled: [0, Regular oversampling disabled]
94-
Enabled: [1, Regular oversampling enabled]
95-
SMPR?:
96-
"SMP?,SMP??":
97-
Cycles2_5: [0, 2.5 ADC clock cycles]
98-
Cycles6_5: [1, 6.5 ADC clock cycles]
99-
Cycles12_5: [2, 12.5 ADC clock cycles]
100-
Cycles24_5: [3, 24.5 ADC clock cycles]
101-
Cycles47_5: [4, 47.5 ADC clock cycles]
102-
Cycles92_5: [5, 92.5 ADC clock cycles]
103-
Cycles247_5: [6, 247.5 ADC clock cycles]
104-
Cycles640_5: [7, 640.5 ADC clock cycles]
105-
TR1:
106-
"[HL]T1": [0, 0xFFF]
107-
"TR[23]":
108-
"[HL]T?": [0, 0xFF]
109-
OFR?:
110-
OFFSET_EN:
111-
Disabled: [0, Offset disabled]
112-
Enabled: [1, Offset enabled]
113-
OFFSET_CH: [0, 31]
114-
OFFSET: [0, 0xFFF]
115-
CALFACT:
116-
CALFACT_?: [0, 0x7F]
117-
118-
JSQR:
119-
JEXTSEL:
120-
TIM1_TRGO: [0, Timer 1 TRGO event]
121-
TIM1_CC4: [1, Timer 1 CC4 event]
122-
TIM2_TRGO: [2, Timer 2 TRGO event]
123-
TIM2_CC1: [3, Timer 2 CC1 event]
124-
TIM3_CC4: [4, Timer 3 CC4 event]
125-
EXTI15: [6, EXTI line 15]
126-
TIM1_TRGO2: [8, Timer 1 TRGO2 event]
127-
TIM3_CC3: [11, Timer 3 CC3 event]
128-
TIM3_TRGO: [12, Timer 3 TRGO event]
129-
TIM3_CC1: [13, Timer 3 CC1 event]
130-
TIM6_TRGO: [14, Timer 6 TRGO event]
131-
TIM15_TRGO: [15, Timer 15 TRGO event]

‎devices/fields/adc/adc_v3_l4.yaml

Lines changed: 2 additions & 105 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,7 @@
11
# ADC v3 with L4/L4+/L5 specific fields
22

3-
CR:
4-
DEEPPWD:
5-
NotDeepPowerDown: [0, ADC not in Deep-power down]
6-
DeepPowerDown: [1, ADC in Deep-power-down (default reset state)]
7-
ADVREGEN:
8-
Disabled: [0, ADC Voltage regulator disabled]
9-
Enabled: [1, ADC Voltage regulator enabled]
3+
_include:
4+
- v3+.yaml
105

116
CFGR:
127
EXTSEL:
@@ -22,104 +17,6 @@ CFGR:
2217
TIM6_TRGO: [13, Timer 6 TRGO event]
2318
TIM15_TRGO: [14, Timer 15 TRGO event]
2419
TIM3_CC4: [15, Timer 3 CC4 event]
25-
ALIGN:
26-
Right: [0, Right alignment]
27-
Left: [1, Left alignment]
28-
RES:
29-
Bits12: [0, 12-bit]
30-
Bits10: [1, 10-bit]
31-
Bits8: [2, 8-bit]
32-
Bits6: [3, 6-bit]
33-
#DFSDMCFG:
34-
# Disabled: [ 0, DFSDM mode disabled]
35-
# Enabled: [ 1, DFSDM mode enabled]
36-
DMACFG:
37-
OneShot: [0, DMA One Shot mode selected]
38-
Circular: [1, DMA Circular mode selected]
39-
DMAEN:
40-
Disabled: [0, DMA disabled]
41-
Enabled: [1, DMA enabled]
42-
43-
CFGR2:
44-
ROVSM:
45-
ContinuedMode:
46-
[
47-
0,
48-
"When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)",
49-
]
50-
ResumedMode:
51-
[
52-
1,
53-
"When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)",
54-
]
55-
TOVS,TROVS:
56-
All: [0, All oversampled conversions for a channel are done consecutively following a trigger]
57-
Single: [1, Each oversampled conversion for a channel needs a new trigger]
58-
OVSS:
59-
NoShift: [0, No Shift]
60-
Shift1Bit: [1, Shift 1-bit]
61-
Shift2Bit: [2, Shift 2-bit]
62-
Shift3Bit: [3, Shift 3-bit]
63-
Shift4Bit: [4, Shift 4-bit]
64-
Shift5Bit: [5, Shift 5-bit]
65-
Shift6Bit: [6, Shift 6-bit]
66-
Shift7Bit: [7, Shift 7-bit]
67-
Shift8Bit: [8, Shift 8-bit]
68-
OVSR:
69-
Ratio2: [0, 2x]
70-
Ratio4: [1, 4x]
71-
Ratio8: [2, 8x]
72-
Ratio16: [3, 16x]
73-
Ratio32: [4, 32x]
74-
Ratio64: [5, 64x]
75-
Ratio128: [6, 128x]
76-
Ratio256: [7, 256x]
77-
JOVSE:
78-
Disabled: [0, Injected Oversampling disabled]
79-
Enabled: [1, Injected Oversampling enabled]
80-
ROVSE:
81-
Disabled: [0, Regular Oversampling disabled]
82-
Enabled: [1, Regular Oversampling enabled]
83-
84-
SMPR?:
85-
SMP?,SMP??:
86-
Cycles2_5: [0, 2.5 ADC clock cycles]
87-
Cycles6_5: [1, 6.5 ADC clock cycles]
88-
Cycles12_5: [2, 12.5 ADC clock cycles]
89-
Cycles24_5: [3, 24.5 ADC clock cycles]
90-
Cycles47_5: [4, 47.5 ADC clock cycles]
91-
Cycles92_5: [5, 92.5 ADC clock cycles]
92-
Cycles247_5: [6, 247.5 ADC clock cycles]
93-
Cycles640_5: [7, 640.5 ADC clock cycles]
94-
95-
TR1:
96-
HT1: [0, 0xFFF]
97-
LT1: [0, 0xFFF]
98-
99-
TR2:
100-
HT2: [0, 0xFF]
101-
LT2: [0, 0xFF]
102-
103-
TR3:
104-
HT3: [0, 0xFF]
105-
LT3: [0, 0xFF]
106-
107-
DR:
108-
RDATA: [0, 0xFFFF]
109-
110-
OFR?:
111-
"OFFSET?_EN,OFFSET_EN":
112-
Disabled: [0, "This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]"]
113-
Enabled: [1, "This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]"]
114-
"OFFSET?_CH,OFFSET_CH": [0, 0x1F]
115-
"OFFSET?,OFFSET": [0, 0xFFF]
116-
117-
JDR?:
118-
JDATA: [0, 0xFFFF]
119-
120-
CALFACT:
121-
CALFACT_D: [0, 0x7F]
122-
CALFACT_S: [0, 0x7F]
12320

12421
JSQR:
12522
JEXTSEL:

‎devices/fields/adc/adc_h5.yaml renamed to ‎devices/fields/adc/sampling.yaml

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,3 @@
1-
# ADC v3 with H5 specific fields
2-
3-
_include: adc_v3_l4.yaml
41
CFGR2:
52
SMPTRIG:
63
Disabled: [0, Sampling time control trigger mode disabled]

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