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Merge pull request #1167 from stm32-rs/dma-ref
DMA refactor
2 parents 329bd23 + cf1cee9 commit ddea8ae

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‎CHANGELOG.md

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Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
* Refactor timers, add enums
88
* Add placeholders for all peripherals
99
* STM32H5xx: Add H533 (#1129)
10+
* Fix DMA & collect
1011
* G4: Fix swapped reset values for SPI4 CR1 and CR2 by deriving SPI4 from SPI1 (#957)
1112
* STM32H5xx: Update SVD to version 1.7 and add H523 (#1124)
1213
* TIM3's CCRx is 16-bit for G0Bx and G0C0

‎devices/collect/dma/dmamux.yaml

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Original file line numberDiff line numberDiff line change
@@ -4,3 +4,20 @@ _array:
44
description: DMA Multiplexer Channel %s Control register
55
RG*CR:
66
name: RGCR%s
7+
8+
CSR:
9+
_array:
10+
SOF*:
11+
description: Synchronization Overrun Flag %s
12+
"CFR,CCFR":
13+
_array:
14+
CSOF*:
15+
description: Synchronization Clear Overrun Flag %s
16+
RGSR:
17+
_array:
18+
OF?:
19+
description: Generator Overrun Flag %s
20+
RGCFR:
21+
_array:
22+
COF?:
23+
description: Generator Clear Overrun Flag %s

‎devices/collect/dma/l5.yaml

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@@ -11,3 +11,6 @@ _cluster:
1111
name: M0AR
1212
CM1AR?:
1313
name: M1AR
14+
15+
_include:
16+
- isr_array.yaml

‎devices/fields/adc/adc_v3_f3.yaml

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@@ -1,7 +1,6 @@
11
# ADC v3 with F3 specific fields
22

33
_include:
4-
- ../../patches/adc/split.yaml
54
- adc_v3.yaml
65
CR:
76
ADVREGEN:

‎devices/fields/dma/common.yaml

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
ISR:
2+
TEIF*:
3+
NoError: [0, No transfer error]
4+
Error: [1, A transfer error has occured]
5+
HTIF*:
6+
NotHalf: [0, No half transfer event]
7+
Half: [1, A half transfer event has occured]
8+
TCIF*:
9+
NotComplete: [0, No transfer complete event]
10+
Complete: [1, A transfer complete event has occured]
11+
GIF*:
12+
NoEvent: [0, "No transfer error, half event, complete event"]
13+
Event: [1, "A transfer error, half event or complete event has occured"]
14+
IFCR:
15+
CTEIF*:
16+
Clear: [1, Clears the TEIF flag in the ISR register]
17+
CHTIF*:
18+
Clear: [1, Clears the HTIF flag in the ISR register]
19+
CTCIF*:
20+
Clear: [1, Clears the TCIF flag in the ISR register]
21+
CGIF*:
22+
Clear: [1, "Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register"]
23+
24+
CCR*:
25+
MEM2MEM:
26+
Disabled: [0, Memory to memory mode disabled]
27+
Enabled: [1, Memory to memory mode enabled]
28+
PL:
29+
Low: [0, Low priority]
30+
Medium: [1, Medium priority]
31+
High: [2, High priority]
32+
VeryHigh: [3, Very high priority]
33+
"[MP]SIZE":
34+
Bits8: [0, 8-bit size] # or Byte
35+
Bits16: [1, 16-bit size] # or HalfWord
36+
Bits32: [2, 32-bit size] # or Word
37+
"[MP]INC":
38+
Disabled: [0, Increment mode disabled]
39+
Enabled: [1, Increment mode enabled]
40+
CIRC:
41+
Disabled: [0, Circular buffer disabled]
42+
Enabled: [1, Circular buffer enabled]
43+
DIR:
44+
FromPeripheral: [0, Read from peripheral]
45+
FromMemory: [1, Read from memory]
46+
TEIE:
47+
Disabled: [0, Transfer Error interrupt disabled]
48+
Enabled: [1, Transfer Error interrupt enabled]
49+
HTIE:
50+
Disabled: [0, Half Transfer interrupt disabled]
51+
Enabled: [1, Half Transfer interrupt enabled]
52+
TCIE:
53+
Disabled: [0, Transfer Complete interrupt disabled]
54+
Enabled: [1, Transfer Complete interrupt enabled]
55+
EN:
56+
Disabled: [0, Channel disabled]
57+
Enabled: [1, Channel enabled]

‎devices/fields/dma/dma_wl.yaml

Lines changed: 3 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -1,75 +1,10 @@
1-
ISR:
2-
TCIF?:
3-
NotComplete: [0, No transfer complete event on channel x]
4-
Complete: [1, A transfer complete event occurred on channel x]
5-
HTIF?:
6-
NotHalf: [0, No half transfer event on channel x]
7-
Half: [1, A half transfer event occurred on channel x]
8-
TEIF?:
9-
NoError: [0, No transfer error on channel x]
10-
Error: [1, A transfer error occurred on channel x]
11-
GIF?:
12-
NoEvent: [0, "No TE, HT or TC event on channel x"]
13-
Event: [1, "A TE, HT or TC event occurred on channel x"]
14-
IFCR:
15-
TCIF?:
16-
Clear: [1, Clear the corresponding TCIFx flag]
17-
HTIF?:
18-
Clear: [1, Clear the corresponding HTIFx flag]
19-
TEIF?:
20-
Clear: [1, Clear the corresponding TEIFx flag]
21-
GIF?:
22-
Clear: [1, Clear the corresponding CGIFx flag]
1+
_include:
2+
- common.yaml
3+
234
CCR?:
245
PRIV:
256
Disabled: [0, Disabled]
267
Enabled: [1, Enabled]
27-
MEM2MEM:
28-
Disabled: [0, Disabled]
29-
Enabled: [1, Enabled]
30-
PL:
31-
Low: [0, Low]
32-
Medium: [1, Medium]
33-
High: [2, High]
34-
VeryHigh: [3, Very high]
35-
MSIZE:
36-
Bits8: [0, 8 bits]
37-
Bits16: [1, 16 bits]
38-
Bits32: [2, 32 bits]
39-
PSIZE:
40-
Bits8: [0, 8 bits]
41-
Bits16: [1, 16 bits]
42-
Bits32: [2, 32 bits]
43-
MINC:
44-
Disabled: [0, Disabled]
45-
Enabled: [1, Enabled]
46-
PINC:
47-
Disabled: [0, Disabled]
48-
Enabled: [1, Enabled]
49-
CIRC:
50-
Disabled: [0, Disabled]
51-
Enabled: [1, Enabled]
52-
DIR:
53-
Peripheral: [0, Read from peripheral]
54-
Memory: [1, Read from memory]
55-
TEIE:
56-
Disabled: [0, Disabled]
57-
Enabled: [1, Enabled]
58-
HTIE:
59-
Disabled: [0, Disabled]
60-
Enabled: [1, Enabled]
61-
TCIE:
62-
Disabled: [0, Disabled]
63-
Enabled: [1, Enabled]
64-
EN:
65-
Disabled: [0, Disabled]
66-
Enabled: [1, Enabled]
678

689
CNDTR?:
6910
NDT: [0, 0x3FFFF]
70-
71-
CPAR?:
72-
PA: [0, 0xFFFFFFFF]
73-
74-
CMAR?:
75-
MA: [0, 0xFFFFFFFF]

‎devices/fields/dma/dmamux_v1.yaml

Lines changed: 26 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ C*CR:
1414
SOIE:
1515
Disabled: [0, Synchronization overrun interrupt disabled]
1616
Enabled: [1, Synchronization overrun interrupt enabled]
17-
RG*CR:
17+
RG?CR:
1818
GNBREQ: [0, 31]
1919
GPOL:
2020
NoEdge: [0, "No event, i.e. no detection nor generation"]
@@ -27,3 +27,28 @@ RG*CR:
2727
OIE:
2828
Disabled: [0, Trigger overrun interrupt disabled]
2929
Enabled: [1, Trigger overrun interrupt enabled]
30+
CSR:
31+
SOF*:
32+
NoSyncEvent:
33+
[
34+
0,
35+
"No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ",
36+
]
37+
SyncEvent:
38+
[
39+
1,
40+
"Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ",
41+
]
42+
"CFR,CCFR":
43+
CSOF*:
44+
_W1C:
45+
Clear: [1, Clear synchronization flag]
46+
RGSR:
47+
"OF?":
48+
NoTrigger:
49+
[0, "No new trigger event occured on DMA request generator channel x, before the request counter underrun"]
50+
Trigger: [1, "New trigger event occured on DMA request generator channel x, before the request counter underrun"]
51+
RGCFR:
52+
COF?:
53+
_W1C:
54+
Clear: [1, Clear overrun flag]

‎devices/fields/dma/dmamux_wl.yaml

Lines changed: 0 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -21,21 +21,6 @@ C?CR:
2121
lptim1_out: [18, "Signal `lptim1_out` selected as synchronization input"]
2222
lptim2_out: [19, "Signal `lptim2_out` selected as synchronization input"]
2323
lptim3_out: [20, "Signal `lptim3_out` selected as synchronization input"]
24-
NBREQ: [0, 31]
25-
SPOL:
26-
NoEdge: [0, "No event, i.e. no synchronization nor detection"]
27-
RisingEdge: [1, Rising edge]
28-
FallingEdge: [2, Falling edge]
29-
BothEdges: [3, Rising and falling edges]
30-
SE:
31-
Disabled: [0, Synchronization disabled]
32-
Enabled: [1, Synchronization enabled]
33-
EGE:
34-
Disabled: [0, Event generation disabled]
35-
Enabled: [1, Event generation enabled]
36-
SOIE:
37-
Disabled: [0, Synchronization overrun interrupt disabled]
38-
Enabled: [1, Synchronization overrun interrupt enabled]
3924
DMAREQ_ID:
4025
none: [0, No signal selected as request input]
4126
dmamux1_req_gen0: [1, "Signal `dmamux1_req_gen0` selected as request input"]
@@ -81,18 +66,6 @@ C?CR:
8166
subghzspi_rx: [41, "Signal `subghzspi_rx` selected as request input"]
8267
subghzspi_tx: [42, "Signal `subghzspi_tx` selected as request input"]
8368
RG?CR:
84-
GNBREQ: [0, 31]
85-
GPOL:
86-
NoEdge: [0, "No event, i.e. no detection nor generation"]
87-
RisingEdge: [1, Rising edge]
88-
FallingEdge: [2, Falling edge]
89-
BothEdges: [3, Rising and falling edges]
90-
GE:
91-
Disabled: [0, DMA request generation disabled]
92-
Enabled: [1, DMA request enabled]
93-
OIE:
94-
Disabled: [0, Trigger overrun interrupt disabled]
95-
Enabled: [1, Trigger overrun interrupt enabled]
9669
SIG_ID:
9770
exti0: [0, "Signal `EXTIx` selected as synchronization input"]
9871
exti1: [1, "Signal `EXTIx` selected as synchronization input"]
@@ -115,26 +88,3 @@ RG?CR:
11588
lptim1_out: [18, "Signal `lptim1_out` selected as synchronization input"]
11689
lptim2_out: [19, "Signal `lptim2_out` selected as synchronization input"]
11790
lptim3_out: [20, "Signal `lptim3_out` selected as synchronization input"]
118-
CSR:
119-
SOF*:
120-
NoSyncEvent:
121-
[
122-
0,
123-
"No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ",
124-
]
125-
SyncEvent:
126-
[
127-
1,
128-
"Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ",
129-
]
130-
"CFR,CCFR":
131-
CSOF*:
132-
Clear: [1, Clear synchronization flag]
133-
RGSR:
134-
"OF[0123]":
135-
NoTrigger:
136-
[0, "No new trigger event occured on DMA request generator channel x, before the request counter underrun"]
137-
Trigger: [1, "New trigger event occured on DMA request generator channel x, before the request counter underrun"]
138-
RGCFR:
139-
"COF[0123]":
140-
Clear: [1, Clear overrun flag]

‎devices/fields/dma/v1.yaml

Lines changed: 4 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -1,58 +1,5 @@
1-
ISR:
2-
TEIF*:
3-
NoError: [0, No transfer error]
4-
Error: [1, A transfer error has occured]
5-
HTIF*:
6-
NotHalf: [0, No half transfer event]
7-
Half: [1, A half transfer event has occured]
8-
TCIF*:
9-
NotComplete: [0, No transfer complete event]
10-
Complete: [1, A transfer complete event has occured]
11-
GIF*:
12-
NoEvent: [0, "No transfer error, half event, complete event"]
13-
Event: [1, "A transfer error, half event or complete event has occured"]
14-
IFCR:
15-
CTEIF*:
16-
Clear: [1, Clears the TEIF flag in the ISR register]
17-
CHTIF*:
18-
Clear: [1, Clears the HTIF flag in the ISR register]
19-
CTCIF*:
20-
Clear: [1, Clears the TCIF flag in the ISR register]
21-
CGIF*:
22-
Clear: [1, "Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register"]
23-
CCR*:
24-
MEM2MEM:
25-
Disabled: [0, Memory to memory mode disabled]
26-
Enabled: [1, Memory to memory mode enabled]
27-
PL:
28-
Low: [0, Low priority]
29-
Medium: [1, Medium priority]
30-
High: [2, High priority]
31-
VeryHigh: [3, Very high priority]
32-
"[MP]SIZE":
33-
Bits8: [0, 8-bit size] # or Byte
34-
Bits16: [1, 16-bit size] # or HalfWord
35-
Bits32: [2, 32-bit size] # or Word
36-
"[MP]INC":
37-
Disabled: [0, Increment mode disabled]
38-
Enabled: [1, Increment mode enabled]
39-
CIRC:
40-
Disabled: [0, Circular buffer disabled]
41-
Enabled: [1, Circular buffer enabled]
42-
DIR:
43-
FromPeripheral: [0, Read from peripheral]
44-
FromMemory: [1, Read from memory]
45-
TEIE:
46-
Disabled: [0, Transfer Error interrupt disabled]
47-
Enabled: [1, Transfer Error interrupt enabled]
48-
HTIE:
49-
Disabled: [0, Half Transfer interrupt disabled]
50-
Enabled: [1, Half Transfer interrupt enabled]
51-
TCIE:
52-
Disabled: [0, Transfer Complete interrupt disabled]
53-
Enabled: [1, Transfer Complete interrupt enabled]
54-
EN:
55-
Disabled: [0, Channel disabled]
56-
Enabled: [1, Channel enabled]
1+
_include:
2+
- common.yaml
3+
574
CNDTR*:
58-
NDT: [0, 65535]
5+
NDT: [0, 0xFFFF]

‎devices/patches/dma/dmamux_add_csr06.yaml

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
_add:
2+
CSR:
3+
displayName: CSR
4+
description: DMAMUX request line multiplexer interrupt channel status register
5+
addressOffset: 128
6+
size: 32
7+
access: read-only
8+
resetValue: 0
9+
resetMask: 4294967295
10+
fields:
11+
SOF:
12+
description: Synchronization Overrun Flag
13+
bitOffset: 0
14+
bitWidth: 7
15+
access: read-only
16+
CFR:
17+
displayName: CFR
18+
description: DMAMUX request line multiplexer interrupt clear flag register
19+
addressOffset: 132
20+
size: 32
21+
access: write-only
22+
resetValue: 0
23+
resetMask: 4294967295
24+
fields:
25+
CSOF:
26+
description: Synchronization Clear Overrun Flag
27+
bitOffset: 0
28+
bitWidth: 7
29+
access: write-only

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