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‎devices/fields/crs/crs.yaml

Lines changed: 49 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -1,53 +1,52 @@
1-
CRS:
2-
CR:
3-
TRIM: [0, 0x3F]
4-
SWSYNC:
5-
Sync: [1, A software sync is generated]
6-
AUTOTRIMEN:
7-
Disabled: [0, Automatic trimming disabled]
8-
Enabled: [1, Automatic trimming enabled]
9-
CEN:
10-
Disabled: [0, Frequency error counter disabled]
11-
Enabled: [1, Frequency error counter enabled]
12-
"*IE":
13-
Disabled: [0, Interrupt disabled]
14-
Enabled: [1, Interrupt enabled]
1+
CR:
2+
TRIM: [0, 0x3F]
3+
SWSYNC:
4+
Sync: [1, A software sync is generated]
5+
AUTOTRIMEN:
6+
Disabled: [0, Automatic trimming disabled]
7+
Enabled: [1, Automatic trimming enabled]
8+
CEN:
9+
Disabled: [0, Frequency error counter disabled]
10+
Enabled: [1, Frequency error counter enabled]
11+
"*IE":
12+
Disabled: [0, Interrupt disabled]
13+
Enabled: [1, Interrupt enabled]
1514

16-
CFGR:
17-
SYNCPOL:
18-
RisingEdge: [0, SYNC active on rising edge]
19-
FallingEdge: [1, SYNC active on falling edge]
20-
SYNCSRC:
21-
GPIO_AF: [0, GPIO AF (crs_sync_in_1) selected as SYNC signal source]
22-
LSE: [1, LSE (crs_sync_in_2) selected as SYNC signal source]
23-
USB_SOF: [2, USB SOF (crs_sync_in_3) selected as SYNC signal source]
24-
SYNCDIV:
25-
NotDivided: [0, SYNC not divided]
26-
DivideBy2: [1, SYNC divided by 2]
27-
DivideBy4: [2, SYNC divided by 4]
28-
DivideBy8: [3, SYNC divided by 8]
29-
DivideBy16: [4, SYNC divided by 16]
30-
DivideBy32: [5, SYNC divided by 32]
31-
DivideBy64: [6, SYNC divided by 64]
32-
DivideBy128: [7, SYNC divided by 128]
33-
FELIM: [0, 0xFF]
34-
RELOAD: [0, 0xFFFF]
15+
CFGR:
16+
SYNCPOL:
17+
RisingEdge: [0, SYNC active on rising edge]
18+
FallingEdge: [1, SYNC active on falling edge]
19+
SYNCSRC:
20+
GPIO_AF: [0, GPIO AF (crs_sync_in_1) selected as SYNC signal source]
21+
LSE: [1, LSE (crs_sync_in_2) selected as SYNC signal source]
22+
USB_SOF: [2, USB SOF (crs_sync_in_3) selected as SYNC signal source]
23+
SYNCDIV:
24+
NotDivided: [0, SYNC not divided]
25+
DivideBy2: [1, SYNC divided by 2]
26+
DivideBy4: [2, SYNC divided by 4]
27+
DivideBy8: [3, SYNC divided by 8]
28+
DivideBy16: [4, SYNC divided by 16]
29+
DivideBy32: [5, SYNC divided by 32]
30+
DivideBy64: [6, SYNC divided by 64]
31+
DivideBy128: [7, SYNC divided by 128]
32+
FELIM: [0, 0xFF]
33+
RELOAD: [0, 0xFFFF]
3534

36-
ISR:
37-
FECAP: [0, 0xFFFF]
38-
FEDIR:
39-
UpCounting: [0, Error in up-counting direction]
40-
DownCounting: [1, Error in down-counting direction]
41-
SYNCMISS:
42-
NotSignaled: [0, Signal not set]
43-
Signaled: [1, Signal set]
44-
SYNCERR:
45-
NotSignaled: [0, Signal not set]
46-
Signaled: [1, Signal set]
47-
"*F":
48-
NotSignaled: [0, Signal not set]
49-
Signaled: [1, Signal set]
35+
ISR:
36+
FECAP: [0, 0xFFFF]
37+
FEDIR:
38+
UpCounting: [0, Error in up-counting direction]
39+
DownCounting: [1, Error in down-counting direction]
40+
SYNCMISS:
41+
NotSignaled: [0, Signal not set]
42+
Signaled: [1, Signal set]
43+
SYNCERR:
44+
NotSignaled: [0, Signal not set]
45+
Signaled: [1, Signal set]
46+
"*F":
47+
NotSignaled: [0, Signal not set]
48+
Signaled: [1, Signal set]
5049

51-
ICR:
52-
"*C":
53-
Clear: [1, Clear flag]
50+
ICR:
51+
"*C":
52+
Clear: [1, Clear flag]

‎devices/fields/sbs/sbs.yaml

Lines changed: 81 additions & 82 deletions
Original file line numberDiff line numberDiff line change
@@ -1,97 +1,96 @@
11
# System configuration, boot, and security (SBS). Applicable to H5 family, at least.
22

3-
SBS:
4-
HDPLCR:
5-
INCR_HDPL:
6-
Increment: [0x6A, Increment HDPL value]
3+
HDPLCR:
4+
INCR_HDPL:
5+
Increment: [0x6A, Increment HDPL value]
76

8-
HDPLSR:
9-
HDPL:
10-
_read:
11-
HDPL0: [0xB4, Protection level reserved for ST code and data]
12-
HDPL1: [0x51, Protection level to be used to execute and protect immutable Root of Trust (IROT) stage]
13-
HDPL2: [0x8A, Protection level to be used to execute and protect an updatable Root of Trust (UROT) stage]
14-
HDPL3: [0x6F, Protection level to be used to execute the application]
15-
16-
DBGCR:
17-
DBG_AUTH_HDPL:
7+
HDPLSR:
8+
HDPL:
9+
_read:
10+
HDPL0: [0xB4, Protection level reserved for ST code and data]
1811
HDPL1: [0x51, Protection level to be used to execute and protect immutable Root of Trust (IROT) stage]
1912
HDPL2: [0x8A, Protection level to be used to execute and protect an updatable Root of Trust (UROT) stage]
2013
HDPL3: [0x6F, Protection level to be used to execute the application]
21-
DBG_UNLOCK:
22-
Unlocked: [0xB4, "Debug unlocked when HDPLSR:HDPL is equal to DBG_AUTH_HDPL"]
23-
AP_UNLOCK:
24-
Unlocked: [0xB4, Device access port unlocked]
2514

26-
DBGLOCKR:
27-
DBGCFG_LOCK:
28-
_write:
29-
Locked: [0xC3, Debug configuration register (DBGCR) locked]
30-
Unlocked: [0xB4, Debug configuration register (DBGCR) unlocked]
31-
_read:
32-
Locked: [0x6A, Debug configuration register (DBGCR) locked]
33-
Unlocked: [0xB4, Debug configuration register (DBGCR) unlocked]
15+
DBGCR:
16+
DBG_AUTH_HDPL:
17+
HDPL1: [0x51, Protection level to be used to execute and protect immutable Root of Trust (IROT) stage]
18+
HDPL2: [0x8A, Protection level to be used to execute and protect an updatable Root of Trust (UROT) stage]
19+
HDPL3: [0x6F, Protection level to be used to execute the application]
20+
DBG_UNLOCK:
21+
Unlocked: [0xB4, "Debug unlocked when HDPLSR:HDPL is equal to DBG_AUTH_HDPL"]
22+
AP_UNLOCK:
23+
Unlocked: [0xB4, Device access port unlocked]
24+
25+
DBGLOCKR:
26+
DBGCFG_LOCK:
27+
_write:
28+
Locked: [0xC3, Debug configuration register (DBGCR) locked]
29+
Unlocked: [0xB4, Debug configuration register (DBGCR) unlocked]
30+
_read:
31+
Locked: [0x6A, Debug configuration register (DBGCR) locked]
32+
Unlocked: [0xB4, Debug configuration register (DBGCR) unlocked]
3433

35-
PMCR:
36-
PB8_FMP:
37-
Disabled: [0, Fast-mode Plus mode on PB8 disabled]
38-
Enabled: [1, Fast-mode Plus mode on PB8 enabled]
39-
PB7_FMP:
40-
Disabled: [0, Fast-mode Plus mode on PB7 disabled]
41-
Enabled: [1, Fast-mode Plus mode on PB7 enabled]
42-
PB6_FMP:
43-
Disabled: [0, Fast-mode Plus mode on PB6 disabled]
44-
Enabled: [1, Fast-mode Plus mode on PB6 enabled]
34+
PMCR:
35+
PB8_FMP:
36+
Disabled: [0, Fast-mode Plus mode on PB8 disabled]
37+
Enabled: [1, Fast-mode Plus mode on PB8 enabled]
38+
PB7_FMP:
39+
Disabled: [0, Fast-mode Plus mode on PB7 disabled]
40+
Enabled: [1, Fast-mode Plus mode on PB7 enabled]
41+
PB6_FMP:
42+
Disabled: [0, Fast-mode Plus mode on PB6 disabled]
43+
Enabled: [1, Fast-mode Plus mode on PB6 enabled]
4544

46-
FPUIMR:
47-
FPU_IE?:
48-
Disabled: [0, Interrupt disabled]
49-
Enabled: [1, Interrupt enabled]
45+
FPUIMR:
46+
FPU_IE?:
47+
Disabled: [0, Interrupt disabled]
48+
Enabled: [1, Interrupt enabled]
5049

51-
MESR:
52-
IPMEE:
53-
_read:
54-
EraseInProgress: [0, ICACHE erase ongoing]
55-
EraseCompleted: [1, ICACHE erase completed]
56-
_W1C:
57-
Clear: [1, Clear ICACHE erase status flag]
58-
MCLR:
59-
_read:
60-
EraseInProgress: [0, Memory erase in progress]
61-
EraseComplete: [1, Memory erase complete]
62-
_W1C:
63-
Clear: [1, Clear memory erase status flag]
50+
MESR:
51+
IPMEE:
52+
_read:
53+
EraseInProgress: [0, ICACHE erase ongoing]
54+
EraseCompleted: [1, ICACHE erase completed]
55+
_W1C:
56+
Clear: [1, Clear ICACHE erase status flag]
57+
MCLR:
58+
_read:
59+
EraseInProgress: [0, Memory erase in progress]
60+
EraseComplete: [1, Memory erase complete]
61+
_W1C:
62+
Clear: [1, Clear memory erase status flag]
6463

65-
CCCSR:
66-
RDY?:
67-
_read:
68-
NotReady: [0, VDDIO compensation cell not ready]
69-
Ready: [1, VDDIO compensation cell ready]
70-
CS?:
71-
Cell: [0, Code from cell selected]
72-
CCSWCR: [1, Code from CCSWCR selected]
73-
EN?:
74-
Disabled: [0, I/O compensation cell disabled]
75-
Enabled: [1, I/O compensation cell enabled]
64+
CCCSR:
65+
RDY?:
66+
_read:
67+
NotReady: [0, VDDIO compensation cell not ready]
68+
Ready: [1, VDDIO compensation cell ready]
69+
CS?:
70+
Cell: [0, Code from cell selected]
71+
CCSWCR: [1, Code from CCSWCR selected]
72+
EN?:
73+
Disabled: [0, I/O compensation cell disabled]
74+
Enabled: [1, I/O compensation cell enabled]
7675

77-
CCSWCR:
78-
SW_APSRC?: [0, 0xF]
79-
SW_ANSRC?: [0, 0xF]
76+
CCSWCR:
77+
SW_APSRC?: [0, 0xF]
78+
SW_ANSRC?: [0, 0xF]
8079

81-
CFGR2:
82-
"*L":
83-
Disconnected: [0, Flag/Interrupt disconnected from timer break inputs]
84-
Connected: [1, Flag/Interrupt connected to timer break inputs]
80+
CFGR2:
81+
"*L":
82+
Disconnected: [0, Flag/Interrupt disconnected from timer break inputs]
83+
Connected: [1, Flag/Interrupt connected to timer break inputs]
8584

86-
CNSLCKR:
87-
LOCKNSMPU:
88-
Unlocked: [0, MPU registers write enabled]
89-
Locked: [1, MPU registers write disabled]
90-
LOCKNSVTOR:
91-
Unlocked: [0, VTOR_NS register write enabled]
92-
Locked: [1, VTOR_NS register write disabled]
85+
CNSLCKR:
86+
LOCKNSMPU:
87+
Unlocked: [0, MPU registers write enabled]
88+
Locked: [1, MPU registers write disabled]
89+
LOCKNSVTOR:
90+
Unlocked: [0, VTOR_NS register write enabled]
91+
Locked: [1, VTOR_NS register write disabled]
9392

94-
ECCNMIR:
95-
ECCNMI_MASK_EN:
96-
Enabled: [0, NMI enabled]
97-
Disabled: [1, NMI disabled]
93+
ECCNMIR:
94+
ECCNMI_MASK_EN:
95+
Enabled: [0, NMI enabled]
96+
Disabled: [1, NMI disabled]

‎devices/patches/exti/exti4_5.yaml

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
_modify:
2+
_interrupts:
3+
EXTI4_5:
4+
name: EXTI4_15
5+
description: EXTI line 4 to 15 interrupt

‎devices/patches/h5.yaml

Lines changed: 0 additions & 100 deletions
This file was deleted.

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