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variants: add support for F446ZXX and nucleo F446ZE
1 parent 01e4f0c commit 2413a74

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‎README.md

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Original file line numberDiff line numberDiff line change
@@ -91,6 +91,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
9191
| :green_heart: | STM32F412ZG | [Nucleo F412ZG](http://www.st.com/en/evaluation-tools/nucleo-f412zg.html) | *2.6.0* | |
9292
| :green_heart: | STM32F413ZH | [Nucleo F413ZH](http://www.st.com/en/evaluation-tools/nucleo-f413zh.html) | *2.4.0* | |
9393
| :green_heart: | STM32F429ZI | [Nucleo F429ZI](http://www.st.com/en/evaluation-tools/nucleo-f429zi.html) | *0.1.0* | |
94+
| :yellow_heart: | STM32F446ZE | [Nucleo F446ZE](http://www.st.com/en/evaluation-tools/nucleo-f446ze.html) | *2.7.0* | |
9495
| :green_heart: | STM32F722ZE | [Nucleo F722ZE](http://www.st.com/en/evaluation-tools/nucleo-f722ze.html) | *2.4.0* | |
9596
| :green_heart: | STM32F767ZI | [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) | *1.4.0* | |
9697
| :green_heart: | STM32F746ZG | [Nucleo F746ZG](https://www.st.com/en/evaluation-tools/nucleo-f746zg.html) | *1.9.0* | |
@@ -368,6 +369,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
368369
| :green_heart: | STM32F437ZG<br>STM32F437ZI | Generic Board | **2.0.0** |
369370
| :green_heart: | STM32F439ZG<br>STM32F439ZI | Generic Board | **2.0.0** |
370371
| :green_heart: | STM32F446RC<br>STM32F446RE | Generic Board | *1.9.0* | |
372+
| :yellow_heart: | STM32F446ZC<br>STM32F446ZE | Generic Board | *2.6.0* | |
371373
| :green_heart: | STM32F446VC<br>STM32F446VE | Generic Board | **2.0.0** |
372374
| :green_heart: | STM32F411CE | [ThunderPack v1.1+](https://github.com/jgillick/ThunderPack) | *1.9.0* | |
373375

‎boards.txt

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Original file line numberDiff line numberDiff line change
@@ -76,6 +76,20 @@ Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.series=STM32F4xx
7676
Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.product_line=STM32F429xx
7777
Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.variant=STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)
7878

79+
# NUCLEO_F446RE board
80+
Nucleo_144.menu.pnum.NUCLEO_F446ZE=Nucleo F446ZE
81+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.node=NODE_F446ZE
82+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.upload.maximum_size=524288
83+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.upload.maximum_data_size=131072
84+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.mcu=cortex-m4
85+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.fpu=-mfpu=fpv4-sp-d16
86+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.float-abi=-mfloat-abi=hard
87+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.board=NUCLEO_F446ZE
88+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.series=STM32F4xx
89+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.product_line=STM32F446xx
90+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
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Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.variant_h=variant_NUCLEO_F446ZE.h
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7993
# NUCLEO_F722ZE board
8094
Nucleo_144.menu.pnum.NUCLEO_F722ZE=Nucleo F722ZE
8195
Nucleo_144.menu.pnum.NUCLEO_F722ZE.node=NODE_F722ZE
@@ -4451,6 +4465,54 @@ GenF4.menu.pnum.GENERIC_F446VETX.build.board=GENERIC_F446VETX
44514465
GenF4.menu.pnum.GENERIC_F446VETX.build.product_line=STM32F446xx
44524466
GenF4.menu.pnum.GENERIC_F446VETX.build.variant=STM32F4xx/F446V(C-E)T
44534467

4468+
# Generic F446ZCHx
4469+
GenF4.menu.pnum.GENERIC_F446ZCHX=Generic F446ZEHx
4470+
GenF4.menu.pnum.GENERIC_F446ZCHX.upload.maximum_size=262144
4471+
GenF4.menu.pnum.GENERIC_F446ZCHX.upload.maximum_data_size=131072
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GenF4.menu.pnum.GENERIC_F446ZCHX.build.board=GENERIC_F446ZEHX
4473+
GenF4.menu.pnum.GENERIC_F446ZCHX.build.product_line=STM32F446xx
4474+
GenF4.menu.pnum.GENERIC_F446ZCHX.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
4475+
4476+
# Generic F446ZCJx
4477+
GenF4.menu.pnum.GENERIC_F446ZCJX=Generic F446ZEJx
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GenF4.menu.pnum.GENERIC_F446ZCJX.upload.maximum_size=262144
4479+
GenF4.menu.pnum.GENERIC_F446ZCJX.upload.maximum_data_size=131072
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GenF4.menu.pnum.GENERIC_F446ZCJX.build.board=GENERIC_F446ZEJX
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GenF4.menu.pnum.GENERIC_F446ZCJX.build.product_line=STM32F446xx
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GenF4.menu.pnum.GENERIC_F446ZCJX.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
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4484+
# Generic F446ZCTx
4485+
GenF4.menu.pnum.GENERIC_F446ZCTX=Generic F446ZETx
4486+
GenF4.menu.pnum.GENERIC_F446ZCTX.upload.maximum_size=262144
4487+
GenF4.menu.pnum.GENERIC_F446ZCTX.upload.maximum_data_size=131072
4488+
GenF4.menu.pnum.GENERIC_F446ZCTX.build.board=GENERIC_F446ZETX
4489+
GenF4.menu.pnum.GENERIC_F446ZCTX.build.product_line=STM32F446xx
4490+
GenF4.menu.pnum.GENERIC_F446ZCTX.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
4491+
4492+
# Generic F446ZEHx
4493+
GenF4.menu.pnum.GENERIC_F446ZEHX=Generic F446ZEHx
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GenF4.menu.pnum.GENERIC_F446ZEHX.upload.maximum_size=524288
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GenF4.menu.pnum.GENERIC_F446ZEHX.upload.maximum_data_size=131072
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GenF4.menu.pnum.GENERIC_F446ZEHX.build.board=GENERIC_F446ZEHX
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GenF4.menu.pnum.GENERIC_F446ZEHX.build.product_line=STM32F446xx
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GenF4.menu.pnum.GENERIC_F446ZEHX.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
4499+
4500+
# Generic F446ZEJx
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GenF4.menu.pnum.GENERIC_F446ZEJX=Generic F446ZEJx
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GenF4.menu.pnum.GENERIC_F446ZEJX.upload.maximum_size=524288
4503+
GenF4.menu.pnum.GENERIC_F446ZEJX.upload.maximum_data_size=131072
4504+
GenF4.menu.pnum.GENERIC_F446ZEJX.build.board=GENERIC_F446ZEJX
4505+
GenF4.menu.pnum.GENERIC_F446ZEJX.build.product_line=STM32F446xx
4506+
GenF4.menu.pnum.GENERIC_F446ZEJX.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
4507+
4508+
# Generic F446ZETx
4509+
GenF4.menu.pnum.GENERIC_F446ZETX=Generic F446ZETx
4510+
GenF4.menu.pnum.GENERIC_F446ZETX.upload.maximum_size=524288
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GenF4.menu.pnum.GENERIC_F446ZETX.upload.maximum_data_size=131072
4512+
GenF4.menu.pnum.GENERIC_F446ZETX.build.board=GENERIC_F446ZETX
4513+
GenF4.menu.pnum.GENERIC_F446ZETX.build.product_line=STM32F446xx
4514+
GenF4.menu.pnum.GENERIC_F446ZETX.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
4515+
44544516
# Upload menu
44554517
GenF4.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD)
44564518
GenF4.menu.upload_method.swdMethod.upload.protocol=0

‎variants/STM32F4xx/F446Z(C-E)(H-J-T)/generic_clock.c

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Original file line numberDiff line numberDiff line change
@@ -22,8 +22,58 @@
2222
*/
2323
WEAK void SystemClock_Config(void)
2424
{
25-
/* SystemClock_Config can be generated by STM32CubeMX */
26-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
25+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
26+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
27+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
28+
29+
/** Configure the main internal regulator output voltage
30+
*/
31+
__HAL_RCC_PWR_CLK_ENABLE();
32+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
33+
/** Initializes the RCC Oscillators according to the specified parameters
34+
* in the RCC_OscInitTypeDef structure.
35+
*/
36+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
37+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
38+
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
39+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
40+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
41+
RCC_OscInitStruct.PLL.PLLM = 8;
42+
RCC_OscInitStruct.PLL.PLLN = 180;
43+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
44+
RCC_OscInitStruct.PLL.PLLQ = 8;
45+
RCC_OscInitStruct.PLL.PLLR = 2;
46+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
47+
Error_Handler();
48+
}
49+
/** Activate the Over-Drive mode
50+
*/
51+
if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
52+
Error_Handler();
53+
}
54+
/** Initializes the CPU, AHB and APB buses clocks
55+
*/
56+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
57+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
58+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLRCLK;
59+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
60+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
61+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
62+
63+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
64+
Error_Handler();
65+
}
66+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_CLK48;
67+
PeriphClkInitStruct.PLLSAI.PLLSAIM = 16;
68+
PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
69+
PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2;
70+
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;
71+
PeriphClkInitStruct.PLLSAIDivQ = 1;
72+
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
73+
PeriphClkInitStruct.SdioClockSelection = RCC_SDIOCLKSOURCE_CLK48;
74+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
75+
Error_Handler();
76+
}
2777
}
2878

2979
#endif /* ARDUINO_GENERIC_* */

‎variants/STM32F4xx/F446Z(C-E)(H-J-T)/ldscript.ld

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@@ -0,0 +1,185 @@
1+
/*
2+
******************************************************************************
3+
**
4+
** @file : LinkerScript.ld
5+
**
6+
** @author : Auto-generated by STM32CubeIDE
7+
**
8+
** @brief : Linker script for STM32F446ZETx Device from STM32F4 series
9+
** 512Kbytes FLASH
10+
** 128Kbytes RAM
11+
**
12+
** Set heap size, stack size and stack location according
13+
** to application requirements.
14+
**
15+
** Set memory bank area and size if external memory is used
16+
**
17+
** Target : STMicroelectronics STM32
18+
**
19+
** Distribution: The file is distributed as is, without any warranty
20+
** of any kind.
21+
**
22+
******************************************************************************
23+
** @attention
24+
**
25+
** Copyright (c) 2023 STMicroelectronics.
26+
** All rights reserved.
27+
**
28+
** This software is licensed under terms that can be found in the LICENSE file
29+
** in the root directory of this software component.
30+
** If no LICENSE file comes with this software, it is provided AS-IS.
31+
**
32+
******************************************************************************
33+
*/
34+
35+
/* Entry Point */
36+
ENTRY(Reset_Handler)
37+
38+
/* Highest address of the user mode stack */
39+
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
40+
41+
_Min_Heap_Size = 0x200; /* required amount of heap */
42+
_Min_Stack_Size = 0x400; /* required amount of stack */
43+
44+
/* Memories definition */
45+
MEMORY
46+
{
47+
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
48+
FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
49+
}
50+
51+
/* Sections */
52+
SECTIONS
53+
{
54+
/* The startup code into "FLASH" Rom type memory */
55+
.isr_vector :
56+
{
57+
. = ALIGN(4);
58+
KEEP(*(.isr_vector)) /* Startup code */
59+
. = ALIGN(4);
60+
} >FLASH
61+
62+
/* The program code and other data into "FLASH" Rom type memory */
63+
.text :
64+
{
65+
. = ALIGN(4);
66+
*(.text) /* .text sections (code) */
67+
*(.text*) /* .text* sections (code) */
68+
*(.glue_7) /* glue arm to thumb code */
69+
*(.glue_7t) /* glue thumb to arm code */
70+
*(.eh_frame)
71+
72+
KEEP (*(.init))
73+
KEEP (*(.fini))
74+
75+
. = ALIGN(4);
76+
_etext = .; /* define a global symbols at end of code */
77+
} >FLASH
78+
79+
/* Constant data into "FLASH" Rom type memory */
80+
.rodata :
81+
{
82+
. = ALIGN(4);
83+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
84+
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
85+
. = ALIGN(4);
86+
} >FLASH
87+
88+
.ARM.extab : {
89+
. = ALIGN(4);
90+
*(.ARM.extab* .gnu.linkonce.armextab.*)
91+
. = ALIGN(4);
92+
} >FLASH
93+
94+
.ARM : {
95+
. = ALIGN(4);
96+
__exidx_start = .;
97+
*(.ARM.exidx*)
98+
__exidx_end = .;
99+
. = ALIGN(4);
100+
} >FLASH
101+
102+
.preinit_array :
103+
{
104+
. = ALIGN(4);
105+
PROVIDE_HIDDEN (__preinit_array_start = .);
106+
KEEP (*(.preinit_array*))
107+
PROVIDE_HIDDEN (__preinit_array_end = .);
108+
. = ALIGN(4);
109+
} >FLASH
110+
111+
.init_array :
112+
{
113+
. = ALIGN(4);
114+
PROVIDE_HIDDEN (__init_array_start = .);
115+
KEEP (*(SORT(.init_array.*)))
116+
KEEP (*(.init_array*))
117+
PROVIDE_HIDDEN (__init_array_end = .);
118+
. = ALIGN(4);
119+
} >FLASH
120+
121+
.fini_array :
122+
{
123+
. = ALIGN(4);
124+
PROVIDE_HIDDEN (__fini_array_start = .);
125+
KEEP (*(SORT(.fini_array.*)))
126+
KEEP (*(.fini_array*))
127+
PROVIDE_HIDDEN (__fini_array_end = .);
128+
. = ALIGN(4);
129+
} >FLASH
130+
131+
/* Used by the startup to initialize data */
132+
_sidata = LOADADDR(.data);
133+
134+
/* Initialized data sections into "RAM" Ram type memory */
135+
.data :
136+
{
137+
. = ALIGN(4);
138+
_sdata = .; /* create a global symbol at data start */
139+
*(.data) /* .data sections */
140+
*(.data*) /* .data* sections */
141+
*(.RamFunc) /* .RamFunc sections */
142+
*(.RamFunc*) /* .RamFunc* sections */
143+
144+
. = ALIGN(4);
145+
_edata = .; /* define a global symbol at data end */
146+
147+
} >RAM AT> FLASH
148+
149+
/* Uninitialized data section into "RAM" Ram type memory */
150+
. = ALIGN(4);
151+
.bss :
152+
{
153+
/* This is used by the startup in order to initialize the .bss section */
154+
_sbss = .; /* define a global symbol at bss start */
155+
__bss_start__ = _sbss;
156+
*(.bss)
157+
*(.bss*)
158+
*(COMMON)
159+
160+
. = ALIGN(4);
161+
_ebss = .; /* define a global symbol at bss end */
162+
__bss_end__ = _ebss;
163+
} >RAM
164+
165+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
166+
._user_heap_stack :
167+
{
168+
. = ALIGN(8);
169+
PROVIDE ( end = . );
170+
PROVIDE ( _end = . );
171+
. = . + _Min_Heap_Size;
172+
. = . + _Min_Stack_Size;
173+
. = ALIGN(8);
174+
} >RAM
175+
176+
/* Remove information from the compiler libraries */
177+
/DISCARD/ :
178+
{
179+
libc.a ( * )
180+
libm.a ( * )
181+
libgcc.a ( * )
182+
}
183+
184+
.ARM.attributes 0 : { *(.ARM.attributes) }
185+
}

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