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12 | 12 | ****************************************************************************** |
13 | 13 | * @attention |
14 | 14 | * |
15 | | - * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
16 | | - * All rights reserved.</center></h2> |
| 15 | + * Copyright (c) 2016 STMicroelectronics. |
| 16 | + * All rights reserved. |
17 | 17 | * |
18 | | - * This software component is licensed by ST under BSD 3-Clause license, |
19 | | - * the "License"; You may not use this file except in compliance with the |
20 | | - * License. You may obtain a copy of the License at: |
21 | | - * opensource.org/licenses/BSD-3-Clause |
| 18 | + * This software is licensed under terms that can be found in the LICENSE file |
| 19 | + * in the root directory of this software component. |
| 20 | + * If no LICENSE file comes with this software, it is provided AS-IS. |
22 | 21 | * |
23 | 22 | ****************************************************************************** |
24 | 23 | */ |
@@ -571,6 +570,10 @@ typedef struct |
571 | 570 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
572 | 571 | } WWDG_TypeDef; |
573 | 572 |
|
| 573 | +/** |
| 574 | + * @} |
| 575 | + */ |
| 576 | + |
574 | 577 | /** @addtogroup Peripheral_memory_map |
575 | 578 | * @{ |
576 | 579 | */ |
@@ -746,7 +749,7 @@ typedef struct |
746 | 749 | #define ADC5_V1_1 /*!< ADC IP version */ |
747 | 750 |
|
748 | 751 | /* |
749 | | - * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie) |
| 752 | + * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) |
750 | 753 | */ |
751 | 754 | /* Note: No specific macro feature on this device */ |
752 | 755 |
|
@@ -883,7 +886,7 @@ typedef struct |
883 | 886 |
|
884 | 887 | #define ADC_CFGR_ALIGN_Pos (5U) |
885 | 888 | #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ |
886 | | -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ |
| 889 | +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ |
887 | 890 |
|
888 | 891 | #define ADC_CFGR_EXTSEL_Pos (6U) |
889 | 892 | #define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ |
@@ -2241,7 +2244,7 @@ typedef struct |
2241 | 2244 | #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */ |
2242 | 2245 | #define OPAMP2_CSR_OUTCAL_Pos (30U) |
2243 | 2246 | #define OPAMP2_CSR_OUTCAL_Msk (0x1UL << OPAMP2_CSR_OUTCAL_Pos) /*!< 0x40000000 */ |
2244 | | -#define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ |
| 2247 | +#define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ |
2245 | 2248 | #define OPAMP2_CSR_LOCK_Pos (31U) |
2246 | 2249 | #define OPAMP2_CSR_LOCK_Msk (0x1UL << OPAMP2_CSR_LOCK_Pos) /*!< 0x80000000 */ |
2247 | 2250 | #define OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk /*!< OPAMP lock */ |
@@ -2303,7 +2306,7 @@ typedef struct |
2303 | 2306 | #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */ |
2304 | 2307 | #define OPAMP_CSR_OUTCAL_Pos (30U) |
2305 | 2308 | #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ |
2306 | | -#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ |
| 2309 | +#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ |
2307 | 2310 | #define OPAMP_CSR_LOCK_Pos (31U) |
2308 | 2311 | #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ |
2309 | 2312 | #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP lock */ |
@@ -2356,7 +2359,7 @@ typedef struct |
2356 | 2359 | /******************************************************************************/ |
2357 | 2360 |
|
2358 | 2361 | /* |
2359 | | - * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie) |
| 2362 | + * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) |
2360 | 2363 | */ |
2361 | 2364 | /* Note: No specific macro feature on this device */ |
2362 | 2365 |
|
@@ -5348,7 +5351,7 @@ typedef struct |
5348 | 5351 | /* */ |
5349 | 5352 | /******************************************************************************/ |
5350 | 5353 | /* |
5351 | | -* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie) |
| 5354 | +* @brief Specific device feature definitions (not present on all devices in the STM32F3 series) |
5352 | 5355 | */ |
5353 | 5356 | #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ |
5354 | 5357 | #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ |
@@ -6030,7 +6033,7 @@ typedef struct |
6030 | 6033 | /******************************************************************************/ |
6031 | 6034 |
|
6032 | 6035 | /* |
6033 | | - * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie) |
| 6036 | + * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) |
6034 | 6037 | */ |
6035 | 6038 | #define SPI_I2S_SUPPORT /*!< I2S support */ |
6036 | 6039 | #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */ |
@@ -7138,11 +7141,11 @@ typedef struct |
7138 | 7141 | #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ |
7139 | 7142 |
|
7140 | 7143 | /******************* Bit definition for TIM16_OR register *********************/ |
7141 | | -#define TIM16_OR_TI1_RMP_Pos (6U) |
7142 | | -#define TIM16_OR_TI1_RMP_Msk (0x3UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x000000C0 */ |
| 7144 | +#define TIM16_OR_TI1_RMP_Pos (0U) |
| 7145 | +#define TIM16_OR_TI1_RMP_Msk (0x3UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000003 */ |
7143 | 7146 | #define TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */ |
7144 | | -#define TIM16_OR_TI1_RMP_0 (0x1UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000040 */ |
7145 | | -#define TIM16_OR_TI1_RMP_1 (0x2UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000080 */ |
| 7147 | +#define TIM16_OR_TI1_RMP_0 (0x1UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000001 */ |
| 7148 | +#define TIM16_OR_TI1_RMP_1 (0x2UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000002 */ |
7146 | 7149 |
|
7147 | 7150 | /******************* Bit definition for TIM1_OR register *********************/ |
7148 | 7151 | #define TIM1_OR_ETR_RMP_Pos (0U) |
@@ -7740,7 +7743,7 @@ typedef struct |
7740 | 7743 | /******************************************************************************/ |
7741 | 7744 |
|
7742 | 7745 | /* |
7743 | | -* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie) |
| 7746 | +* @brief Specific device feature definitions (not present on all devices in the STM32F3 series) |
7744 | 7747 | */ |
7745 | 7748 |
|
7746 | 7749 | /* Support of 7 bits data length feature */ |
@@ -8612,8 +8615,6 @@ typedef struct |
8612 | 8615 | * @} |
8613 | 8616 | */ |
8614 | 8617 |
|
8615 | | - /** |
| 8618 | +/** |
8616 | 8619 | * @} |
8617 | 8620 | */ |
8618 | | - |
8619 | | -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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