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system(H5): update STM32H5xx CMSIS Drivers to v1.3.0
Included in STM32CubeH5 FW v1.3.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 113ef68 commit 7dff59c

16 files changed

+324
-316
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h523xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -505,7 +505,7 @@
505505
#define NVIC_INIT_ITNS3 1
506506

507507
/*
508-
// Interrupts 96..127
508+
// Interrupts 96..124
509509
// <o.0> GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
510510
// <o.1> GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
511511
// <o.7> FPU_IRQn <0=> Secure state <1=> Non-Secure state

‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h533xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -506,7 +506,7 @@
506506
#define NVIC_INIT_ITNS3 1
507507

508508
/*
509-
// Interrupts 96..127
509+
// Interrupts 96..124
510510
// <o.0> GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
511511
// <o.1> GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
512512
// <o.7> FPU_IRQn <0=> Secure state <1=> Non-Secure state

‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h

Lines changed: 35 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
* This file contains:
88
* - Data structures and the address mapping for all peripherals
99
* - Peripheral's registers declarations and bits definition
10-
* - Macros to access peripheral’s registers hardware
10+
* - Macros to access peripheral's registers hardware
1111
*
1212
******************************************************************************
1313
* @attention
@@ -175,7 +175,7 @@ typedef enum
175175

176176
/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
177177
#define __CM33_REV 0x0000U /* Core revision r0p1 */
178-
#define __SAUREGION_PRESENT 1U /* SAU regions present */
178+
#define __SAUREGION_PRESENT 0U /* SAU regions present */
179179
#define __MPU_PRESENT 1U /* MPU present */
180180
#define __VTOR_PRESENT 1U /* VTOR present */
181181
#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */
@@ -349,7 +349,6 @@ typedef struct
349349
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
350350
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
351351
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
352-
uint32_t RESERVED;
353352
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
354353
} RNG_TypeDef;
355354

@@ -1064,10 +1063,8 @@ typedef struct
10641063

10651064
typedef struct
10661065
{
1067-
__IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */
1068-
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */
1066+
uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x300 + 0x00 */
10691067
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */
1070-
__IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
10711068
} ADC_Common_TypeDef;
10721069

10731070

@@ -1262,12 +1259,10 @@ typedef struct
12621259
#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL)
12631260
#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL)
12641261
#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL)
1265-
12661262
#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL)
12671263
#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL)
12681264
#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL)
12691265

1270-
12711266
/*!< APB3 Non secure peripherals */
12721267
#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL)
12731268
#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL)
@@ -1284,12 +1279,10 @@ typedef struct
12841279

12851280
/* Debug MCU registers base address */
12861281
#define DBGMCU_BASE (0x44024000UL)
1287-
12881282
#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */
12891283
#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */
12901284
#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */
12911285

1292-
12931286
/* Internal Flash OTP Area */
12941287
#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */
12951288
#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */
@@ -3044,11 +3037,16 @@ typedef struct
30443037
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
30453038
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
30463039

3040+
30473041
/******************** Bits definition for RNG_HTCR register *******************/
30483042
#define RNG_HTCR_HTCFG_Pos (0U)
30493043
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
30503044
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
30513045

3046+
/******************** RNG Nist Compliance Values ******************************/
3047+
#define RNG_CR_NIST_VALUE (0x00F00D00U)
3048+
#define RNG_HTCR_NIST_VALUE (0xAAC7U)
3049+
30523050
/******************************************************************************/
30533051
/* */
30543052
/* Digital to Analog Converter */
@@ -4368,26 +4366,26 @@ typedef struct
43684366
#define EXTI_PRIVENR1_PRIV29 EXTI_PRIVENR1_PRIV29_Msk /*!< Privilege enable on line 29 */
43694367

43704368
/****************** Bit definition for EXTI_RTSR2 register *******************/
4371-
#define EXTI_RTSR2_TR_Pos (16U)
4372-
#define EXTI_RTSR2_TR_Msk (0x24UL << EXTI_RTSR2_TR_Pos) /*!< 0x00240000 */
4373-
#define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */
4374-
#define EXTI_RTSR2_TR50_Pos (18U)
4375-
#define EXTI_RTSR2_TR50_Msk (0x1UL << EXTI_RTSR2_TR50_Pos) /*!< 0x00040000 */
4376-
#define EXTI_RTSR2_TR50 EXTI_RTSR2_TR50_Msk /*!< Rising trigger event configuration bit of line 50 */
4377-
#define EXTI_RTSR2_TR53_Pos (21U)
4378-
#define EXTI_RTSR2_TR53_Msk (0x1UL << EXTI_RTSR2_TR53_Pos) /*!< 0x00200000 */
4379-
#define EXTI_RTSR2_TR53 EXTI_RTSR2_TR53_Msk /*!< Rising trigger event configuration bit of line 53 */
4369+
#define EXTI_RTSR2_RT_Pos (16U)
4370+
#define EXTI_RTSR2_RT_Msk (0x24UL << EXTI_RTSR2_RT_Pos) /*!< 0x00240000 */
4371+
#define EXTI_RTSR2_RT EXTI_RTSR2_RT_Msk /*!< Rising trigger event configuration bit */
4372+
#define EXTI_RTSR2_RT50_Pos (18U)
4373+
#define EXTI_RTSR2_RT50_Msk (0x1UL << EXTI_RTSR2_RT50_Pos) /*!< 0x00040000 */
4374+
#define EXTI_RTSR2_RT50 EXTI_RTSR2_RT50_Msk /*!< Rising trigger event configuration bit of line 50 */
4375+
#define EXTI_RTSR2_RT53_Pos (21U)
4376+
#define EXTI_RTSR2_RT53_Msk (0x1UL << EXTI_RTSR2_RT53_Pos) /*!< 0x00200000 */
4377+
#define EXTI_RTSR2_RT53 EXTI_RTSR2_RT53_Msk /*!< Rising trigger event configuration bit of line 53 */
43804378

43814379
/****************** Bit definition for EXTI_FTSR2 register *******************/
4382-
#define EXTI_FTSR2_TR_Pos (16U)
4383-
#define EXTI_FTSR2_TR_Msk (0x24 << EXTI_FTSR2_TR_Pos) /*!< 0x00240000 */
4384-
#define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */
4385-
#define EXTI_FTSR2_TR50_Pos (18U)
4386-
#define EXTI_FTSR2_TR50_Msk (0x1UL << EXTI_FTSR2_TR50_Pos) /*!< 0x00040000 */
4387-
#define EXTI_FTSR2_TR50 EXTI_FTSR2_TR50_Msk /*!< Falling trigger event configuration bit of line 50 */
4388-
#define EXTI_FTSR2_TR53_Pos (21U)
4389-
#define EXTI_FTSR2_TR53_Msk (0x1UL << EXTI_FTSR2_TR53_Pos) /*!< 0x00200000 */
4390-
#define EXTI_FTSR2_TR53 EXTI_FTSR2_TR53_Msk /*!< Falling trigger event configuration bit of line 53 */
4380+
#define EXTI_FTSR2_FT_Pos (16U)
4381+
#define EXTI_FTSR2_FT_Msk (0x24 << EXTI_FTSR2_FT_Pos) /*!< 0x00240000 */
4382+
#define EXTI_FTSR2_FT EXTI_FTSR2_FT_Msk /*!< Falling trigger event configuration bit */
4383+
#define EXTI_FTSR2_FT50_Pos (18U)
4384+
#define EXTI_FTSR2_FT50_Msk (0x1UL << EXTI_FTSR2_FT50_Pos) /*!< 0x00040000 */
4385+
#define EXTI_FTSR2_FT50 EXTI_FTSR2_FT50_Msk /*!< Falling trigger event configuration bit of line 50 */
4386+
#define EXTI_FTSR2_FT53_Pos (21U)
4387+
#define EXTI_FTSR2_FT53_Msk (0x1UL << EXTI_FTSR2_FT53_Pos) /*!< 0x00200000 */
4388+
#define EXTI_FTSR2_FT53 EXTI_FTSR2_FT53_Msk /*!< Falling trigger event configuration bit of line 53 */
43914389

43924390
/****************** Bit definition for EXTI_SWIER2 register ******************/
43934391
#define EXTI_SWIER2_SWIER50_Pos (18U)
@@ -5580,10 +5578,10 @@ typedef struct
55805578

55815579
/****************** Bits definition for FLASH_HDPEXTR register *****************/
55825580
#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U)
5583-
#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000007F */
5581+
#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7UL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x00000007 */
55845582
#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */
55855583
#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U)
5586-
#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x007F0000 */
5584+
#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7UL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x00070000 */
55875585
#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */
55885586

55895587
/******************* Bits definition for FLASH_OPTSR register ***************/
@@ -7273,27 +7271,27 @@ typedef struct
72737271

72747272
/******************* Bit definition for TIM_CCR1 register *******************/
72757273
#define TIM_CCR1_CCR1_Pos (0U)
7276-
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
7274+
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
72777275
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
72787276

72797277
/******************* Bit definition for TIM_CCR2 register *******************/
72807278
#define TIM_CCR2_CCR2_Pos (0U)
7281-
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
7279+
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
72827280
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
72837281

72847282
/******************* Bit definition for TIM_CCR3 register *******************/
72857283
#define TIM_CCR3_CCR3_Pos (0U)
7286-
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
7284+
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
72877285
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
72887286

72897287
/******************* Bit definition for TIM_CCR4 register *******************/
72907288
#define TIM_CCR4_CCR4_Pos (0U)
7291-
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
7289+
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
72927290
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
72937291

72947292
/******************* Bit definition for TIM_CCR5 register *******************/
72957293
#define TIM_CCR5_CCR5_Pos (0U)
7296-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
7294+
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
72977295
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
72987296
#define TIM_CCR5_GC5C1_Pos (29U)
72997297
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
@@ -7307,7 +7305,7 @@ typedef struct
73077305

73087306
/******************* Bit definition for TIM_CCR6 register *******************/
73097307
#define TIM_CCR6_CCR6_Pos (0U)
7310-
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
7308+
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
73117309
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
73127310

73137311
/******************* Bit definition for TIM_BDTR register *******************/
@@ -9099,9 +9097,6 @@ typedef struct
90999097
#define RCC_AHB2LPENR_RNGLPEN_Pos (18U)
91009098
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00040000 */
91019099
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
9102-
#define RCC_AHB2LPENR_PKALPEN_Pos (19U)
9103-
#define RCC_AHB2LPENR_PKALPEN_Msk (0x1UL << RCC_AHB2LPENR_PKALPEN_Pos) /*!< 0x00080000 */
9104-
#define RCC_AHB2LPENR_PKALPEN RCC_AHB2LPENR_PKALPEN_Msk
91059100
#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
91069101
#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
91079102
#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
@@ -10901,8 +10896,6 @@ typedef struct
1090110896
#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos)
1090210897
#define GTZC_CFGR3_RNG_Pos (18U)
1090310898
#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos)
10904-
#define GTZC_CFGR3_PKA_Pos (20U)
10905-
#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos)
1090610899
#define GTZC_CFGR3_RAMCFG_Pos (26U)
1090710900
#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos)
1090810901

@@ -11004,8 +10997,6 @@ typedef struct
1100410997
#define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk
1100510998
#define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos
1100610999
#define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk
11007-
#define GTZC_TZSC1_PRIVCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos
11008-
#define GTZC_TZSC1_PRIVCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk
1100911000
#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos
1101011001
#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk
1101111002

@@ -11018,6 +11009,7 @@ typedef struct
1101811009
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
1101911010
/* */
1102011011
/******************************************************************************/
11012+
#define USART_DMAREQUESTS_SW_WA
1102111013
/****************** Bit definition for USART_CR1 register *******************/
1102211014
#define USART_CR1_UE_Pos (0U)
1102311015
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */

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