system(F0): update system_stm32f0xx.c

fpistm · fpistm · commit c51ff4b6fc88 · 2023-03-20T09:14:58.000+01:00
Signed-off-by: Frederic Pillon &lt;frederic.pillon@st.com&gt;
diff --git a/system/STM32F0xx/system_stm32f0xx.c b/system/STM32F0xx/system_stm32f0xx.c
@@ -40,8 +40,8 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
   *
   * This software component is licensed by ST under BSD 3-Clause license,
   * the "License"; You may not use this file except in compliance with the
@@ -212,6 +212,8 @@ void SystemInit(void)
   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
   *
+  *           - If SYSCLK source is HSI48, SystemCoreClock will contain the HSI48_VALUE(***)
+  *
   *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
   *             8 MHz) but the real value may vary depending on the variations
   *             in voltage and temperature.
@@ -221,6 +223,10 @@ void SystemInit(void)
   *              is same as the real frequency of the crystal used. Otherwise, this function
   *              may have wrong result.
   *
+  *         (***) HSI48_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
+  *             48 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
   *         - The result of this function could be not correct when using fractional
   *           value for HSE crystal.
   *
@@ -254,13 +260,13 @@ void SystemCoreClockUpdate (void)
         /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
         SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
       }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
       else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
       {
         /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
         SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
       }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
       else
       {
 #if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) \

Original file line number	Diff line number	Diff line change
`@@ -40,8 +40,8 @@`
`40`	`40`	`******************************************************************************`
`41`	`41`	`* @attention`
`42`	`42`	`*`
`43`		`- * <h2><center>© Copyright (c) 2016 STMicroelectronics.`
`44`		`- * All rights reserved.</center></h2>`
	`43`	`+ * Copyright (c) 2016 STMicroelectronics.`
	`44`	`+ * All rights reserved.`
`45`	`45`	`*`
`46`	`46`	`* This software component is licensed by ST under BSD 3-Clause license,`
`47`	`47`	`* the "License"; You may not use this file except in compliance with the`
`@@ -212,6 +212,8 @@ void SystemInit(void)`
`212`	`212`	`* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)`
`213`	`213`	`* or HSI_VALUE(*) multiplied/divided by the PLL factors.`
`214`	`214`	`*`
	`215`	`+ * - If SYSCLK source is HSI48, SystemCoreClock will contain the HSI48_VALUE(***)`
	`216`	`+ *`
`215`	`217`	`* (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value`
`216`	`218`	`* 8 MHz) but the real value may vary depending on the variations`
`217`	`219`	`* in voltage and temperature.`
`@@ -221,6 +223,10 @@ void SystemInit(void)`
`221`	`223`	`* is same as the real frequency of the crystal used. Otherwise, this function`
`222`	`224`	`* may have wrong result.`
`223`	`225`	`*`
	`226`	`+ * (***) HSI48_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value`
	`227`	`+ * 48 MHz) but the real value may vary depending on the variations`
	`228`	`+ * in voltage and temperature.`
	`229`	`+ *`
`224`	`230`	`* - The result of this function could be not correct when using fractional`
`225`	`231`	`* value for HSE crystal.`
`226`	`232`	`*`
`@@ -254,13 +260,13 @@ void SystemCoreClockUpdate (void)`
`254`	`260`	`/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */`
`255`	`261`	`SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;`
`256`	`262`	`}`
`257`		`-#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F091xC) \|\| defined(STM32F098xx)`
	`263`	`+#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F091xC) \|\| defined(STM32F098xx)`
`258`	`264`	`else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)`
`259`	`265`	`{`
`260`	`266`	`/* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */`
`261`	`267`	`SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;`
`262`	`268`	`}`
`263`		`-#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx */`
	`269`	`+#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx */`
`264`	`270`	`else`
`265`	`271`	`{`
`266`	`272`	`#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \`