From b6fb89d27bf841079a58ac43631347514e75c9d8 Mon Sep 17 00:00:00 2001
From: Francois Ramu <francois.ramu@st.com>
Date: Mon, 9 Nov 2020 11:00:15 +0100
Subject: [PATCH] [PNUCLEO_WB55RG] BLE support configuration

Enable IPCC HAL module which transport the HCI command
over the Shared Mem.
Update clock configuration for BLE on this nucleo_wb55rg
Manage OTP to access the device bd address

Signed-off-by: Francois Ramu <francois.ramu@st.com>
---
 variants/PNUCLEO_WB55RG/otp.h       | 46 ++++++++++++++
 variants/PNUCLEO_WB55RG/variant.cpp | 93 +++++++++++++++++++----------
 variants/PNUCLEO_WB55RG/variant.h   |  2 +
 3 files changed, 109 insertions(+), 32 deletions(-)
 create mode 100644 variants/PNUCLEO_WB55RG/otp.h

diff --git a/variants/PNUCLEO_WB55RG/otp.h b/variants/PNUCLEO_WB55RG/otp.h
new file mode 100644
index 0000000000..0574fa9e81
--- /dev/null
+++ b/variants/PNUCLEO_WB55RG/otp.h
@@ -0,0 +1,46 @@
+/**
+  ******************************************************************************
+  * @file    otp.h
+  * @author  MCD Application Team
+  * @brief   OTP manager  interface
+  ******************************************************************************
+   * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __OTP_H
+#define __OTP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct __packed {
+  uint8_t   bd_address[6];
+  uint8_t   hse_tuning;
+  uint8_t   id;
+} OTP_ID0_t;
+
+/* Exported constants --------------------------------------------------------*/
+#define CFG_OTP_BASE_ADDRESS  OTP_AREA_BASE
+
+#define CFG_OTP_END_ADDRESS OTP_AREA_END_ADDR
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__OTP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/variants/PNUCLEO_WB55RG/variant.cpp b/variants/PNUCLEO_WB55RG/variant.cpp
index 67f7b6650c..ef7a2de156 100644
--- a/variants/PNUCLEO_WB55RG/variant.cpp
+++ b/variants/PNUCLEO_WB55RG/variant.cpp
@@ -17,6 +17,7 @@
 */
 
 #include "pins_arduino.h"
+#include "otp.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -88,6 +89,36 @@ const PinName digitalPin[] = {
 extern "C" {
 #endif
 
+static uint8_t *OTP_Read(uint8_t id)
+{
+  uint8_t *p_id;
+
+  p_id = (uint8_t *)(CFG_OTP_END_ADDRESS - 7) ;
+
+  while (((*(p_id + 7)) != id) && (p_id != (uint8_t *)CFG_OTP_BASE_ADDRESS)) {
+    p_id -= 8 ;
+  }
+
+  if ((*(p_id + 7)) != id) {
+    p_id = 0 ;
+  }
+
+  return p_id ;
+}
+
+static void Config_HSE(void)
+{
+  OTP_ID0_t *p_otp;
+
+  /**
+   * Read HSE_Tuning from OTP
+   */
+  p_otp = (OTP_ID0_t *) OTP_Read(0);
+  if (p_otp) {
+    LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
+  }
+}
+
 /**
   * @brief  System Clock Configuration
   * @param  None
@@ -99,60 +130,58 @@ WEAK void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
 
-  /* Configure LSE Drive Capability */
+  Config_HSE();
+
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
-  /* Configure the main internal regulator output voltage */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /* Initializes the CPU, AHB and APB busses clocks  */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
-                                     | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
+
+  /* Initializes the CPU, AHB and APB busses clocks */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48
+                                     | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
-  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
-  RCC_OscInitStruct.PLL.PLLN = 32;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
     Error_Handler();
   }
+
   /* Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
                                 | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
                                 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
-
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
     Error_Handler();
   }
-  /* Initializes the peripherals clocks */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.PLLSAI1.PLLN = 24;
-  PeriphClkInitStruct.PLLSAI1.PLLP = RCC_PLLP_DIV2;
-  PeriphClkInitStruct.PLLSAI1.PLLQ = RCC_PLLQ_DIV2;
-  PeriphClkInitStruct.PLLSAI1.PLLR = RCC_PLLR_DIV2;
-  PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_USBCLK;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
-  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
-  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
 
+  /* Initializes the peripherals clocks */
+  /* RNG needs to be configured like in M0 core, i.e. with HSI48 */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP
+                                             | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
+  PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
     Error_Handler();
   }
-  /* Enable MSI Auto calibration */
-  HAL_RCCEx_EnableMSIPLLMode();
+
+  LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+  LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+  LL_PWR_SMPS_Enable();
+
+  /* Select HSI as system clock source after Wake Up from Stop mode */
+  LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
+
 }
 
 #ifdef __cplusplus
diff --git a/variants/PNUCLEO_WB55RG/variant.h b/variants/PNUCLEO_WB55RG/variant.h
index 5c63db398a..5cb020a38b 100644
--- a/variants/PNUCLEO_WB55RG/variant.h
+++ b/variants/PNUCLEO_WB55RG/variant.h
@@ -120,6 +120,8 @@ extern "C" {
 // for EEPROM emulation to the last 512k pages.
 #define FLASH_PAGE_NUMBER       127
 
+#define HAL_IPCC_MODULE_ENABLED
+
 #ifdef __cplusplus
 } // extern "C"
 #endif

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