diff --git a/README.md b/README.md
index f1e08f9540..90e8aabc57 100644
--- a/README.md
+++ b/README.md
@@ -213,7 +213,17 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| Status | Device(s) | Name | Release | Notes |
| :----: | :-------: | ---- | :-----: | :---- |
+| :yellow_heart: | STM32F205RB
STM32F205RC
STM32F205RE
STM32F205RF | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32F205VB
STM32F205VC
STM32F205VE
STM32F205VF
STM32F205VG | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32F205ZC
STM32F205ZE
STM32F205ZF
STM32F205ZG | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32F207IC
STM32F207IE
STM32F207IF
STM32F207IG | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32F207VC
STM32F207VE
STM32F207VF
STM32F207VG | Generic Board | **2.4.0** | |
| :green_heart: | STM32F207ZC
STM32F207ZE
STM32F207ZF
STM32F207ZG | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32F215RE
STM32F215RG | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32F215VE
STM32F215VG | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32F215ZE
STM32F215ZG | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32F217IE
STM32F217IG | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32F217VE
STM32F217VG | Generic Board | **2.4.0** | |
| :green_heart: | STM32F217ZE
STM32F217ZG | Generic Board | *2.0.0* | |
### Generic STM32F3 boards
diff --git a/boards.txt b/boards.txt
index 32531ce5da..2ebaa61c6b 100644
--- a/boards.txt
+++ b/boards.txt
@@ -1929,6 +1929,238 @@ GenF2.build.cmsis_lib_gcc=arm_cortexM3l_math
GenF2.upload.maximum_size=0
GenF2.upload.maximum_data_size=0
+# Generic F205RBTx
+GenF2.menu.pnum.GENERIC_F205RBTX=Generic F205RBTx
+GenF2.menu.pnum.GENERIC_F205RBTX.upload.maximum_size=131072
+GenF2.menu.pnum.GENERIC_F205RBTX.upload.maximum_data_size=65536
+GenF2.menu.pnum.GENERIC_F205RBTX.build.board=GENERIC_F205RBTX
+GenF2.menu.pnum.GENERIC_F205RBTX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205RBTX.build.variant=STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T
+
+# Generic F205RCTx
+GenF2.menu.pnum.GENERIC_F205RCTX=Generic F205RCTx
+GenF2.menu.pnum.GENERIC_F205RCTX.upload.maximum_size=262144
+GenF2.menu.pnum.GENERIC_F205RCTX.upload.maximum_data_size=98304
+GenF2.menu.pnum.GENERIC_F205RCTX.build.board=GENERIC_F205RCTX
+GenF2.menu.pnum.GENERIC_F205RCTX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205RCTX.build.variant=STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T
+
+# Generic F205RETx
+GenF2.menu.pnum.GENERIC_F205RETX=Generic F205RETx
+GenF2.menu.pnum.GENERIC_F205RETX.upload.maximum_size=524288
+GenF2.menu.pnum.GENERIC_F205RETX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F205RETX.build.board=GENERIC_F205RETX
+GenF2.menu.pnum.GENERIC_F205RETX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205RETX.build.variant=STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T
+
+# Generic F205RFTx
+GenF2.menu.pnum.GENERIC_F205RFTX=Generic F205RFTx
+GenF2.menu.pnum.GENERIC_F205RFTX.upload.maximum_size=786432
+GenF2.menu.pnum.GENERIC_F205RFTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F205RFTX.build.board=GENERIC_F205RFTX
+GenF2.menu.pnum.GENERIC_F205RFTX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205RFTX.build.variant=STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T
+
+# Generic F205RGTx
+GenF2.menu.pnum.GENERIC_F205RGTX=Generic F205RGTx
+GenF2.menu.pnum.GENERIC_F205RGTX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F205RGTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F205RGTX.build.board=GENERIC_F205RGTX
+GenF2.menu.pnum.GENERIC_F205RGTX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205RGTX.build.variant=STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T
+
+# Generic F205REYx
+GenF2.menu.pnum.GENERIC_F205REYX=Generic F205REYx
+GenF2.menu.pnum.GENERIC_F205REYX.upload.maximum_size=524288
+GenF2.menu.pnum.GENERIC_F205REYX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F205REYX.build.board=GENERIC_F205REYX
+GenF2.menu.pnum.GENERIC_F205REYX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205REYX.build.variant=STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T
+
+# Generic F205RGYx
+GenF2.menu.pnum.GENERIC_F205RGYX=Generic F205RGYx
+GenF2.menu.pnum.GENERIC_F205RGYX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F205RGYX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F205RGYX.build.board=GENERIC_F205RGYX
+GenF2.menu.pnum.GENERIC_F205RGYX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205RGYX.build.variant=STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T
+
+# Generic F205RGEx
+GenF2.menu.pnum.GENERIC_F205RGEX=Generic F205RGEx
+GenF2.menu.pnum.GENERIC_F205RGEX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F205RGEX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F205RGEX.build.board=GENERIC_F205RGEX
+GenF2.menu.pnum.GENERIC_F205RGEX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205RGEX.build.variant=STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T
+
+# Generic F205VBTx
+GenF2.menu.pnum.GENERIC_F205VBTX=Generic F205VBTx
+GenF2.menu.pnum.GENERIC_F205VBTX.upload.maximum_size=131072
+GenF2.menu.pnum.GENERIC_F205VBTX.upload.maximum_data_size=65536
+GenF2.menu.pnum.GENERIC_F205VBTX.build.board=GENERIC_F205VBTX
+GenF2.menu.pnum.GENERIC_F205VBTX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205VBTX.build.variant=STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T
+
+# Generic F205VCTx
+GenF2.menu.pnum.GENERIC_F205VCTX=Generic F205VCTx
+GenF2.menu.pnum.GENERIC_F205VCTX.upload.maximum_size=262144
+GenF2.menu.pnum.GENERIC_F205VCTX.upload.maximum_data_size=98304
+GenF2.menu.pnum.GENERIC_F205VCTX.build.board=GENERIC_F205VCTX
+GenF2.menu.pnum.GENERIC_F205VCTX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205VCTX.build.variant=STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T
+
+# Generic F205VETx
+GenF2.menu.pnum.GENERIC_F205VETX=Generic F205VETx
+GenF2.menu.pnum.GENERIC_F205VETX.upload.maximum_size=524288
+GenF2.menu.pnum.GENERIC_F205VETX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F205VETX.build.board=GENERIC_F205VETX
+GenF2.menu.pnum.GENERIC_F205VETX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205VETX.build.variant=STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T
+
+# Generic F205VFTx
+GenF2.menu.pnum.GENERIC_F205VFTX=Generic F205VFTx
+GenF2.menu.pnum.GENERIC_F205VFTX.upload.maximum_size=786432
+GenF2.menu.pnum.GENERIC_F205VFTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F205VFTX.build.board=GENERIC_F205VFTX
+GenF2.menu.pnum.GENERIC_F205VFTX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205VFTX.build.variant=STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T
+
+# Generic F205VGTx
+GenF2.menu.pnum.GENERIC_F205VGTX=Generic F205VGTx
+GenF2.menu.pnum.GENERIC_F205VGTX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F205VGTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F205VGTX.build.board=GENERIC_F205VGTX
+GenF2.menu.pnum.GENERIC_F205VGTX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205VGTX.build.variant=STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T
+
+# Generic F205ZCTx
+GenF2.menu.pnum.GENERIC_F205ZCTX=Generic F205ZCTx
+GenF2.menu.pnum.GENERIC_F205ZCTX.upload.maximum_size=262144
+GenF2.menu.pnum.GENERIC_F205ZCTX.upload.maximum_data_size=98304
+GenF2.menu.pnum.GENERIC_F205ZCTX.build.board=GENERIC_F205ZCTX
+GenF2.menu.pnum.GENERIC_F205ZCTX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205ZCTX.build.variant=STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T
+
+# Generic F205ZETx
+GenF2.menu.pnum.GENERIC_F205ZETX=Generic F205ZETx
+GenF2.menu.pnum.GENERIC_F205ZETX.upload.maximum_size=524288
+GenF2.menu.pnum.GENERIC_F205ZETX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F205ZETX.build.board=GENERIC_F205ZETX
+GenF2.menu.pnum.GENERIC_F205ZETX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205ZETX.build.variant=STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T
+
+# Generic F205ZFTx
+GenF2.menu.pnum.GENERIC_F205ZFTX=Generic F205ZFTx
+GenF2.menu.pnum.GENERIC_F205ZFTX.upload.maximum_size=786432
+GenF2.menu.pnum.GENERIC_F205ZFTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F205ZFTX.build.board=GENERIC_F205ZFTX
+GenF2.menu.pnum.GENERIC_F205ZFTX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205ZFTX.build.variant=STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T
+
+# Generic F205ZGTx
+GenF2.menu.pnum.GENERIC_F205ZGTX=Generic F205ZGTx
+GenF2.menu.pnum.GENERIC_F205ZGTX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F205ZGTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F205ZGTX.build.board=GENERIC_F205ZGTX
+GenF2.menu.pnum.GENERIC_F205ZGTX.build.product_line=STM32F205xx
+GenF2.menu.pnum.GENERIC_F205ZGTX.build.variant=STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T
+
+# Generic F207ICHx
+GenF2.menu.pnum.GENERIC_F207ICHX=Generic F207ICHx
+GenF2.menu.pnum.GENERIC_F207ICHX.upload.maximum_size=262144
+GenF2.menu.pnum.GENERIC_F207ICHX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F207ICHX.build.board=GENERIC_F207ICHX
+GenF2.menu.pnum.GENERIC_F207ICHX.build.product_line=STM32F207xx
+GenF2.menu.pnum.GENERIC_F207ICHX.build.variant=STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)
+
+# Generic F207IEHx
+GenF2.menu.pnum.GENERIC_F207IEHX=Generic F207IEHx
+GenF2.menu.pnum.GENERIC_F207IEHX.upload.maximum_size=524288
+GenF2.menu.pnum.GENERIC_F207IEHX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F207IEHX.build.board=GENERIC_F207IEHX
+GenF2.menu.pnum.GENERIC_F207IEHX.build.product_line=STM32F207xx
+GenF2.menu.pnum.GENERIC_F207IEHX.build.variant=STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)
+
+# Generic F207IFHx
+GenF2.menu.pnum.GENERIC_F207IFHX=Generic F207IFHx
+GenF2.menu.pnum.GENERIC_F207IFHX.upload.maximum_size=786432
+GenF2.menu.pnum.GENERIC_F207IFHX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F207IFHX.build.board=GENERIC_F207IFHX
+GenF2.menu.pnum.GENERIC_F207IFHX.build.product_line=STM32F207xx
+GenF2.menu.pnum.GENERIC_F207IFHX.build.variant=STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)
+
+# Generic F207IGHx
+GenF2.menu.pnum.GENERIC_F207IGHX=Generic F207IGHx
+GenF2.menu.pnum.GENERIC_F207IGHX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F207IGHX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F207IGHX.build.board=GENERIC_F207IGHX
+GenF2.menu.pnum.GENERIC_F207IGHX.build.product_line=STM32F207xx
+GenF2.menu.pnum.GENERIC_F207IGHX.build.variant=STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)
+
+# Generic F207ICTx
+GenF2.menu.pnum.GENERIC_F207ICTX=Generic F207ICTx
+GenF2.menu.pnum.GENERIC_F207ICTX.upload.maximum_size=262144
+GenF2.menu.pnum.GENERIC_F207ICTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F207ICTX.build.board=GENERIC_F207ICTX
+GenF2.menu.pnum.GENERIC_F207ICTX.build.product_line=STM32F207xx
+GenF2.menu.pnum.GENERIC_F207ICTX.build.variant=STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)
+
+# Generic F207IETx
+GenF2.menu.pnum.GENERIC_F207IETX=Generic F207IETx
+GenF2.menu.pnum.GENERIC_F207IETX.upload.maximum_size=524288
+GenF2.menu.pnum.GENERIC_F207IETX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F207IETX.build.board=GENERIC_F207IETX
+GenF2.menu.pnum.GENERIC_F207IETX.build.product_line=STM32F207xx
+GenF2.menu.pnum.GENERIC_F207IETX.build.variant=STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)
+
+# Generic F207IFTx
+GenF2.menu.pnum.GENERIC_F207IFTX=Generic F207IFTx
+GenF2.menu.pnum.GENERIC_F207IFTX.upload.maximum_size=786432
+GenF2.menu.pnum.GENERIC_F207IFTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F207IFTX.build.board=GENERIC_F207IFTX
+GenF2.menu.pnum.GENERIC_F207IFTX.build.product_line=STM32F207xx
+GenF2.menu.pnum.GENERIC_F207IFTX.build.variant=STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)
+
+# Generic F207IGTx
+GenF2.menu.pnum.GENERIC_F207IGTX=Generic F207IGTx
+GenF2.menu.pnum.GENERIC_F207IGTX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F207IGTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F207IGTX.build.board=GENERIC_F207IGTX
+GenF2.menu.pnum.GENERIC_F207IGTX.build.product_line=STM32F207xx
+GenF2.menu.pnum.GENERIC_F207IGTX.build.variant=STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)
+
+# Generic F207VCTx
+GenF2.menu.pnum.GENERIC_F207VCTX=Generic F207VCTx
+GenF2.menu.pnum.GENERIC_F207VCTX.upload.maximum_size=262144
+GenF2.menu.pnum.GENERIC_F207VCTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F207VCTX.build.board=GENERIC_F207VCTX
+GenF2.menu.pnum.GENERIC_F207VCTX.build.product_line=STM32F207xx
+GenF2.menu.pnum.GENERIC_F207VCTX.build.variant=STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T
+
+# Generic F207VETx
+GenF2.menu.pnum.GENERIC_F207VETX=Generic F207VETx
+GenF2.menu.pnum.GENERIC_F207VETX.upload.maximum_size=524288
+GenF2.menu.pnum.GENERIC_F207VETX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F207VETX.build.board=GENERIC_F207VETX
+GenF2.menu.pnum.GENERIC_F207VETX.build.product_line=STM32F207xx
+GenF2.menu.pnum.GENERIC_F207VETX.build.variant=STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T
+
+# Generic F207VFTx
+GenF2.menu.pnum.GENERIC_F207VFTX=Generic F207VFTx
+GenF2.menu.pnum.GENERIC_F207VFTX.upload.maximum_size=786432
+GenF2.menu.pnum.GENERIC_F207VFTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F207VFTX.build.board=GENERIC_F207VFTX
+GenF2.menu.pnum.GENERIC_F207VFTX.build.product_line=STM32F207xx
+GenF2.menu.pnum.GENERIC_F207VFTX.build.variant=STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T
+
+# Generic F207VGTx
+GenF2.menu.pnum.GENERIC_F207VGTX=Generic F207VGTx
+GenF2.menu.pnum.GENERIC_F207VGTX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F207VGTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F207VGTX.build.board=GENERIC_F207VGTX
+GenF2.menu.pnum.GENERIC_F207VGTX.build.product_line=STM32F207xx
+GenF2.menu.pnum.GENERIC_F207VGTX.build.variant=STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T
+
# Generic F207ZCTx
GenF2.menu.pnum.GENERIC_F207ZCTX=Generic F207ZCTx
GenF2.menu.pnum.GENERIC_F207ZCTX.upload.maximum_size=262144
@@ -1961,6 +2193,102 @@ GenF2.menu.pnum.GENERIC_F207ZGTX.build.board=GENERIC_F207ZGTX
GenF2.menu.pnum.GENERIC_F207ZGTX.build.product_line=STM32F207xx
GenF2.menu.pnum.GENERIC_F207ZGTX.build.variant=STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T
+# Generic F215RETx
+GenF2.menu.pnum.GENERIC_F215RETX=Generic F215RETx
+GenF2.menu.pnum.GENERIC_F215RETX.upload.maximum_size=524288
+GenF2.menu.pnum.GENERIC_F215RETX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F215RETX.build.board=GENERIC_F215RETX
+GenF2.menu.pnum.GENERIC_F215RETX.build.product_line=STM32F215xx
+GenF2.menu.pnum.GENERIC_F215RETX.build.variant=STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T
+
+# Generic F215RGTx
+GenF2.menu.pnum.GENERIC_F215RGTX=Generic F215RGTx
+GenF2.menu.pnum.GENERIC_F215RGTX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F215RGTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F215RGTX.build.board=GENERIC_F215RGTX
+GenF2.menu.pnum.GENERIC_F215RGTX.build.product_line=STM32F215xx
+GenF2.menu.pnum.GENERIC_F215RGTX.build.variant=STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T
+
+# Generic F215VETx
+GenF2.menu.pnum.GENERIC_F215VETX=Generic F215VETx
+GenF2.menu.pnum.GENERIC_F215VETX.upload.maximum_size=524288
+GenF2.menu.pnum.GENERIC_F215VETX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F215VETX.build.board=GENERIC_F215VETX
+GenF2.menu.pnum.GENERIC_F215VETX.build.product_line=STM32F215xx
+GenF2.menu.pnum.GENERIC_F215VETX.build.variant=STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T
+
+# Generic F215VGTx
+GenF2.menu.pnum.GENERIC_F215VGTX=Generic F215VGTx
+GenF2.menu.pnum.GENERIC_F215VGTX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F215VGTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F215VGTX.build.board=GENERIC_F215VGTX
+GenF2.menu.pnum.GENERIC_F215VGTX.build.product_line=STM32F215xx
+GenF2.menu.pnum.GENERIC_F215VGTX.build.variant=STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T
+
+# Generic F215ZETx
+GenF2.menu.pnum.GENERIC_F215ZETX=Generic F215ZETx
+GenF2.menu.pnum.GENERIC_F215ZETX.upload.maximum_size=524288
+GenF2.menu.pnum.GENERIC_F215ZETX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F215ZETX.build.board=GENERIC_F215ZETX
+GenF2.menu.pnum.GENERIC_F215ZETX.build.product_line=STM32F215xx
+GenF2.menu.pnum.GENERIC_F215ZETX.build.variant=STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T
+
+# Generic F215ZGTx
+GenF2.menu.pnum.GENERIC_F215ZGTX=Generic F215ZGTx
+GenF2.menu.pnum.GENERIC_F215ZGTX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F215ZGTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F215ZGTX.build.board=GENERIC_F215ZGTX
+GenF2.menu.pnum.GENERIC_F215ZGTX.build.product_line=STM32F215xx
+GenF2.menu.pnum.GENERIC_F215ZGTX.build.variant=STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T
+
+# Generic F217IEHx
+GenF2.menu.pnum.GENERIC_F217IEHX=Generic F217IEHx
+GenF2.menu.pnum.GENERIC_F217IEHX.upload.maximum_size=524288
+GenF2.menu.pnum.GENERIC_F217IEHX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F217IEHX.build.board=GENERIC_F217IEHX
+GenF2.menu.pnum.GENERIC_F217IEHX.build.product_line=STM32F217xx
+GenF2.menu.pnum.GENERIC_F217IEHX.build.variant=STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)
+
+# Generic F217IGHx
+GenF2.menu.pnum.GENERIC_F217IGHX=Generic F217IGHx
+GenF2.menu.pnum.GENERIC_F217IGHX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F217IGHX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F217IGHX.build.board=GENERIC_F217IGHX
+GenF2.menu.pnum.GENERIC_F217IGHX.build.product_line=STM32F217xx
+GenF2.menu.pnum.GENERIC_F217IGHX.build.variant=STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)
+
+# Generic F217IETx
+GenF2.menu.pnum.GENERIC_F217IETX=Generic F217IETx
+GenF2.menu.pnum.GENERIC_F217IETX.upload.maximum_size=524288
+GenF2.menu.pnum.GENERIC_F217IETX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F217IETX.build.board=GENERIC_F217IETX
+GenF2.menu.pnum.GENERIC_F217IETX.build.product_line=STM32F217xx
+GenF2.menu.pnum.GENERIC_F217IETX.build.variant=STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)
+
+# Generic F217IGTx
+GenF2.menu.pnum.GENERIC_F217IGTX=Generic F217IGTx
+GenF2.menu.pnum.GENERIC_F217IGTX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F217IGTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F217IGTX.build.board=GENERIC_F217IGTX
+GenF2.menu.pnum.GENERIC_F217IGTX.build.product_line=STM32F217xx
+GenF2.menu.pnum.GENERIC_F217IGTX.build.variant=STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)
+
+# Generic F217VETx
+GenF2.menu.pnum.GENERIC_F217VETX=Generic F217VETx
+GenF2.menu.pnum.GENERIC_F217VETX.upload.maximum_size=524288
+GenF2.menu.pnum.GENERIC_F217VETX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F217VETX.build.board=GENERIC_F217VETX
+GenF2.menu.pnum.GENERIC_F217VETX.build.product_line=STM32F217xx
+GenF2.menu.pnum.GENERIC_F217VETX.build.variant=STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T
+
+# Generic F217VGTx
+GenF2.menu.pnum.GENERIC_F217VGTX=Generic F217VGTx
+GenF2.menu.pnum.GENERIC_F217VGTX.upload.maximum_size=1048576
+GenF2.menu.pnum.GENERIC_F217VGTX.upload.maximum_data_size=131072
+GenF2.menu.pnum.GENERIC_F217VGTX.build.board=GENERIC_F217VGTX
+GenF2.menu.pnum.GENERIC_F217VGTX.build.product_line=STM32F217xx
+GenF2.menu.pnum.GENERIC_F217VGTX.build.variant=STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T
+
# Generic F217ZETx
GenF2.menu.pnum.GENERIC_F217ZETX=Generic F217ZETx
GenF2.menu.pnum.GENERIC_F217ZETX.upload.maximum_size=524288
diff --git a/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/generic_clock.c b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/generic_clock.c
index 208bb138ec..197011a006 100644
--- a/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/generic_clock.c
+++ b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/generic_clock.c
@@ -24,8 +24,37 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 13;
+ RCC_OscInitStruct.PLL.PLLN = 195;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 5;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/ldscript.ld b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/ldscript.ld
new file mode 100644
index 0000000000..841f1efb96
--- /dev/null
+++ b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/ldscript.ld
@@ -0,0 +1,187 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32F205RBTx Device from STM32F2 series
+** 128Kbytes FLASH
+** 48Kbytes RAM
+** 16Kbytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ RAM2 (xrw) : ORIGIN = 0x2001C000, LENGTH = 16K
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/generic_clock.c b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/generic_clock.c
index 40925da016..77eaba905e 100644
--- a/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/generic_clock.c
+++ b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/generic_clock.c
@@ -23,8 +23,37 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 13;
+ RCC_OscInitStruct.PLL.PLLN = 195;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 5;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/ldscript.ld b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/ldscript.ld
new file mode 100644
index 0000000000..9ed028a7fd
--- /dev/null
+++ b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/ldscript.ld
@@ -0,0 +1,187 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32F205VBTx Device from STM32F2 series
+** 128Kbytes FLASH
+** 48Kbytes RAM
+** 16Kbytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ RAM2 (xrw) : ORIGIN = 0x2001C000, LENGTH = 16K
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/generic_clock.c b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/generic_clock.c
index 0946c15122..a91d222256 100644
--- a/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/generic_clock.c
+++ b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/generic_clock.c
@@ -22,8 +22,37 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 13;
+ RCC_OscInitStruct.PLL.PLLN = 195;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 5;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/ldscript.ld b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/ldscript.ld
new file mode 100644
index 0000000000..fc5e524605
--- /dev/null
+++ b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/ldscript.ld
@@ -0,0 +1,187 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32F205ZCTx Device from STM32F2 series
+** 256Kbytes FLASH
+** 80Kbytes RAM
+** 16Kbytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ RAM2 (xrw) : ORIGIN = 0x2001C000, LENGTH = 16K
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/generic_clock.c b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/generic_clock.c
index 28dd0d1e75..697297aaa1 100644
--- a/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/generic_clock.c
+++ b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/generic_clock.c
@@ -25,8 +25,37 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 13;
+ RCC_OscInitStruct.PLL.PLLN = 195;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 5;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/ldscript.ld b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/ldscript.ld
new file mode 100644
index 0000000000..f81dcef83c
--- /dev/null
+++ b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/ldscript.ld
@@ -0,0 +1,187 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32F207ICHx Device from STM32F2 series
+** 256Kbytes FLASH
+** 112Kbytes RAM
+** 16Kbytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ RAM2 (xrw) : ORIGIN = 0x2001C000, LENGTH = 16K
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/generic_clock.c b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/generic_clock.c
index 3bcfa6f1a2..b2bab76778 100644
--- a/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/generic_clock.c
+++ b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/generic_clock.c
@@ -22,8 +22,37 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 13;
+ RCC_OscInitStruct.PLL.PLLN = 195;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 5;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/ldscript.ld b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/ldscript.ld
new file mode 100644
index 0000000000..3ade4112d4
--- /dev/null
+++ b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/ldscript.ld
@@ -0,0 +1,187 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32F207VCTx Device from STM32F2 series
+** 256Kbytes FLASH
+** 112Kbytes RAM
+** 16Kbytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ RAM2 (xrw) : ORIGIN = 0x2001C000, LENGTH = 16K
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
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