From f3292f257d649789fddaf7dadde3870f5b44d86a Mon Sep 17 00:00:00 2001
From: alextrical <35117191+alextrical@users.noreply.github.com>
Date: Thu, 11 Aug 2022 12:58:02 +0100
Subject: [PATCH] variant(L0): add some missing generic
| :yellow_heart: | STM32L010C6 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L010F4 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L010R8 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L011D3
STM32L011D4 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L011E3
STM32L011E4 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L011F3
STM32L011F4 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L011G3
STM32L011G4 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L011K3
STM32L011K4 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L021F4 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L021D4 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L021F4 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L021G4 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L021K4 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L031C4
STM32L031C6 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L031E4
STM32L031E6 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L031F4
STM32L031F6 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L031G4
STM32L031G6 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L041C4
STM32L041C6 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L041E6 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L041F6 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L041G6 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L052C6
STM32L052C8 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L052K6
STM32L052K8 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L052R6
STM32L052R8 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L052T6
STM32L052T8 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L053C6
STM32L053C8 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L053R6
STM32L053R8 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L062C8 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L062K8 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L063C8 | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L072CB
STM32L072CZ | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L072KB
STM32L072KZ | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L072RB
STM32L072RZ | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L072V8
STM32L072VB
STM32L072VZ | Generic Board | **2.4.0** |
| :yellow_heart: | STM32L073V8
STM32L073VB
STM32L073VZ | Generic Board | **2.4.0** |
| :yellow_heart: | STM32L073CB
STM32L073CZ | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L073RB
STM32L073RZ | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L082CZ | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L082KB
STM32L082KZ | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L083CB
STM32L083CZ | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L083RB
STM32L083RZ | Generic Board | **2.4.0** | |
| :yellow_heart: | STM32L083V8
STM32L083VB
STM32L083VZ | Generic Board | **2.4.0** |
Corrected ldscript.ld names
Fixed issue caused by incorrect RegEx query, removing parenthesis
---
README.md | 44 +
boards.txt | 832 ++++++++++++++++++
variants/STM32L0xx/L010C6T/generic_clock.c | 35 +-
variants/STM32L0xx/L010C6T/ldscript.ld | 185 ++++
.../generic_clock.c | 35 +-
.../L010F4P_L011F(3-4)P_L021F4P/ldscript.ld | 185 ++++
.../generic_clock.c | 35 +-
.../L010K4T_L011K(3-4)T_L021K4T/ldscript.ld | 185 ++++
variants/STM32L0xx/L010R8T/generic_clock.c | 35 +-
variants/STM32L0xx/L010R8T/ldscript.ld | 185 ++++
.../L011D(3-4)P_L021D4P/generic_clock.c | 35 +-
.../STM32L0xx/L011D(3-4)P_L021D4P/ldscript.ld | 185 ++++
.../STM32L0xx/L011E(3-4)Y/generic_clock.c | 35 +-
variants/STM32L0xx/L011E(3-4)Y/ldscript.ld | 185 ++++
.../L011F(3-4)U_L021F4U/generic_clock.c | 35 +-
.../STM32L0xx/L011F(3-4)U_L021F4U/ldscript.ld | 185 ++++
.../L011G(3-4)U_L021G4U/generic_clock.c | 35 +-
.../STM32L0xx/L011G(3-4)U_L021G4U/ldscript.ld | 185 ++++
.../L011K(3-4)U_L021K4U/generic_clock.c | 35 +-
.../STM32L0xx/L011K(3-4)U_L021K4U/ldscript.ld | 185 ++++
.../generic_clock.c | 35 +-
.../ldscript.ld | 185 ++++
.../L031E(4-6)Y_L041E6Y/generic_clock.c | 35 +-
.../STM32L0xx/L031E(4-6)Y_L041E6Y/ldscript.ld | 185 ++++
.../L031F(4-6)P_L041F6P/generic_clock.c | 35 +-
.../STM32L0xx/L031F(4-6)P_L041F6P/ldscript.ld | 185 ++++
.../L031G(4-6)U_L041G6U/generic_clock.c | 35 +-
.../STM32L0xx/L031G(4-6)U_L041G6U/ldscript.ld | 185 ++++
.../generic_clock.c | 42 +-
.../ldscript.ld | 185 ++++
.../L052K(6-8)T_L062K8T/generic_clock.c | 42 +-
.../STM32L0xx/L052K(6-8)T_L062K8T/ldscript.ld | 185 ++++
.../L052R(6-8)H_L053R(6-8)H/generic_clock.c | 42 +-
.../L052R(6-8)H_L053R(6-8)H/ldscript.ld | 185 ++++
.../L052T6Y_L052T8(F-Y)/generic_clock.c | 42 +-
.../STM32L0xx/L052T6Y_L052T8(F-Y)/ldscript.ld | 185 ++++
.../generic_clock.c | 42 +-
.../ldscript.ld | 185 ++++
.../L072K(B-Z)U_L082K(B-Z)U/generic_clock.c | 42 +-
.../L072K(B-Z)U_L082K(B-Z)U/ldscript.ld | 185 ++++
.../generic_clock.c | 42 +-
.../ldscript.ld | 185 ++++
.../generic_clock.c | 42 +-
.../ldscript.ld | 185 ++++
44 files changed, 5510 insertions(+), 42 deletions(-)
create mode 100644 variants/STM32L0xx/L010C6T/ldscript.ld
create mode 100644 variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/ldscript.ld
create mode 100644 variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/ldscript.ld
create mode 100644 variants/STM32L0xx/L010R8T/ldscript.ld
create mode 100644 variants/STM32L0xx/L011D(3-4)P_L021D4P/ldscript.ld
create mode 100644 variants/STM32L0xx/L011E(3-4)Y/ldscript.ld
create mode 100644 variants/STM32L0xx/L011F(3-4)U_L021F4U/ldscript.ld
create mode 100644 variants/STM32L0xx/L011G(3-4)U_L021G4U/ldscript.ld
create mode 100644 variants/STM32L0xx/L011K(3-4)U_L021K4U/ldscript.ld
create mode 100644 variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/ldscript.ld
create mode 100644 variants/STM32L0xx/L031E(4-6)Y_L041E6Y/ldscript.ld
create mode 100644 variants/STM32L0xx/L031F(4-6)P_L041F6P/ldscript.ld
create mode 100644 variants/STM32L0xx/L031G(4-6)U_L041G6U/ldscript.ld
create mode 100644 variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/ldscript.ld
create mode 100644 variants/STM32L0xx/L052K(6-8)T_L062K8T/ldscript.ld
create mode 100644 variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/ldscript.ld
create mode 100644 variants/STM32L0xx/L052T6Y_L052T8(F-Y)/ldscript.ld
create mode 100644 variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/ldscript.ld
create mode 100644 variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/ldscript.ld
create mode 100644 variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/ldscript.ld
create mode 100644 variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/ldscript.ld
diff --git a/README.md b/README.md
index 7d52a3de30..4cd184c95d 100644
--- a/README.md
+++ b/README.md
@@ -485,23 +485,67 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| Status | Device(s) | Name | Release | Notes |
| :----: | :-------: | ---- | :-----: | :---- |
+| :yellow_heart: | STM32L010C6 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L010F4 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L010R8 | Generic Board | **2.4.0** | |
| :green_heart: | STM32L010RB | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L011D3
STM32L011D4 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L011E3
STM32L011E4 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L011F3
STM32L011F4 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L011G3
STM32L011G4 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L011K3
STM32L011K4 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L021F4 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L021D4 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L021F4 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L021G4 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L021K4 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L031C4
STM32L031C6 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L031E4
STM32L031E6 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L031F4
STM32L031F6 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L031G4
STM32L031G6 | Generic Board | **2.4.0** | |
| :green_heart: | STM32L031K4T
STM32L031K6T | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L041C4
STM32L041C6 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L041E6 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L041F6 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L041G6 | Generic Board | **2.4.0** | |
| :green_heart: | STM32L041K6T | Generic Board | *2.0.0* | |
| :green_heart: | STM32L051C6
STM32L051C8 | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L052C6
STM32L052C8 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L052K6
STM32L052K8 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L052R6
STM32L052R8 | Generic Board | **2.4.0** | |
| :green_heart: | STM32L052R6T
STM32L052R8T | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L052T6
STM32L052T8 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L053C6
STM32L053C8 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L053R6
STM32L053R8 | Generic Board | **2.4.0** | |
| :green_heart: | STM32L053R6T
STM32L053R8T | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L062C8 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L062K8 | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L063C8 | Generic Board | **2.4.0** | |
| :green_heart: | STM32L063R8T | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L072CB
STM32L072CZ | Generic Board | **2.4.0** | |
| :green_heart: | STM32L072CBY
STM32L072CZE
STM32L072CZY | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L072KB
STM32L072KZ | Generic Board | **2.4.0** | |
| :green_heart: | STM32L072KBT
STM32L072KZT | Generic Board | *2.0.0* | |
| :green_heart: | STM32L072KZT | [ThunderPack v1.0](https://github.com/jgillick/ThunderPack) | *1.8.0* | |
| :green_heart: | STM32L072RBT | [PX-HER0](https://piconomix.com/fwlib/_p_i_c_o_n_o_m_i_x__s_t_m32__h_e_r_o__b_o_a_r_d.html) | *1.8.0* | |
+| :yellow_heart: | STM32L072RB
STM32L072RZ | Generic Board | **2.4.0** | |
| :green_heart: | STM32L072RBT
STM32L072RZT | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L072V8
STM32L072VB
STM32L072VZ | Generic Board | **2.4.0** |
+| :yellow_heart: | STM32L073CB
STM32L073CZ | Generic Board | **2.4.0** | |
| :green_heart: | STM32L073CZY | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L073RB
STM32L073RZ | Generic Board | **2.4.0** | |
| :green_heart: | STM32L073RBT
STM32L073RZT | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L073V8
STM32L073VB
STM32L073VZ | Generic Board | **2.4.0** |
+| :yellow_heart: | STM32L082CZ | Generic Board | **2.4.0** | |
| :green_heart: | STM32L082CZY | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L082KB
STM32L082KZ | Generic Board | **2.4.0** | |
| :green_heart: | STM32L082KBT
STM32L082KZT | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L083CB | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L083CZ | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L083RB | Generic Board | **2.4.0** | |
| :green_heart: | STM32L083RBT
STM32L083RZT | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L083RZ | Generic Board | **2.4.0** | |
+| :yellow_heart: | STM32L083V8
STM32L083VB
STM32L083VZ | Generic Board | **2.4.0** |
### Generic STM32L1 boards
diff --git a/boards.txt b/boards.txt
index c2dd40ccc6..9447264aea 100644
--- a/boards.txt
+++ b/boards.txt
@@ -6804,6 +6804,38 @@ GenL0.menu.pnum.PX_HER0.build.variant_h=variant_{build.board}.h
GenL0.menu.pnum.PX_HER0.build.variant=STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T
GenL0.menu.pnum.PX_HER0.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
+# Generic L010C6Tx
+GenL0.menu.pnum.GENERIC_L010C6TX=Generic L010C6Tx
+GenL0.menu.pnum.GENERIC_L010C6TX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L010C6TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L010C6TX.build.board=GENERIC_L010C6TX
+GenL0.menu.pnum.GENERIC_L010C6TX.build.product_line=STM32L010x6
+GenL0.menu.pnum.GENERIC_L010C6TX.build.variant=STM32L0xx/L010C6T
+
+# Generic L010F4Px
+GenL0.menu.pnum.GENERIC_L010F4PX=Generic L010F4Px
+GenL0.menu.pnum.GENERIC_L010F4PX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L010F4PX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L010F4PX.build.board=GENERIC_L010F4PX
+GenL0.menu.pnum.GENERIC_L010F4PX.build.product_line=STM32L010x4
+GenL0.menu.pnum.GENERIC_L010F4PX.build.variant=STM32L0xx/L010F4P_L011F(3-4)P_L021F4P
+
+# Generic L010K4Tx
+GenL0.menu.pnum.GENERIC_L010K4TX=Generic L010K4Tx
+GenL0.menu.pnum.GENERIC_L010K4TX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L010K4TX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L010K4TX.build.board=GENERIC_L010K4TX
+GenL0.menu.pnum.GENERIC_L010K4TX.build.product_line=STM32L010x4
+GenL0.menu.pnum.GENERIC_L010K4TX.build.variant=STM32L0xx/L010K4T_L011K(3-4)T_L021K4T
+
+# Generic L010R8Tx
+GenL0.menu.pnum.GENERIC_L010R8TX=Generic L010R8Tx
+GenL0.menu.pnum.GENERIC_L010R8TX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L010R8TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L010R8TX.build.board=GENERIC_L010R8TX
+GenL0.menu.pnum.GENERIC_L010R8TX.build.product_line=STM32L010x8
+GenL0.menu.pnum.GENERIC_L010R8TX.build.variant=STM32L0xx/L010R8T
+
# Generic L010RBTx
GenL0.menu.pnum.GENERIC_L010RBTX=Generic L010RBTx
GenL0.menu.pnum.GENERIC_L010RBTX.upload.maximum_size=131072
@@ -6812,6 +6844,246 @@ GenL0.menu.pnum.GENERIC_L010RBTX.build.board=GENERIC_L010RBTX
GenL0.menu.pnum.GENERIC_L010RBTX.build.product_line=STM32L010xB
GenL0.menu.pnum.GENERIC_L010RBTX.build.variant=STM32L0xx/L010RBT
+# Generic L011D3Px
+GenL0.menu.pnum.GENERIC_L011D3PX=Generic L011D3Px
+GenL0.menu.pnum.GENERIC_L011D3PX.upload.maximum_size=8192
+GenL0.menu.pnum.GENERIC_L011D3PX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011D3PX.build.board=GENERIC_L011D3PX
+GenL0.menu.pnum.GENERIC_L011D3PX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011D3PX.build.variant=STM32L0xx/L011D(3-4)P_L021D4P
+
+# Generic L011D4Px
+GenL0.menu.pnum.GENERIC_L011D4PX=Generic L011D4Px
+GenL0.menu.pnum.GENERIC_L011D4PX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L011D4PX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011D4PX.build.board=GENERIC_L011D4PX
+GenL0.menu.pnum.GENERIC_L011D4PX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011D4PX.build.variant=STM32L0xx/L011D(3-4)P_L021D4P
+
+# Generic L011E3Yx
+GenL0.menu.pnum.GENERIC_L011E3YX=Generic L011E3Yx
+GenL0.menu.pnum.GENERIC_L011E3YX.upload.maximum_size=8192
+GenL0.menu.pnum.GENERIC_L011E3YX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011E3YX.build.board=GENERIC_L011E3YX
+GenL0.menu.pnum.GENERIC_L011E3YX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011E3YX.build.variant=STM32L0xx/L011E(3-4)Y
+
+# Generic L011E4Yx
+GenL0.menu.pnum.GENERIC_L011E4YX=Generic L011E4Yx
+GenL0.menu.pnum.GENERIC_L011E4YX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L011E4YX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011E4YX.build.board=GENERIC_L011E4YX
+GenL0.menu.pnum.GENERIC_L011E4YX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011E4YX.build.variant=STM32L0xx/L011E(3-4)Y
+
+# Generic L011F3Px
+GenL0.menu.pnum.GENERIC_L011F3PX=Generic L011F3Px
+GenL0.menu.pnum.GENERIC_L011F3PX.upload.maximum_size=8192
+GenL0.menu.pnum.GENERIC_L011F3PX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011F3PX.build.board=GENERIC_L011F3PX
+GenL0.menu.pnum.GENERIC_L011F3PX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011F3PX.build.variant=STM32L0xx/L010F4P_L011F(3-4)P_L021F4P
+
+# Generic L011F4Px
+GenL0.menu.pnum.GENERIC_L011F4PX=Generic L011F4Px
+GenL0.menu.pnum.GENERIC_L011F4PX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L011F4PX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011F4PX.build.board=GENERIC_L011F4PX
+GenL0.menu.pnum.GENERIC_L011F4PX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011F4PX.build.variant=STM32L0xx/L010F4P_L011F(3-4)P_L021F4P
+
+# Generic L011F3Ux
+GenL0.menu.pnum.GENERIC_L011F3UX=Generic L011F3Ux
+GenL0.menu.pnum.GENERIC_L011F3UX.upload.maximum_size=8192
+GenL0.menu.pnum.GENERIC_L011F3UX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011F3UX.build.board=GENERIC_L011F3UX
+GenL0.menu.pnum.GENERIC_L011F3UX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011F3UX.build.variant=STM32L0xx/L011F(3-4)U_L021F4U
+
+# Generic L011F4Ux
+GenL0.menu.pnum.GENERIC_L011F4UX=Generic L011F4Ux
+GenL0.menu.pnum.GENERIC_L011F4UX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L011F4UX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011F4UX.build.board=GENERIC_L011F4UX
+GenL0.menu.pnum.GENERIC_L011F4UX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011F4UX.build.variant=STM32L0xx/L011F(3-4)U_L021F4U
+
+# Generic L011G3Ux
+GenL0.menu.pnum.GENERIC_L011G3UX=Generic L011G3Ux
+GenL0.menu.pnum.GENERIC_L011G3UX.upload.maximum_size=8192
+GenL0.menu.pnum.GENERIC_L011G3UX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011G3UX.build.board=GENERIC_L011G3UX
+GenL0.menu.pnum.GENERIC_L011G3UX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011G3UX.build.variant=STM32L0xx/L011G(3-4)U_L021G4U
+
+# Generic L011G4Ux
+GenL0.menu.pnum.GENERIC_L011G4UX=Generic L011G4Ux
+GenL0.menu.pnum.GENERIC_L011G4UX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L011G4UX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011G4UX.build.board=GENERIC_L011G4UX
+GenL0.menu.pnum.GENERIC_L011G4UX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011G4UX.build.variant=STM32L0xx/L011G(3-4)U_L021G4U
+
+# Generic L011K3Tx
+GenL0.menu.pnum.GENERIC_L011K3TX=Generic L011K3Tx
+GenL0.menu.pnum.GENERIC_L011K3TX.upload.maximum_size=8192
+GenL0.menu.pnum.GENERIC_L011K3TX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011K3TX.build.board=GENERIC_L011K3TX
+GenL0.menu.pnum.GENERIC_L011K3TX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011K3TX.build.variant=STM32L0xx/L010K4T_L011K(3-4)T_L021K4T
+
+# Generic L011K3Ux
+GenL0.menu.pnum.GENERIC_L011K3UX=Generic L011K3Ux
+GenL0.menu.pnum.GENERIC_L011K3UX.upload.maximum_size=8192
+GenL0.menu.pnum.GENERIC_L011K3UX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011K3UX.build.board=GENERIC_L011K3UX
+GenL0.menu.pnum.GENERIC_L011K3UX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011K3UX.build.variant=STM32L0xx/L011K(3-4)U_L021K4U
+
+# Generic L011K4Tx
+GenL0.menu.pnum.GENERIC_L011K4TX=Generic L011K4Tx
+GenL0.menu.pnum.GENERIC_L011K4TX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L011K4TX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011K4TX.build.board=GENERIC_L011K4TX
+GenL0.menu.pnum.GENERIC_L011K4TX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011K4TX.build.variant=STM32L0xx/L010K4T_L011K(3-4)T_L021K4T
+
+# Generic L011K4Ux
+GenL0.menu.pnum.GENERIC_L011K4UX=Generic L011K4Ux
+GenL0.menu.pnum.GENERIC_L011K4UX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L011K4UX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L011K4UX.build.board=GENERIC_L011K4UX
+GenL0.menu.pnum.GENERIC_L011K4UX.build.product_line=STM32L011xx
+GenL0.menu.pnum.GENERIC_L011K4UX.build.variant=STM32L0xx/L011K(3-4)U_L021K4U
+
+# Generic L021F4Px
+GenL0.menu.pnum.GENERIC_L021F4PX=Generic L021F4Px
+GenL0.menu.pnum.GENERIC_L021F4PX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L021F4PX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L021F4PX.build.board=GENERIC_L021F4PX
+GenL0.menu.pnum.GENERIC_L021F4PX.build.product_line=STM32L021xx
+GenL0.menu.pnum.GENERIC_L021F4PX.build.variant=STM32L0xx/L010F4P_L011F(3-4)P_L021F4P
+
+# Generic L021K4Tx
+GenL0.menu.pnum.GENERIC_L021K4TX=Generic L021K4Tx
+GenL0.menu.pnum.GENERIC_L021K4TX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L021K4TX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L021K4TX.build.board=GENERIC_L021K4TX
+GenL0.menu.pnum.GENERIC_L021K4TX.build.product_line=STM32L021xx
+GenL0.menu.pnum.GENERIC_L021K4TX.build.variant=STM32L0xx/L010K4T_L011K(3-4)T_L021K4T
+
+# Generic L021D4Px
+GenL0.menu.pnum.GENERIC_L021D4PX=Generic L021D4Px
+GenL0.menu.pnum.GENERIC_L021D4PX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L021D4PX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L021D4PX.build.board=GENERIC_L021D4PX
+GenL0.menu.pnum.GENERIC_L021D4PX.build.product_line=STM32L021xx
+GenL0.menu.pnum.GENERIC_L021D4PX.build.variant=STM32L0xx/L011D(3-4)P_L021D4P
+
+# Generic L021F4Ux
+GenL0.menu.pnum.GENERIC_L021F4UX=Generic L021F4Ux
+GenL0.menu.pnum.GENERIC_L021F4UX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L021F4UX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L021F4UX.build.board=GENERIC_L021F4UX
+GenL0.menu.pnum.GENERIC_L021F4UX.build.product_line=STM32L021xx
+GenL0.menu.pnum.GENERIC_L021F4UX.build.variant=STM32L0xx/L011F(3-4)U_L021F4U
+
+# Generic L021G4Ux
+GenL0.menu.pnum.GENERIC_L021G4UX=Generic L021G4Ux
+GenL0.menu.pnum.GENERIC_L021G4UX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L021G4UX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L021G4UX.build.board=GENERIC_L021G4UX
+GenL0.menu.pnum.GENERIC_L021G4UX.build.product_line=STM32L021xx
+GenL0.menu.pnum.GENERIC_L021G4UX.build.variant=STM32L0xx/L011G(3-4)U_L021G4U
+
+# Generic L021K4Ux
+GenL0.menu.pnum.GENERIC_L021K4UX=Generic L021K4Ux
+GenL0.menu.pnum.GENERIC_L021K4UX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L021K4UX.upload.maximum_data_size=2048
+GenL0.menu.pnum.GENERIC_L021K4UX.build.board=GENERIC_L021K4UX
+GenL0.menu.pnum.GENERIC_L021K4UX.build.product_line=STM32L021xx
+GenL0.menu.pnum.GENERIC_L021K4UX.build.variant=STM32L0xx/L011K(3-4)U_L021K4U
+
+# Generic L031C4Tx
+GenL0.menu.pnum.GENERIC_L031C4TX=Generic L031C4Tx
+GenL0.menu.pnum.GENERIC_L031C4TX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L031C4TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L031C4TX.build.board=GENERIC_L031C4TX
+GenL0.menu.pnum.GENERIC_L031C4TX.build.product_line=STM32L031xx
+GenL0.menu.pnum.GENERIC_L031C4TX.build.variant=STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)
+
+# Generic L031C6Tx
+GenL0.menu.pnum.GENERIC_L031C6TX=Generic L031C6Tx
+GenL0.menu.pnum.GENERIC_L031C6TX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L031C6TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L031C6TX.build.board=GENERIC_L031C6TX
+GenL0.menu.pnum.GENERIC_L031C6TX.build.product_line=STM32L031xx
+GenL0.menu.pnum.GENERIC_L031C6TX.build.variant=STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)
+
+# Generic L031C4Ux
+GenL0.menu.pnum.GENERIC_L031C4UX=Generic L031C4Ux
+GenL0.menu.pnum.GENERIC_L031C4UX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L031C4UX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L031C4UX.build.board=GENERIC_L031C4UX
+GenL0.menu.pnum.GENERIC_L031C4UX.build.product_line=STM32L031xx
+GenL0.menu.pnum.GENERIC_L031C4UX.build.variant=STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)
+
+# Generic L031C6Ux
+GenL0.menu.pnum.GENERIC_L031C6UX=Generic L031C6Ux
+GenL0.menu.pnum.GENERIC_L031C6UX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L031C6UX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L031C6UX.build.board=GENERIC_L031C6UX
+GenL0.menu.pnum.GENERIC_L031C6UX.build.product_line=STM32L031xx
+GenL0.menu.pnum.GENERIC_L031C6UX.build.variant=STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)
+
+# Generic L031E4Yx
+GenL0.menu.pnum.GENERIC_L031E4YX=Generic L031E4Yx
+GenL0.menu.pnum.GENERIC_L031E4YX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L031E4YX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L031E4YX.build.board=GENERIC_L031E4YX
+GenL0.menu.pnum.GENERIC_L031E4YX.build.product_line=STM32L031xx
+GenL0.menu.pnum.GENERIC_L031E4YX.build.variant=STM32L0xx/L031E(4-6)Y_L041E6Y
+
+# Generic L031E6Yx
+GenL0.menu.pnum.GENERIC_L031E6YX=Generic L031E6Yx
+GenL0.menu.pnum.GENERIC_L031E6YX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L031E6YX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L031E6YX.build.board=GENERIC_L031E6YX
+GenL0.menu.pnum.GENERIC_L031E6YX.build.product_line=STM32L031xx
+GenL0.menu.pnum.GENERIC_L031E6YX.build.variant=STM32L0xx/L031E(4-6)Y_L041E6Y
+
+# Generic L031F4Px
+GenL0.menu.pnum.GENERIC_L031F4PX=Generic L031F4Px
+GenL0.menu.pnum.GENERIC_L031F4PX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L031F4PX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L031F4PX.build.board=GENERIC_L031F4PX
+GenL0.menu.pnum.GENERIC_L031F4PX.build.product_line=STM32L031xx
+GenL0.menu.pnum.GENERIC_L031F4PX.build.variant=STM32L0xx/L031F(4-6)P_L041F6P
+
+# Generic L031F6Px
+GenL0.menu.pnum.GENERIC_L031F6PX=Generic L031F6Px
+GenL0.menu.pnum.GENERIC_L031F6PX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L031F6PX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L031F6PX.build.board=GENERIC_L031F6PX
+GenL0.menu.pnum.GENERIC_L031F6PX.build.product_line=STM32L031xx
+GenL0.menu.pnum.GENERIC_L031F6PX.build.variant=STM32L0xx/L031F(4-6)P_L041F6P
+
+# Generic L031G4Ux
+GenL0.menu.pnum.GENERIC_L031G4UX=Generic L031G4Ux
+GenL0.menu.pnum.GENERIC_L031G4UX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L031G4UX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L031G4UX.build.board=GENERIC_L031G4UX
+GenL0.menu.pnum.GENERIC_L031G4UX.build.product_line=STM32L031xx
+GenL0.menu.pnum.GENERIC_L031G4UX.build.variant=STM32L0xx/L031G(4-6)U_L041G6U
+
+# Generic L031G6Ux
+GenL0.menu.pnum.GENERIC_L031G6UX=Generic L031G6Ux
+GenL0.menu.pnum.GENERIC_L031G6UX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L031G6UX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L031G6UX.build.board=GENERIC_L031G6UX
+GenL0.menu.pnum.GENERIC_L031G6UX.build.product_line=STM32L031xx
+GenL0.menu.pnum.GENERIC_L031G6UX.build.variant=STM32L0xx/L031G(4-6)U_L041G6U
+
# Generic L031K4Tx
GenL0.menu.pnum.GENERIC_L031K4TX=Generic L031K4Tx
GenL0.menu.pnum.GENERIC_L031K4TX.upload.maximum_size=16384
@@ -6828,6 +7100,54 @@ GenL0.menu.pnum.GENERIC_L031K6TX.build.board=GENERIC_L031K6TX
GenL0.menu.pnum.GENERIC_L031K6TX.build.product_line=STM32L031xx
GenL0.menu.pnum.GENERIC_L031K6TX.build.variant=STM32L0xx/L031K(4-6)T_L041K6T
+# Generic L041C4Tx
+GenL0.menu.pnum.GENERIC_L041C4TX=Generic L041C4Tx
+GenL0.menu.pnum.GENERIC_L041C4TX.upload.maximum_size=16384
+GenL0.menu.pnum.GENERIC_L041C4TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L041C4TX.build.board=GENERIC_L041C4TX
+GenL0.menu.pnum.GENERIC_L041C4TX.build.product_line=STM32L041xx
+GenL0.menu.pnum.GENERIC_L041C4TX.build.variant=STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)
+
+# Generic L041C6Tx
+GenL0.menu.pnum.GENERIC_L041C6TX=Generic L041C6Tx
+GenL0.menu.pnum.GENERIC_L041C6TX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L041C6TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L041C6TX.build.board=GENERIC_L041C6TX
+GenL0.menu.pnum.GENERIC_L041C6TX.build.product_line=STM32L041xx
+GenL0.menu.pnum.GENERIC_L041C6TX.build.variant=STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)
+
+# Generic L041C6Ux
+GenL0.menu.pnum.GENERIC_L041C6UX=Generic L041C6Ux
+GenL0.menu.pnum.GENERIC_L041C6UX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L041C6UX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L041C6UX.build.board=GENERIC_L041C6UX
+GenL0.menu.pnum.GENERIC_L041C6UX.build.product_line=STM32L041xx
+GenL0.menu.pnum.GENERIC_L041C6UX.build.variant=STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)
+
+# Generic L041E6Yx
+GenL0.menu.pnum.GENERIC_L041E6YX=Generic L041E6Yx
+GenL0.menu.pnum.GENERIC_L041E6YX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L041E6YX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L041E6YX.build.board=GENERIC_L041E6YX
+GenL0.menu.pnum.GENERIC_L041E6YX.build.product_line=STM32L041xx
+GenL0.menu.pnum.GENERIC_L041E6YX.build.variant=STM32L0xx/L031E(4-6)Y_L041E6Y
+
+# Generic L041F6Px
+GenL0.menu.pnum.GENERIC_L041F6PX=Generic L041F6Px
+GenL0.menu.pnum.GENERIC_L041F6PX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L041F6PX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L041F6PX.build.board=GENERIC_L041F6PX
+GenL0.menu.pnum.GENERIC_L041F6PX.build.product_line=STM32L041xx
+GenL0.menu.pnum.GENERIC_L041F6PX.build.variant=STM32L0xx/L031F(4-6)P_L041F6P
+
+# Generic L041G6Ux
+GenL0.menu.pnum.GENERIC_L041G6UX=Generic L041G6Ux
+GenL0.menu.pnum.GENERIC_L041G6UX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L041G6UX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L041G6UX.build.board=GENERIC_L041G6UX
+GenL0.menu.pnum.GENERIC_L041G6UX.build.product_line=STM32L041xx
+GenL0.menu.pnum.GENERIC_L041G6UX.build.variant=STM32L0xx/L031G(4-6)U_L041G6U
+
# Generic L041K6Tx
GenL0.menu.pnum.GENERIC_L041K6TX=Generic L041K6Tx
GenL0.menu.pnum.GENERIC_L041K6TX.upload.maximum_size=32768
@@ -6868,6 +7188,70 @@ GenL0.menu.pnum.GENERIC_L051C8UX.build.board=GENERIC_L051C8UX
GenL0.menu.pnum.GENERIC_L051C8UX.build.product_line=STM32L051xx
GenL0.menu.pnum.GENERIC_L051C8UX.build.variant=STM32L0xx/L051C(6-8)(T-U)
+# Generic L052C6Tx
+GenL0.menu.pnum.GENERIC_L052C6TX=Generic L052C6Tx
+GenL0.menu.pnum.GENERIC_L052C6TX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L052C6TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L052C6TX.build.board=GENERIC_L052C6TX
+GenL0.menu.pnum.GENERIC_L052C6TX.build.product_line=STM32L052xx
+GenL0.menu.pnum.GENERIC_L052C6TX.build.variant=STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)
+
+# Generic L052C8Tx
+GenL0.menu.pnum.GENERIC_L052C8TX=Generic L052C8Tx
+GenL0.menu.pnum.GENERIC_L052C8TX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L052C8TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L052C8TX.build.board=GENERIC_L052C8TX
+GenL0.menu.pnum.GENERIC_L052C8TX.build.product_line=STM32L052xx
+GenL0.menu.pnum.GENERIC_L052C8TX.build.variant=STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)
+
+# Generic L052C6Ux
+GenL0.menu.pnum.GENERIC_L052C6UX=Generic L052C6Ux
+GenL0.menu.pnum.GENERIC_L052C6UX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L052C6UX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L052C6UX.build.board=GENERIC_L052C6UX
+GenL0.menu.pnum.GENERIC_L052C6UX.build.product_line=STM32L052xx
+GenL0.menu.pnum.GENERIC_L052C6UX.build.variant=STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)
+
+# Generic L052C8Ux
+GenL0.menu.pnum.GENERIC_L052C8UX=Generic L052C8Ux
+GenL0.menu.pnum.GENERIC_L052C8UX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L052C8UX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L052C8UX.build.board=GENERIC_L052C8UX
+GenL0.menu.pnum.GENERIC_L052C8UX.build.product_line=STM32L052xx
+GenL0.menu.pnum.GENERIC_L052C8UX.build.variant=STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)
+
+# Generic L052K6Tx
+GenL0.menu.pnum.GENERIC_L052K6TX=Generic L052K6Tx
+GenL0.menu.pnum.GENERIC_L052K6TX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L052K6TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L052K6TX.build.board=GENERIC_L052K6TX
+GenL0.menu.pnum.GENERIC_L052K6TX.build.product_line=STM32L052xx
+GenL0.menu.pnum.GENERIC_L052K6TX.build.variant=STM32L0xx/L052K(6-8)T_L062K8T
+
+# Generic L052K8Tx
+GenL0.menu.pnum.GENERIC_L052K8TX=Generic L052K8Tx
+GenL0.menu.pnum.GENERIC_L052K8TX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L052K8TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L052K8TX.build.board=GENERIC_L052K8TX
+GenL0.menu.pnum.GENERIC_L052K8TX.build.product_line=STM32L052xx
+GenL0.menu.pnum.GENERIC_L052K8TX.build.variant=STM32L0xx/L052K(6-8)T_L062K8T
+
+# Generic L052R6Hx
+GenL0.menu.pnum.GENERIC_L052R6HX=Generic L052R6Hx
+GenL0.menu.pnum.GENERIC_L052R6HX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L052R6HX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L052R6HX.build.board=GENERIC_L052R6HX
+GenL0.menu.pnum.GENERIC_L052R6HX.build.product_line=STM32L052xx
+GenL0.menu.pnum.GENERIC_L052R6HX.build.variant=STM32L0xx/L052R(6-8)H_L053R(6-8)H
+
+# Generic L052R8Hx
+GenL0.menu.pnum.GENERIC_L052R8HX=Generic L052R8Hx
+GenL0.menu.pnum.GENERIC_L052R8HX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L052R8HX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L052R8HX.build.board=GENERIC_L052R8HX
+GenL0.menu.pnum.GENERIC_L052R8HX.build.product_line=STM32L052xx
+GenL0.menu.pnum.GENERIC_L052R8HX.build.variant=STM32L0xx/L052R(6-8)H_L053R(6-8)H
+
# Generic L052R6Tx
GenL0.menu.pnum.GENERIC_L052R6TX=Generic L052R6Tx
GenL0.menu.pnum.GENERIC_L052R6TX.upload.maximum_size=32768
@@ -6884,6 +7268,78 @@ GenL0.menu.pnum.GENERIC_L052R8TX.build.board=GENERIC_L052R8TX
GenL0.menu.pnum.GENERIC_L052R8TX.build.product_line=STM32L052xx
GenL0.menu.pnum.GENERIC_L052R8TX.build.variant=STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T
+# Generic L052T6Yx
+GenL0.menu.pnum.GENERIC_L052T6YX=Generic L052T6Yx
+GenL0.menu.pnum.GENERIC_L052T6YX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L052T6YX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L052T6YX.build.board=GENERIC_L052T6YX
+GenL0.menu.pnum.GENERIC_L052T6YX.build.product_line=STM32L052xx
+GenL0.menu.pnum.GENERIC_L052T6YX.build.variant=STM32L0xx/L052T6Y_L052T8(F-Y)
+
+# Generic L052T8Yx
+GenL0.menu.pnum.GENERIC_L052T8YX=Generic L052T8Yx
+GenL0.menu.pnum.GENERIC_L052T8YX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L052T8YX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L052T8YX.build.board=GENERIC_L052T8YX
+GenL0.menu.pnum.GENERIC_L052T8YX.build.product_line=STM32L052xx
+GenL0.menu.pnum.GENERIC_L052T8YX.build.variant=STM32L0xx/L052T6Y_L052T8(F-Y)
+
+# Generic L052T8Fx
+GenL0.menu.pnum.GENERIC_L052T8FX=Generic L052T8Fx
+GenL0.menu.pnum.GENERIC_L052T8FX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L052T8FX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L052T8FX.build.board=GENERIC_L052T8FX
+GenL0.menu.pnum.GENERIC_L052T8FX.build.product_line=STM32L052xx
+GenL0.menu.pnum.GENERIC_L052T8FX.build.variant=STM32L0xx/L052T6Y_L052T8(F-Y)
+
+# Generic L053C6Tx
+GenL0.menu.pnum.GENERIC_L053C6TX=Generic L053C6Tx
+GenL0.menu.pnum.GENERIC_L053C6TX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L053C6TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L053C6TX.build.board=GENERIC_L053C6TX
+GenL0.menu.pnum.GENERIC_L053C6TX.build.product_line=STM32L053xx
+GenL0.menu.pnum.GENERIC_L053C6TX.build.variant=STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)
+
+# Generic L053C8Tx
+GenL0.menu.pnum.GENERIC_L053C8TX=Generic L053C8Tx
+GenL0.menu.pnum.GENERIC_L053C8TX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L053C8TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L053C8TX.build.board=GENERIC_L053C8TX
+GenL0.menu.pnum.GENERIC_L053C8TX.build.product_line=STM32L053xx
+GenL0.menu.pnum.GENERIC_L053C8TX.build.variant=STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)
+
+# Generic L053C6Ux
+GenL0.menu.pnum.GENERIC_L053C6UX=Generic L053C6Ux
+GenL0.menu.pnum.GENERIC_L053C6UX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L053C6UX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L053C6UX.build.board=GENERIC_L053C6UX
+GenL0.menu.pnum.GENERIC_L053C6UX.build.product_line=STM32L053xx
+GenL0.menu.pnum.GENERIC_L053C6UX.build.variant=STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)
+
+# Generic L053C8Ux
+GenL0.menu.pnum.GENERIC_L053C8UX=Generic L053C8Ux
+GenL0.menu.pnum.GENERIC_L053C8UX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L053C8UX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L053C8UX.build.board=GENERIC_L053C8UX
+GenL0.menu.pnum.GENERIC_L053C8UX.build.product_line=STM32L053xx
+GenL0.menu.pnum.GENERIC_L053C8UX.build.variant=STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)
+
+# Generic L053R6Hx
+GenL0.menu.pnum.GENERIC_L053R6HX=Generic L053R6Hx
+GenL0.menu.pnum.GENERIC_L053R6HX.upload.maximum_size=32768
+GenL0.menu.pnum.GENERIC_L053R6HX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L053R6HX.build.board=GENERIC_L053R6HX
+GenL0.menu.pnum.GENERIC_L053R6HX.build.product_line=STM32L053xx
+GenL0.menu.pnum.GENERIC_L053R6HX.build.variant=STM32L0xx/L052R(6-8)H_L053R(6-8)H
+
+# Generic L053R8Hx
+GenL0.menu.pnum.GENERIC_L053R8HX=Generic L053R8Hx
+GenL0.menu.pnum.GENERIC_L053R8HX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L053R8HX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L053R8HX.build.board=GENERIC_L053R8HX
+GenL0.menu.pnum.GENERIC_L053R8HX.build.product_line=STM32L053xx
+GenL0.menu.pnum.GENERIC_L053R8HX.build.variant=STM32L0xx/L052R(6-8)H_L053R(6-8)H
+
# Generic L053R6Tx
GenL0.menu.pnum.GENERIC_L053R6TX=Generic L053R6Tx
GenL0.menu.pnum.GENERIC_L053R6TX.upload.maximum_size=32768
@@ -6900,6 +7356,38 @@ GenL0.menu.pnum.GENERIC_L053R8TX.build.board=GENERIC_L053R8TX
GenL0.menu.pnum.GENERIC_L053R8TX.build.product_line=STM32L053xx
GenL0.menu.pnum.GENERIC_L053R8TX.build.variant=STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T
+# Generic L062C8Ux
+GenL0.menu.pnum.GENERIC_L062C8UX=Generic L062C8Ux
+GenL0.menu.pnum.GENERIC_L062C8UX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L062C8UX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L062C8UX.build.board=GENERIC_L062C8UX
+GenL0.menu.pnum.GENERIC_L062C8UX.build.product_line=STM32L062xx
+GenL0.menu.pnum.GENERIC_L062C8UX.build.variant=STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)
+
+# Generic L062K8Tx
+GenL0.menu.pnum.GENERIC_L062K8TX=Generic L062K8Tx
+GenL0.menu.pnum.GENERIC_L062K8TX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L062K8TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L062K8TX.build.board=GENERIC_L062K8TX
+GenL0.menu.pnum.GENERIC_L062K8TX.build.product_line=STM32L062xx
+GenL0.menu.pnum.GENERIC_L062K8TX.build.variant=STM32L0xx/L052K(6-8)T_L062K8T
+
+# Generic L063C8Tx
+GenL0.menu.pnum.GENERIC_L063C8TX=Generic L063C8Tx
+GenL0.menu.pnum.GENERIC_L063C8TX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L063C8TX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L063C8TX.build.board=GENERIC_L063C8TX
+GenL0.menu.pnum.GENERIC_L063C8TX.build.product_line=STM32L063xx
+GenL0.menu.pnum.GENERIC_L063C8TX.build.variant=STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)
+
+# Generic L063C8Ux
+GenL0.menu.pnum.GENERIC_L063C8UX=Generic L063C8Ux
+GenL0.menu.pnum.GENERIC_L063C8UX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L063C8UX.upload.maximum_data_size=8192
+GenL0.menu.pnum.GENERIC_L063C8UX.build.board=GENERIC_L063C8UX
+GenL0.menu.pnum.GENERIC_L063C8UX.build.product_line=STM32L063xx
+GenL0.menu.pnum.GENERIC_L063C8UX.build.variant=STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)
+
# Generic L063R8Tx
GenL0.menu.pnum.GENERIC_L063R8TX=Generic L063R8Tx
GenL0.menu.pnum.GENERIC_L063R8TX.upload.maximum_size=65536
@@ -6908,6 +7396,22 @@ GenL0.menu.pnum.GENERIC_L063R8TX.build.board=GENERIC_L063R8TX
GenL0.menu.pnum.GENERIC_L063R8TX.build.product_line=STM32L063xx
GenL0.menu.pnum.GENERIC_L063R8TX.build.variant=STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T
+# Generic L072CBTx
+GenL0.menu.pnum.GENERIC_L072CBTX=Generic L072CBTx
+GenL0.menu.pnum.GENERIC_L072CBTX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L072CBTX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072CBTX.build.board=GENERIC_L072CBTX
+GenL0.menu.pnum.GENERIC_L072CBTX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072CBTX.build.variant=STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)
+
+# Generic L072CBUx
+GenL0.menu.pnum.GENERIC_L072CBUX=Generic L072CBUx
+GenL0.menu.pnum.GENERIC_L072CBUX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L072CBUX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072CBUX.build.board=GENERIC_L072CBUX
+GenL0.menu.pnum.GENERIC_L072CBUX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072CBUX.build.variant=STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)
+
# Generic L072CBYx
GenL0.menu.pnum.GENERIC_L072CBYX=Generic L072CBYx
GenL0.menu.pnum.GENERIC_L072CBYX.upload.maximum_size=131072
@@ -6924,6 +7428,22 @@ GenL0.menu.pnum.GENERIC_L072CZEX.build.board=GENERIC_L072CZEX
GenL0.menu.pnum.GENERIC_L072CZEX.build.product_line=STM32L072xx
GenL0.menu.pnum.GENERIC_L072CZEX.build.variant=STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY
+# Generic L072CZTx
+GenL0.menu.pnum.GENERIC_L072CZTX=Generic L072CZTx
+GenL0.menu.pnum.GENERIC_L072CZTX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L072CZTX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072CZTX.build.board=GENERIC_L072CZTX
+GenL0.menu.pnum.GENERIC_L072CZTX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072CZTX.build.variant=STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)
+
+# Generic L072CZUx
+GenL0.menu.pnum.GENERIC_L072CZUX=Generic L072CZUx
+GenL0.menu.pnum.GENERIC_L072CZUX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L072CZUX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072CZUX.build.board=GENERIC_L072CZUX
+GenL0.menu.pnum.GENERIC_L072CZUX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072CZUX.build.variant=STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)
+
# Generic L072CZYx
GenL0.menu.pnum.GENERIC_L072CZYX=Generic L072CZYx
GenL0.menu.pnum.GENERIC_L072CZYX.upload.maximum_size=196608
@@ -6940,6 +7460,14 @@ GenL0.menu.pnum.GENERIC_L072KBTX.build.board=GENERIC_L072KBTX
GenL0.menu.pnum.GENERIC_L072KBTX.build.product_line=STM32L072xx
GenL0.menu.pnum.GENERIC_L072KBTX.build.variant=STM32L0xx/L072K(B-Z)T_L082K(B-Z)T
+# Generic L072KBUx
+GenL0.menu.pnum.GENERIC_L072KBUX=Generic L072KBUx
+GenL0.menu.pnum.GENERIC_L072KBUX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L072KBUX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072KBUX.build.board=GENERIC_L072KBUX
+GenL0.menu.pnum.GENERIC_L072KBUX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072KBUX.build.variant=STM32L0xx/L072K(B-Z)U_L082K(B-Z)U
+
# Generic L072KZTx
GenL0.menu.pnum.GENERIC_L072KZTX=Generic L072KZTx
GenL0.menu.pnum.GENERIC_L072KZTX.upload.maximum_size=196608
@@ -6948,6 +7476,30 @@ GenL0.menu.pnum.GENERIC_L072KZTX.build.board=GENERIC_L072KZTX
GenL0.menu.pnum.GENERIC_L072KZTX.build.product_line=STM32L072xx
GenL0.menu.pnum.GENERIC_L072KZTX.build.variant=STM32L0xx/L072K(B-Z)T_L082K(B-Z)T
+# Generic L072KZUx
+GenL0.menu.pnum.GENERIC_L072KZUX=Generic L072KZUx
+GenL0.menu.pnum.GENERIC_L072KZUX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L072KZUX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072KZUX.build.board=GENERIC_L072KZUX
+GenL0.menu.pnum.GENERIC_L072KZUX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072KZUX.build.variant=STM32L0xx/L072K(B-Z)U_L082K(B-Z)U
+
+# Generic L072RBHx
+GenL0.menu.pnum.GENERIC_L072RBHX=Generic L072RBHx
+GenL0.menu.pnum.GENERIC_L072RBHX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L072RBHX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072RBHX.build.board=GENERIC_L072RBHX
+GenL0.menu.pnum.GENERIC_L072RBHX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072RBHX.build.variant=STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H
+
+# Generic L072RBIx
+GenL0.menu.pnum.GENERIC_L072RBIX=Generic L072RBIx
+GenL0.menu.pnum.GENERIC_L072RBIX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L072RBIX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072RBIX.build.board=GENERIC_L072RBIX
+GenL0.menu.pnum.GENERIC_L072RBIX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072RBIX.build.variant=STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H
+
# Generic L072RBTx
GenL0.menu.pnum.GENERIC_L072RBTX=Generic L072RBTx
GenL0.menu.pnum.GENERIC_L072RBTX.upload.maximum_size=131072
@@ -6956,6 +7508,22 @@ GenL0.menu.pnum.GENERIC_L072RBTX.build.board=GENERIC_L072RBTX
GenL0.menu.pnum.GENERIC_L072RBTX.build.product_line=STM32L072xx
GenL0.menu.pnum.GENERIC_L072RBTX.build.variant=STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T
+# Generic L072RZHx
+GenL0.menu.pnum.GENERIC_L072RZHX=Generic L072RZHx
+GenL0.menu.pnum.GENERIC_L072RZHX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L072RZHX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072RZHX.build.board=GENERIC_L072RZHX
+GenL0.menu.pnum.GENERIC_L072RZHX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072RZHX.build.variant=STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H
+
+# Generic L072RZIx
+GenL0.menu.pnum.GENERIC_L072RZIX=Generic L072RZIx
+GenL0.menu.pnum.GENERIC_L072RZIX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L072RZIX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072RZIX.build.board=GENERIC_L072RZIX
+GenL0.menu.pnum.GENERIC_L072RZIX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072RZIX.build.variant=STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H
+
# Generic L072RZTx
GenL0.menu.pnum.GENERIC_L072RZTX=Generic L072RZTx
GenL0.menu.pnum.GENERIC_L072RZTX.upload.maximum_size=196608
@@ -6964,6 +7532,86 @@ GenL0.menu.pnum.GENERIC_L072RZTX.build.board=GENERIC_L072RZTX
GenL0.menu.pnum.GENERIC_L072RZTX.build.product_line=STM32L072xx
GenL0.menu.pnum.GENERIC_L072RZTX.build.variant=STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T
+# Generic L072VBIx
+GenL0.menu.pnum.GENERIC_L072VBIX=Generic L072VBIx
+GenL0.menu.pnum.GENERIC_L072VBIX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L072VBIX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072VBIX.build.board=GENERIC_L072VBIX
+GenL0.menu.pnum.GENERIC_L072VBIX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072VBIX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L072VZIx
+GenL0.menu.pnum.GENERIC_L072VZIX=Generic L072VZIx
+GenL0.menu.pnum.GENERIC_L072VZIX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L072VZIX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072VZIX.build.board=GENERIC_L072VZIX
+GenL0.menu.pnum.GENERIC_L072VZIX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072VZIX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L072VBTx
+GenL0.menu.pnum.GENERIC_L072VBTX=Generic L072VBTx
+GenL0.menu.pnum.GENERIC_L072VBTX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L072VBTX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072VBTX.build.board=GENERIC_L072VBTX
+GenL0.menu.pnum.GENERIC_L072VBTX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072VBTX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L072VZTx
+GenL0.menu.pnum.GENERIC_L072VZTX=Generic L072VZTx
+GenL0.menu.pnum.GENERIC_L072VZTX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L072VZTX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072VZTX.build.board=GENERIC_L072VZTX
+GenL0.menu.pnum.GENERIC_L072VZTX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072VZTX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L072V8Ix
+GenL0.menu.pnum.GENERIC_L072V8IX=Generic L072V8Ix
+GenL0.menu.pnum.GENERIC_L072V8IX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L072V8IX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072V8IX.build.board=GENERIC_L072V8IX
+GenL0.menu.pnum.GENERIC_L072V8IX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072V8IX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L072V8Tx
+GenL0.menu.pnum.GENERIC_L072V8TX=Generic L072V8Tx
+GenL0.menu.pnum.GENERIC_L072V8TX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L072V8TX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L072V8TX.build.board=GENERIC_L072V8TX
+GenL0.menu.pnum.GENERIC_L072V8TX.build.product_line=STM32L072xx
+GenL0.menu.pnum.GENERIC_L072V8TX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L073CBTx
+GenL0.menu.pnum.GENERIC_L073CBTX=Generic L073CBTx
+GenL0.menu.pnum.GENERIC_L073CBTX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L073CBTX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L073CBTX.build.board=GENERIC_L073CBTX
+GenL0.menu.pnum.GENERIC_L073CBTX.build.product_line=STM32L073xx
+GenL0.menu.pnum.GENERIC_L073CBTX.build.variant=STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)
+
+# Generic L073CBUx
+GenL0.menu.pnum.GENERIC_L073CBUX=Generic L073CBUx
+GenL0.menu.pnum.GENERIC_L073CBUX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L073CBUX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L073CBUX.build.board=GENERIC_L073CBUX
+GenL0.menu.pnum.GENERIC_L073CBUX.build.product_line=STM32L073xx
+GenL0.menu.pnum.GENERIC_L073CBUX.build.variant=STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)
+
+# Generic L073CZTx
+GenL0.menu.pnum.GENERIC_L073CZTX=Generic L073CZTx
+GenL0.menu.pnum.GENERIC_L073CZTX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L073CZTX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L073CZTX.build.board=GENERIC_L073CZTX
+GenL0.menu.pnum.GENERIC_L073CZTX.build.product_line=STM32L073xx
+GenL0.menu.pnum.GENERIC_L073CZTX.build.variant=STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)
+
+# Generic L073CZUx
+GenL0.menu.pnum.GENERIC_L073CZUX=Generic L073CZUx
+GenL0.menu.pnum.GENERIC_L073CZUX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L073CZUX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L073CZUX.build.board=GENERIC_L073CZUX
+GenL0.menu.pnum.GENERIC_L073CZUX.build.product_line=STM32L073xx
+GenL0.menu.pnum.GENERIC_L073CZUX.build.variant=STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)
+
# Generic L073CZYx
GenL0.menu.pnum.GENERIC_L073CZYX=Generic L073CZYx
GenL0.menu.pnum.GENERIC_L073CZYX.upload.maximum_size=196608
@@ -6980,6 +7628,30 @@ GenL0.menu.pnum.GENERIC_L073RBTX.build.board=GENERIC_L073RBTX
GenL0.menu.pnum.GENERIC_L073RBTX.build.product_line=STM32L073xx
GenL0.menu.pnum.GENERIC_L073RBTX.build.variant=STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T
+# Generic L073RBHx
+GenL0.menu.pnum.GENERIC_L073RBHX=Generic L073RBHx
+GenL0.menu.pnum.GENERIC_L073RBHX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L073RBHX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L073RBHX.build.board=GENERIC_L073RBHX
+GenL0.menu.pnum.GENERIC_L073RBHX.build.product_line=STM32L073xx
+GenL0.menu.pnum.GENERIC_L073RBHX.build.variant=STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H
+
+# Generic L073RZHx
+GenL0.menu.pnum.GENERIC_L073RZHX=Generic L073RZHx
+GenL0.menu.pnum.GENERIC_L073RZHX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L073RZHX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L073RZHX.build.board=GENERIC_L073RZHX
+GenL0.menu.pnum.GENERIC_L073RZHX.build.product_line=STM32L073xx
+GenL0.menu.pnum.GENERIC_L073RZHX.build.variant=STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H
+
+# Generic L073RZIx
+GenL0.menu.pnum.GENERIC_L073RZIX=Generic L073RZIx
+GenL0.menu.pnum.GENERIC_L073RZIX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L073RZIX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L073RZIX.build.board=GENERIC_L073RZIX
+GenL0.menu.pnum.GENERIC_L073RZIX.build.product_line=STM32L073xx
+GenL0.menu.pnum.GENERIC_L073RZIX.build.variant=STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H
+
# Generic L073RZTx
GenL0.menu.pnum.GENERIC_L073RZTX=Generic L073RZTx
GenL0.menu.pnum.GENERIC_L073RZTX.upload.maximum_size=196608
@@ -6988,6 +7660,62 @@ GenL0.menu.pnum.GENERIC_L073RZTX.build.board=GENERIC_L073RZTX
GenL0.menu.pnum.GENERIC_L073RZTX.build.product_line=STM32L073xx
GenL0.menu.pnum.GENERIC_L073RZTX.build.variant=STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T
+# Generic L073VBIx
+GenL0.menu.pnum.GENERIC_L073VBIX=Generic L073VBIx
+GenL0.menu.pnum.GENERIC_L073VBIX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L073VBIX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L073VBIX.build.board=GENERIC_L073VBIX
+GenL0.menu.pnum.GENERIC_L073VBIX.build.product_line=STM32L073xx
+GenL0.menu.pnum.GENERIC_L073VBIX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L073VZIx
+GenL0.menu.pnum.GENERIC_L073VZIX=Generic L073VZIx
+GenL0.menu.pnum.GENERIC_L073VZIX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L073VZIX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L073VZIX.build.board=GENERIC_L073VZIX
+GenL0.menu.pnum.GENERIC_L073VZIX.build.product_line=STM32L073xx
+GenL0.menu.pnum.GENERIC_L073VZIX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L073VBTx
+GenL0.menu.pnum.GENERIC_L073VBTX=Generic L073VBTx
+GenL0.menu.pnum.GENERIC_L073VBTX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L073VBTX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L073VBTX.build.board=GENERIC_L073VBTX
+GenL0.menu.pnum.GENERIC_L073VBTX.build.product_line=STM32L073xx
+GenL0.menu.pnum.GENERIC_L073VBTX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L073VZTx
+GenL0.menu.pnum.GENERIC_L073VZTX=Generic L073VZTx
+GenL0.menu.pnum.GENERIC_L073VZTX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L073VZTX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L073VZTX.build.board=GENERIC_L073VZTX
+GenL0.menu.pnum.GENERIC_L073VZTX.build.product_line=STM32L073xx
+GenL0.menu.pnum.GENERIC_L073VZTX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L073V8Ix
+GenL0.menu.pnum.GENERIC_L073V8IX=Generic L073V8Ix
+GenL0.menu.pnum.GENERIC_L073V8IX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L073V8IX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L073V8IX.build.board=GENERIC_L073V8IX
+GenL0.menu.pnum.GENERIC_L073V8IX.build.product_line=STM32L073xx
+GenL0.menu.pnum.GENERIC_L073V8IX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L073V8Tx
+GenL0.menu.pnum.GENERIC_L073V8TX=Generic L073V8Tx
+GenL0.menu.pnum.GENERIC_L073V8TX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L073V8TX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L073V8TX.build.board=GENERIC_L073V8TX
+GenL0.menu.pnum.GENERIC_L073V8TX.build.product_line=STM32L073xx
+GenL0.menu.pnum.GENERIC_L073V8TX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L082CZUx
+GenL0.menu.pnum.GENERIC_L082CZUX=Generic L082CZUx
+GenL0.menu.pnum.GENERIC_L082CZUX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L082CZUX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L082CZUX.build.board=GENERIC_L082CZUX
+GenL0.menu.pnum.GENERIC_L082CZUX.build.product_line=STM32L082xx
+GenL0.menu.pnum.GENERIC_L082CZUX.build.variant=STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)
+
# Generic L082CZYx
GenL0.menu.pnum.GENERIC_L082CZYX=Generic L082CZYx
GenL0.menu.pnum.GENERIC_L082CZYX.upload.maximum_size=196608
@@ -7004,6 +7732,14 @@ GenL0.menu.pnum.GENERIC_L082KBTX.build.board=GENERIC_L082KBTX
GenL0.menu.pnum.GENERIC_L082KBTX.build.product_line=STM32L082xx
GenL0.menu.pnum.GENERIC_L082KBTX.build.variant=STM32L0xx/L072K(B-Z)T_L082K(B-Z)T
+# Generic L082KBUx
+GenL0.menu.pnum.GENERIC_L082KBUX=Generic L082KBUx
+GenL0.menu.pnum.GENERIC_L082KBUX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L082KBUX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L082KBUX.build.board=GENERIC_L082KBUX
+GenL0.menu.pnum.GENERIC_L082KBUX.build.product_line=STM32L082xx
+GenL0.menu.pnum.GENERIC_L082KBUX.build.variant=STM32L0xx/L072K(B-Z)U_L082K(B-Z)U
+
# Generic L082KZTx
GenL0.menu.pnum.GENERIC_L082KZTX=Generic L082KZTx
GenL0.menu.pnum.GENERIC_L082KZTX.upload.maximum_size=196608
@@ -7012,6 +7748,46 @@ GenL0.menu.pnum.GENERIC_L082KZTX.build.board=GENERIC_L082KZTX
GenL0.menu.pnum.GENERIC_L082KZTX.build.product_line=STM32L082xx
GenL0.menu.pnum.GENERIC_L082KZTX.build.variant=STM32L0xx/L072K(B-Z)T_L082K(B-Z)T
+# Generic L082KZUx
+GenL0.menu.pnum.GENERIC_L082KZUX=Generic L082KZUx
+GenL0.menu.pnum.GENERIC_L082KZUX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L082KZUX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L082KZUX.build.board=GENERIC_L082KZUX
+GenL0.menu.pnum.GENERIC_L082KZUX.build.product_line=STM32L082xx
+GenL0.menu.pnum.GENERIC_L082KZUX.build.variant=STM32L0xx/L072K(B-Z)U_L082K(B-Z)U
+
+# Generic L083CBTx
+GenL0.menu.pnum.GENERIC_L083CBTX=Generic L083CBTx
+GenL0.menu.pnum.GENERIC_L083CBTX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L083CBTX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L083CBTX.build.board=GENERIC_L083CBTX
+GenL0.menu.pnum.GENERIC_L083CBTX.build.product_line=STM32L083xx
+GenL0.menu.pnum.GENERIC_L083CBTX.build.variant=STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)
+
+# Generic L083CZTx
+GenL0.menu.pnum.GENERIC_L083CZTX=Generic L083CZTx
+GenL0.menu.pnum.GENERIC_L083CZTX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L083CZTX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L083CZTX.build.board=GENERIC_L083CZTX
+GenL0.menu.pnum.GENERIC_L083CZTX.build.product_line=STM32L083xx
+GenL0.menu.pnum.GENERIC_L083CZTX.build.variant=STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)
+
+# Generic L083CZUx
+GenL0.menu.pnum.GENERIC_L083CZUX=Generic L083CZUx
+GenL0.menu.pnum.GENERIC_L083CZUX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L083CZUX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L083CZUX.build.board=GENERIC_L083CZUX
+GenL0.menu.pnum.GENERIC_L083CZUX.build.product_line=STM32L083xx
+GenL0.menu.pnum.GENERIC_L083CZUX.build.variant=STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)
+
+# Generic L083RBHx
+GenL0.menu.pnum.GENERIC_L083RBHX=Generic L083RBHx
+GenL0.menu.pnum.GENERIC_L083RBHX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L083RBHX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L083RBHX.build.board=GENERIC_L083RBHX
+GenL0.menu.pnum.GENERIC_L083RBHX.build.product_line=STM32L083xx
+GenL0.menu.pnum.GENERIC_L083RBHX.build.variant=STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H
+
# Generic L083RBTx
GenL0.menu.pnum.GENERIC_L083RBTX=Generic L083RBTx
GenL0.menu.pnum.GENERIC_L083RBTX.upload.maximum_size=131072
@@ -7020,6 +7796,14 @@ GenL0.menu.pnum.GENERIC_L083RBTX.build.board=GENERIC_L083RBTX
GenL0.menu.pnum.GENERIC_L083RBTX.build.product_line=STM32L083xx
GenL0.menu.pnum.GENERIC_L083RBTX.build.variant=STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T
+# Generic L083RZHx
+GenL0.menu.pnum.GENERIC_L083RZHX=Generic L083RZHx
+GenL0.menu.pnum.GENERIC_L083RZHX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L083RZHX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L083RZHX.build.board=GENERIC_L083RZHX
+GenL0.menu.pnum.GENERIC_L083RZHX.build.product_line=STM32L083xx
+GenL0.menu.pnum.GENERIC_L083RZHX.build.variant=STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H
+
# Generic L083RZTx
GenL0.menu.pnum.GENERIC_L083RZTX=Generic L083RZTx
GenL0.menu.pnum.GENERIC_L083RZTX.upload.maximum_size=196608
@@ -7028,6 +7812,54 @@ GenL0.menu.pnum.GENERIC_L083RZTX.build.board=GENERIC_L083RZTX
GenL0.menu.pnum.GENERIC_L083RZTX.build.product_line=STM32L083xx
GenL0.menu.pnum.GENERIC_L083RZTX.build.variant=STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T
+# Generic L083VBIx
+GenL0.menu.pnum.GENERIC_L083VBIX=Generic L083VBIx
+GenL0.menu.pnum.GENERIC_L083VBIX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L083VBIX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L083VBIX.build.board=GENERIC_L083VBIX
+GenL0.menu.pnum.GENERIC_L083VBIX.build.product_line=STM32L083xx
+GenL0.menu.pnum.GENERIC_L083VBIX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L083VZIx
+GenL0.menu.pnum.GENERIC_L083VZIX=Generic L083VZIx
+GenL0.menu.pnum.GENERIC_L083VZIX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L083VZIX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L083VZIX.build.board=GENERIC_L083VZIX
+GenL0.menu.pnum.GENERIC_L083VZIX.build.product_line=STM32L083xx
+GenL0.menu.pnum.GENERIC_L083VZIX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L083VBTx
+GenL0.menu.pnum.GENERIC_L083VBTX=Generic L083VBTx
+GenL0.menu.pnum.GENERIC_L083VBTX.upload.maximum_size=131072
+GenL0.menu.pnum.GENERIC_L083VBTX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L083VBTX.build.board=GENERIC_L083VBTX
+GenL0.menu.pnum.GENERIC_L083VBTX.build.product_line=STM32L083xx
+GenL0.menu.pnum.GENERIC_L083VBTX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L083VZTx
+GenL0.menu.pnum.GENERIC_L083VZTX=Generic L083VZTx
+GenL0.menu.pnum.GENERIC_L083VZTX.upload.maximum_size=196608
+GenL0.menu.pnum.GENERIC_L083VZTX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L083VZTX.build.board=GENERIC_L083VZTX
+GenL0.menu.pnum.GENERIC_L083VZTX.build.product_line=STM32L083xx
+GenL0.menu.pnum.GENERIC_L083VZTX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L083V8Ix
+GenL0.menu.pnum.GENERIC_L083V8IX=Generic L083V8Ix
+GenL0.menu.pnum.GENERIC_L083V8IX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L083V8IX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L083V8IX.build.board=GENERIC_L083V8IX
+GenL0.menu.pnum.GENERIC_L083V8IX.build.product_line=STM32L083xx
+GenL0.menu.pnum.GENERIC_L083V8IX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
+# Generic L083V8Tx
+GenL0.menu.pnum.GENERIC_L083V8TX=Generic L083V8Tx
+GenL0.menu.pnum.GENERIC_L083V8TX.upload.maximum_size=65536
+GenL0.menu.pnum.GENERIC_L083V8TX.upload.maximum_data_size=20480
+GenL0.menu.pnum.GENERIC_L083V8TX.build.board=GENERIC_L083V8TX
+GenL0.menu.pnum.GENERIC_L083V8TX.build.product_line=STM32L083xx
+GenL0.menu.pnum.GENERIC_L083V8TX.build.variant=STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)
+
# Upload menu
GenL0.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD)
GenL0.menu.upload_method.swdMethod.upload.protocol=0
diff --git a/variants/STM32L0xx/L010C6T/generic_clock.c b/variants/STM32L0xx/L010C6T/generic_clock.c
index ca646b72b2..075dd019e5 100644
--- a/variants/STM32L0xx/L010C6T/generic_clock.c
+++ b/variants/STM32L0xx/L010C6T/generic_clock.c
@@ -20,8 +20,39 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L010C6T/ldscript.ld b/variants/STM32L0xx/L010C6T/ldscript.ld
new file mode 100644
index 0000000000..dc57472282
--- /dev/null
+++ b/variants/STM32L0xx/L010C6T/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L010C6Tx Device from STM32L0 series
+** 32Kbytes FLASH
+** 8Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/generic_clock.c b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/generic_clock.c
index 6e86048e75..56ff2b1645 100644
--- a/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/generic_clock.c
+++ b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/generic_clock.c
@@ -21,8 +21,39 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/ldscript.ld b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/ldscript.ld
new file mode 100644
index 0000000000..33682a5441
--- /dev/null
+++ b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L010F4Px Device from STM32L0 series
+** 16Kbytes FLASH
+** 2Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/generic_clock.c b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/generic_clock.c
index d3a973ca60..94a37cd05f 100644
--- a/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/generic_clock.c
+++ b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/generic_clock.c
@@ -21,8 +21,39 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/ldscript.ld b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/ldscript.ld
new file mode 100644
index 0000000000..9952c1b309
--- /dev/null
+++ b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L010K4Tx Device from STM32L0 series
+** 16Kbytes FLASH
+** 2Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L010R8T/generic_clock.c b/variants/STM32L0xx/L010R8T/generic_clock.c
index 4fcb97d9ee..24f4e4a58f 100644
--- a/variants/STM32L0xx/L010R8T/generic_clock.c
+++ b/variants/STM32L0xx/L010R8T/generic_clock.c
@@ -20,8 +20,39 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L010R8T/ldscript.ld b/variants/STM32L0xx/L010R8T/ldscript.ld
new file mode 100644
index 0000000000..48f2f6afa0
--- /dev/null
+++ b/variants/STM32L0xx/L010R8T/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L010R8Tx Device from STM32L0 series
+** 64Kbytes FLASH
+** 8Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L011D(3-4)P_L021D4P/generic_clock.c b/variants/STM32L0xx/L011D(3-4)P_L021D4P/generic_clock.c
index 97de4e82e9..5f03c973a8 100644
--- a/variants/STM32L0xx/L011D(3-4)P_L021D4P/generic_clock.c
+++ b/variants/STM32L0xx/L011D(3-4)P_L021D4P/generic_clock.c
@@ -21,8 +21,39 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L011D(3-4)P_L021D4P/ldscript.ld b/variants/STM32L0xx/L011D(3-4)P_L021D4P/ldscript.ld
new file mode 100644
index 0000000000..36cd27ff6d
--- /dev/null
+++ b/variants/STM32L0xx/L011D(3-4)P_L021D4P/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L011D3Px Device from STM32L0 series
+** 8Kbytes FLASH
+** 2Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L011E(3-4)Y/generic_clock.c b/variants/STM32L0xx/L011E(3-4)Y/generic_clock.c
index 59d3f2bb60..bd754bb326 100644
--- a/variants/STM32L0xx/L011E(3-4)Y/generic_clock.c
+++ b/variants/STM32L0xx/L011E(3-4)Y/generic_clock.c
@@ -20,8 +20,39 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L011E(3-4)Y/ldscript.ld b/variants/STM32L0xx/L011E(3-4)Y/ldscript.ld
new file mode 100644
index 0000000000..49e25b4d2b
--- /dev/null
+++ b/variants/STM32L0xx/L011E(3-4)Y/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L011E3Yx Device from STM32L0 series
+** 8Kbytes FLASH
+** 2Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L011F(3-4)U_L021F4U/generic_clock.c b/variants/STM32L0xx/L011F(3-4)U_L021F4U/generic_clock.c
index 830c69d924..a771625eb7 100644
--- a/variants/STM32L0xx/L011F(3-4)U_L021F4U/generic_clock.c
+++ b/variants/STM32L0xx/L011F(3-4)U_L021F4U/generic_clock.c
@@ -21,8 +21,39 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L011F(3-4)U_L021F4U/ldscript.ld b/variants/STM32L0xx/L011F(3-4)U_L021F4U/ldscript.ld
new file mode 100644
index 0000000000..08c7f25ca2
--- /dev/null
+++ b/variants/STM32L0xx/L011F(3-4)U_L021F4U/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L011F3Px Device from STM32L0 series
+** 8Kbytes FLASH
+** 2Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L011G(3-4)U_L021G4U/generic_clock.c b/variants/STM32L0xx/L011G(3-4)U_L021G4U/generic_clock.c
index 55e8c2398a..7fc9c71e8e 100644
--- a/variants/STM32L0xx/L011G(3-4)U_L021G4U/generic_clock.c
+++ b/variants/STM32L0xx/L011G(3-4)U_L021G4U/generic_clock.c
@@ -21,8 +21,39 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L011G(3-4)U_L021G4U/ldscript.ld b/variants/STM32L0xx/L011G(3-4)U_L021G4U/ldscript.ld
new file mode 100644
index 0000000000..13e9725028
--- /dev/null
+++ b/variants/STM32L0xx/L011G(3-4)U_L021G4U/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L011G3Ux Device from STM32L0 series
+** 8Kbytes FLASH
+** 2Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L011K(3-4)U_L021K4U/generic_clock.c b/variants/STM32L0xx/L011K(3-4)U_L021K4U/generic_clock.c
index 56760a3690..2b5b7ed4e6 100644
--- a/variants/STM32L0xx/L011K(3-4)U_L021K4U/generic_clock.c
+++ b/variants/STM32L0xx/L011K(3-4)U_L021K4U/generic_clock.c
@@ -21,8 +21,39 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L011K(3-4)U_L021K4U/ldscript.ld b/variants/STM32L0xx/L011K(3-4)U_L021K4U/ldscript.ld
new file mode 100644
index 0000000000..5743887aa3
--- /dev/null
+++ b/variants/STM32L0xx/L011K(3-4)U_L021K4U/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L011K3Ux Device from STM32L0 series
+** 8Kbytes FLASH
+** 2Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/generic_clock.c b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/generic_clock.c
index 43bb25e1c3..c7f1a8dad0 100644
--- a/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/generic_clock.c
+++ b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/generic_clock.c
@@ -23,8 +23,39 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/ldscript.ld b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/ldscript.ld
new file mode 100644
index 0000000000..906009f96c
--- /dev/null
+++ b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L031C4Tx Device from STM32L0 series
+** 16Kbytes FLASH
+** 8Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/generic_clock.c b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/generic_clock.c
index 3fe9cef6dc..25d0e1c80a 100644
--- a/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/generic_clock.c
+++ b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/generic_clock.c
@@ -21,8 +21,39 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/ldscript.ld b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/ldscript.ld
new file mode 100644
index 0000000000..e480e7159c
--- /dev/null
+++ b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L031E4Yx Device from STM32L0 series
+** 16Kbytes FLASH
+** 8Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L031F(4-6)P_L041F6P/generic_clock.c b/variants/STM32L0xx/L031F(4-6)P_L041F6P/generic_clock.c
index 37792debf7..ad387a098c 100644
--- a/variants/STM32L0xx/L031F(4-6)P_L041F6P/generic_clock.c
+++ b/variants/STM32L0xx/L031F(4-6)P_L041F6P/generic_clock.c
@@ -21,8 +21,39 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L031F(4-6)P_L041F6P/ldscript.ld b/variants/STM32L0xx/L031F(4-6)P_L041F6P/ldscript.ld
new file mode 100644
index 0000000000..8137ef8255
--- /dev/null
+++ b/variants/STM32L0xx/L031F(4-6)P_L041F6P/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L031F4Px Device from STM32L0 series
+** 16Kbytes FLASH
+** 8Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L031G(4-6)U_L041G6U/generic_clock.c b/variants/STM32L0xx/L031G(4-6)U_L041G6U/generic_clock.c
index 045e04f922..bed8a9ede4 100644
--- a/variants/STM32L0xx/L031G(4-6)U_L041G6U/generic_clock.c
+++ b/variants/STM32L0xx/L031G(4-6)U_L041G6U/generic_clock.c
@@ -21,8 +21,39 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L031G(4-6)U_L041G6U/ldscript.ld b/variants/STM32L0xx/L031G(4-6)U_L041G6U/ldscript.ld
new file mode 100644
index 0000000000..59a3d75e55
--- /dev/null
+++ b/variants/STM32L0xx/L031G(4-6)U_L041G6U/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L031G4Ux Device from STM32L0 series
+** 16Kbytes FLASH
+** 8Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/generic_clock.c b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/generic_clock.c
index 1c3b0b9ede..692ee7b731 100644
--- a/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/generic_clock.c
+++ b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/generic_clock.c
@@ -25,8 +25,46 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/ldscript.ld b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/ldscript.ld
new file mode 100644
index 0000000000..cb1e9b47ba
--- /dev/null
+++ b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L052C6Tx Device from STM32L0 series
+** 32Kbytes FLASH
+** 8Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L052K(6-8)T_L062K8T/generic_clock.c b/variants/STM32L0xx/L052K(6-8)T_L062K8T/generic_clock.c
index cf5e0ae676..2fd8c740e5 100644
--- a/variants/STM32L0xx/L052K(6-8)T_L062K8T/generic_clock.c
+++ b/variants/STM32L0xx/L052K(6-8)T_L062K8T/generic_clock.c
@@ -21,8 +21,46 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L052K(6-8)T_L062K8T/ldscript.ld b/variants/STM32L0xx/L052K(6-8)T_L062K8T/ldscript.ld
new file mode 100644
index 0000000000..249c528508
--- /dev/null
+++ b/variants/STM32L0xx/L052K(6-8)T_L062K8T/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L052K6Tx Device from STM32L0 series
+** 32Kbytes FLASH
+** 8Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/generic_clock.c b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/generic_clock.c
index 9f1a74f42b..4df9ec3126 100644
--- a/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/generic_clock.c
+++ b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/generic_clock.c
@@ -21,8 +21,46 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/ldscript.ld b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/ldscript.ld
new file mode 100644
index 0000000000..e7a50a858a
--- /dev/null
+++ b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L052R6Hx Device from STM32L0 series
+** 32Kbytes FLASH
+** 8Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/generic_clock.c b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/generic_clock.c
index 1caf4e270e..a39d4b58d2 100644
--- a/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/generic_clock.c
+++ b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/generic_clock.c
@@ -21,8 +21,46 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/ldscript.ld b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/ldscript.ld
new file mode 100644
index 0000000000..62372cbc42
--- /dev/null
+++ b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L052T6Yx Device from STM32L0 series
+** 32Kbytes FLASH
+** 8Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/generic_clock.c b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/generic_clock.c
index 432305a08d..3fffeab23c 100644
--- a/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/generic_clock.c
+++ b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/generic_clock.c
@@ -25,8 +25,46 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/ldscript.ld b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/ldscript.ld
new file mode 100644
index 0000000000..fd0f38888c
--- /dev/null
+++ b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L073CBTx Device from STM32L0 series
+** 128Kbytes FLASH
+** 20Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/generic_clock.c b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/generic_clock.c
index 693c2eb685..74b283f696 100644
--- a/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/generic_clock.c
+++ b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/generic_clock.c
@@ -21,8 +21,46 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/ldscript.ld b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/ldscript.ld
new file mode 100644
index 0000000000..efd2e77ecc
--- /dev/null
+++ b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L072KBUx Device from STM32L0 series
+** 128Kbytes FLASH
+** 20Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/generic_clock.c b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/generic_clock.c
index 10410b3fe7..3446cf0b97 100644
--- a/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/generic_clock.c
+++ b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/generic_clock.c
@@ -24,8 +24,46 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/ldscript.ld b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/ldscript.ld
new file mode 100644
index 0000000000..b438397e2b
--- /dev/null
+++ b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L072RBHx Device from STM32L0 series
+** 128Kbytes FLASH
+** 20Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/generic_clock.c b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/generic_clock.c
index 6a712a94b6..a257a3e757 100644
--- a/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/generic_clock.c
+++ b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/generic_clock.c
@@ -28,8 +28,46 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+ RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/ldscript.ld b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/ldscript.ld
new file mode 100644
index 0000000000..df02826b41
--- /dev/null
+++ b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32L072V8Ix Device from STM32L0 series
+** 64Kbytes FLASH
+** 20Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
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