From e9001752624092e0b2e7889e50e608e068a1bfc2 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 26 Jan 2023 10:25:37 +0100 Subject: [PATCH 1/3] fix: some STM32 mcu have only USB_OTG_HS available generate an explicit #error ex: STM32H723ZGTx have only USB_OTG_HS Fixes #1931 Signed-off-by: Frederic Pillon --- cores/arduino/stm32/usb/usbd_conf.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cores/arduino/stm32/usb/usbd_conf.h b/cores/arduino/stm32/usb/usbd_conf.h index 01d13c7b66..7eb1619e1b 100644 --- a/cores/arduino/stm32/usb/usbd_conf.h +++ b/cores/arduino/stm32/usb/usbd_conf.h @@ -35,6 +35,10 @@ extern "C" { #if defined(USE_USB_HS) && !defined(USB_OTG_HS) #error "This board does not support USB High Speed! Select 'Full Speed' in the 'Tools->USB interface' menu" #endif +#if !defined(USB_BASE) && !defined(USB_OTG_FS) && defined(USB_OTG_HS) && !defined(USE_USB_HS) +#error "This board support only USB High Speed! Select 'High Speed' or 'High Speed in Full Speed mode' in the 'Tools->USB interface' menu" +#endif + #include #include From dd2385fe2674241fbc5a93a3c1576b71ac3dcfa0 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 26 Jan 2023 14:58:55 +0100 Subject: [PATCH 2/3] fix: peripheral clock configuration for STM32H723ZGT Signed-off-by: Frederic Pillon --- .../generic_clock.c | 18 ++++++++++++++++++ .../variant_NUCLEO_H723ZG.cpp | 19 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/generic_clock.c b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/generic_clock.c index 0dca70160e..19b49e9962 100644 --- a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/generic_clock.c +++ b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/generic_clock.c @@ -23,6 +23,7 @@ WEAK void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; /** Supply configuration update enable */ @@ -71,5 +72,22 @@ WEAK void SystemClock_Config(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { Error_Handler(); } + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PLL2.PLL2M = 32; + PeriphClkInitStruct.PLL2.PLL2N = 96; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 2; + PeriphClkInitStruct.PLL2.PLL2R = 4; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_1; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0; + PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL2; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.cpp b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.cpp index c97087f8d5..2d2304e675 100644 --- a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.cpp +++ b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.cpp @@ -183,6 +183,7 @@ WEAK void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; /** Supply configuration update enable */ @@ -230,6 +231,24 @@ WEAK void SystemClock_Config(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { Error_Handler(); } + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PLL2.PLL2M = 1; + PeriphClkInitStruct.PLL2.PLL2N = 24; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 2; + PeriphClkInitStruct.PLL2.PLL2R = 4; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL2; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } + } #ifdef __cplusplus From bec02966e034b81c6d0564abca298891eac13484 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 26 Jan 2023 14:59:03 +0100 Subject: [PATCH 3/3] chore: configure the clock recovery system for STM32H723ZGT Signed-off-by: Frederic Pillon --- .../generic_clock.c | 23 +++++++++++++++++++ .../variant_NUCLEO_H723ZG.cpp | 22 ++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/generic_clock.c b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/generic_clock.c index 19b49e9962..bc12a2cd8e 100644 --- a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/generic_clock.c +++ b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/generic_clock.c @@ -24,6 +24,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + RCC_CRSInitTypeDef RCC_CRSInitStruct = {}; /** Supply configuration update enable */ @@ -89,5 +90,27 @@ WEAK void SystemClock_Config(void) if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } + + /*Configure the clock recovery system (CRS)**********************************/ + + /*Enable CRS Clock*/ + __HAL_RCC_CRS_CLK_ENABLE(); + + /* Default Synchro Signal division factor (not divided) */ + RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; + + /* Set the SYNCSRC[1:0] bits according to CRS_Source value */ + RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB1; + + /* HSI48 is synchronized with USB SOF at 1KHz rate */ + RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT; + RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT; + RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING; + + /* Set the TRIM[5:0] to the default value */ + RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT; + + /* Start automatic synchronization */ + HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.cpp b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.cpp index 2d2304e675..8cc9fc96b5 100644 --- a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.cpp +++ b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.cpp @@ -184,6 +184,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + RCC_CRSInitTypeDef RCC_CRSInitStruct = {}; /** Supply configuration update enable */ @@ -249,6 +250,27 @@ WEAK void SystemClock_Config(void) Error_Handler(); } + /*Configure the clock recovery system (CRS)**********************************/ + + /*Enable CRS Clock*/ + __HAL_RCC_CRS_CLK_ENABLE(); + + /* Default Synchro Signal division factor (not divided) */ + RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; + + /* Set the SYNCSRC[1:0] bits according to CRS_Source value */ + RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB1; + + /* HSI48 is synchronized with USB SOF at 1KHz rate */ + RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT; + RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT; + RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING; + + /* Set the TRIM[5:0] to the default value */ + RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT; + + /* Start automatic synchronization */ + HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); } #ifdef __cplusplus pFad - Phonifier reborn

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