From d3465d5651cdac37fec556440667cc1570533d5f Mon Sep 17 00:00:00 2001
From: Mathieu CHOPLAIN <mathieu.choplain@st.com>
Date: Tue, 17 Oct 2023 15:25:33 +0200
Subject: [PATCH 1/4] variant(H7): add generic H747X(G-I)xx support

This commit adds generic support for H747XIH and compatible MCUs:
* H742X(G-I)H
* H743X(G-I)H
* H745X(G-I)H
* H747X(G-I)H
* H750XBH
* H753XIH
* H755XIH
* H757XIH

The clock is configured to have core running at 480MHz.

Tested successfully (working LED/Joystick via GPIO) on STM32H747I-DISCO.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
---
 README.md                                     |   8 +
 boards.txt                                    |  96 ++++++++
 .../generic_clock.c                           | 111 +++++++++-
 .../ldscript.ld                               | 205 ++++++++++++++++++
 4 files changed, 418 insertions(+), 2 deletions(-)
 create mode 100644 variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/ldscript.ld

diff --git a/README.md b/README.md
index f108692c8a..5b3ba3470e 100644
--- a/README.md
+++ b/README.md
@@ -541,14 +541,18 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
 | :green_heart:  | STM32H733ZGT | Generic Board | *2.4.0* |  |
 | :green_heart: | STM32H742IG<br>STM32H742II | Generic Board | *2.1.0* |  |
 | :green_heart: | STM32H742VG<br>STM32H742VI | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32H742XG<br>STM32H742XI | Generic Board | **2.7.0** |  |
 | :green_heart: | STM32H742ZG<br>STM32H742ZI | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32H743IG<br>STM32H743II | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32H743VG<br>STM32H743VI | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32H743VI | [DevEBox H743VIT6](https://github.com/mcauser/MCUDEV_DEVEBOX_H7XX_M) | *2.2.0* | |
 | :green_heart: | STM32H743VI | [WeAct MiniSTM32H743VIT6](https://github.com/WeActStudio/MiniSTM32H7xx) | *2.2.0* | [More info](https://github.com/stm32duino/Arduino_Core_STM32/pull/1552) |
+| :yellow_heart: | STM32H743XG<br>STM32H743XI | Generic Board | **2.7.0** |  |
 | :green_heart: | STM32H743ZG<br>STM32H743ZI | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32H745XG<br>STM32H745XI | Generic Board | **2.7.0** |  |
 | :green_heart: | STM32H747AG<br>STM32H747AI | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32H747IG<br>STM32H747II | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32H747XG<br>STM32H747XI | Generic Board | **2.7.0** |  |
 | :green_heart: | STM32H750ZB | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32H750IB<br>STM32H750II | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32H750IB | [Daisy](https://www.electro-smith.com/daisy/daisy) | *1.9.0* |  |
@@ -557,10 +561,14 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
 | :green_heart: | STM32H750VB | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32H750VB | [DevEBox H750VBT6](https://github.com/mcauser/MCUDEV_DEVEBOX_H7XX_M) | *2.2.0* | |
 | :green_heart: | STM32H750VB | [WeAct MiniSTM32H750VBT6](https://github.com/WeActStudio/MiniSTM32H7xx) | *2.2.0* | [More info](https://github.com/stm32duino/Arduino_Core_STM32/pull/1552) |
+| :yellow_heart: | STM32H750XB | Generic Board | **2.7.0** |  |
 | :green_heart: | STM32H753VI | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32H753XI | Generic Board | **2.7.0** |  |
 | :green_heart: | STM32H753ZI | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32H755XI | Generic Board | **2.7.0** |  |
 | :green_heart: | STM32H757AI | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32H757II | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32H757XI | Generic Board | **2.7.0** |  |
 
 ### Generic STM32L0 boards
 
diff --git a/boards.txt b/boards.txt
index a6772f8989..4fbe9e34c3 100644
--- a/boards.txt
+++ b/boards.txt
@@ -7540,6 +7540,22 @@ GenH7.menu.pnum.GENERIC_H742VITX.build.board=GENERIC_H742VITX
 GenH7.menu.pnum.GENERIC_H742VITX.build.product_line=STM32H742xx
 GenH7.menu.pnum.GENERIC_H742VITX.build.variant=STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)
 
+# Generic H742XGHx
+GenH7.menu.pnum.GENERIC_H742XGHX=Generic H742XGHx
+GenH7.menu.pnum.GENERIC_H742XGHX.upload.maximum_size=1048576
+GenH7.menu.pnum.GENERIC_H742XGHX.upload.maximum_data_size=524288
+GenH7.menu.pnum.GENERIC_H742XGHX.build.board=GENERIC_H742XGHX
+GenH7.menu.pnum.GENERIC_H742XGHX.build.product_line=STM32H742xx
+GenH7.menu.pnum.GENERIC_H742XGHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
+
+# Generic H742XIHx
+GenH7.menu.pnum.GENERIC_H742XIHX=Generic H742XIHx
+GenH7.menu.pnum.GENERIC_H742XIHX.upload.maximum_size=2097152
+GenH7.menu.pnum.GENERIC_H742XIHX.upload.maximum_data_size=524288
+GenH7.menu.pnum.GENERIC_H742XIHX.build.board=GENERIC_H742XIHX
+GenH7.menu.pnum.GENERIC_H742XIHX.build.product_line=STM32H742xx
+GenH7.menu.pnum.GENERIC_H742XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
+
 # Generic H742ZGTx
 GenH7.menu.pnum.GENERIC_H742ZGTX=Generic H742ZGTx
 GenH7.menu.pnum.GENERIC_H742ZGTX.upload.maximum_size=1048576
@@ -7620,6 +7636,22 @@ GenH7.menu.pnum.GENERIC_H743VITX.build.board=GENERIC_H743VITX
 GenH7.menu.pnum.GENERIC_H743VITX.build.product_line=STM32H743xx
 GenH7.menu.pnum.GENERIC_H743VITX.build.variant=STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)
 
+# Generic H743XGHx
+GenH7.menu.pnum.GENERIC_H743XGHX=Generic H743XGHx
+GenH7.menu.pnum.GENERIC_H743XGHX.upload.maximum_size=1048576
+GenH7.menu.pnum.GENERIC_H743XGHX.upload.maximum_data_size=524288
+GenH7.menu.pnum.GENERIC_H743XGHX.build.board=GENERIC_H743XGHX
+GenH7.menu.pnum.GENERIC_H743XGHX.build.product_line=STM32H743xx
+GenH7.menu.pnum.GENERIC_H743XGHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
+
+# Generic H743XIHx
+GenH7.menu.pnum.GENERIC_H743XIHX=Generic H743XIHx
+GenH7.menu.pnum.GENERIC_H743XIHX.upload.maximum_size=2097152
+GenH7.menu.pnum.GENERIC_H743XIHX.upload.maximum_data_size=524288
+GenH7.menu.pnum.GENERIC_H743XIHX.build.board=GENERIC_H743XIHX
+GenH7.menu.pnum.GENERIC_H743XIHX.build.product_line=STM32H743xx
+GenH7.menu.pnum.GENERIC_H743XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
+
 # Generic H743ZGTx
 GenH7.menu.pnum.GENERIC_H743ZGTX=Generic H743ZGTx
 GenH7.menu.pnum.GENERIC_H743ZGTX.upload.maximum_size=1048576
@@ -7636,6 +7668,22 @@ GenH7.menu.pnum.GENERIC_H743ZITX.build.board=GENERIC_H743ZITX
 GenH7.menu.pnum.GENERIC_H743ZITX.build.product_line=STM32H743xx
 GenH7.menu.pnum.GENERIC_H743ZITX.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT
 
+# Generic H745XGHx
+GenH7.menu.pnum.GENERIC_H745XGHX=Generic H745XGHx
+GenH7.menu.pnum.GENERIC_H745XGHX.upload.maximum_size=1048576
+GenH7.menu.pnum.GENERIC_H745XGHX.upload.maximum_data_size=524288
+GenH7.menu.pnum.GENERIC_H745XGHX.build.board=GENERIC_H745XGHX
+GenH7.menu.pnum.GENERIC_H745XGHX.build.product_line=STM32H745xG
+GenH7.menu.pnum.GENERIC_H745XGHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
+
+# Generic H745XIHx
+GenH7.menu.pnum.GENERIC_H745XIHX=Generic H745XIHx
+GenH7.menu.pnum.GENERIC_H745XIHX.upload.maximum_size=2097152
+GenH7.menu.pnum.GENERIC_H745XIHX.upload.maximum_data_size=524288
+GenH7.menu.pnum.GENERIC_H745XIHX.build.board=GENERIC_H745XIHX
+GenH7.menu.pnum.GENERIC_H745XIHX.build.product_line=STM32H745xx
+GenH7.menu.pnum.GENERIC_H745XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
+
 # Generic H747AGIx
 GenH7.menu.pnum.GENERIC_H747AGIX=Generic H747AGIx
 GenH7.menu.pnum.GENERIC_H747AGIX.upload.maximum_size=1048576
@@ -7668,6 +7716,22 @@ GenH7.menu.pnum.GENERIC_H747IITX.build.board=GENERIC_H747IITX
 GenH7.menu.pnum.GENERIC_H747IITX.build.product_line=STM32H747xx
 GenH7.menu.pnum.GENERIC_H747IITX.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT
 
+# Generic H747XGHx
+GenH7.menu.pnum.GENERIC_H747XGHX=Generic H747XGHx
+GenH7.menu.pnum.GENERIC_H747XGHX.upload.maximum_size=1048576
+GenH7.menu.pnum.GENERIC_H747XGHX.upload.maximum_data_size=524288
+GenH7.menu.pnum.GENERIC_H747XGHX.build.board=GENERIC_H747XGHX
+GenH7.menu.pnum.GENERIC_H747XGHX.build.product_line=STM32H747xG
+GenH7.menu.pnum.GENERIC_H747XGHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
+
+# Generic H747XIHx
+GenH7.menu.pnum.GENERIC_H747XIHX=Generic H747XIHx
+GenH7.menu.pnum.GENERIC_H747XIHX.upload.maximum_size=2097152
+GenH7.menu.pnum.GENERIC_H747XIHX.upload.maximum_data_size=524288
+GenH7.menu.pnum.GENERIC_H747XIHX.build.board=GENERIC_H747XIHX
+GenH7.menu.pnum.GENERIC_H747XIHX.build.product_line=STM32H747xx
+GenH7.menu.pnum.GENERIC_H747XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
+
 # Generic H750IBKx
 GenH7.menu.pnum.GENERIC_H750IBKX=Generic H750IBKx
 GenH7.menu.pnum.GENERIC_H750IBKX.upload.maximum_size=131072
@@ -7692,6 +7756,14 @@ GenH7.menu.pnum.GENERIC_H750VBTX.build.board=GENERIC_H750VBTX
 GenH7.menu.pnum.GENERIC_H750VBTX.build.product_line=STM32H750xx
 GenH7.menu.pnum.GENERIC_H750VBTX.build.variant=STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)
 
+# Generic H750XBHx
+GenH7.menu.pnum.GENERIC_H750XBHX=Generic H750XBHx
+GenH7.menu.pnum.GENERIC_H750XBHX.upload.maximum_size=131072
+GenH7.menu.pnum.GENERIC_H750XBHX.upload.maximum_data_size=524288
+GenH7.menu.pnum.GENERIC_H750XBHX.build.board=GENERIC_H750XBHX
+GenH7.menu.pnum.GENERIC_H750XBHX.build.product_line=STM32H750xx
+GenH7.menu.pnum.GENERIC_H750XBHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
+
 # Generic H750ZBTx
 GenH7.menu.pnum.GENERIC_H750ZBTX=Generic H750ZBTx
 GenH7.menu.pnum.GENERIC_H750ZBTX.upload.maximum_size=131072
@@ -7732,6 +7804,14 @@ GenH7.menu.pnum.GENERIC_H753VITX.build.board=GENERIC_H753VITX
 GenH7.menu.pnum.GENERIC_H753VITX.build.product_line=STM32H753xx
 GenH7.menu.pnum.GENERIC_H753VITX.build.variant=STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)
 
+# Generic H753XIHx
+GenH7.menu.pnum.GENERIC_H753XIHX=Generic H753XIHx
+GenH7.menu.pnum.GENERIC_H753XIHX.upload.maximum_size=2097152
+GenH7.menu.pnum.GENERIC_H753XIHX.upload.maximum_data_size=524288
+GenH7.menu.pnum.GENERIC_H753XIHX.build.board=GENERIC_H753XIHX
+GenH7.menu.pnum.GENERIC_H753XIHX.build.product_line=STM32H753xx
+GenH7.menu.pnum.GENERIC_H753XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
+
 # Generic H753ZITx
 GenH7.menu.pnum.GENERIC_H753ZITX=Generic H753ZITx
 GenH7.menu.pnum.GENERIC_H753ZITX.upload.maximum_size=2097152
@@ -7740,6 +7820,14 @@ GenH7.menu.pnum.GENERIC_H753ZITX.build.board=GENERIC_H753ZITX
 GenH7.menu.pnum.GENERIC_H753ZITX.build.product_line=STM32H753xx
 GenH7.menu.pnum.GENERIC_H753ZITX.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT
 
+# Generic H755XIHx
+GenH7.menu.pnum.GENERIC_H755XIHX=Generic H755XIHx
+GenH7.menu.pnum.GENERIC_H755XIHX.upload.maximum_size=2097152
+GenH7.menu.pnum.GENERIC_H755XIHX.upload.maximum_data_size=524288
+GenH7.menu.pnum.GENERIC_H755XIHX.build.board=GENERIC_H755XIHX
+GenH7.menu.pnum.GENERIC_H755XIHX.build.product_line=STM32H755xx
+GenH7.menu.pnum.GENERIC_H755XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
+
 # Generic H757AIIx
 GenH7.menu.pnum.GENERIC_H757AIIX=Generic H757AIIx
 GenH7.menu.pnum.GENERIC_H757AIIX.upload.maximum_size=2097152
@@ -7756,6 +7844,14 @@ GenH7.menu.pnum.GENERIC_H757IITX.build.board=GENERIC_H757IITX
 GenH7.menu.pnum.GENERIC_H757IITX.build.product_line=STM32H757xx
 GenH7.menu.pnum.GENERIC_H757IITX.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT
 
+# Generic H757XIHx
+GenH7.menu.pnum.GENERIC_H757XIHX=Generic H757XIHx
+GenH7.menu.pnum.GENERIC_H757XIHX.upload.maximum_size=2097152
+GenH7.menu.pnum.GENERIC_H757XIHX.upload.maximum_data_size=524288
+GenH7.menu.pnum.GENERIC_H757XIHX.build.board=GENERIC_H757XIHX
+GenH7.menu.pnum.GENERIC_H757XIHX.build.product_line=STM32H757xx
+GenH7.menu.pnum.GENERIC_H757XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
+
 # Upload menu
 GenH7.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD)
 GenH7.menu.upload_method.swdMethod.upload.protocol=0
diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/generic_clock.c b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/generic_clock.c
index fb9444e7c9..26228f0a6a 100644
--- a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/generic_clock.c
+++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/generic_clock.c
@@ -25,8 +25,115 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Supply configuration update enable
+  */
+#if defined(SMPS)
+  /** If SMPS is available on this MCU, assume that the MCU's board is
+   *  built to power the MCU using the SMPS since it's more efficient.
+   *  In this case, we must configure the MCU to use DIRECT_SMPS_SUPPLY.
+   *
+   *  N.B.: if the hardware configuration does not match the argument to
+   *  HAL_PWREx_ConfigSupply(), the board will deadlock at this function call.
+   *  This can manifest immediately or after a RESET/power cycle.
+   *
+   *  Trying to flash the board at this point will result in errors such as
+   *  "No STM32 target found". To overcome this problem, erase the MCU's flash.
+   *
+   *  The following settings in STM32CubeProgrammer appear to work for this purpose:
+   *   - Mode: Power down
+   *   - Reset mode: Hardware reset
+   */
+  HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
+#else
+  /** No SMPS available: use the internal voltage regulator (LDO).
+   */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+#endif
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+  while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_CSI
+                                     | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.CSIState = RCC_CSI_ON;
+  RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = 4;
+  RCC_OscInitStruct.PLL.PLLN = 60;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 5;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+                                | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
+
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Initializes the peripherals clock
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_CKPER
+                                             | RCC_PERIPHCLK_HRTIM1 | RCC_PERIPHCLK_I2C123 | RCC_PERIPHCLK_I2C4
+                                             | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM3
+                                             | RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_USB
+                                             | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6
+                                             | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578
+                                             | RCC_PERIPHCLK_RTC;
+  PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP;
+  PeriphClkInitStruct.CecClockSelection = RCC_CECCLKSOURCE_CSI;
+  PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI;
+  PeriphClkInitStruct.Hrtim1ClockSelection = RCC_HRTIM1CLK_CPUCLK;
+  PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
+  PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_D3PCLK1;
+  PeriphClkInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_D2PCLK1;
+  PeriphClkInitStruct.Lptim2ClockSelection = RCC_LPTIM2CLKSOURCE_D3PCLK1;
+  PeriphClkInitStruct.Lptim345ClockSelection = RCC_LPTIM345CLKSOURCE_D3PCLK1;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_D3PCLK1;
+  PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+  PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL;
+  PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL;
+  PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_D2PCLK1;
+  PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_D3PCLK1;
+  PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
+  PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/ldscript.ld b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/ldscript.ld
new file mode 100644
index 0000000000..f5102fa972
--- /dev/null
+++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/ldscript.ld
@@ -0,0 +1,205 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE & Mathieu CHOPLAIN
+**
+**  Abstract    : Linker script for STM32H7XIHx series
+**                      2048Kbytes FLASH
+**                       512Kbytes RAM_D1
+**                       288Kbytes RAM_D2  (stack)
+**                        64Kbytes RAM_D3  (unused)
+**                       128Kbytes ITCMRAM (unused)
+**                        64Kbytes DTCMRAM (unused)
+**
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2023 STMicroelectronics.
+** All rights reserved.
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM_D2) + LENGTH(RAM_D2); /* Use the otherwise wasted RAM_D2 region for stack */
+
+/* Special value for CRT to prevent heap overflow into address space hole:
+  _sbrk assumes the RAM between _end and _estack is contiguous and prevents
+  heap overflowing into the stack by checking that the heap end pointer is
+  never going past (_estack - _Min_Stack_Size).
+
+  By setting _Min_Stack_Size to this value, we ensure that _sbrk considers the
+  end of RAM_D1 as the heap's upper limit, preventing reserved memory space from
+  being used as heap memory improperly.
+*/
+_Min_Stack_Size = _estack - (ORIGIN(RAM_D1) + LENGTH(RAM_D1));
+_Min_Heap_Size = 0x200; /* required amount of heap  */
+
+
+/* Memories definition */
+MEMORY
+{
+  FLASH   (rx)   : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+  ITCMRAM (xrw)  : ORIGIN = 0x00000000, LENGTH = 64K
+  DTCMRAM (xrw)  : ORIGIN = 0x20000000, LENGTH = 128K
+  RAM_D1 (xrw)   : ORIGIN = 0x24000000, LENGTH = LD_MAX_DATA_SIZE
+  RAM_D2 (xrw)   : ORIGIN = 0x30000000, LENGTH = 288K
+  RAM_D3 (xrw)   : ORIGIN = 0x38000000, LENGTH = 64K
+
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM_D1 AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM_D1
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+/*  . = . + _Min_Stack_Size; - stack is in a separate SRAM region, no need to check its size */
+    . = ALIGN(8);
+  } >RAM_D1
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

From 332cdf04512c086718f4f04c4fe20808f33895ae Mon Sep 17 00:00:00 2001
From: Mathieu CHOPLAIN <mathieu.choplain@st.com>
Date: Tue, 17 Oct 2023 18:13:35 +0200
Subject: [PATCH 2/4] variant(H7): add STM32H747I-DISCO support

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
---
 README.md                                     |   1 +
 boards.txt                                    |  15 +
 .../CMakeLists.txt                            |   1 +
 .../PeripheralPins_DISCO_H747I.c              | 781 ++++++++++++++++++
 .../variant_STM32H747I_DISCO.cpp              | 313 +++++++
 .../variant_STM32H747I_DISCO.h                | 357 ++++++++
 6 files changed, 1468 insertions(+)
 create mode 100644 variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins_DISCO_H747I.c
 create mode 100644 variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.cpp
 create mode 100644 variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h

diff --git a/README.md b/README.md
index 5b3ba3470e..d1534a8efa 100644
--- a/README.md
+++ b/README.md
@@ -172,6 +172,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
 | :green_heart:  | STM32G031J6 | [STM32G0316-DISCO](https://www.st.com/en/evaluation-tools/stm32g0316-disco.html) | *1.9.0* |  |
 | :green_heart:  | STM32G431CB | [B-G431B-ESC1](https://www.st.com/en/evaluation-tools/b-g431b-esc1.html) | *2.0.0* |  |
 | :green_heart:  | STM32H573IIKxQ  | [STM32H573I-DK](https://www.st.com/en/evaluation-tools/stm32h573i-dk.html) | *2.6.0* |  |
+| :yellow_heart:  | STM32H747XIHx  | [STM32H747I-DISCO](https://www.st.com/en/evaluation-tools/stm32h747i-disco.html) | **2.7.0** |  |
 | :green_heart:  | STM32L4S5VI | [B-L4S5I-IOT01A](https://www.st.com/en/evaluation-tools/b-l4s5i-iot01a.html) | *2.0.0* | |
 | :green_heart: | STM32U585AIIxQ | [B-U585I-IOT02A](https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html) | *2.1.0* |  |
 | :green_heart: | STM32WB5MMG | [STM32WB5MM-DK](https://www.st.com/en/evaluation-tools/stm32wb5mm-dk.html) | *2.1.0* |  |
diff --git a/boards.txt b/boards.txt
index 4fbe9e34c3..a4a192a0e3 100644
--- a/boards.txt
+++ b/boards.txt
@@ -1047,6 +1047,21 @@ Disco.menu.pnum.STM32H573I_DK.build.product_line=STM32H573xx
 Disco.menu.pnum.STM32H573I_DK.build.variant=STM32H5xx/H573IIKxQ
 Disco.menu.pnum.STM32H573I_DK.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
 
+# STM32H747I-DISCO
+Disco.menu.pnum.STM32H747I_DISCO=STM32H747I-DISCO
+Disco.menu.pnum.STM32H747I_DISCO.node=DIS_H747XI
+Disco.menu.pnum.STM32H747I_DISCO.upload.maximum_size=2097152
+Disco.menu.pnum.STM32H747I_DISCO.upload.maximum_data_size=524288
+Disco.menu.pnum.STM32H747I_DISCO.build.mcu=cortex-m7
+Disco.menu.pnum.STM32H747I_DISCO.build.fpu=-mfpu=fpv4-sp-d16
+Disco.menu.pnum.STM32H747I_DISCO.build.float-abi=-mfloat-abi=hard
+Disco.menu.pnum.STM32H747I_DISCO.build.board=STM32H747I_DISCO
+Disco.menu.pnum.STM32H747I_DISCO.build.series=STM32H7xx
+Disco.menu.pnum.STM32H747I_DISCO.build.product_line=STM32H747xx
+Disco.menu.pnum.STM32H747I_DISCO.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
+Disco.menu.pnum.STM32H747I_DISCO.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -DCORE_CM7
+Disco.menu.pnum.STM32H747I_DISCO.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
+
 # STM32WB5MM-DK board
 Disco.menu.pnum.STM32WB5MM_DK=STM32WB5MM-DK
 Disco.menu.pnum.STM32WB5MM_DK.node="DIS_WB5MMG"
diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt
index 2a4d55b6b1..b9cca5b0a1 100644
--- a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt
+++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt
@@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
   generic_clock.c
   PeripheralPins.c
   variant_generic.cpp
+  variant_DISCO_H747I.cpp
 )
 target_link_libraries(variant_bin PUBLIC variant_usage)
 
diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins_DISCO_H747I.c b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins_DISCO_H747I.c
new file mode 100644
index 0000000000..b364cd946c
--- /dev/null
+++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins_DISCO_H747I.c
@@ -0,0 +1,781 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+/*
+ * Automatically generated from STM32H742X(G-I)Hx.xml, STM32H743XGHx.xml
+ * STM32H743XIHx.xml, STM32H745XGHx.xml
+ * STM32H745XIHx.xml, STM32H747XGHx.xml
+ * STM32H747XIHx.xml, STM32H750XBHx.xml
+ * STM32H753XIHx.xml, STM32H755XIHx.xml
+ * STM32H757XIHx.xml
+ * CubeMX DB release 6.0.90
+ */
+#if defined(ARDUINO_STM32H747I_DISCO)
+#include "Arduino.h"
+#include "PeripheralPins.h"
+
+/* =====
+ * Notes:
+ * - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+ *   HW peripheral instances. You can use them the same way as any other "normal"
+ *   pin (i.e. analogWrite(PA7_ALT1, 128);).
+ *
+ * - Commented lines are alternative possibilities which are not used per default.
+ *   If you change them, you will have to know what you do
+ * =====
+ */
+
+//*** ADC ***
+
+#ifdef HAL_ADC_MODULE_ENABLED
+WEAK const PinMap PinMap_ADC[] = {
+  {PA_0,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16
+  {PA_0_C,      ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0
+  {PA_0_C_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0
+  //  {PA_1,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17
+  {PA_1_C,      ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1
+  {PA_1_C_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1
+  //  {PA_2,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14
+  //  {PA_2_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14
+  //  {PA_3,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15
+  //  {PA_3_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15
+  {PA_4,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18
+  {PA_4_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18
+  //  {PA_5,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19
+  //  {PA_5_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19
+  {PA_6,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3
+  {PA_6_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3
+  //  {PA_7,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7
+  //  {PA_7_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7
+  //  {PB_0,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9
+  //  {PB_0_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9
+  //  {PB_1,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5
+  //  {PB_1_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5
+  //  {PC_0,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10
+  //  {PC_0_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10
+  //  {PC_0_ALT2,   ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10
+  //  {PC_1,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11
+  //  {PC_1_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11
+  //  {PC_1_ALT2,   ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11
+  {PC_2,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12
+  {PC_2_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12
+  {PC_2_ALT2,   ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_INP12
+  {PC_2_C,      ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0
+  {PC_3,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13
+  {PC_3_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13
+  {PC_3_C,      ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1
+  //  {PC_4,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4
+  //  {PC_4_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4
+  //  {PC_5,        ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8
+  //  {PC_5_ALT1,   ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8
+  //  {PF_3,        ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INP5
+  //  {PF_4,        ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_INP9
+  //  {PF_5,        ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INP4
+  //  {PF_6,        ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_INP8
+  //  {PF_7,        ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INP3
+  {PF_8,        ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_INP7
+  //  {PF_9,        ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INP2
+  {PF_10,       ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_INP6
+  //  {PF_11,       ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2
+  //  {PF_12,       ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6
+  //  {PF_13,       ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2
+  //  {PF_14,       ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6
+  //  {PH_2,        ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INP13
+  //  {PH_3,        ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INP14
+  //  {PH_4,        ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INP15
+  //  {PH_5,        ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_INP16
+  {NC,          NP,   0}
+};
+#endif
+
+//*** DAC ***
+
+#ifdef HAL_DAC_MODULE_ENABLED
+WEAK const PinMap PinMap_DAC[] = {
+  {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1
+  //  {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2
+  {NC,   NP,   0}
+};
+#endif
+
+//*** I2C ***
+
+#ifdef HAL_I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SDA[] = {
+  //  {PB_7,      I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+  //  {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)},
+  {PB_9,      I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+  {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)},
+  //  {PB_11,     I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+  //  {PC_9,      I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+  {PD_13,     I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+  //  {PF_0,      I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+  //  {PF_15,     I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+  //  {PH_5,      I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+  //  {PH_8,      I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+  //  {PH_12,     I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+  {NC,        NP,   0}
+};
+#endif
+
+#ifdef HAL_I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SCL[] = {
+  //  {PA_8,      I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+  //  {PB_6,      I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+  //  {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)},
+  {PB_8,      I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+  {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)},
+  //  {PB_10,     I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+  {PD_12,     I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+  //  {PF_1,      I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+  //  {PF_14,     I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+  //  {PH_4,      I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+  //  {PH_7,      I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+  //  {PH_11,     I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+  {NC,        NP,   0}
+};
+#endif
+
+//*** No I3C ***
+
+//*** TIM ***
+
+#ifdef HAL_TIM_MODULE_ENABLED
+WEAK const PinMap PinMap_TIM[] = {
+  {PA_0,        TIM2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+  {PA_0_ALT1,   TIM5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+  {PA_0_C,      TIM2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+  {PA_0_C_ALT1, TIM5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+  //  {PA_1,        TIM2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+  //  {PA_1_ALT1,   TIM5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+  //  {PA_1_ALT2,   TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N
+  {PA_1_C,      TIM2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+  {PA_1_C_ALT1, TIM5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+  {PA_1_C_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N
+  // {PA_2,        TIM2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+  // {PA_2_ALT1,   TIM5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+  // {PA_2_ALT2,   TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1
+  // {PA_3,        TIM2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+  // {PA_3_ALT1,   TIM5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+  // {PA_3_ALT2,   TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2
+  // {PA_5,        TIM2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+  // {PA_5_ALT1,   TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+  {PA_6,        TIM3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+  {PA_6_ALT1,   TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+  //  {PA_7,        TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+  //  {PA_7_ALT1,   TIM3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+  //  {PA_7_ALT2,   TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+  //  {PA_7_ALT3,   TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+  //  {PA_8,        TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+  //  {PA_9,        TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+  //  {PA_10,       TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+  {PA_11,       TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+  //  {PA_15,       TIM2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+  //  {PB_0,        TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+  //  {PB_0_ALT1,   TIM3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+  //  {PB_0_ALT2,   TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+  //  {PB_1,        TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+  //  {PB_1_ALT1,   TIM3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+  //  {PB_1_ALT2,   TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+  //  {PB_3,        TIM2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+  //  {PB_4,        TIM3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+  //  {PB_5,        TIM3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+  //  {PB_6,        TIM4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+  //  {PB_6_ALT1,   TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N
+  //  {PB_7,        TIM4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+  //  {PB_7_ALT1,   TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N
+  {PB_8,        TIM4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+  {PB_8_ALT1,   TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1
+  {PB_9,        TIM4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+  {PB_9_ALT1,   TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1
+  //  {PB_10,       TIM2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+  //  {PB_11,       TIM2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+  //  {PB_13,       TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+  {PB_14,       TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+  {PB_14_ALT1,  TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+  {PB_14_ALT2,  TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1
+  {PB_15,       TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+  {PB_15_ALT1,  TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+  {PB_15_ALT2,  TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2
+  {PC_6,        TIM3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+  {PC_6_ALT1,   TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+  {PC_7,        TIM3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+  {PC_7_ALT1,   TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+  {PC_8,        TIM3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+  {PC_8_ALT1,   TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+  //  {PC_9,        TIM3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+  //  {PC_9_ALT1,   TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+  {PD_12,       TIM4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+  {PD_13,       TIM4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+  //  {PD_14,       TIM4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+  //  {PD_15,       TIM4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+  //  {PE_4,        TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N
+  //  {PE_5,        TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1
+  //  {PE_6,        TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2
+  //  {PE_8,        TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+  //  {PE_9,        TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+  //  {PE_10,       TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+  //  {PE_11,       TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+  //  {PE_12,       TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+  //  {PE_13,       TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+  //  {PE_14,       TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+  //  {PF_6,        TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1
+  //  {PF_7,        TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1
+  {PF_8,        TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+  {PF_8_ALT1,   TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N
+  //  {PF_9,        TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+  //  {PF_9_ALT1,   TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N
+  //  {PH_6,        TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1
+  //  {PH_9,        TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2
+  //  {PH_10,       TIM5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+  //  {PH_11,       TIM5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+  //  {PH_12,       TIM5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+  //  {PH_13,       TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+  //  {PH_14,       TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+  //  {PH_15,       TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+  //  {PI_0,        TIM5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+  //  {PI_2,        TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+  //  {PI_5,        TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+  //  {PI_6,        TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+  //  {PI_7,        TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+  {PJ_6,        TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+  {PJ_7,        TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+  {PJ_8,        TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+  {PJ_8_ALT1,   TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+  {PJ_9,        TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+  {PJ_9_ALT1,   TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+  {PJ_10,       TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+  {PJ_10_ALT1,  TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+  {PJ_11,       TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+  {PJ_11_ALT1,  TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+  {PK_0,        TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+  {PK_0_ALT1,   TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+  {PK_1,        TIM1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+  {PK_1_ALT1,   TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+  {NC,          NP,    0}
+};
+#endif
+
+//*** UART ***
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_TX[] = {
+  {PA_0,       UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  {PA_0_C,     UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  //  {PA_2,       USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+  {PA_9,       LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)},
+  {PA_9_ALT1,  USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+  {PA_12,      UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)},
+  //  {PA_15,      UART7,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)},
+  //  {PB_4,       UART7,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)},
+  //  {PB_6,       LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)},
+  //  {PB_6_ALT1,  UART5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)},
+  //  {PB_6_ALT2,  USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+  {PB_9,       UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  //  {PB_10,      USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+  //  {PB_13,      UART5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)},
+  {PB_14,      USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+  {PC_6,       USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+  //  {PC_10,      UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  //  {PC_10_ALT1, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+  //  {PC_12,      UART5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+  //  {PD_1,       UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  {PD_5,       USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+  //  {PD_8,       USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+  //  {PE_1,       UART8,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+  //  {PE_8,       UART7,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)},
+  //  {PF_7,       UART7,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)},
+  //  {PG_14,      USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+  //  {PH_13,      UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  {PJ_8,       UART8,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+  {NC,         NP,      0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RX[] = {
+  //  {PA_1,       UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  {PA_1_C,     UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  //  {PA_3,       USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+  //  {PA_8,       UART7,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)},
+  {PA_10,      LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)},
+  {PA_10_ALT1, USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+  {PA_11,      UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)},
+  //  {PB_3,       UART7,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)},
+  //  {PB_5,       UART5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)},
+  //  {PB_7,       LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)},
+  //  {PB_7_ALT1,  USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+  {PB_8,       UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  //  {PB_11,      USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+  //  {PB_12,      UART5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)},
+  {PB_15,      USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+  {PC_7,       USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+  //  {PC_11,      UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  //  {PC_11_ALT1, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+  //  {PD_0,       UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  //  {PD_2,       UART5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+  {PD_6,       USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+  //  {PD_9,       USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+  //  {PE_0,       UART8,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+  //  {PE_7,       UART7,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)},
+  //  {PF_6,       UART7,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)},
+  //  {PG_9,       USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+  //  {PH_14,      UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  //  {PI_9,       UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  {PJ_9,       UART8,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+  {NC,         NP,      0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RTS[] = {
+  //  {PA_1,       USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+  {PA_1_C,     USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+  {PA_12,      LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)},
+  {PA_12_ALT1, USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+  //  {PA_15,      UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  {PB_14,      UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  //  {PB_14_ALT1, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+  //  {PC_8,       UART5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+  {PD_4,       USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+  //  {PD_12,      USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+  //  {PD_15,      UART8,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+  //  {PE_9,       UART7,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)},
+  //  {PF_8,       UART7,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)},
+  //  {PG_8,       USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+  //  {PG_12,      USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+  {NC,         NP,      0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_CTS[] = {
+  {PA_0,       USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+  {PA_0_C,     USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+  {PA_11,      LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)},
+  {PA_11_ALT1, USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+  //  {PB_0,       UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  //  {PB_13,      USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+  {PB_15,      UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+  //  {PC_9,       UART5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+  {PD_3,       USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+  //  {PD_11,      USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+  //  {PD_14,      UART8,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+  //  {PE_10,      UART7,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)},
+  //  {PF_9,       UART7,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)},
+  //  {PG_13,      USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+  //  {PG_15,      USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+  {NC,         NP,      0}
+};
+#endif
+
+//*** SPI ***
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MOSI[] = {
+  //  {PA_7,      SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+  //  {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)},
+  //  {PB_2,      SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)},
+  //  {PB_5,      SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+  //  {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)},
+  //  {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)},
+  {PB_15,     SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  //  {PC_1,      SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  {PC_3,      SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  {PC_3_C,    SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  //  {PC_12,     SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+  //  {PD_6,      SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)},
+  //  {PD_7,      SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+  //  {PE_6,      SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+  //  {PE_14,     SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+  //  {PF_9,      SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+  //  {PF_11,     SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+  //  {PG_14,     SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
+  //  {PI_3,      SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  {PJ_10,     SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+  {NC,        NP,   0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MISO[] = {
+  //  {PA_6,      SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+  //  {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)},
+  //  {PB_4,      SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+  //  {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+  //  {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)},
+  {PB_14,     SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  {PC_2,      SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  {PC_2_C,    SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  //  {PC_11,     SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+  //  {PE_5,      SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+  //  {PE_13,     SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+  {PF_8,      SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+  //  {PG_9,      SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+  //  {PG_12,     SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
+  //  {PH_7,      SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+  //  {PI_2,      SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  {PJ_11,     SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+  {NC,        NP,   0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SCLK[] = {
+  //  {PA_5,      SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+  //  {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)},
+  //  {PA_9,      SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  {PA_12,     SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  //  {PB_3,      SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+  //  {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+  //  {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)},
+  //  {PB_10,     SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  //  {PB_13,     SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  //  {PC_10,     SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+  {PD_3,      SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  //  {PE_2,      SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+  //  {PE_12,     SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+  //  {PF_7,      SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+  //  {PG_11,     SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+  //  {PG_13,     SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
+  //  {PH_6,      SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+  //  {PI_1,      SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  {PK_0,      SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+  {NC,        NP,   0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SSEL[] = {
+  //  {PA_4,       SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+  //  {PA_4_ALT1,  SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+  //  {PA_4_ALT2,  SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)},
+  {PA_11,      SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  //  {PA_15,      SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+  //  {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+  //  {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)},
+  //  {PB_4,       SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)},
+  {PB_9,       SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  //  {PB_12,      SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  //  {PE_4,       SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+  //  {PE_11,      SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+  //  {PF_6,       SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+  //  {PG_8,       SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
+  //  {PG_10,      SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+  //  {PH_5,       SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+  //  {PI_0,       SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+  {PK_1,       SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+  {NC,         NP,   0}
+};
+#endif
+
+//*** FDCAN ***
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+WEAK const PinMap PinMap_CAN_RD[] = {
+  {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+  //  {PB_5,  FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)},
+  {PB_8,  FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+  //  {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)},
+  //  {PD_0,  FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+  //  {PH_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+  //  {PI_9,  FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+  {NC,    NP,     0}
+};
+#endif
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+WEAK const PinMap PinMap_CAN_TD[] = {
+  {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+  //  {PB_6,  FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)},
+  {PB_9,  FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+  //  {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)},
+  //  {PD_1,  FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+  //  {PH_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+  {NC,    NP,     0}
+};
+#endif
+
+//*** ETHERNET ***
+
+#if defined(HAL_ETH_MODULE_ENABLED) || defined(HAL_ETH_LEGACY_MODULE_ENABLED)
+WEAK const PinMap PinMap_Ethernet[] = {
+  //  {PA_0,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
+  //  {PA_0_C,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
+  {PA_1,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK
+  //  {PA_1_ALT1,   ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK
+  //  {PA_1_C,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK
+  //  {PA_1_C_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK
+  {PA_2,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO
+  //  {PA_3,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL
+  {PA_7,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV
+  //  {PA_7_ALT1,   ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV
+  //  {PB_0,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2
+  //  {PB_1,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3
+  //  {PB_5,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT
+  //  {PB_8,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3
+  //  {PB_10,       ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER
+  //  {PB_11,       ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN
+  //  {PB_12,       ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0
+  //  {PB_13,       ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1
+  //  {PC_1,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC
+  //  {PC_2,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2
+  //  {PC_2_C,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2
+  //  {PC_3,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK
+  //  {PC_3_C,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK
+  {PC_4,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0
+  {PC_5,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1
+  //  {PE_2,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3
+  //  {PG_8,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT
+  {PG_11,       ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN
+  {PG_12,       ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1
+  {PG_13,       ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0
+  //  {PG_14,       ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1
+  //  {PH_2,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
+  //  {PH_3,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL
+  //  {PH_6,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2
+  //  {PH_7,        ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3
+  //  {PI_10,       ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER
+  {NC,          NP,  0}
+};
+#endif
+
+//*** QUADSPI ***
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_QUADSPI_DATA0[] = {
+  //  {PC_9,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0
+  {PD_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0
+  //  {PE_7,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0
+  //  {PF_8,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
+  {PH_2,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO0
+  {NC,    NP,      0}
+};
+#endif
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_QUADSPI_DATA1[] = {
+  //  {PC_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1
+  //  {PD_12, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1
+  //  {PE_8,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1
+  {PF_9,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
+  {PH_3,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO1
+  {NC,    NP,      0}
+};
+#endif
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_QUADSPI_DATA2[] = {
+  //  {PE_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2
+  //  {PE_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2
+  {PF_7, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2
+  {PG_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2
+  {NC,   NP,      0}
+};
+#endif
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_QUADSPI_DATA3[] = {
+  //  {PA_1,   QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3
+  //  {PA_1_C, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3
+  //  {PD_13,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3
+  //  {PE_10,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3
+  {PF_6,   QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3
+  {PG_14,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3
+  {NC,     NP,      0}
+};
+#endif
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_QUADSPI_SCLK[] = {
+  {PB_2,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK
+  //  {PF_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK
+  {NC,    NP,      0}
+};
+#endif
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_QUADSPI_SSEL[] = {
+  //  {PB_6,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+  //  {PB_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS
+  //  {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS
+  {PG_6,  QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+  {NC,    NP,      0}
+};
+#endif
+
+//*** USB ***
+
+#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED)
+WEAK const PinMap PinMap_USB_OTG_FS[] = {
+  //  {PA_8,  USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_SOF
+  //  {PA_9,  USB_OTG_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS
+  //  {PA_10, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_ID
+  //  {PA_11, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DM
+  //  {PA_12, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DP
+  {NC,    NP,         0}
+};
+
+#ifndef USE_USB_HS
+  #error USB speed cannot be "Low/Full Speed" on this board
+#endif
+
+#endif
+
+#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED)
+WEAK const PinMap PinMap_USB_OTG_HS[] = {
+#ifdef USE_USB_HS_IN_FS
+#error USB speed cannot be "High Speed in Full Speed mode" on this board
+  //  {PA_4,   USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_SOF
+  //  {PB_12,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_ID
+  //  {PB_13,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS
+  //  {PB_14,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DM
+  //  {PB_15,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DP
+#else
+  {PA_3,   USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D0
+  {PA_5,   USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_CK
+  {PB_0,   USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D1
+  {PB_1,   USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D2
+  {PB_5,   USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D7
+  {PB_10,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D3
+  {PB_11,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D4
+  {PB_12,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D5
+  {PB_13,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D6
+  {PC_0,   USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_STP
+  //  {PC_2,   USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR
+  //  {PC_2_C, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR
+  //  {PC_3,   USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT
+  //  {PC_3_C, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT
+  {PH_4,   USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT
+  {PI_11,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR
+#endif /* USE_USB_HS_IN_FS */
+  {NC,     NP,         0}
+};
+#endif
+
+//*** SD ***
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_CMD[] = {
+
+  {PD_2,   SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDIO1)}, // SDMMC1_CMD
+  {PA_0,   SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDIO2)}, // SDMMC2_CMD
+  {PA_0_C, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDIO2)}, // SDMMC2_CMD
+  //  {PD_7,   SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDIO2)}, // SDMMC2_CMD
+  {NC,     NP,     0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_CK[] = {
+  // {PC_1,  SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDIO2)}, // SDMMC2_CK
+  {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDIO1)}, // SDMMC1_CK
+  {PD_6,  SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDIO2)}, // SDMMC2_CK
+  {NC,    NP,     0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA0[] = {
+
+  {PC_8,  SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D0
+  {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDIO2)}, // SDMMC2_D0
+  {NC,    NP,     0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA1[] = {
+  //  {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDIO2)}, // SDMMC2_D1
+  {PC_9,  SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D1
+  {NC,    NP,     0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA2[] = {
+  //  {PB_3,  SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDIO2)}, // SDMMC2_D2
+  {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D2
+  //  {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D2
+  {NC,    NP,     0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA3[] = {
+  //  {PB_4,  SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDIO2)}, // SDMMC2_D3
+  {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D3
+  {NC,    NP,     0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA4[] = {
+  //  {PB_8,      SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D4
+  //  {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D4
+  {NC,        NP,     0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA5[] = {
+  //  {PB_9,      SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D5
+  //  {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D5
+  {NC,        NP,     0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA6[] = {
+  //  {PC_6,      SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D6
+  //  {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D6
+  {NC,        NP,     0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA7[] = {
+  //  {PC_7,      SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO1)}, // SDMMC1_D7
+  //  {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDIO2)}, // SDMMC2_D7
+  {NC,        NP,     0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_CKIN[] = {
+  //  {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDIO1)}, // SDMMC1_CKIN
+  {NC,   NP,     0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_CDIR[] = {
+  //  {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDIO1)}, // SDMMC1_CDIR
+  {NC,   NP,     0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_D0DIR[] = {
+  //  {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDIO1)}, // SDMMC1_D0DIR
+  {NC,   NP,     0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_D123DIR[] = {
+  //  {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDIO1)}, // SDMMC1_D123DIR
+  {NC,   NP,     0}
+};
+#endif
+
+#endif /* ARDUINO_STM32H747I_DISCO */
diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.cpp b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.cpp
new file mode 100644
index 0000000000..8bcaf7fcc5
--- /dev/null
+++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.cpp
@@ -0,0 +1,313 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2023, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_STM32H747I_DISCO)
+#include "pins_arduino.h"
+
+//Digital pin number mapping array
+const PinName digitalPin[] = {
+  PJ_9,
+  PJ_8,
+  PJ_3,
+  PF_8,
+  PJ_4,
+  PA_6,
+  PJ_7,
+  PJ_0,
+  PJ_5,
+  PJ_6,
+  PK_1,
+  PJ_10,
+  PJ_11,
+  PK_0,
+  PD_13,
+  PD_12,
+  PA_4,
+  PF_10,
+  PA_0_C,
+  PA_1_C,
+  PC_2_C,
+  PC_3_C,
+  PI_12,
+  PI_13,
+  PI_14,
+  PI_15,
+  PA_10,
+  PA_9,
+  PA_11,
+  PA_12,
+  PC_2,
+  PC_3,
+  PK_2,
+  PK_3,
+  PK_4,
+  PK_5,
+  PK_6,
+  PC_13,
+  PB_2,
+  PG_6,
+  PD_11,
+  PF_9,
+  PF_7,
+  PF_6,
+  PH_2,
+  PH_3,
+  PG_9,
+  PG_14,
+  PC_8,
+  PC_9,
+  PC_10,
+  PC_11,
+  PC_12,
+  PD_2,
+  PI_8,
+  PG_10,
+  PB_7,
+  PJ_14,
+  PA_5,
+  PA_3,
+  PB_0,
+  PB_1,
+  PB_10,
+  PB_11,
+  PB_12,
+  PB_13,
+  PB_5,
+  PC_0,
+  PH_4,
+  PI_11,
+  PJ_1,
+  PD_7,
+  PE_3,
+  PE_4,
+  PE_5,
+  PE_6,
+  PG_7,
+  PC_1,
+  PE_2,
+  PJ_15,
+  PA_0,
+  PD_5,
+  PD_6,
+  PD_4,
+  PB_15,
+  PB_14,
+  PC_6,
+  PJ_13,
+  PC_7,
+  PD_3,
+  PB_9,
+  PB_8,
+  PH_0,
+  PH_1,
+  PC_14,
+  PC_15,
+  PA_8,
+  PJ_12,
+  PG_3,
+  PJ_2,
+  PB_6,
+  PK_7,
+  PE_0,
+  PE_1,
+  PI_4,
+  PI_5,
+  PG_8,
+  PH_5,
+  PH_6,
+  PH_7,
+  PF_11,
+  PG_15,
+  PD_14,
+  PD_15,
+  PD_0,
+  PD_1,
+  PE_7,
+  PE_8,
+  PE_9,
+  PE_10,
+  PE_11,
+  PE_12,
+  PE_13,
+  PE_14,
+  PE_15,
+  PD_8,
+  PD_9,
+  PD_10,
+  PH_8,
+  PH_9,
+  PH_10,
+  PH_11,
+  PH_12,
+  PH_13,
+  PH_14,
+  PH_15,
+  PI_0,
+  PI_1,
+  PI_2,
+  PI_3,
+  PI_6,
+  PI_7,
+  PI_9,
+  PI_10,
+  PF_0,
+  PF_1,
+  PF_2,
+  PF_3,
+  PF_4,
+  PF_5,
+  PF_12,
+  PF_13,
+  PF_14,
+  PF_15,
+  PG_0,
+  PG_1,
+  PG_2,
+  PG_4,
+  PG_5,
+  PA_13,
+  PA_14,
+  PA_15,
+  PB_3,
+  PB_4,
+  PA_1,
+  PA_2,
+  PA_7,
+  PC_4,
+  PC_5,
+  PG_11,
+  PG_12,
+  PG_13
+};
+
+// Analog (Ax) pin number mapping array
+const uint32_t analogInputPin[] = {
+  16, //A0
+  17, //A1
+  18, //A2
+  19, //A3
+  20, //A4
+  21  //A5
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  * @brief  System Clock Configuration
+  * @param  None
+  * @retval None
+  */
+WEAK void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Supply configuration update enable
+  */
+  HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+    * in the RCC_OscInitTypeDef structure.
+    */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_CSI
+                                     | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
+                                     | RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.CSIState = RCC_CSI_ON;
+  RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 5;
+  RCC_OscInitStruct.PLL.PLLN = 192;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 6;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+                                | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
+  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1);
+
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
+
+  /** Initializes the peripherals clock
+  */
+  /** Initializes the peripherals clock
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_CKPER
+                                             | RCC_PERIPHCLK_HRTIM1 | RCC_PERIPHCLK_I2C123 | RCC_PERIPHCLK_I2C4
+                                             | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM3
+                                             | RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_USB
+                                             | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6
+                                             | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578
+                                             | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_FMC;
+  PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP;
+  PeriphClkInitStruct.CecClockSelection = RCC_CECCLKSOURCE_CSI;
+  PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI;
+  PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_D1HCLK;
+  PeriphClkInitStruct.Hrtim1ClockSelection = RCC_HRTIM1CLK_CPUCLK;
+  PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
+  PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_D3PCLK1;
+  PeriphClkInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_D2PCLK1;
+  PeriphClkInitStruct.Lptim2ClockSelection = RCC_LPTIM2CLKSOURCE_D3PCLK1;
+  PeriphClkInitStruct.Lptim345ClockSelection = RCC_LPTIM345CLKSOURCE_D3PCLK1;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_D3PCLK1;
+  PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL;
+  PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL;
+  PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_D2PCLK1;
+  PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_D3PCLK1;
+  PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
+  PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ARDUINO_STM32H747I_DISCO */
diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h
new file mode 100644
index 0000000000..43c21a3f4e
--- /dev/null
+++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h
@@ -0,0 +1,357 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2023, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ *        STM32 pins number
+ *----------------------------------------------------------------------------*/
+#define PJ9                             0       // UART8_RX
+#define PJ8                             1       // UART8_TX
+#define PJ3                             2
+#define PF8                             3       // S_TIM13_CH1 / PMOD #14
+#define PJ4                             4
+#define PA6                             5       // DCMI_PIXCK
+#define PJ7                             6       // TIM8_CH2N
+#define PJ0                             7
+#define PJ5                             8
+#define PJ6                             9       // S_TIM8_CH2
+#define PK1                             10      // SPI5_NSS
+#define PJ10                            11      // SPI5_MOSI
+#define PJ11                            12      // SPI5_MISO
+#define PK0                             13      // SPI5_SCK
+#define PD13                            14      // I2C4_SDA / PMOD #10
+#define PD12                            15      // I2C4_SCL / PMOD #7
+#define PA4                             PIN_A0  // Pin 16 - ADC12_INP18 / DCMI_HSYNC / PMOD #13
+#define PF10                            PIN_A1  // Pin 17 - ADC3_INP6
+#define PA0_C                           PIN_A2  // Pin 18 - ADC12_INP0
+#define PA1_C                           PIN_A3  // Pin 19 - ADC12_INP1
+#define PC2_C                           PIN_A4  // Pin 20 - ADC3_INP0
+#define PC3_C                           PIN_A5  // Pin 21 - ADC3_INP1
+
+// User LEDs
+#define PI12                            22      // LED1
+#define PI13                            23      // LED2
+#define PI14                            24      // LED3
+#define PI15                            25      // LED4
+
+// ST-Link UART
+#define PA10                            26      // USART1_RX / ST-Link Tx
+#define PA9                             27      // USART1_TX / ST-Link Rx
+
+// SPI
+#define PA11                            28      // SPI2_NSS / PMOD #1 NSS
+#define PA12                            29      // SPI2_SCK / PMOD #4 SCK
+#define PC2                             30      // SPI2_MISO / PMOD #3 MISOp
+#define PC3                             31      // SPI2_MOSI / PMOD #2 MOSIp
+
+// GPIO Buttons
+#define PK2                             32      // JOY_SEL
+#define PK3                             33      // JOY_DOWN
+#define PK4                             34      // JOY_LEFT
+#define PK5                             35      // JOY_RIGHT
+#define PK6                             36      // JOY_UP
+#define PC13                            37      // Wakeup Button / RTC_TAMP1
+
+// QuadSPI
+#define PB2                             38      // QUADSPI_CLK
+#define PG6                             39      // QUADSPI_BK1_NCS
+#define PD11                            40      // QUADSPI_BK1_IO0
+#define PF9                             41      // QUADSPI_BK1_IO1
+#define PF7                             42      // QUADSPI_BK1_IO2
+#define PF6                             43      // QUADSPI_BK1_IO3
+#define PH2                             44      // QUADSPI_BK2_IO0
+#define PH3                             45      // QUADSPI_BK2_IO1
+#define PG9                             46      // QUADSPI_BK2_IO2
+#define PG14                            47      // QUADSPI_BK2_IO3
+
+// SDIO/SDMMC
+#define PC8                             48      // SDMMC1_D0 / SDIO1_D0
+#define PC9                             49      // SDMMC1_D1 / SDIO1_D1 / DCMI_D3
+#define PC10                            50      // SDMMC1_D2 / SDIO1_D2
+#define PC11                            51      // SDMMC1_D3 / SDIO1_D3 / DCMI_D4
+#define PC12                            52      // SDMMC1_CK / SDIO1_CK
+#define PD2                             53      // SDMMC1_CMD / SDIO1_CMD
+#define PI8                             54      // uSD_Detect
+
+// Digital Camera Interface
+#define PG10                            55      // DCMI_D2
+#define PB7                             56      // DCMI_VSYNC
+#define PJ14                            57      // DCMI_PWR_EN
+
+// USB
+#define PA5                             58      // USB_OTG_HS_ULPI_CK
+#define PA3                             59      // USB_OTG_HS_ULPI_D0
+#define PB0                             60      // USB_OTG_HS_ULPI_D1
+#define PB1                             61      // USB_OTG_HS_ULPI_D2
+#define PB10                            62      // USB_OTG_HS_ULPI_D3
+#define PB11                            63      // USB_OTG_HS_ULPI_D4
+#define PB12                            64      // USB_OTG_HS_ULPI_D5
+#define PB13                            65      // USB_OTG_HS_ULPI_D6
+#define PB5                             66      // USB_OTG_HS_ULPI_D7
+#define PC0                             67      // USB_OTG_HS_ULPI_STP
+#define PH4                             68      // USB_OTG_HS_ULPI_NXT
+#define PI11                            69      // USB_OTG_HS_ULPI_DIR
+#define PJ1                             70      // OTG_HS_OverCurrent
+
+// Audio
+#define PD7                             71      // SPDIF_RX0
+#define PE3                             72      // SAI1_SD_B
+#define PE4                             73      // SAI1_FS_A
+#define PE5                             74      // SAI1_SCK_A
+#define PE6                             75      // SAI1_SD_A
+#define PG7                             76      // SAI1_MCLK_A
+#define PC1                             77      // SAI4_D1  / ETH_MDC
+#define PE2                             78      // SAI4_CK1 / ETH_nINT
+#define PJ15                            79      // Audio_INT (Audio Codec IRQ)
+
+// Pmod™
+#define PA0                             80      // PMOD #1 CTS
+#define PD5                             81      // PMOD #2 TX
+#define PD6                             82      // PMOD #3 RX
+#define PD4                             83      // PMOD #4 RTS
+#define PB15                            84      // PMOD #8
+#define PB14                            85      // PMOD #9
+#define PC6                             86      // PMOD #11 / DCMI_D0
+#define PJ13                            87      // PMOD #12
+#define PC7                             88      // PMOD #17 / DCMI_D1
+#define PD3                             89      // PMOD #18 / DCMI_D5
+#define PB9                             90      // PMOD #19
+#define PB8                             91      // PMOD #20
+
+// Clock outputs
+#define PH0                             92      // RCC_OSC_IN
+#define PH1                             93      // RCC_OSC_OUT
+#define PC14                            94      // RCC_OSC32_IN
+#define PC15                            95      // RCC_OSC32_OUT
+#define PA8                             96      // CEC_CK / RCC_MCO_1
+
+// LCD/DSI
+#define PJ12                            97      // LCD_BL_CTRL
+#define PG3                             98      // DSI_Reset
+#define PJ2                             99      // DSI_TE
+#define PB6                             100     // HDMI_CEC
+
+// Touch Screen Controller
+#define PK7                             101     // TOUCH_INT
+
+// Flash Memory Controller
+#define PE0                             102     // FMC_NBL0
+#define PE1                             103     // FMC_NBL1
+#define PI4                             104     // FMC_NBL2
+#define PI5                             105     // FMC_NBL3
+#define PG8                             106     // FMC_SDCLK
+#define PH5                             107     // FMC_SDNWE
+#define PH6                             108     // FMC_SDNE1
+#define PH7                             109     // FMC_SDCKE1
+#define PF11                            110     // FMC_SDNRAS
+#define PG15                            111     // FMC_SDNCAS
+#define PD14                            112     // FMC_D0
+#define PD15                            113     // FMC_D1
+#define PD0                             114     // FMC_D2
+#define PD1                             115     // FMC_D3
+#define PE7                             116     // FMC_D4
+#define PE8                             117     // FMC_D5
+#define PE9                             118     // FMC_D6
+#define PE10                            119     // FMC_D7
+#define PE11                            120     // FMC_D8
+#define PE12                            121     // FMC_D9
+#define PE13                            122     // FMC_D10
+#define PE14                            123     // FMC_D11
+#define PE15                            124     // FMC_D12
+#define PD8                             125     // FMC_D13
+#define PD9                             126     // FMC_D14
+#define PD10                            127     // FMC_D15
+#define PH8                             128     // FMC_D16
+#define PH9                             129     // FMC_D17
+#define PH10                            130     // FMC_D18
+#define PH11                            131     // FMC_D19
+#define PH12                            132     // FMC_D20
+#define PH13                            133     // FMC_D21
+#define PH14                            134     // FMC_D22
+#define PH15                            135     // FMC_D23
+#define PI0                             136     // FMC_D24
+#define PI1                             137     // FMC_D25
+#define PI2                             138     // FMC_D26
+#define PI3                             139     // FMC_D27
+#define PI6                             140     // FMC_D28
+#define PI7                             141     // FMC_D29
+#define PI9                             142     // FMC_D30
+#define PI10                            143     // FMC_D31
+#define PF0                             144     // FMC_A0
+#define PF1                             145     // FMC_A1
+#define PF2                             146     // FMC_A2
+#define PF3                             147     // FMC_A3
+#define PF4                             148     // FMC_A4
+#define PF5                             149     // FMC_A5
+#define PF12                            150     // FMC_A6
+#define PF13                            151     // FMC_A7
+#define PF14                            152     // FMC_A8
+#define PF15                            153     // FMC_A9
+#define PG0                             154     // FMC_A10
+#define PG1                             155     // FMC_A11
+#define PG2                             156     // FMC_A12
+// FMC_A13 does not exist
+#define PG4                             157     // FMC_A14
+#define PG5                             158     // FMC A15
+
+// JTAG/SWD
+#define PA13                            159     // TMS / SWDIO
+#define PA14                            160     // TCK / SWCLK
+#define PA15                            161     // TDI
+#define PB3                             162     // TDO / SWO
+#define PB4                             163     // TRST
+
+/* WARNING: Ethernet is unusable by default on the board */
+// Ethernet port
+#define PA1                             164     // ETH_REF_CLK
+#define PA2                             165     // ETH_MDIO
+#define PA7                             166     // ETH_CRS_DV
+#define PC4                             167     // ETH_RXD0
+#define PC5                             168     // ETH_RXD1
+#define PG11                            169     // ETH_TX_EN
+#define PG12                            170     // ETH_TXD1
+#define PG13                            171     // ETH_TXD0
+
+// Alternate pins number
+#define PA0_ALT1                        (PA0   | ALT1)
+#define PA0_C_ALT1                      (PA0_C | ALT1)
+#define PA1_C_ALT1                      (PA1_C | ALT1)
+#define PA1_C_ALT2                      (PA1_C | ALT2)
+#define PA4_ALT1                        (PA4   | ALT1)
+#define PA6_ALT1                        (PA6   | ALT1)
+#define PA9_ALT                         (PA9   | ALT1)
+#define PA10_ALT1                       (PA10  | ALT1)
+#define PA11_ALT1                       (PA11  | ALT1)
+#define PA12_ALT1                       (PA12  | ALT1)
+#define PB8_ALT1                        (PB8   | ALT1)
+#define PB9_ALT1                        (PB9   | ALT1)
+#define PB14_ALT1                       (PB14  | ALT1)
+#define PB14_ALT2                       (PB14  | ALT2)
+#define PB15_ALT1                       (PB15  | ALT1)
+#define PB15_ALT2                       (PB15  | ALT2)
+#define PC2_ALT1                        (PC2   | ALT1)
+#define PC2_ALT2                        (PC2   | ALT2)
+#define PC3_ALT1                        (PC3   | ALT1)
+#define PC6_ALT1                        (PC6   | ALT1)
+#define PC7_ALT1                        (PC7   | ALT1)
+#define PC8_ALT1                        (PC8   | ALT1)
+#define PF8_ALT1                        (PF8   | ALT1)
+#define PJ8_ALT1                        (PJ8   | ALT1)
+#define PJ9_ALT1                        (PJ9   | ALT1)
+#define PJ10_ALT1                       (PJ10  | ALT1)
+#define PJ11_ALT1                       (PJ11  | ALT1)
+#define PK0_ALT1                        (PK0   | ALT1)
+#define PK1_ALT1                        (PK1   | ALT1)
+
+#define NUM_DIGITAL_PINS        172
+#define NUM_DUALPAD_PINS        4
+#define NUM_ANALOG_INPUTS       6
+
+// On-board LED pin number
+#define LED_GREEN   PI12  //LED1
+#define LED_ORANGE  PI13  //LED2
+#define LED_RED     PI14  //LED3
+#define LED_BLUE    PI15  //LED4
+
+#ifndef LED_BUILTIN
+  #define LED_BUILTIN LED_GREEN
+#endif
+
+// On-board user button
+#ifndef USER_BTN
+  #define USER_BTN    PC13    //Wakeup button
+#endif
+
+// SPI Definitions are provided by "pins_arduino.h"
+// I2C definitions are provided by "pins_arduino.h"
+
+// UART Definitions
+#ifndef SERIAL_UART_INSTANCE
+  #define SERIAL_UART_INSTANCE  101 //LPUART1 is connected to ST-Link
+#endif
+
+// Timer Definitions
+// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+  #define TIMER_TONE            TIM6
+#endif
+#ifndef TIMER_SERVO
+  #define TIMER_SERVO           TIM7
+#endif
+
+// Default pin used for generic 'Serial' instance (wired to ST-Link)
+#ifndef PIN_SERIAL_RX
+  #define PIN_SERIAL_RX         PA10
+#endif
+#ifndef PIN_SERIAL_TX
+  #define PIN_SERIAL_TX         PA9
+#endif
+
+// SDMMC signals - only define not available,
+// the rest is automatically provided by PeripheralPins
+#define SDMMC_CKIN_NA
+#define SDMMC_CDIR_NA
+#define SDMMC_D0DIR_NA
+#define SDMMC_D123DIR_NA
+
+// SD detect signal
+#ifndef SD_DETECT_PIN
+  #define SD_DETECT_PIN         PI8
+#endif
+
+// HAL configuration
+#define HSE_VALUE               25000000U
+
+// Extra HAL modules
+#if !defined(HAL_DAC_MODULE_DISABLED)
+  #define HAL_DAC_MODULE_ENABLED
+#endif
+#if !defined(HAL_ETH_MODULE_DISABLED)
+  #define HAL_ETH_MODULE_ENABLED
+#endif
+#if !defined(HAL_QSPI_MODULE_DISABLED)
+  #define HAL_QSPI_MODULE_ENABLED
+#endif
+#if !defined(HAL_SD_MODULE_DISABLED)
+  #define HAL_SD_MODULE_ENABLED
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *        Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+  // These serial port names are intended to allow libraries and architecture-neutral
+  // sketches to automatically default to the correct port name for a particular type
+  // of use.  For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+  // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+  //
+  // SERIAL_PORT_MONITOR        Port which normally prints to the Arduino Serial Monitor
+  //
+  // SERIAL_PORT_USBVIRTUAL     Port which is USB virtual serial
+  //
+  // SERIAL_PORT_LINUXBRIDGE    Port which connects to a Linux system via Bridge library
+  //
+  // SERIAL_PORT_HARDWARE       Hardware serial port, physical RX & TX pins.
+  //
+  // SERIAL_PORT_HARDWARE_OPEN  Hardware serial ports which are open for use.  Their RX & TX
+  //                            pins are NOT connected to anything by default.
+  #ifndef SERIAL_PORT_MONITOR
+    #define SERIAL_PORT_MONITOR   Serial
+  #endif
+
+  #ifndef SERIAL_PORT_HARDWARE
+    #define SERIAL_PORT_HARDWARE  Serial
+  #endif
+#endif

From 384ee0039f6c818ee9e37cc19ce5a8911b46ef13 Mon Sep 17 00:00:00 2001
From: Mathieu Choplain <mathieu.choplain@st.com>
Date: Mon, 30 Oct 2023 15:20:20 +0100
Subject: [PATCH 3/4] chore(cmake): update files

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
---
 cmake/boards_db.cmake                         | 1530 +++++++++++++++++
 .../CMakeLists.txt                            |    3 +-
 .../CMakeLists.txt                            |    2 +
 3 files changed, 1534 insertions(+), 1 deletion(-)

diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake
index bfa15ec206..efb6d9af9b 100644
--- a/cmake/boards_db.cmake
+++ b/cmake/boards_db.cmake
@@ -4786,6 +4786,60 @@ target_compile_options(DevEBoxH750VBTX_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# DEVKIT_IOT_CONTINUUM
+# -----------------------------------------------------------------------------
+
+set(DEVKIT_IOT_CONTINUUM_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)")
+set(DEVKIT_IOT_CONTINUUM_MAXSIZE 2097152)
+set(DEVKIT_IOT_CONTINUUM_MAXDATASIZE 786432)
+set(DEVKIT_IOT_CONTINUUM_MCU cortex-m33)
+set(DEVKIT_IOT_CONTINUUM_FPCONF "fpv4-sp-d16-hard")
+add_library(DEVKIT_IOT_CONTINUUM INTERFACE)
+target_compile_options(DEVKIT_IOT_CONTINUUM INTERFACE
+  "SHELL:-DSTM32U585xx "
+  "SHELL:-DCUSTOM_PERIPHERAL_PINS"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${DEVKIT_IOT_CONTINUUM_MCU}
+)
+target_compile_definitions(DEVKIT_IOT_CONTINUUM INTERFACE
+  "STM32U5xx"
+	"ARDUINO_DEVKIT_IOT_CONTINUUM"
+	"BOARD_NAME=\"DEVKIT_IOT_CONTINUUM\""
+	"BOARD_ID=DEVKIT_IOT_CONTINUUM"
+	"VARIANT_H=\"variant_DEVKIT_IOT_CONTINUUM.h\""
+)
+target_include_directories(DEVKIT_IOT_CONTINUUM INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
+  ${DEVKIT_IOT_CONTINUUM_VARIANT_PATH}
+)
+
+target_link_options(DEVKIT_IOT_CONTINUUM INTERFACE
+  "LINKER:--default-script=${DEVKIT_IOT_CONTINUUM_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=786432"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${DEVKIT_IOT_CONTINUUM_MCU}
+)
+
+add_library(DEVKIT_IOT_CONTINUUM_serial_disabled INTERFACE)
+target_compile_options(DEVKIT_IOT_CONTINUUM_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(DEVKIT_IOT_CONTINUUM_serial_generic INTERFACE)
+target_compile_options(DEVKIT_IOT_CONTINUUM_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(DEVKIT_IOT_CONTINUUM_serial_none INTERFACE)
+target_compile_options(DEVKIT_IOT_CONTINUUM_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+
 # DISCO_F030R8
 # -----------------------------------------------------------------------------
 
@@ -73450,6 +73504,170 @@ target_compile_options(GENERIC_H742VITX_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# GENERIC_H742XGHX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H742XGHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH")
+set(GENERIC_H742XGHX_MAXSIZE 1048576)
+set(GENERIC_H742XGHX_MAXDATASIZE 524288)
+set(GENERIC_H742XGHX_MCU cortex-m7)
+set(GENERIC_H742XGHX_FPCONF "-")
+add_library(GENERIC_H742XGHX INTERFACE)
+target_compile_options(GENERIC_H742XGHX INTERFACE
+  "SHELL:-DCORE_CM7 -DSTM32H742xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H742XGHX_MCU}
+)
+target_compile_definitions(GENERIC_H742XGHX INTERFACE
+  "STM32H7xx"
+	"ARDUINO_GENERIC_H742XGHX"
+	"BOARD_NAME=\"GENERIC_H742XGHX\""
+	"BOARD_ID=GENERIC_H742XGHX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H742XGHX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${GENERIC_H742XGHX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H742XGHX INTERFACE
+  "LINKER:--default-script=${GENERIC_H742XGHX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=1048576"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H742XGHX_MCU}
+)
+
+add_library(GENERIC_H742XGHX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H742XGHX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H742XGHX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H742XGHX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H742XGHX_serial_none INTERFACE)
+target_compile_options(GENERIC_H742XGHX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H742XGHX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H742XGHX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H742XGHX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H742XGHX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H742XGHX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H742XGHX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H742XGHX_usb_none INTERFACE)
+target_compile_options(GENERIC_H742XGHX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H742XGHX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H742XGHX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H742XGHX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H742XGHX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H742XGHX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H742XGHX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_H742XIHX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H742XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH")
+set(GENERIC_H742XIHX_MAXSIZE 2097152)
+set(GENERIC_H742XIHX_MAXDATASIZE 524288)
+set(GENERIC_H742XIHX_MCU cortex-m7)
+set(GENERIC_H742XIHX_FPCONF "-")
+add_library(GENERIC_H742XIHX INTERFACE)
+target_compile_options(GENERIC_H742XIHX INTERFACE
+  "SHELL:-DCORE_CM7 -DSTM32H742xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H742XIHX_MCU}
+)
+target_compile_definitions(GENERIC_H742XIHX INTERFACE
+  "STM32H7xx"
+	"ARDUINO_GENERIC_H742XIHX"
+	"BOARD_NAME=\"GENERIC_H742XIHX\""
+	"BOARD_ID=GENERIC_H742XIHX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H742XIHX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${GENERIC_H742XIHX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H742XIHX INTERFACE
+  "LINKER:--default-script=${GENERIC_H742XIHX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H742XIHX_MCU}
+)
+
+add_library(GENERIC_H742XIHX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H742XIHX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H742XIHX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H742XIHX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H742XIHX_serial_none INTERFACE)
+target_compile_options(GENERIC_H742XIHX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H742XIHX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H742XIHX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H742XIHX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H742XIHX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H742XIHX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H742XIHX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H742XIHX_usb_none INTERFACE)
+target_compile_options(GENERIC_H742XIHX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H742XIHX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H742XIHX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H742XIHX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H742XIHX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H742XIHX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H742XIHX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # GENERIC_H742ZGTX
 # -----------------------------------------------------------------------------
 
@@ -74270,6 +74488,170 @@ target_compile_options(GENERIC_H743VITX_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# GENERIC_H743XGHX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H743XGHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH")
+set(GENERIC_H743XGHX_MAXSIZE 1048576)
+set(GENERIC_H743XGHX_MAXDATASIZE 524288)
+set(GENERIC_H743XGHX_MCU cortex-m7)
+set(GENERIC_H743XGHX_FPCONF "-")
+add_library(GENERIC_H743XGHX INTERFACE)
+target_compile_options(GENERIC_H743XGHX INTERFACE
+  "SHELL:-DCORE_CM7 -DSTM32H743xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H743XGHX_MCU}
+)
+target_compile_definitions(GENERIC_H743XGHX INTERFACE
+  "STM32H7xx"
+	"ARDUINO_GENERIC_H743XGHX"
+	"BOARD_NAME=\"GENERIC_H743XGHX\""
+	"BOARD_ID=GENERIC_H743XGHX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H743XGHX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${GENERIC_H743XGHX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H743XGHX INTERFACE
+  "LINKER:--default-script=${GENERIC_H743XGHX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=1048576"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H743XGHX_MCU}
+)
+
+add_library(GENERIC_H743XGHX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H743XGHX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H743XGHX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H743XGHX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H743XGHX_serial_none INTERFACE)
+target_compile_options(GENERIC_H743XGHX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H743XGHX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H743XGHX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H743XGHX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H743XGHX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H743XGHX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H743XGHX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H743XGHX_usb_none INTERFACE)
+target_compile_options(GENERIC_H743XGHX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H743XGHX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H743XGHX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H743XGHX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H743XGHX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H743XGHX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H743XGHX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_H743XIHX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H743XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH")
+set(GENERIC_H743XIHX_MAXSIZE 2097152)
+set(GENERIC_H743XIHX_MAXDATASIZE 524288)
+set(GENERIC_H743XIHX_MCU cortex-m7)
+set(GENERIC_H743XIHX_FPCONF "-")
+add_library(GENERIC_H743XIHX INTERFACE)
+target_compile_options(GENERIC_H743XIHX INTERFACE
+  "SHELL:-DCORE_CM7 -DSTM32H743xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H743XIHX_MCU}
+)
+target_compile_definitions(GENERIC_H743XIHX INTERFACE
+  "STM32H7xx"
+	"ARDUINO_GENERIC_H743XIHX"
+	"BOARD_NAME=\"GENERIC_H743XIHX\""
+	"BOARD_ID=GENERIC_H743XIHX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H743XIHX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${GENERIC_H743XIHX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H743XIHX INTERFACE
+  "LINKER:--default-script=${GENERIC_H743XIHX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H743XIHX_MCU}
+)
+
+add_library(GENERIC_H743XIHX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H743XIHX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H743XIHX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H743XIHX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H743XIHX_serial_none INTERFACE)
+target_compile_options(GENERIC_H743XIHX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H743XIHX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H743XIHX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H743XIHX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H743XIHX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H743XIHX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H743XIHX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H743XIHX_usb_none INTERFACE)
+target_compile_options(GENERIC_H743XIHX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H743XIHX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H743XIHX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H743XIHX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H743XIHX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H743XIHX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H743XIHX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # GENERIC_H743ZGTX
 # -----------------------------------------------------------------------------
 
@@ -74434,6 +74816,170 @@ target_compile_options(GENERIC_H743ZITX_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# GENERIC_H745XGHX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H745XGHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH")
+set(GENERIC_H745XGHX_MAXSIZE 1048576)
+set(GENERIC_H745XGHX_MAXDATASIZE 524288)
+set(GENERIC_H745XGHX_MCU cortex-m7)
+set(GENERIC_H745XGHX_FPCONF "-")
+add_library(GENERIC_H745XGHX INTERFACE)
+target_compile_options(GENERIC_H745XGHX INTERFACE
+  "SHELL:-DCORE_CM7 -DSTM32H745xG  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H745XGHX_MCU}
+)
+target_compile_definitions(GENERIC_H745XGHX INTERFACE
+  "STM32H7xx"
+	"ARDUINO_GENERIC_H745XGHX"
+	"BOARD_NAME=\"GENERIC_H745XGHX\""
+	"BOARD_ID=GENERIC_H745XGHX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H745XGHX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${GENERIC_H745XGHX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H745XGHX INTERFACE
+  "LINKER:--default-script=${GENERIC_H745XGHX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=1048576"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H745XGHX_MCU}
+)
+
+add_library(GENERIC_H745XGHX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H745XGHX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H745XGHX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H745XGHX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H745XGHX_serial_none INTERFACE)
+target_compile_options(GENERIC_H745XGHX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H745XGHX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H745XGHX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H745XGHX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H745XGHX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H745XGHX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H745XGHX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H745XGHX_usb_none INTERFACE)
+target_compile_options(GENERIC_H745XGHX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H745XGHX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H745XGHX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H745XGHX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H745XGHX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H745XGHX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H745XGHX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_H745XIHX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H745XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH")
+set(GENERIC_H745XIHX_MAXSIZE 2097152)
+set(GENERIC_H745XIHX_MAXDATASIZE 524288)
+set(GENERIC_H745XIHX_MCU cortex-m7)
+set(GENERIC_H745XIHX_FPCONF "-")
+add_library(GENERIC_H745XIHX INTERFACE)
+target_compile_options(GENERIC_H745XIHX INTERFACE
+  "SHELL:-DCORE_CM7 -DSTM32H745xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H745XIHX_MCU}
+)
+target_compile_definitions(GENERIC_H745XIHX INTERFACE
+  "STM32H7xx"
+	"ARDUINO_GENERIC_H745XIHX"
+	"BOARD_NAME=\"GENERIC_H745XIHX\""
+	"BOARD_ID=GENERIC_H745XIHX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H745XIHX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${GENERIC_H745XIHX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H745XIHX INTERFACE
+  "LINKER:--default-script=${GENERIC_H745XIHX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H745XIHX_MCU}
+)
+
+add_library(GENERIC_H745XIHX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H745XIHX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H745XIHX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H745XIHX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H745XIHX_serial_none INTERFACE)
+target_compile_options(GENERIC_H745XIHX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H745XIHX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H745XIHX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H745XIHX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H745XIHX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H745XIHX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H745XIHX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H745XIHX_usb_none INTERFACE)
+target_compile_options(GENERIC_H745XIHX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H745XIHX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H745XIHX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H745XIHX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H745XIHX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H745XIHX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H745XIHX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # GENERIC_H747AGIX
 # -----------------------------------------------------------------------------
 
@@ -74762,6 +75308,170 @@ target_compile_options(GENERIC_H747IITX_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# GENERIC_H747XGHX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H747XGHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH")
+set(GENERIC_H747XGHX_MAXSIZE 1048576)
+set(GENERIC_H747XGHX_MAXDATASIZE 524288)
+set(GENERIC_H747XGHX_MCU cortex-m7)
+set(GENERIC_H747XGHX_FPCONF "-")
+add_library(GENERIC_H747XGHX INTERFACE)
+target_compile_options(GENERIC_H747XGHX INTERFACE
+  "SHELL:-DCORE_CM7 -DSTM32H747xG  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H747XGHX_MCU}
+)
+target_compile_definitions(GENERIC_H747XGHX INTERFACE
+  "STM32H7xx"
+	"ARDUINO_GENERIC_H747XGHX"
+	"BOARD_NAME=\"GENERIC_H747XGHX\""
+	"BOARD_ID=GENERIC_H747XGHX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H747XGHX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${GENERIC_H747XGHX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H747XGHX INTERFACE
+  "LINKER:--default-script=${GENERIC_H747XGHX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=1048576"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H747XGHX_MCU}
+)
+
+add_library(GENERIC_H747XGHX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H747XGHX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H747XGHX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H747XGHX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H747XGHX_serial_none INTERFACE)
+target_compile_options(GENERIC_H747XGHX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H747XGHX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H747XGHX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H747XGHX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H747XGHX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H747XGHX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H747XGHX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H747XGHX_usb_none INTERFACE)
+target_compile_options(GENERIC_H747XGHX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H747XGHX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H747XGHX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H747XGHX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H747XGHX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H747XGHX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H747XGHX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_H747XIHX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H747XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH")
+set(GENERIC_H747XIHX_MAXSIZE 2097152)
+set(GENERIC_H747XIHX_MAXDATASIZE 524288)
+set(GENERIC_H747XIHX_MCU cortex-m7)
+set(GENERIC_H747XIHX_FPCONF "-")
+add_library(GENERIC_H747XIHX INTERFACE)
+target_compile_options(GENERIC_H747XIHX INTERFACE
+  "SHELL:-DCORE_CM7 -DSTM32H747xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H747XIHX_MCU}
+)
+target_compile_definitions(GENERIC_H747XIHX INTERFACE
+  "STM32H7xx"
+	"ARDUINO_GENERIC_H747XIHX"
+	"BOARD_NAME=\"GENERIC_H747XIHX\""
+	"BOARD_ID=GENERIC_H747XIHX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H747XIHX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${GENERIC_H747XIHX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H747XIHX INTERFACE
+  "LINKER:--default-script=${GENERIC_H747XIHX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H747XIHX_MCU}
+)
+
+add_library(GENERIC_H747XIHX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H747XIHX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H747XIHX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H747XIHX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H747XIHX_serial_none INTERFACE)
+target_compile_options(GENERIC_H747XIHX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H747XIHX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H747XIHX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H747XIHX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H747XIHX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H747XIHX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H747XIHX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H747XIHX_usb_none INTERFACE)
+target_compile_options(GENERIC_H747XIHX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H747XIHX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H747XIHX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H747XIHX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H747XIHX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H747XIHX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H747XIHX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # GENERIC_H750IBKX
 # -----------------------------------------------------------------------------
 
@@ -75008,6 +75718,88 @@ target_compile_options(GENERIC_H750VBTX_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# GENERIC_H750XBHX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H750XBHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH")
+set(GENERIC_H750XBHX_MAXSIZE 131072)
+set(GENERIC_H750XBHX_MAXDATASIZE 524288)
+set(GENERIC_H750XBHX_MCU cortex-m7)
+set(GENERIC_H750XBHX_FPCONF "-")
+add_library(GENERIC_H750XBHX INTERFACE)
+target_compile_options(GENERIC_H750XBHX INTERFACE
+  "SHELL:-DCORE_CM7 -DSTM32H750xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H750XBHX_MCU}
+)
+target_compile_definitions(GENERIC_H750XBHX INTERFACE
+  "STM32H7xx"
+	"ARDUINO_GENERIC_H750XBHX"
+	"BOARD_NAME=\"GENERIC_H750XBHX\""
+	"BOARD_ID=GENERIC_H750XBHX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H750XBHX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${GENERIC_H750XBHX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H750XBHX INTERFACE
+  "LINKER:--default-script=${GENERIC_H750XBHX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=131072"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H750XBHX_MCU}
+)
+
+add_library(GENERIC_H750XBHX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H750XBHX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H750XBHX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H750XBHX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H750XBHX_serial_none INTERFACE)
+target_compile_options(GENERIC_H750XBHX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H750XBHX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H750XBHX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H750XBHX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H750XBHX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H750XBHX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H750XBHX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H750XBHX_usb_none INTERFACE)
+target_compile_options(GENERIC_H750XBHX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H750XBHX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H750XBHX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H750XBHX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H750XBHX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H750XBHX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H750XBHX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # GENERIC_H750ZBTX
 # -----------------------------------------------------------------------------
 
@@ -75418,6 +76210,88 @@ target_compile_options(GENERIC_H753VITX_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# GENERIC_H753XIHX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H753XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH")
+set(GENERIC_H753XIHX_MAXSIZE 2097152)
+set(GENERIC_H753XIHX_MAXDATASIZE 524288)
+set(GENERIC_H753XIHX_MCU cortex-m7)
+set(GENERIC_H753XIHX_FPCONF "-")
+add_library(GENERIC_H753XIHX INTERFACE)
+target_compile_options(GENERIC_H753XIHX INTERFACE
+  "SHELL:-DCORE_CM7 -DSTM32H753xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H753XIHX_MCU}
+)
+target_compile_definitions(GENERIC_H753XIHX INTERFACE
+  "STM32H7xx"
+	"ARDUINO_GENERIC_H753XIHX"
+	"BOARD_NAME=\"GENERIC_H753XIHX\""
+	"BOARD_ID=GENERIC_H753XIHX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H753XIHX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${GENERIC_H753XIHX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H753XIHX INTERFACE
+  "LINKER:--default-script=${GENERIC_H753XIHX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H753XIHX_MCU}
+)
+
+add_library(GENERIC_H753XIHX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H753XIHX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H753XIHX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H753XIHX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H753XIHX_serial_none INTERFACE)
+target_compile_options(GENERIC_H753XIHX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H753XIHX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H753XIHX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H753XIHX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H753XIHX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H753XIHX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H753XIHX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H753XIHX_usb_none INTERFACE)
+target_compile_options(GENERIC_H753XIHX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H753XIHX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H753XIHX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H753XIHX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H753XIHX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H753XIHX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H753XIHX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # GENERIC_H753ZITX
 # -----------------------------------------------------------------------------
 
@@ -75500,6 +76374,88 @@ target_compile_options(GENERIC_H753ZITX_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# GENERIC_H755XIHX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H755XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH")
+set(GENERIC_H755XIHX_MAXSIZE 2097152)
+set(GENERIC_H755XIHX_MAXDATASIZE 524288)
+set(GENERIC_H755XIHX_MCU cortex-m7)
+set(GENERIC_H755XIHX_FPCONF "-")
+add_library(GENERIC_H755XIHX INTERFACE)
+target_compile_options(GENERIC_H755XIHX INTERFACE
+  "SHELL:-DCORE_CM7 -DSTM32H755xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H755XIHX_MCU}
+)
+target_compile_definitions(GENERIC_H755XIHX INTERFACE
+  "STM32H7xx"
+	"ARDUINO_GENERIC_H755XIHX"
+	"BOARD_NAME=\"GENERIC_H755XIHX\""
+	"BOARD_ID=GENERIC_H755XIHX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H755XIHX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${GENERIC_H755XIHX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H755XIHX INTERFACE
+  "LINKER:--default-script=${GENERIC_H755XIHX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H755XIHX_MCU}
+)
+
+add_library(GENERIC_H755XIHX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H755XIHX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H755XIHX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H755XIHX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H755XIHX_serial_none INTERFACE)
+target_compile_options(GENERIC_H755XIHX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H755XIHX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H755XIHX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H755XIHX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H755XIHX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H755XIHX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H755XIHX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H755XIHX_usb_none INTERFACE)
+target_compile_options(GENERIC_H755XIHX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H755XIHX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H755XIHX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H755XIHX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H755XIHX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H755XIHX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H755XIHX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # GENERIC_H757AIIX
 # -----------------------------------------------------------------------------
 
@@ -75664,6 +76620,88 @@ target_compile_options(GENERIC_H757IITX_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# GENERIC_H757XIHX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H757XIHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH")
+set(GENERIC_H757XIHX_MAXSIZE 2097152)
+set(GENERIC_H757XIHX_MAXDATASIZE 524288)
+set(GENERIC_H757XIHX_MCU cortex-m7)
+set(GENERIC_H757XIHX_FPCONF "-")
+add_library(GENERIC_H757XIHX INTERFACE)
+target_compile_options(GENERIC_H757XIHX INTERFACE
+  "SHELL:-DCORE_CM7 -DSTM32H757xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H757XIHX_MCU}
+)
+target_compile_definitions(GENERIC_H757XIHX INTERFACE
+  "STM32H7xx"
+	"ARDUINO_GENERIC_H757XIHX"
+	"BOARD_NAME=\"GENERIC_H757XIHX\""
+	"BOARD_ID=GENERIC_H757XIHX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H757XIHX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${GENERIC_H757XIHX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H757XIHX INTERFACE
+  "LINKER:--default-script=${GENERIC_H757XIHX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H757XIHX_MCU}
+)
+
+add_library(GENERIC_H757XIHX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H757XIHX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H757XIHX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H757XIHX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H757XIHX_serial_none INTERFACE)
+target_compile_options(GENERIC_H757XIHX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H757XIHX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H757XIHX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H757XIHX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H757XIHX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H757XIHX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H757XIHX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H757XIHX_usb_none INTERFACE)
+target_compile_options(GENERIC_H757XIHX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H757XIHX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H757XIHX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H757XIHX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H757XIHX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H757XIHX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H757XIHX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # GENERIC_L010C6TX
 # -----------------------------------------------------------------------------
 
@@ -94168,6 +95206,170 @@ target_compile_options(GENERIC_U575AIIXQ_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# GENERIC_U575CITX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_U575CITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)")
+set(GENERIC_U575CITX_MAXSIZE 2097152)
+set(GENERIC_U575CITX_MAXDATASIZE 786432)
+set(GENERIC_U575CITX_MCU cortex-m33)
+set(GENERIC_U575CITX_FPCONF "-")
+add_library(GENERIC_U575CITX INTERFACE)
+target_compile_options(GENERIC_U575CITX INTERFACE
+  "SHELL:-DSTM32U575xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_U575CITX_MCU}
+)
+target_compile_definitions(GENERIC_U575CITX INTERFACE
+  "STM32U5xx"
+	"ARDUINO_GENERIC_U575CITX"
+	"BOARD_NAME=\"GENERIC_U575CITX\""
+	"BOARD_ID=GENERIC_U575CITX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_U575CITX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
+  ${GENERIC_U575CITX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_U575CITX INTERFACE
+  "LINKER:--default-script=${GENERIC_U575CITX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=786432"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_U575CITX_MCU}
+)
+
+add_library(GENERIC_U575CITX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_U575CITX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_U575CITX_serial_generic INTERFACE)
+target_compile_options(GENERIC_U575CITX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_U575CITX_serial_none INTERFACE)
+target_compile_options(GENERIC_U575CITX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_U575CITX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_U575CITX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_U575CITX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_U575CITX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_U575CITX_usb_HID INTERFACE)
+target_compile_options(GENERIC_U575CITX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_U575CITX_usb_none INTERFACE)
+target_compile_options(GENERIC_U575CITX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_U575CITX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_U575CITX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_U575CITX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_U575CITX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_U575CITX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_U575CITX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_U575CIUX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_U575CIUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)")
+set(GENERIC_U575CIUX_MAXSIZE 2097152)
+set(GENERIC_U575CIUX_MAXDATASIZE 786432)
+set(GENERIC_U575CIUX_MCU cortex-m33)
+set(GENERIC_U575CIUX_FPCONF "-")
+add_library(GENERIC_U575CIUX INTERFACE)
+target_compile_options(GENERIC_U575CIUX INTERFACE
+  "SHELL:-DSTM32U575xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_U575CIUX_MCU}
+)
+target_compile_definitions(GENERIC_U575CIUX INTERFACE
+  "STM32U5xx"
+	"ARDUINO_GENERIC_U575CIUX"
+	"BOARD_NAME=\"GENERIC_U575CIUX\""
+	"BOARD_ID=GENERIC_U575CIUX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_U575CIUX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
+  ${GENERIC_U575CIUX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_U575CIUX INTERFACE
+  "LINKER:--default-script=${GENERIC_U575CIUX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=786432"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_U575CIUX_MCU}
+)
+
+add_library(GENERIC_U575CIUX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_U575CIUX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_U575CIUX_serial_generic INTERFACE)
+target_compile_options(GENERIC_U575CIUX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_U575CIUX_serial_none INTERFACE)
+target_compile_options(GENERIC_U575CIUX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_U575CIUX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_U575CIUX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_U575CIUX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_U575CIUX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_U575CIUX_usb_HID INTERFACE)
+target_compile_options(GENERIC_U575CIUX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_U575CIUX_usb_none INTERFACE)
+target_compile_options(GENERIC_U575CIUX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_U575CIUX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_U575CIUX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_U575CIUX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_U575CIUX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_U575CIUX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_U575CIUX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # GENERIC_U575ZGTXQ
 # -----------------------------------------------------------------------------
 
@@ -94414,6 +95616,170 @@ target_compile_options(GENERIC_U585AIIXQ_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# GENERIC_U585CITX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_U585CITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)")
+set(GENERIC_U585CITX_MAXSIZE 2097152)
+set(GENERIC_U585CITX_MAXDATASIZE 786432)
+set(GENERIC_U585CITX_MCU cortex-m33)
+set(GENERIC_U585CITX_FPCONF "-")
+add_library(GENERIC_U585CITX INTERFACE)
+target_compile_options(GENERIC_U585CITX INTERFACE
+  "SHELL:-DSTM32U585xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_U585CITX_MCU}
+)
+target_compile_definitions(GENERIC_U585CITX INTERFACE
+  "STM32U5xx"
+	"ARDUINO_GENERIC_U585CITX"
+	"BOARD_NAME=\"GENERIC_U585CITX\""
+	"BOARD_ID=GENERIC_U585CITX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_U585CITX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
+  ${GENERIC_U585CITX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_U585CITX INTERFACE
+  "LINKER:--default-script=${GENERIC_U585CITX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=786432"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_U585CITX_MCU}
+)
+
+add_library(GENERIC_U585CITX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_U585CITX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_U585CITX_serial_generic INTERFACE)
+target_compile_options(GENERIC_U585CITX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_U585CITX_serial_none INTERFACE)
+target_compile_options(GENERIC_U585CITX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_U585CITX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_U585CITX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_U585CITX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_U585CITX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_U585CITX_usb_HID INTERFACE)
+target_compile_options(GENERIC_U585CITX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_U585CITX_usb_none INTERFACE)
+target_compile_options(GENERIC_U585CITX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_U585CITX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_U585CITX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_U585CITX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_U585CITX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_U585CITX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_U585CITX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_U585CIUX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_U585CIUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)")
+set(GENERIC_U585CIUX_MAXSIZE 2097152)
+set(GENERIC_U585CIUX_MAXDATASIZE 786432)
+set(GENERIC_U585CIUX_MCU cortex-m33)
+set(GENERIC_U585CIUX_FPCONF "-")
+add_library(GENERIC_U585CIUX INTERFACE)
+target_compile_options(GENERIC_U585CIUX INTERFACE
+  "SHELL:-DSTM32U585xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_U585CIUX_MCU}
+)
+target_compile_definitions(GENERIC_U585CIUX INTERFACE
+  "STM32U5xx"
+	"ARDUINO_GENERIC_U585CIUX"
+	"BOARD_NAME=\"GENERIC_U585CIUX\""
+	"BOARD_ID=GENERIC_U585CIUX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_U585CIUX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
+  ${GENERIC_U585CIUX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_U585CIUX INTERFACE
+  "LINKER:--default-script=${GENERIC_U585CIUX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=786432"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_U585CIUX_MCU}
+)
+
+add_library(GENERIC_U585CIUX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_U585CIUX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_U585CIUX_serial_generic INTERFACE)
+target_compile_options(GENERIC_U585CIUX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_U585CIUX_serial_none INTERFACE)
+target_compile_options(GENERIC_U585CIUX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_U585CIUX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_U585CIUX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_U585CIUX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_U585CIUX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_U585CIUX_usb_HID INTERFACE)
+target_compile_options(GENERIC_U585CIUX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_U585CIUX_usb_none INTERFACE)
+target_compile_options(GENERIC_U585CIUX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_U585CIUX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_U585CIUX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_U585CIUX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_U585CIUX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_U585CIUX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_U585CIUX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # GENERIC_U585ZITXQ
 # -----------------------------------------------------------------------------
 
@@ -99836,6 +101202,88 @@ target_compile_options(NUCLEO_H743ZI2_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# NUCLEO_H753ZI
+# -----------------------------------------------------------------------------
+
+set(NUCLEO_H753ZI_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT")
+set(NUCLEO_H753ZI_MAXSIZE 2097152)
+set(NUCLEO_H753ZI_MAXDATASIZE 524288)
+set(NUCLEO_H753ZI_MCU cortex-m7)
+set(NUCLEO_H753ZI_FPCONF "fpv4-sp-d16-hard")
+add_library(NUCLEO_H753ZI INTERFACE)
+target_compile_options(NUCLEO_H753ZI INTERFACE
+  "SHELL:-DSTM32H753xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${NUCLEO_H753ZI_MCU}
+)
+target_compile_definitions(NUCLEO_H753ZI INTERFACE
+  "STM32H7xx"
+	"ARDUINO_NUCLEO_H753ZI"
+	"BOARD_NAME=\"NUCLEO_H753ZI\""
+	"BOARD_ID=NUCLEO_H753ZI"
+	"VARIANT_H=\"variant_NUCLEO_H753ZI.h\""
+)
+target_include_directories(NUCLEO_H753ZI INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${NUCLEO_H753ZI_VARIANT_PATH}
+)
+
+target_link_options(NUCLEO_H753ZI INTERFACE
+  "LINKER:--default-script=${NUCLEO_H753ZI_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${NUCLEO_H753ZI_MCU}
+)
+
+add_library(NUCLEO_H753ZI_serial_disabled INTERFACE)
+target_compile_options(NUCLEO_H753ZI_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(NUCLEO_H753ZI_serial_generic INTERFACE)
+target_compile_options(NUCLEO_H753ZI_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(NUCLEO_H753ZI_serial_none INTERFACE)
+target_compile_options(NUCLEO_H753ZI_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(NUCLEO_H753ZI_usb_CDC INTERFACE)
+target_compile_options(NUCLEO_H753ZI_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(NUCLEO_H753ZI_usb_CDCgen INTERFACE)
+target_compile_options(NUCLEO_H753ZI_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(NUCLEO_H753ZI_usb_HID INTERFACE)
+target_compile_options(NUCLEO_H753ZI_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(NUCLEO_H753ZI_usb_none INTERFACE)
+target_compile_options(NUCLEO_H753ZI_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(NUCLEO_H753ZI_xusb_FS INTERFACE)
+target_compile_options(NUCLEO_H753ZI_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(NUCLEO_H753ZI_xusb_HS INTERFACE)
+target_compile_options(NUCLEO_H753ZI_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(NUCLEO_H753ZI_xusb_HSFS INTERFACE)
+target_compile_options(NUCLEO_H753ZI_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # NUCLEO_L010RB
 # -----------------------------------------------------------------------------
 
@@ -103296,6 +104744,88 @@ target_compile_options(STM32H573I_DK_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# STM32H747I_DISCO
+# -----------------------------------------------------------------------------
+
+set(STM32H747I_DISCO_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH")
+set(STM32H747I_DISCO_MAXSIZE 2097152)
+set(STM32H747I_DISCO_MAXDATASIZE 524288)
+set(STM32H747I_DISCO_MCU cortex-m7)
+set(STM32H747I_DISCO_FPCONF "fpv4-sp-d16-hard")
+add_library(STM32H747I_DISCO INTERFACE)
+target_compile_options(STM32H747I_DISCO INTERFACE
+  "SHELL:-DSTM32H747xx   -DCORE_CM7"
+  "SHELL:-DCUSTOM_PERIPHERAL_PINS"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${STM32H747I_DISCO_MCU}
+)
+target_compile_definitions(STM32H747I_DISCO INTERFACE
+  "STM32H7xx"
+	"ARDUINO_STM32H747I_DISCO"
+	"BOARD_NAME=\"STM32H747I_DISCO\""
+	"BOARD_ID=STM32H747I_DISCO"
+	"VARIANT_H=\"variant_STM32H747I_DISCO.h\""
+)
+target_include_directories(STM32H747I_DISCO INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+  ${STM32H747I_DISCO_VARIANT_PATH}
+)
+
+target_link_options(STM32H747I_DISCO INTERFACE
+  "LINKER:--default-script=${STM32H747I_DISCO_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=2097152"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=524288"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${STM32H747I_DISCO_MCU}
+)
+
+add_library(STM32H747I_DISCO_serial_disabled INTERFACE)
+target_compile_options(STM32H747I_DISCO_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(STM32H747I_DISCO_serial_generic INTERFACE)
+target_compile_options(STM32H747I_DISCO_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(STM32H747I_DISCO_serial_none INTERFACE)
+target_compile_options(STM32H747I_DISCO_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(STM32H747I_DISCO_usb_CDC INTERFACE)
+target_compile_options(STM32H747I_DISCO_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(STM32H747I_DISCO_usb_CDCgen INTERFACE)
+target_compile_options(STM32H747I_DISCO_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(STM32H747I_DISCO_usb_HID INTERFACE)
+target_compile_options(STM32H747I_DISCO_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(STM32H747I_DISCO_usb_none INTERFACE)
+target_compile_options(STM32H747I_DISCO_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(STM32H747I_DISCO_xusb_FS INTERFACE)
+target_compile_options(STM32H747I_DISCO_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(STM32H747I_DISCO_xusb_HS INTERFACE)
+target_compile_options(STM32H747I_DISCO_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(STM32H747I_DISCO_xusb_HSFS INTERFACE)
+target_compile_options(STM32H747I_DISCO_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # STM32MP157A_DK1
 # -----------------------------------------------------------------------------
 
diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt
index b9cca5b0a1..4dbf924ae4 100644
--- a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt
+++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/CMakeLists.txt
@@ -21,8 +21,9 @@ target_link_libraries(variant INTERFACE variant_usage)
 add_library(variant_bin STATIC EXCLUDE_FROM_ALL
   generic_clock.c
   PeripheralPins.c
+  PeripheralPins_DISCO_H747I.c
   variant_generic.cpp
-  variant_DISCO_H747I.cpp
+  variant_STM32H747I_DISCO.cpp
 )
 target_link_libraries(variant_bin PUBLIC variant_usage)
 
diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/CMakeLists.txt b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/CMakeLists.txt
index 2a4d55b6b1..4b0ade045e 100644
--- a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/CMakeLists.txt
+++ b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/CMakeLists.txt
@@ -21,6 +21,8 @@ target_link_libraries(variant INTERFACE variant_usage)
 add_library(variant_bin STATIC EXCLUDE_FROM_ALL
   generic_clock.c
   PeripheralPins.c
+  PeripheralPins_DEVKIT_IOT_CONTINUUM.c
+  variant_DEVKIT_IOT_CONTINUUM.cpp
   variant_generic.cpp
 )
 target_link_libraries(variant_bin PUBLIC variant_usage)

From 1cffd988ad813728189c14bfd6ba02d77e5bca7f Mon Sep 17 00:00:00 2001
From: Mathieu Choplain <mathieu.choplain@st.com>
Date: Mon, 30 Oct 2023 15:25:23 +0100
Subject: [PATCH 4/4] chore(CI): update skip list

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
---
 CI/build/conf/cores_config.json    | 16 ++++++++++++++++
 CI/build/conf/cores_config_ci.json | 16 ++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json
index ac16c89faf..91d4d3af5a 100644
--- a/CI/build/conf/cores_config.json
+++ b/CI/build/conf/cores_config.json
@@ -546,6 +546,8 @@
             "GENERIC_H742VGTX",
             "GENERIC_H742VIHX",
             "GENERIC_H742VITX",
+            "GENERIC_H742XGHX",
+            "GENERIC_H742XIHX",
             "GENERIC_H742ZGTX",
             "GENERIC_H742ZITX",
             "GENERIC_H743IGKX",
@@ -556,19 +558,28 @@
             "GENERIC_H743VGTX",
             "GENERIC_H743VIHX",
             "GENERIC_H743VITX",
+            "GENERIC_H743XGHX",
+            "GENERIC_H743XIHX",
             "GENERIC_H743ZGTX",
             "GENERIC_H743ZITX",
+            "GENERIC_H745XGHX",
+            "GENERIC_H745XIHX",
             "GENERIC_H747AGIX",
             "GENERIC_H747AIIX",
             "GENERIC_H747IGTX",
             "GENERIC_H747IITX",
+            "GENERIC_H747XGHX",
+            "GENERIC_H747XIHX",
             "GENERIC_H750IBKX",
             "GENERIC_H750IBTX",
             "GENERIC_H750VBTX",
+            "GENERIC_H750XBHX",
             "GENERIC_H750ZBTX",
             "GENERIC_H753IIKX",
             "GENERIC_H753VIHX",
+            "GENERIC_H753XIHX",
             "GENERIC_H753ZITX",
+            "GENERIC_H755XIHX",
             "GENERIC_H757AIIX",
             "GENERIC_L010F4PX",
             "GENERIC_L010K4TX",
@@ -778,8 +789,13 @@
             "GENERIC_MP157DACX",
             "GENERIC_U575AGIXQ",
             "GENERIC_U575AIIXQ",
+            "GENERIC_U575CGTX",
+            "GENERIC_U575CGUX",
+            "GENERIC_U575CITX",
+            "GENERIC_U575CIUX",
             "GENERIC_U575ZGTXQ",
             "GENERIC_U575ZITXQ",
+            "GENERIC_U585CITX",
             "GENERIC_WB35CCUXA",
             "GENERIC_WB35CEUXA",
             "GENERIC_WB55CCUX",
diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json
index faa9c15f63..61d024436f 100644
--- a/CI/build/conf/cores_config_ci.json
+++ b/CI/build/conf/cores_config_ci.json
@@ -546,6 +546,8 @@
             "GENERIC_H742VGTX",
             "GENERIC_H742VIHX",
             "GENERIC_H742VITX",
+            "GENERIC_H742XGHX",
+            "GENERIC_H742XIHX",
             "GENERIC_H742ZGTX",
             "GENERIC_H742ZITX",
             "GENERIC_H743IGKX",
@@ -556,19 +558,28 @@
             "GENERIC_H743VGTX",
             "GENERIC_H743VIHX",
             "GENERIC_H743VITX",
+            "GENERIC_H743XGHX",
+            "GENERIC_H743XIHX",
             "GENERIC_H743ZGTX",
             "GENERIC_H743ZITX",
+            "GENERIC_H745XGHX",
+            "GENERIC_H745XIHX",
             "GENERIC_H747AGIX",
             "GENERIC_H747AIIX",
             "GENERIC_H747IGTX",
             "GENERIC_H747IITX",
+            "GENERIC_H747XGHX",
+            "GENERIC_H747XIHX",
             "GENERIC_H750IBKX",
             "GENERIC_H750IBTX",
             "GENERIC_H750VBTX",
+            "GENERIC_H750XBHX",
             "GENERIC_H750ZBTX",
             "GENERIC_H753IIKX",
             "GENERIC_H753VIHX",
+            "GENERIC_H753XIHX",
             "GENERIC_H753ZITX",
+            "GENERIC_H755XIHX",
             "GENERIC_H757AIIX",
             "GENERIC_L010F4PX",
             "GENERIC_L010K4TX",
@@ -778,8 +789,13 @@
             "GENERIC_MP157DACX",
             "GENERIC_U575AGIXQ",
             "GENERIC_U575AIIXQ",
+            "GENERIC_U575CGTX",
+            "GENERIC_U575CGUX",
+            "GENERIC_U575CITX",
+            "GENERIC_U575CIUX",
             "GENERIC_U575ZGTXQ",
             "GENERIC_U575ZITXQ",
+            "GENERIC_U585CITX",
             "GENERIC_WB35CCUXA",
             "GENERIC_WB35CEUXA",
             "GENERIC_WB55CCUX",

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