From d4a0b3cbafeb14869d7507e95e39d4ffacfb60cc Mon Sep 17 00:00:00 2001
From: ALTracer <11005378+ALTracer@users.noreply.github.com>
Date: Mon, 6 Jan 2025 05:32:32 +0300
Subject: [PATCH 1/2] variant(g4): correct the clock config for HSE8 on WeAct
G474CEU
* Override HSE value to 8 MHz not 24
* Keep PLL input above 2.66 MHz spec
* Set VCO to a multiple of USB48 and feed that from PLL, sysclk becomes 144
---
.../variant_WEACT_G474CE.cpp | 8 ++++----
.../variant_WEACT_G474CE.h | 4 ++++
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp
index 7f77b7eee5..209da49ce5 100644
--- a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp
+++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp
@@ -111,9 +111,9 @@ WEAK void SystemClock_Config(void)
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+ RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- RCC_OscInitStruct.PLL.PLLN = 85;
+ RCC_OscInitStruct.PLL.PLLN = 72;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV6;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
@@ -135,7 +135,7 @@ WEAK void SystemClock_Config(void)
#ifdef USBCON
/* Initializes the peripherals clocks */
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
- PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
Error_Handler();
}
@@ -146,4 +146,4 @@ WEAK void SystemClock_Config(void)
} // extern "C"
#endif
-#endif /* ARDUINO_NUCLEO_G431RB */
+#endif /* ARDUINO_WEACT_G474CE */
diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.h b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.h
index 2d66c2ab32..785cc5eaf1 100644
--- a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.h
+++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.h
@@ -184,6 +184,10 @@
#define HAL_QSPI_MODULE_ENABLED
#endif
+#ifndef HSE_VALUE
+ #define HSE_VALUE 8000000U
+#endif
+
/*----------------------------------------------------------------------------
* Arduino objects - C++ only
*----------------------------------------------------------------------------*/
From b94080997a8b04cde7dcdd777cdbfe917e76eab1 Mon Sep 17 00:00:00 2001
From: ALTracer <11005378+ALTracer@users.noreply.github.com>
Date: Mon, 6 Jan 2025 05:35:46 +0300
Subject: [PATCH 2/2] variant(g4): enhance WeAct G474CE clock config for USB
* Enable CRS and switch USB to HSI48, decoupling it from PLL
* Increase VCO multiplier to reach 170 MHz max spec
---
.../variant_WEACT_G474CE.cpp | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp
index 209da49ce5..d48e8a9fb1 100644
--- a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp
+++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp
@@ -98,6 +98,7 @@ WEAK void SystemClock_Config(void)
RCC_OscInitTypeDef RCC_OscInitStruct = {};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
#ifdef USBCON
+ RCC_CRSInitTypeDef RCC_CRSInitStruct = {};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
#endif
@@ -113,7 +114,7 @@ WEAK void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- RCC_OscInitStruct.PLL.PLLN = 72;
+ RCC_OscInitStruct.PLL.PLLN = 85;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV6;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
@@ -133,9 +134,22 @@ WEAK void SystemClock_Config(void)
}
#ifdef USBCON
+ /* Enable the SYSCFG APB clock */
+ __HAL_RCC_CRS_CLK_ENABLE();
+
+ /* Configures CRS */
+ RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+ RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+ RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+ RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+ RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+ RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+ HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+
/* Initializes the peripherals clocks */
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
- PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
Error_Handler();
}
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