From 5e8bd0e3525e6af01dbe8bb098578798c6817e97 Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Fri, 12 Jul 2019 22:36:47 -0700 Subject: [PATCH 01/18] Add basic DMA handlers. --- cores/arduino/stm32/dma.c | 370 ++++++++++++++++++++++++++++++++++++++ cores/arduino/stm32/dma.h | 59 ++++++ 2 files changed, 429 insertions(+) create mode 100644 cores/arduino/stm32/dma.c create mode 100644 cores/arduino/stm32/dma.h diff --git a/cores/arduino/stm32/dma.c b/cores/arduino/stm32/dma.c new file mode 100644 index 0000000000..57a7365531 --- /dev/null +++ b/cores/arduino/stm32/dma.c @@ -0,0 +1,370 @@ +/** + ****************************************************************************** + * @file dma.c + * @author xC0000005 + * @version V1.0.0 + * @date 12-July-2019 + * @brief provide dma callbacks for dma + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DMA_H +#define __DMA_H + +#include + +/** + * @brief This function will store the DMA handle in the appropriate slot + * @param dma_handle : dma handle + * @retval None + */ +void prepare_dma(DMA_HandleTypeDef *dma_handle); + +/** + * @brief This function will remove the DMA handle from the appropriate slot + * @param dma_handle : dma handle + * @retval None + */ +void end_dma(DMA_HandleTypeDef *dma_handle); + +#endif From 2d97333d0fc7ae3599c49a7109c2098c8c67292d Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Sat, 13 Jul 2019 00:22:02 -0700 Subject: [PATCH 02/18] Minor updates. --- cores/arduino/stm32/dma.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/cores/arduino/stm32/dma.c b/cores/arduino/stm32/dma.c index 57a7365531..12788612be 100644 --- a/cores/arduino/stm32/dma.c +++ b/cores/arduino/stm32/dma.c @@ -38,6 +38,11 @@ #include #include "dma.h" +#ifdef __cplusplus +extern "C" { +#endif +#if defined(HAL_DMA_MODULE_ENABLED) + #define NC -1 typedef enum @@ -368,3 +373,9 @@ void DMA2_Channel8_IRQHandler() { HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL8_INDEX]); } #endif + +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef __cplusplus +} +#endif From 0a4dbf7ee0f474c38df229a96c640e42c396cf02 Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Sat, 13 Jul 2019 09:19:42 -0700 Subject: [PATCH 03/18] Astyle changes. --- cores/arduino/stm32/dma.c | 238 +++++++++++++++++++------------------- 1 file changed, 119 insertions(+), 119 deletions(-) diff --git a/cores/arduino/stm32/dma.c b/cores/arduino/stm32/dma.c index 12788612be..9eccbb4f49 100644 --- a/cores/arduino/stm32/dma.c +++ b/cores/arduino/stm32/dma.c @@ -48,51 +48,51 @@ extern "C" { typedef enum { #ifdef DMA1_Channel1 - DMA1_CHANNEL1_INDEX, + DMA1_CHANNEL1_INDEX, #endif #ifdef DMA1_Channel2 - DMA1_CHANNEL2_INDEX, + DMA1_CHANNEL2_INDEX, #endif #ifdef DMA1_Channel3 - DMA1_CHANNEL3_INDEX, + DMA1_CHANNEL3_INDEX, #endif #ifdef DMA1_Channel4 - DMA1_CHANNEL4_INDEX, + DMA1_CHANNEL4_INDEX, #endif #ifdef DMA1_Channel5 - DMA1_CHANNEL5_INDEX, + DMA1_CHANNEL5_INDEX, #endif #ifdef DMA1_Channel6 - DMA1_CHANNEL6_INDEX, + DMA1_CHANNEL6_INDEX, #endif #ifdef DMA1_Channel7 - DMA1_CHANNEL7_INDEX, + DMA1_CHANNEL7_INDEX, #endif #ifdef DMA2_Channel1 - DMA2_CHANNEL1_INDEX, + DMA2_CHANNEL1_INDEX, #endif #ifdef DMA2_Channel2 - DMA2_CHANNEL2_INDEX, + DMA2_CHANNEL2_INDEX, #endif #ifdef DMA2_Channel3 - DMA2_CHANNEL3_INDEX, + DMA2_CHANNEL3_INDEX, #endif #ifdef DMA2_Channel4 - DMA2_CHANNEL4_INDEX, + DMA2_CHANNEL4_INDEX, #endif #ifdef DMA2_Channel5 - DMA2_CHANNEL5_INDEX, + DMA2_CHANNEL5_INDEX, #endif #ifdef DMA2_Channel6 - DMA2_CHANNEL6_INDEX, + DMA2_CHANNEL6_INDEX, #endif #ifdef DMA2_Channel7 - DMA2_CHANNEL7_INDEX, + DMA2_CHANNEL7_INDEX, #endif #ifdef DMA2_Channel8 - DMA2_CHANNEL8_INDEX, + DMA2_CHANNEL8_INDEX, #endif - DMA_CHANNEL_NUM + DMA_CHANNEL_NUM } dma_index_t; static DMA_HandleTypeDef *dma_handles[DMA_CHANNEL_NUM] = {NULL}; @@ -103,70 +103,70 @@ static DMA_HandleTypeDef *dma_handles[DMA_CHANNEL_NUM] = {NULL}; * @retval None */ static dma_index_t get_dma_index(DMA_Channel_TypeDef *instance) { - switch ((uint32_t)instance) { - #ifdef DMA1_Channel1 - case (uint32_t)DMA1_Channel1: - return DMA1_CHANNEL1_INDEX; - #endif - #ifdef DMA1_Channel2 - case (uint32_t)DMA1_Channel2: - return DMA1_CHANNEL2_INDEX; - #endif - #ifdef DMA1_Channel3 - case (uint32_t)DMA1_Channel3: - return DMA1_CHANNEL3_INDEX; - #endif - #ifdef DMA1_Channel4 - case (uint32_t)DMA1_Channel4: - return DMA1_CHANNEL4_INDEX; - #endif - #ifdef DMA1_Channel5 - case (uint32_t)DMA1_Channel5: - return DMA1_CHANNEL5_INDEX; - #endif - #ifdef DMA1_Channel6 - case (uint32_t)DMA1_Channel6: - return DMA1_CHANNEL6_INDEX; - #endif - #ifdef DMA1_Channel7 - case (uint32_t)DMA1_Channel7: - return DMA1_CHANNEL7_INDEX; - #endif - #ifdef DMA2_Channel1 - case (uint32_t)DMA2_Channel1: - return DMA2_CHANNEL1_INDEX; - #endif - #ifdef DMA2_Channel2 - case (uint32_t)DMA2_Channel2: - return DMA2_CHANNEL2_INDEX; - #endif - #ifdef DMA2_Channel3 - case (uint32_t)DMA2_Channel3: - return DMA2_CHANNEL3_INDEX; - #endif - #ifdef DMA2_Channel4 - case (uint32_t)DMA2_Channel4: - return DMA2_CHANNEL4_INDEX; - #endif - #ifdef DMA2_Channel5 - case (uint32_t)DMA2_Channel5: - return DMA2_CHANNEL5_INDEX; - #endif - #ifdef DMA2_Channel6 - case (uint32_t)DMA2_Channel6: - return DMA2_CHANNEL6_INDEX; - #endif - #ifdef DMA2_Channel7 - case (uint32_t)DMA2_Channel7: - return DMA2_CHANNEL7_INDEX; - #endif - #ifdef DMA2_Channel8 - case (uint32_t)DMA2_Channel8: - return DMA2_CHANNEL8_INDEX; - #endif + switch ((uint32_t)instance) { +#ifdef DMA1_Channel1 + case (uint32_t)DMA1_Channel1: + return DMA1_CHANNEL1_INDEX; +#endif +#ifdef DMA1_Channel2 + case (uint32_t)DMA1_Channel2: + return DMA1_CHANNEL2_INDEX; +#endif +#ifdef DMA1_Channel3 + case (uint32_t)DMA1_Channel3: + return DMA1_CHANNEL3_INDEX; +#endif +#ifdef DMA1_Channel4 + case (uint32_t)DMA1_Channel4: + return DMA1_CHANNEL4_INDEX; +#endif +#ifdef DMA1_Channel5 + case (uint32_t)DMA1_Channel5: + return DMA1_CHANNEL5_INDEX; +#endif +#ifdef DMA1_Channel6 + case (uint32_t)DMA1_Channel6: + return DMA1_CHANNEL6_INDEX; +#endif +#ifdef DMA1_Channel7 + case (uint32_t)DMA1_Channel7: + return DMA1_CHANNEL7_INDEX; +#endif +#ifdef DMA2_Channel1 + case (uint32_t)DMA2_Channel1: + return DMA2_CHANNEL1_INDEX; +#endif +#ifdef DMA2_Channel2 + case (uint32_t)DMA2_Channel2: + return DMA2_CHANNEL2_INDEX; +#endif +#ifdef DMA2_Channel3 + case (uint32_t)DMA2_Channel3: + return DMA2_CHANNEL3_INDEX; +#endif +#ifdef DMA2_Channel4 + case (uint32_t)DMA2_Channel4: + return DMA2_CHANNEL4_INDEX; +#endif +#ifdef DMA2_Channel5 + case (uint32_t)DMA2_Channel5: + return DMA2_CHANNEL5_INDEX; +#endif +#ifdef DMA2_Channel6 + case (uint32_t)DMA2_Channel6: + return DMA2_CHANNEL6_INDEX; +#endif +#ifdef DMA2_Channel7 + case (uint32_t)DMA2_Channel7: + return DMA2_CHANNEL7_INDEX; +#endif +#ifdef DMA2_Channel8 + case (uint32_t)DMA2_Channel8: + return DMA2_CHANNEL8_INDEX; +#endif default: - return NC; - } + return NC; + } } /** @@ -175,11 +175,11 @@ static dma_index_t get_dma_index(DMA_Channel_TypeDef *instance) { * @retval None */ void prepare_dma(DMA_HandleTypeDef *dma_handle) { - dma_index_t dma_index = get_dma_index(dma_handle->Instance); - if (dma_index == NC) { - return; - } - dma_handles[dma_index] = dma_handle; + dma_index_t dma_index = get_dma_index(dma_handle->Instance); + if (dma_index == NC) { + return; + } + dma_handles[dma_index] = dma_handle; } /** @@ -188,11 +188,11 @@ void prepare_dma(DMA_HandleTypeDef *dma_handle) { * @retval None */ void end_dma(DMA_HandleTypeDef *dma_handle) { - dma_index_t dma_index = get_dma_index(dma_handle->Instance); - if (dma_index == NC) { - return; - } - dma_handles[dma_index] = NULL; + dma_index_t dma_index = get_dma_index(dma_handle->Instance); + if (dma_index == NC) { + return; + } + dma_handles[dma_index] = NULL; } #ifdef DMA1_Channel1 @@ -202,8 +202,8 @@ void end_dma(DMA_HandleTypeDef *dma_handle) { * @retval None */ void DMA1_Channel1_IRQHandler() { - if (dma_handles[DMA1_CHANNEL1_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL1_INDEX]); + if (dma_handles[DMA1_CHANNEL1_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL1_INDEX]); } #endif @@ -214,8 +214,8 @@ void DMA1_Channel1_IRQHandler() { * @retval None */ void DMA1_Channel2_IRQHandler() { - if (dma_handles[DMA1_CHANNEL2_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL2_INDEX]); + if (dma_handles[DMA1_CHANNEL2_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL2_INDEX]); } #endif @@ -226,8 +226,8 @@ void DMA1_Channel2_IRQHandler() { * @retval None */ void DMA1_Channel3_IRQHandler() { - if (dma_handles[DMA1_CHANNEL3_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL3_INDEX]); + if (dma_handles[DMA1_CHANNEL3_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL3_INDEX]); } #endif @@ -238,8 +238,8 @@ void DMA1_Channel3_IRQHandler() { * @retval None */ void DMA1_Channel4_IRQHandler() { - if (dma_handles[DMA1_CHANNEL4_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL4_INDEX]); + if (dma_handles[DMA1_CHANNEL4_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL4_INDEX]); } #endif @@ -250,8 +250,8 @@ void DMA1_Channel4_IRQHandler() { * @retval None */ void DMA1_Channel5_IRQHandler() { - if (dma_handles[DMA1_CHANNEL5_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL5_INDEX]); + if (dma_handles[DMA1_CHANNEL5_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL5_INDEX]); } #endif @@ -261,8 +261,8 @@ void DMA1_Channel5_IRQHandler() { * @retval None */ void DMA1_Channel6_IRQHandler() { - if (dma_handles[DMA1_CHANNEL6_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL6_INDEX]); + if (dma_handles[DMA1_CHANNEL6_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL6_INDEX]); } #endif @@ -273,8 +273,8 @@ void DMA1_Channel6_IRQHandler() { * @retval None */ void DMA1_Channel7_IRQHandler() { - if (dma_handles[DMA1_CHANNEL7_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL7_INDEX]); + if (dma_handles[DMA1_CHANNEL7_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL7_INDEX]); } #endif @@ -285,8 +285,8 @@ void DMA1_Channel7_IRQHandler() { * @retval None */ void DMA2_Channel1_IRQHandler() { - if (dma_handles[DMA2_CHANNEL1_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL1_INDEX]); + if (dma_handles[DMA2_CHANNEL1_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL1_INDEX]); } #endif @@ -297,8 +297,8 @@ void DMA2_Channel1_IRQHandler() { * @retval None */ void DMA2_Channel1_IRQHandler() { - if (dma_handles[DMA2_CHANNEL2_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL2_INDEX]); + if (dma_handles[DMA2_CHANNEL2_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL2_INDEX]); } #endif @@ -309,8 +309,8 @@ void DMA2_Channel1_IRQHandler() { * @retval None */ void DMA2_Channel3_IRQHandler() { - if (dma_handles[DMA2_CHANNEL3_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL3_INDEX]); + if (dma_handles[DMA2_CHANNEL3_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL3_INDEX]); } #endif @@ -321,8 +321,8 @@ void DMA2_Channel3_IRQHandler() { * @retval None */ void DMA2_Channel4_IRQHandler() { - if (dma_handles[DMA2_CHANNEL4_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL4_INDEX]); + if (dma_handles[DMA2_CHANNEL4_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL4_INDEX]); } #endif @@ -333,8 +333,8 @@ void DMA2_Channel4_IRQHandler() { * @retval None */ void DMA2_Channel5_IRQHandler() { - if (dma_handles[DMA2_CHANNEL5_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL5_INDEX]); + if (dma_handles[DMA2_CHANNEL5_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL5_INDEX]); } #endif @@ -345,8 +345,8 @@ void DMA2_Channel5_IRQHandler() { * @retval None */ void DMA2_Channel6_IRQHandler() { - if (dma_handles[DMA2_CHANNEL6_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL6_INDEX]); + if (dma_handles[DMA2_CHANNEL6_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL6_INDEX]); } #endif @@ -357,8 +357,8 @@ void DMA2_Channel6_IRQHandler() { * @retval None */ void DMA2_Channel7_IRQHandler() { - if (dma_handles[DMA2_CHANNEL7_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL7_INDEX]); + if (dma_handles[DMA2_CHANNEL7_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL7_INDEX]); } #endif @@ -369,8 +369,8 @@ void DMA2_Channel7_IRQHandler() { * @retval None */ void DMA2_Channel8_IRQHandler() { - if (dma_handles[DMA2_CHANNEL8_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL8_INDEX]); + if (dma_handles[DMA2_CHANNEL8_INDEX] != NULL) + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL8_INDEX]); } #endif From 50a3309aeb1aec838f0d898963e0cffeb96c46f5 Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Sat, 13 Jul 2019 10:48:04 -0700 Subject: [PATCH 04/18] Implement stream handlers --- cores/arduino/stm32/dma.c | 486 ++++++++++++++++++++++++++++++-------- 1 file changed, 390 insertions(+), 96 deletions(-) diff --git a/cores/arduino/stm32/dma.c b/cores/arduino/stm32/dma.c index 9eccbb4f49..4cdef33f22 100644 --- a/cores/arduino/stm32/dma.c +++ b/cores/arduino/stm32/dma.c @@ -43,58 +43,105 @@ extern "C" { #endif #if defined(HAL_DMA_MODULE_ENABLED) -#define NC -1 - -typedef enum -{ +typedef enum { #ifdef DMA1_Channel1 - DMA1_CHANNEL1_INDEX, + DMA1_CHANNEL1_INDEX, #endif #ifdef DMA1_Channel2 - DMA1_CHANNEL2_INDEX, + DMA1_CHANNEL2_INDEX, #endif #ifdef DMA1_Channel3 - DMA1_CHANNEL3_INDEX, + DMA1_CHANNEL3_INDEX, #endif #ifdef DMA1_Channel4 - DMA1_CHANNEL4_INDEX, + DMA1_CHANNEL4_INDEX, #endif #ifdef DMA1_Channel5 - DMA1_CHANNEL5_INDEX, + DMA1_CHANNEL5_INDEX, #endif #ifdef DMA1_Channel6 - DMA1_CHANNEL6_INDEX, + DMA1_CHANNEL6_INDEX, #endif #ifdef DMA1_Channel7 - DMA1_CHANNEL7_INDEX, + DMA1_CHANNEL7_INDEX, #endif #ifdef DMA2_Channel1 - DMA2_CHANNEL1_INDEX, + DMA2_CHANNEL1_INDEX, #endif #ifdef DMA2_Channel2 - DMA2_CHANNEL2_INDEX, + DMA2_CHANNEL2_INDEX, #endif #ifdef DMA2_Channel3 - DMA2_CHANNEL3_INDEX, + DMA2_CHANNEL3_INDEX, #endif #ifdef DMA2_Channel4 - DMA2_CHANNEL4_INDEX, + DMA2_CHANNEL4_INDEX, #endif #ifdef DMA2_Channel5 - DMA2_CHANNEL5_INDEX, + DMA2_CHANNEL5_INDEX, #endif #ifdef DMA2_Channel6 - DMA2_CHANNEL6_INDEX, + DMA2_CHANNEL6_INDEX, #endif #ifdef DMA2_Channel7 - DMA2_CHANNEL7_INDEX, + DMA2_CHANNEL7_INDEX, #endif #ifdef DMA2_Channel8 - DMA2_CHANNEL8_INDEX, + DMA2_CHANNEL8_INDEX, +#endif +#ifdef DMA1_Stream0 + DMA1_STREAM0_INDEX, +#endif +#ifdef DMA1_Stream1 + DMA1_STREAM1_INDEX, +#endif +#ifdef DMA1_Stream2 + DMA1_STREAM2_INDEX, +#endif +#ifdef DMA1_Stream3 + DMA1_STREAM3_INDEX, +#endif +#ifdef DMA1_Stream4 + DMA1_STREAM4_INDEX, +#endif +#ifdef DMA1_Stream5 + DMA1_STREAM5_INDEX, +#endif +#ifdef DMA1_Stream6 + DMA1_STREAM6_INDEX, +#endif +#ifdef DMA1_Stream7 + DMA1_STREAM7_INDEX, +#endif +#ifdef DMA2_Stream0 + DMA2_STREAM0_INDEX, +#endif +#ifdef DMA2_Stream1 + DMA2_STREAM1_INDEX, +#endif +#ifdef DMA2_Stream2 + DMA2_STREAM2_INDEX, +#endif +#ifdef DMA2_Stream3 + DMA2_STREAM3_INDEX, +#endif +#ifdef DMA2_Stream4 + DMA2_STREAM4_INDEX, #endif - DMA_CHANNEL_NUM +#ifdef DMA2_Stream5 + DMA2_STREAM5_INDEX, +#endif +#ifdef DMA2_Stream6 + DMA2_STREAM6_INDEX, +#endif +#ifdef DMA2_Stream7 + DMA2_STREAM7_INDEX, +#endif + DMA_CHANNEL_NUM } dma_index_t; +#define NC (dma_index_t)-1 + static DMA_HandleTypeDef *dma_handles[DMA_CHANNEL_NUM] = {NULL}; /** @@ -102,71 +149,142 @@ static DMA_HandleTypeDef *dma_handles[DMA_CHANNEL_NUM] = {NULL}; * @param instance : dma instance * @retval None */ -static dma_index_t get_dma_index(DMA_Channel_TypeDef *instance) { - switch ((uint32_t)instance) { +static dma_index_t get_dma_index( +#if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) + DMA_Stream_TypeDef +#else + DMA_Channel_TypeDef +#endif + *instance) +{ + switch ((uint32_t)instance) { #ifdef DMA1_Channel1 case (uint32_t)DMA1_Channel1: - return DMA1_CHANNEL1_INDEX; + return DMA1_CHANNEL1_INDEX; #endif #ifdef DMA1_Channel2 case (uint32_t)DMA1_Channel2: - return DMA1_CHANNEL2_INDEX; + return DMA1_CHANNEL2_INDEX; #endif #ifdef DMA1_Channel3 case (uint32_t)DMA1_Channel3: - return DMA1_CHANNEL3_INDEX; + return DMA1_CHANNEL3_INDEX; #endif #ifdef DMA1_Channel4 case (uint32_t)DMA1_Channel4: - return DMA1_CHANNEL4_INDEX; + return DMA1_CHANNEL4_INDEX; #endif #ifdef DMA1_Channel5 case (uint32_t)DMA1_Channel5: - return DMA1_CHANNEL5_INDEX; + return DMA1_CHANNEL5_INDEX; #endif #ifdef DMA1_Channel6 case (uint32_t)DMA1_Channel6: - return DMA1_CHANNEL6_INDEX; + return DMA1_CHANNEL6_INDEX; #endif #ifdef DMA1_Channel7 case (uint32_t)DMA1_Channel7: - return DMA1_CHANNEL7_INDEX; + return DMA1_CHANNEL7_INDEX; #endif #ifdef DMA2_Channel1 case (uint32_t)DMA2_Channel1: - return DMA2_CHANNEL1_INDEX; + return DMA2_CHANNEL1_INDEX; #endif #ifdef DMA2_Channel2 case (uint32_t)DMA2_Channel2: - return DMA2_CHANNEL2_INDEX; + return DMA2_CHANNEL2_INDEX; #endif #ifdef DMA2_Channel3 case (uint32_t)DMA2_Channel3: - return DMA2_CHANNEL3_INDEX; + return DMA2_CHANNEL3_INDEX; #endif #ifdef DMA2_Channel4 case (uint32_t)DMA2_Channel4: - return DMA2_CHANNEL4_INDEX; + return DMA2_CHANNEL4_INDEX; #endif #ifdef DMA2_Channel5 case (uint32_t)DMA2_Channel5: - return DMA2_CHANNEL5_INDEX; + return DMA2_CHANNEL5_INDEX; #endif #ifdef DMA2_Channel6 case (uint32_t)DMA2_Channel6: - return DMA2_CHANNEL6_INDEX; + return DMA2_CHANNEL6_INDEX; #endif #ifdef DMA2_Channel7 case (uint32_t)DMA2_Channel7: - return DMA2_CHANNEL7_INDEX; + return DMA2_CHANNEL7_INDEX; #endif #ifdef DMA2_Channel8 case (uint32_t)DMA2_Channel8: - return DMA2_CHANNEL8_INDEX; + return DMA2_CHANNEL8_INDEX; +#endif +#ifdef DMA1_Stream0 + case (uint32_t)DMA1_Stream0: + return DMA1_STREAM0_INDEX; +#endif +#ifdef DMA1_Stream1 + case (uint32_t)DMA1_Stream1: + return DMA1_STREAM1_INDEX; +#endif +#ifdef DMA1_Stream2 + case (uint32_t)DMA1_Stream2: + return DMA1_STREAM2_INDEX; +#endif +#ifdef DMA1_Stream3 + case (uint32_t)DMA1_Stream3: + return DMA1_STREAM3_INDEX; +#endif +#ifdef DMA1_Stream4 + case (uint32_t)DMA1_Stream4: + return DMA1_STREAM4_INDEX; +#endif +#ifdef DMA1_Stream5 + case (uint32_t)DMA1_Stream5: + return DMA1_STREAM5_INDEX; +#endif +#ifdef DMA1_Stream6 + case (uint32_t)DMA1_Stream6: + return DMA1_STREAM6_INDEX; +#endif +#ifdef DMA1_Stream7 + case (uint32_t)DMA1_Stream7: + return DMA1_STREAM7_INDEX; +#endif +#ifdef DMA2_Stream0 + case (uint32_t)DMA2_Stream0: + return DMA2_STREAM0_INDEX; +#endif +#ifdef DMA2_Stream1 + case (uint32_t)DMA2_Stream1: + return DMA2_STREAM1_INDEX; +#endif +#ifdef DMA2_Stream2 + case (uint32_t)DMA2_Stream2: + return DMA2_STREAM2_INDEX; +#endif +#ifdef DMA2_Stream3 + case (uint32_t)DMA2_Stream3: + return DMA2_STREAM3_INDEX; +#endif +#ifdef DMA2_Stream4 + case (uint32_t)DMA2_Stream4: + return DMA2_STREAM4_INDEX; +#endif +#ifdef DMA2_Stream5 + case (uint32_t)DMA2_Stream5: + return DMA2_STREAM5_INDEX; +#endif +#ifdef DMA2_Stream6 + case (uint32_t)DMA2_Stream6: + return DMA2_STREAM6_INDEX; +#endif +#ifdef DMA2_Stream7 + case (uint32_t)DMA2_Stream7: + return DMA2_STREAM7_INDEX; #endif default: - return NC; - } + return NC; + } } /** @@ -174,12 +292,13 @@ static dma_index_t get_dma_index(DMA_Channel_TypeDef *instance) { * @param dma_handle : dma handle * @retval None */ -void prepare_dma(DMA_HandleTypeDef *dma_handle) { - dma_index_t dma_index = get_dma_index(dma_handle->Instance); - if (dma_index == NC) { - return; - } - dma_handles[dma_index] = dma_handle; +void prepare_dma(DMA_HandleTypeDef *dma_handle) +{ + dma_index_t dma_index = get_dma_index(dma_handle->Instance); + if (dma_index == NC) { + return; + } + dma_handles[dma_index] = dma_handle; } /** @@ -187,12 +306,13 @@ void prepare_dma(DMA_HandleTypeDef *dma_handle) { * @param dma_handle : dma handle * @retval None */ -void end_dma(DMA_HandleTypeDef *dma_handle) { - dma_index_t dma_index = get_dma_index(dma_handle->Instance); - if (dma_index == NC) { - return; - } - dma_handles[dma_index] = NULL; +void end_dma(DMA_HandleTypeDef *dma_handle) +{ + dma_index_t dma_index = get_dma_index(dma_handle->Instance); + if (dma_index == NC) { + return; + } + dma_handles[dma_index] = NULL; } #ifdef DMA1_Channel1 @@ -201,9 +321,11 @@ void end_dma(DMA_HandleTypeDef *dma_handle) { * @param None * @retval None */ -void DMA1_Channel1_IRQHandler() { - if (dma_handles[DMA1_CHANNEL1_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL1_INDEX]); +void DMA1_Channel1_IRQHandler() +{ + if (dma_handles[DMA1_CHANNEL1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL1_INDEX]); + } } #endif @@ -213,9 +335,11 @@ void DMA1_Channel1_IRQHandler() { * @param None * @retval None */ -void DMA1_Channel2_IRQHandler() { - if (dma_handles[DMA1_CHANNEL2_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL2_INDEX]); +void DMA1_Channel2_IRQHandler() +{ + if (dma_handles[DMA1_CHANNEL2_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL2_INDEX]); + } } #endif @@ -225,9 +349,11 @@ void DMA1_Channel2_IRQHandler() { * @param None * @retval None */ -void DMA1_Channel3_IRQHandler() { - if (dma_handles[DMA1_CHANNEL3_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL3_INDEX]); +void DMA1_Channel3_IRQHandler() +{ + if (dma_handles[DMA1_CHANNEL3_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL3_INDEX]); + } } #endif @@ -237,9 +363,11 @@ void DMA1_Channel3_IRQHandler() { * @param None * @retval None */ -void DMA1_Channel4_IRQHandler() { - if (dma_handles[DMA1_CHANNEL4_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL4_INDEX]); +void DMA1_Channel4_IRQHandler() +{ + if (dma_handles[DMA1_CHANNEL4_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL4_INDEX]); + } } #endif @@ -249,9 +377,11 @@ void DMA1_Channel4_IRQHandler() { * @param None * @retval None */ -void DMA1_Channel5_IRQHandler() { - if (dma_handles[DMA1_CHANNEL5_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL5_INDEX]); +void DMA1_Channel5_IRQHandler() +{ + if (dma_handles[DMA1_CHANNEL5_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL5_INDEX]); + } } #endif @@ -260,9 +390,11 @@ void DMA1_Channel5_IRQHandler() { * @param None * @retval None */ -void DMA1_Channel6_IRQHandler() { - if (dma_handles[DMA1_CHANNEL6_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL6_INDEX]); +void DMA1_Channel6_IRQHandler() +{ + if (dma_handles[DMA1_CHANNEL6_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL6_INDEX]); + } } #endif @@ -272,9 +404,11 @@ void DMA1_Channel6_IRQHandler() { * @param None * @retval None */ -void DMA1_Channel7_IRQHandler() { - if (dma_handles[DMA1_CHANNEL7_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL7_INDEX]); +void DMA1_Channel7_IRQHandler() +{ + if (dma_handles[DMA1_CHANNEL7_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL7_INDEX]); + } } #endif @@ -284,9 +418,11 @@ void DMA1_Channel7_IRQHandler() { * @param None * @retval None */ -void DMA2_Channel1_IRQHandler() { - if (dma_handles[DMA2_CHANNEL1_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL1_INDEX]); +void DMA2_Channel1_IRQHandler() +{ + if (dma_handles[DMA2_CHANNEL1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL1_INDEX]); + } } #endif @@ -296,9 +432,11 @@ void DMA2_Channel1_IRQHandler() { * @param None * @retval None */ -void DMA2_Channel1_IRQHandler() { - if (dma_handles[DMA2_CHANNEL2_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL2_INDEX]); +void DMA2_Channel2_IRQHandler() +{ + if (dma_handles[DMA2_CHANNEL2_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL2_INDEX]); + } } #endif @@ -308,9 +446,11 @@ void DMA2_Channel1_IRQHandler() { * @param None * @retval None */ -void DMA2_Channel3_IRQHandler() { - if (dma_handles[DMA2_CHANNEL3_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL3_INDEX]); +void DMA2_Channel3_IRQHandler() +{ + if (dma_handles[DMA2_CHANNEL3_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL3_INDEX]); + } } #endif @@ -320,9 +460,11 @@ void DMA2_Channel3_IRQHandler() { * @param None * @retval None */ -void DMA2_Channel4_IRQHandler() { - if (dma_handles[DMA2_CHANNEL4_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL4_INDEX]); +void DMA2_Channel4_IRQHandler() +{ + if (dma_handles[DMA2_CHANNEL4_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL4_INDEX]); + } } #endif @@ -332,9 +474,11 @@ void DMA2_Channel4_IRQHandler() { * @param None * @retval None */ -void DMA2_Channel5_IRQHandler() { - if (dma_handles[DMA2_CHANNEL5_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL5_INDEX]); +void DMA2_Channel5_IRQHandler() +{ + if (dma_handles[DMA2_CHANNEL5_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL5_INDEX]); + } } #endif @@ -344,9 +488,11 @@ void DMA2_Channel5_IRQHandler() { * @param None * @retval None */ -void DMA2_Channel6_IRQHandler() { - if (dma_handles[DMA2_CHANNEL6_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL6_INDEX]); +void DMA2_Channel6_IRQHandler() +{ + if (dma_handles[DMA2_CHANNEL6_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL6_INDEX]); + } } #endif @@ -356,9 +502,11 @@ void DMA2_Channel6_IRQHandler() { * @param None * @retval None */ -void DMA2_Channel7_IRQHandler() { - if (dma_handles[DMA2_CHANNEL7_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL7_INDEX]); +void DMA2_Channel7_IRQHandler() +{ + if (dma_handles[DMA2_CHANNEL7_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL7_INDEX]); + } } #endif @@ -368,9 +516,155 @@ void DMA2_Channel7_IRQHandler() { * @param None * @retval None */ -void DMA2_Channel8_IRQHandler() { - if (dma_handles[DMA2_CHANNEL8_INDEX] != NULL) - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL8_INDEX]); +void DMA2_Channel8_IRQHandler() +{ + if (dma_handles[DMA2_CHANNEL8_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL8_INDEX]); + } +} +#endif + +#ifdef DMA1_Stream0 +void DMA1_Stream0_IRQHandler() +{ + if (dma_handles[DMA1_STREAM0_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM0_INDEX]); + } +} +#endif + +#ifdef DMA1_Stream1 +void DMA1_Stream1_IRQHandler() +{ + if (dma_handles[DMA1_STREAM1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM1_INDEX]); + } +} +#endif + +#ifdef DMA1_Stream2 +void DMA1_Stream2_IRQHandler() +{ + if (dma_handles[DMA1_STREAM2_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM2_INDEX]); + } +} +#endif + +#ifdef DMA1_Stream3 +void DMA1_Stream3_IRQHandler() +{ + if (dma_handles[DMA1_STREAM3_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM3_INDEX]); + } +} +#endif + +#ifdef DMA1_Stream4 +void DMA1_Stream4_IRQHandler() +{ + if (dma_handles[DMA1_STREAM4_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM4_INDEX]); + } +} +#endif + +#ifdef DMA1_Stream5 +void DMA1_Stream5_IRQHandler() +{ + if (dma_handles[DMA1_STREAM5_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM5_INDEX]); + } +} +#endif + +#ifdef DMA1_Stream6 +void DMA1_Stream6_IRQHandler() +{ + if (dma_handles[DMA1_STREAM6_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM6_INDEX]); + } +} +#endif + +#ifdef DMA1_Stream7 +void DMA1_Stream7_IRQHandler() +{ + if (dma_handles[DMA1_STREAM7_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM7_INDEX]); + } +} +#endif + +#ifdef DMA2_Stream0 +void DMA2_Stream0_IRQHandler() +{ + if (dma_handles[DMA2_STREAM0_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM0_INDEX]); + } +} +#endif + +#ifdef DMA2_Stream1 +void DMA2_Stream1_IRQHandler() +{ + if (dma_handles[DMA2_STREAM1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM1_INDEX]); + } +} +#endif + +#ifdef DMA2_Stream2 +void DMA2_Stream2_IRQHandler() +{ + if (dma_handles[DMA2_STREAM2_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM2_INDEX]); + } +} +#endif + +#ifdef DMA2_Stream3 +void DMA2_Stream3_IRQHandler() +{ + if (dma_handles[DMA2_STREAM3_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM3_INDEX]); + } +} +#endif + +#ifdef DMA2_Stream4 +void DMA2_Stream4_IRQHandler() +{ + if (dma_handles[DMA2_STREAM4_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM4_INDEX]); + } +} +#endif + +#ifdef DMA2_Stream5 +void DMA2_Stream5_IRQHandler() +{ + if (dma_handles[DMA2_STREAM5_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM5_INDEX]); + } +} +#endif + +#ifdef DMA2_Stream6 +void DMA2_Stream6_IRQHandler() +{ + if (dma_handles[DMA2_STREAM6_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM6_INDEX]); + } +} +#endif + +#ifdef DMA2_Stream7 +void DMA2_Stream7_IRQHandler() +{ + if (dma_handles[DMA2_STREAM7_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM7_INDEX]); + } } #endif From c4ba50cfc0e8177cc1626d32506f8c53ba56f431 Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Sun, 14 Jul 2019 22:36:46 -0700 Subject: [PATCH 05/18] Save off DMATransfer library work. --- libraries/DMA/kewords.txt | 21 +++++++++++ libraries/DMA/library.properties | 7 ++++ libraries/DMA/src/DMATransfer.cpp | 62 +++++++++++++++++++++++++++++++ libraries/DMA/src/DMATransfer.h | 38 +++++++++++++++++++ 4 files changed, 128 insertions(+) create mode 100644 libraries/DMA/kewords.txt create mode 100644 libraries/DMA/library.properties create mode 100644 libraries/DMA/src/DMATransfer.cpp create mode 100644 libraries/DMA/src/DMATransfer.h diff --git a/libraries/DMA/kewords.txt b/libraries/DMA/kewords.txt new file mode 100644 index 0000000000..43f1c9b43e --- /dev/null +++ b/libraries/DMA/kewords.txt @@ -0,0 +1,21 @@ +####################################### +# Syntax Coloring Map For DMA +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +DMA KEYWORD1 +DMA1 KEYWORD1 +DMA2 KEYWORD2 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +start KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### diff --git a/libraries/DMA/library.properties b/libraries/DMA/library.properties new file mode 100644 index 0000000000..d5f0418fce --- /dev/null +++ b/libraries/DMA/library.properties @@ -0,0 +1,7 @@ +name=DMA +version=0.0.1 +author=J.C. Nelson +sentence=Enables Direct Memory Access Transfers. +paragraph=This library allows use of Direct Memory Access (DMA) for transfer between memory locations, to and from peripherals. +category=Data Transfers +architectures=stm32 diff --git a/libraries/DMA/src/DMATransfer.cpp b/libraries/DMA/src/DMATransfer.cpp new file mode 100644 index 0000000000..9d8f31ec40 --- /dev/null +++ b/libraries/DMA/src/DMATransfer.cpp @@ -0,0 +1,62 @@ +#include + +/** + * @brief Prepares for DMA Transfer by enabling clocks + * and storing the settings in the slots + * @param settings : dma transfer settings + * @retval None + */ +void DMATransferClass::prepare(dmatransfer_t *settings) { + if (!_prepared) { + __HAL_RCC_DMA1_CLK_ENABLE(); + + _transfer_settings.dma_settings.Init.Direction = DMA_MEMORY_TO_PERIPH; + _transfer_settings.dma_settings.Init.PeriphInc = DMA_PINC_DISABLE; + _transfer_settings.dma_settings.Init.MemInc = DMA_MINC_DISABLE; + _transfer_settings.dma_settings.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + _transfer_settings.dma_settings.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + _transfer_settings.dma_settings.Init.Mode = settings.circular ? DMA_CIRCULAR : DMA_NORMAL; + _transfer_settings.dma_settings.Init.Priority = DMA_PRIORITY_VERY_HIGH; + _transfer_settings.dma_settings.Instance = settings.channel_stream; + + // Perform HAL Initialization first. + HAL_DMA_Init(&dmaUpdate); + + // Call dma prepare + prepare_dma(&_transfer_settings); + } +} + +/** + * @brief Begin the DMA transfer + * @retval None + */ +void DMATransferClass::begin(int bytes_to_transfer) { + if (!prepared) { + // call dma prepare + prepare_dma(&_transfer_settings); + } + + // Reset flags so it starts over + __HAL_DMA_CLEAR_FLAG(&_transfer_settings, DMA_FLAG_TC2 | DMA_FLAG_HT2 | DMA_FLAG_TE2); + + // Set size to transfer + _transfer_settings.dma_settings.Instance->CNDTR = bytes_to_transfer; + + // and enable it + __HAL_DMA_ENABLE(&_transfer_settings.dma_settings); +} + +/** + * @brief End the DMA transfer + * @retval None + */ +void DMATransferClass::end() { + + __HAL_DMA_DISABLE(&_transfer_settings); + + if (_prepared) { + end_dma(&_transfer_settings); + _prepared = false; + } +} diff --git a/libraries/DMA/src/DMATransfer.h b/libraries/DMA/src/DMATransfer.h new file mode 100644 index 0000000000..a37af00677 --- /dev/null +++ b/libraries/DMA/src/DMATransfer.h @@ -0,0 +1,38 @@ +#ifndef __DMATRANSFER_H__ +#define __DMATRANSFER_H__ + +#include "Arduino.h" + +typedef struct dmatransfer_s dmatransfer_t; + +#if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) + typedef DMA_Stream_TypeDef DMA_CS_Selection; +#else + typedef DMA_Channel_TypeDef DMA_CS_Selection; +#endif + + +struct dmatransfer_s { + /* Keep this the first member so casting back and forth is easy + */ + DMA_HandleTypeDef *dma_settings; + DMA_CS_Selection channel_stream; + boolean circular; + void (*transferComplete)(DMA_HandleTypeDef *); + void (*transferHalfComplete)(DMA_HandleTypeDef *); + void (*transferError)(DMA_HandleTypeDef *); +}; + +class DMATransferClass { + + public: + void prepare(dmatransfer_t *settings); + void begin(int bytes_to_transfer); + void end(); + private: + bool _prepared; + dmatransfer_t _transfer_settings; +}; + + +#endif /* __DMATRANSFER_H__ */ From e5f33645a02808c41bdadd9681809adf90b8ac67 Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Sun, 14 Jul 2019 22:40:23 -0700 Subject: [PATCH 06/18] Minor fixes. --- cores/arduino/board.h | 1 + libraries/DMA/src/DMATransfer.cpp | 6 +++++- libraries/DMA/src/DMATransfer.h | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/cores/arduino/board.h b/cores/arduino/board.h index 1b5be5a272..72cdc11fe5 100644 --- a/cores/arduino/board.h +++ b/cores/arduino/board.h @@ -10,6 +10,7 @@ #include "clock.h" #include "core_callback.h" #include "digital_io.h" +#include "dma.h" #include "dwt.h" #include "hw_config.h" #include "low_power.h" diff --git a/libraries/DMA/src/DMATransfer.cpp b/libraries/DMA/src/DMATransfer.cpp index 9d8f31ec40..c2bcdeddcc 100644 --- a/libraries/DMA/src/DMATransfer.cpp +++ b/libraries/DMA/src/DMATransfer.cpp @@ -8,9 +8,12 @@ */ void DMATransferClass::prepare(dmatransfer_t *settings) { if (!_prepared) { + // TODO - figure out which DMA to enable the clock for. __HAL_RCC_DMA1_CLK_ENABLE(); + + memcpy(&_transfer_settings, settings, sizeof(dmatransfer_t)); - _transfer_settings.dma_settings.Init.Direction = DMA_MEMORY_TO_PERIPH; + _transfer_settings.dma_settings.Init.Direction = transfer_direction; _transfer_settings.dma_settings.Init.PeriphInc = DMA_PINC_DISABLE; _transfer_settings.dma_settings.Init.MemInc = DMA_MINC_DISABLE; _transfer_settings.dma_settings.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; @@ -18,6 +21,7 @@ void DMATransferClass::prepare(dmatransfer_t *settings) { _transfer_settings.dma_settings.Init.Mode = settings.circular ? DMA_CIRCULAR : DMA_NORMAL; _transfer_settings.dma_settings.Init.Priority = DMA_PRIORITY_VERY_HIGH; _transfer_settings.dma_settings.Instance = settings.channel_stream; + // TODO - intialize the callbacks. // Perform HAL Initialization first. HAL_DMA_Init(&dmaUpdate); diff --git a/libraries/DMA/src/DMATransfer.h b/libraries/DMA/src/DMATransfer.h index a37af00677..a1e9fca91d 100644 --- a/libraries/DMA/src/DMATransfer.h +++ b/libraries/DMA/src/DMATransfer.h @@ -17,6 +17,7 @@ struct dmatransfer_s { */ DMA_HandleTypeDef *dma_settings; DMA_CS_Selection channel_stream; + uint32_t transfer_direction; boolean circular; void (*transferComplete)(DMA_HandleTypeDef *); void (*transferHalfComplete)(DMA_HandleTypeDef *); From e7b4a8ae7daca66776539b1bc459ee0c4fbbabe6 Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Mon, 15 Jul 2019 08:26:50 -0700 Subject: [PATCH 07/18] Save morning's work. --- cores/arduino/stm32/dma.h | 8 ++++++++ libraries/DMA/library.properties | 3 ++- libraries/DMA/src/DMATransfer.cpp | 30 +++++++++++++++++------------- libraries/DMA/src/DMATransfer.h | 12 ++++++------ 4 files changed, 33 insertions(+), 20 deletions(-) diff --git a/cores/arduino/stm32/dma.h b/cores/arduino/stm32/dma.h index 2391e6e8b4..85d21d54f4 100644 --- a/cores/arduino/stm32/dma.h +++ b/cores/arduino/stm32/dma.h @@ -40,6 +40,10 @@ #ifndef __DMA_H #define __DMA_H +#ifdef __cplusplus +extern "C" { +#endif + #include /** @@ -56,4 +60,8 @@ void prepare_dma(DMA_HandleTypeDef *dma_handle); */ void end_dma(DMA_HandleTypeDef *dma_handle); +#ifdef __cplusplus +} +#endif + #endif diff --git a/libraries/DMA/library.properties b/libraries/DMA/library.properties index d5f0418fce..9de7ffeff0 100644 --- a/libraries/DMA/library.properties +++ b/libraries/DMA/library.properties @@ -1,7 +1,8 @@ name=DMA version=0.0.1 author=J.C. Nelson +maintainer=xC0000005 sentence=Enables Direct Memory Access Transfers. paragraph=This library allows use of Direct Memory Access (DMA) for transfer between memory locations, to and from peripherals. -category=Data Transfers +category=Uncategorized architectures=stm32 diff --git a/libraries/DMA/src/DMATransfer.cpp b/libraries/DMA/src/DMATransfer.cpp index c2bcdeddcc..084d80399a 100644 --- a/libraries/DMA/src/DMATransfer.cpp +++ b/libraries/DMA/src/DMATransfer.cpp @@ -1,4 +1,5 @@ #include +#include /** * @brief Prepares for DMA Transfer by enabling clocks @@ -6,28 +7,29 @@ * @param settings : dma transfer settings * @retval None */ -void DMATransferClass::prepare(dmatransfer_t *settings) { +void DMATransferClass::prepare(dmatransfer_t *settings) +{ if (!_prepared) { // TODO - figure out which DMA to enable the clock for. __HAL_RCC_DMA1_CLK_ENABLE(); - + memcpy(&_transfer_settings, settings, sizeof(dmatransfer_t)); - _transfer_settings.dma_settings.Init.Direction = transfer_direction; + _transfer_settings.dma_settings.Init.Direction = _transfer_settings.transfer_direction; _transfer_settings.dma_settings.Init.PeriphInc = DMA_PINC_DISABLE; _transfer_settings.dma_settings.Init.MemInc = DMA_MINC_DISABLE; _transfer_settings.dma_settings.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; _transfer_settings.dma_settings.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; - _transfer_settings.dma_settings.Init.Mode = settings.circular ? DMA_CIRCULAR : DMA_NORMAL; + _transfer_settings.dma_settings.Init.Mode = _transfer_settings.circular ? DMA_CIRCULAR : DMA_NORMAL; _transfer_settings.dma_settings.Init.Priority = DMA_PRIORITY_VERY_HIGH; - _transfer_settings.dma_settings.Instance = settings.channel_stream; + _transfer_settings.dma_settings.Instance = _transfer_settings.channel_stream; // TODO - intialize the callbacks. // Perform HAL Initialization first. - HAL_DMA_Init(&dmaUpdate); + HAL_DMA_Init(&_transfer_settings.dma_settings); // Call dma prepare - prepare_dma(&_transfer_settings); + prepare_dma(&_transfer_settings.dma_settings); } } @@ -35,10 +37,11 @@ void DMATransferClass::prepare(dmatransfer_t *settings) { * @brief Begin the DMA transfer * @retval None */ -void DMATransferClass::begin(int bytes_to_transfer) { - if (!prepared) { +void DMATransferClass::begin(int bytes_to_transfer) +{ + if (!_prepared) { // call dma prepare - prepare_dma(&_transfer_settings); + prepare_dma(&_transfer_settings.dma_settings); } // Reset flags so it starts over @@ -55,12 +58,13 @@ void DMATransferClass::begin(int bytes_to_transfer) { * @brief End the DMA transfer * @retval None */ -void DMATransferClass::end() { +void DMATransferClass::end() +{ - __HAL_DMA_DISABLE(&_transfer_settings); + __HAL_DMA_DISABLE(&_transfer_settings.dma_settings); if (_prepared) { - end_dma(&_transfer_settings); + end_dma(&_transfer_settings.dma_settings); _prepared = false; } } diff --git a/libraries/DMA/src/DMATransfer.h b/libraries/DMA/src/DMATransfer.h index a1e9fca91d..7f3b136589 100644 --- a/libraries/DMA/src/DMATransfer.h +++ b/libraries/DMA/src/DMATransfer.h @@ -6,17 +6,17 @@ typedef struct dmatransfer_s dmatransfer_t; #if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) - typedef DMA_Stream_TypeDef DMA_CS_Selection; +typedef DMA_Stream_TypeDef DMA_CS_Selection; #else - typedef DMA_Channel_TypeDef DMA_CS_Selection; +typedef DMA_Channel_TypeDef DMA_CS_Selection; #endif struct dmatransfer_s { - /* Keep this the first member so casting back and forth is easy - */ - DMA_HandleTypeDef *dma_settings; - DMA_CS_Selection channel_stream; + /* Keep this the first member so casting back and forth is easy + */ + DMA_HandleTypeDef dma_settings; + DMA_CS_Selection *channel_stream; uint32_t transfer_direction; boolean circular; void (*transferComplete)(DMA_HandleTypeDef *); From dc4bc59dccfc75214c05dfeedc5445f465561615 Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Mon, 15 Jul 2019 09:31:41 -0700 Subject: [PATCH 08/18] Minor refactoring. --- libraries/DMA/src/DMATransfer.cpp | 6 +++++- libraries/DMA/src/DMATransfer.h | 6 ++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/libraries/DMA/src/DMATransfer.cpp b/libraries/DMA/src/DMATransfer.cpp index 084d80399a..3ca8074d82 100644 --- a/libraries/DMA/src/DMATransfer.cpp +++ b/libraries/DMA/src/DMATransfer.cpp @@ -30,6 +30,8 @@ void DMATransferClass::prepare(dmatransfer_t *settings) // Call dma prepare prepare_dma(&_transfer_settings.dma_settings); + + _prepared = true; } } @@ -45,13 +47,15 @@ void DMATransferClass::begin(int bytes_to_transfer) } // Reset flags so it starts over - __HAL_DMA_CLEAR_FLAG(&_transfer_settings, DMA_FLAG_TC2 | DMA_FLAG_HT2 | DMA_FLAG_TE2); + __HAL_DMA_CLEAR_FLAG(&_transfer_settings.dma_settings, DMA_FLAG_TC2 | DMA_FLAG_HT2 | DMA_FLAG_TE2); // Set size to transfer _transfer_settings.dma_settings.Instance->CNDTR = bytes_to_transfer; // and enable it __HAL_DMA_ENABLE(&_transfer_settings.dma_settings); + + HAL_DMA_Start(&_transfer_settings.dma_settings, _transfer_settings.source, _transfer_settings.destination, bytes_to_transfer); } /** diff --git a/libraries/DMA/src/DMATransfer.h b/libraries/DMA/src/DMATransfer.h index 7f3b136589..f7e0c29ae3 100644 --- a/libraries/DMA/src/DMATransfer.h +++ b/libraries/DMA/src/DMATransfer.h @@ -19,12 +19,14 @@ struct dmatransfer_s { DMA_CS_Selection *channel_stream; uint32_t transfer_direction; boolean circular; + uint32_t source; + uint32_t destination; void (*transferComplete)(DMA_HandleTypeDef *); void (*transferHalfComplete)(DMA_HandleTypeDef *); void (*transferError)(DMA_HandleTypeDef *); }; -class DMATransferClass { +typedef class DMATransferClass { public: void prepare(dmatransfer_t *settings); @@ -33,7 +35,7 @@ class DMATransferClass { private: bool _prepared; dmatransfer_t _transfer_settings; -}; +} DMATransfer; #endif /* __DMATRANSFER_H__ */ From 12825f8b490d18e91f10976159951c20c542f325 Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Tue, 16 Jul 2019 15:40:59 -0700 Subject: [PATCH 09/18] Support starting interrupt DMAs. --- cores/arduino/stm32/dma.c | 143 ++++++++++++++++++++++++++++++ cores/arduino/stm32/dma.h | 13 +++ libraries/DMA/src/DMATransfer.cpp | 39 +++++--- libraries/DMA/src/DMATransfer.h | 26 ++---- 4 files changed, 190 insertions(+), 31 deletions(-) diff --git a/cores/arduino/stm32/dma.c b/cores/arduino/stm32/dma.c index 4cdef33f22..d2115c1fa8 100644 --- a/cores/arduino/stm32/dma.c +++ b/cores/arduino/stm32/dma.c @@ -287,6 +287,149 @@ static dma_index_t get_dma_index( } } +/** + * @brief This function will get the interrupt number for a DMA + * @param dma_handle : dma channel or strea + * @retval None + */ +IRQn_Type get_dma_interrupt( +#if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) + DMA_Stream_TypeDef +#else + DMA_Channel_TypeDef +#endif + *instance) +{ + switch ((uint32_t)instance) { +#ifdef DMA1_Channel1 + case (uint32_t)DMA1_Channel1: + return DMA1_Channel1_IRQn; +#endif +#ifdef DMA1_Channel2 + case (uint32_t)DMA1_Channel2: + return DMA1_Channel2_IRQn; +#endif +#ifdef DMA1_Channel3 + case (uint32_t)DMA1_Channel3: + return DMA1_Channel3_IRQn; +#endif +#ifdef DMA1_Channel4 + case (uint32_t)DMA1_Channel4: + return DMA1_Channel4_IRQn; +#endif +#ifdef DMA1_Channel5 + case (uint32_t)DMA1_Channel5: + return DMA1_Channel5_IRQn; +#endif +#ifdef DMA1_Channel6 + case (uint32_t)DMA1_Channel6: + return DMA1_Channel6_IRQn; +#endif +#ifdef DMA1_Channel7 + case (uint32_t)DMA1_Channel7: + return DMA1_Channel7_IRQn; +#endif +#ifdef DMA2_Channel1 + case (uint32_t)DMA2_Channel1: + return DMA2_Channel1_IRQn; +#endif +#ifdef DMA2_Channel2 + case (uint32_t)DMA2_Channel2: + return DMA2_Channel2_IRQn; +#endif +#ifdef DMA2_Channel3 + case (uint32_t)DMA2_Channel3: + return DMA2_Channel3_IRQn; +#endif +#ifdef DMA2_Channel4 + case (uint32_t)DMA2_Channel4: + return DMA2_Channel4_IRQn; +#endif +#ifdef DMA2_Channel5 + case (uint32_t)DMA2_Channel5: + return DMA2_Channel5_IRQn; +#endif +#ifdef DMA2_Channel6 + case (uint32_t)DMA2_Channel6: + return DMA2_Channel6_IRQn; +#endif +#ifdef DMA2_Channel7 + case (uint32_t)DMA2_Channel7: + return DMA2_Channel7_IRQn; +#endif +#ifdef DMA2_Channel8 + case (uint32_t)DMA2_Channel8: + return DMA2_Channel8_IRQn; +#endif +#ifdef DMA1_Stream0 + case (uint32_t)DMA1_Stream0: + return DMA1_Stream0_IRQn; +#endif +#ifdef DMA1_Stream1 + case (uint32_t)DMA1_Stream1: + return DMA1_Stream1_IRQn; +#endif +#ifdef DMA1_Stream2 + case (uint32_t)DMA1_Stream2: + return DMA1_Stream2_IRQn; +#endif +#ifdef DMA1_Stream3 + case (uint32_t)DMA1_Stream3: + return DMA1_Stream3_IRQn; +#endif +#ifdef DMA1_Stream4 + case (uint32_t)DMA1_Stream4: + return DMA1_Stream4_IRQn; +#endif +#ifdef DMA1_Stream5 + case (uint32_t)DMA1_Stream5: + return DMA1_Stream5_IRQn; +#endif +#ifdef DMA1_Stream6 + case (uint32_t)DMA1_Stream6: + return DMA1_Stream6_IRQn; +#endif +#ifdef DMA1_Stream7 + case (uint32_t)DMA1_Stream7: + return DMA1_Stream7_IRQn; +#endif +#ifdef DMA2_Stream0 + case (uint32_t)DMA2_Stream0: + return DMA2_Stream0_IRQn; +#endif +#ifdef DMA2_Stream1 + case (uint32_t)DMA2_Stream1: + return DMA2_Stream1_IRQn; +#endif +#ifdef DMA2_Stream2 + case (uint32_t)DMA2_Stream2: + return DMA2_Stream2_IRQn; +#endif +#ifdef DMA2_Stream3 + case (uint32_t)DMA2_Stream3: + return DMA2_Stream3_IRQn; +#endif +#ifdef DMA2_Stream4 + case (uint32_t)DMA2_Stream4: + return DMA2_Stream4_IRQn; +#endif +#ifdef DMA2_Stream5 + case (uint32_t)DMA2_Stream5: + return DMA2_Stream5_IRQn; +#endif +#ifdef DMA2_Stream6 + case (uint32_t)DMA2_Stream6: + return DMA2_Stream6_IRQn; +#endif +#ifdef DMA2_Stream7 + case (uint32_t)DMA2_Stream7: + return DMA2_Stream7_IRQn; +#endif + default: + return NC; + } +} + /** * @brief This function will store the DMA handle in the appropriate slot * @param dma_handle : dma handle diff --git a/cores/arduino/stm32/dma.h b/cores/arduino/stm32/dma.h index 85d21d54f4..0909dd60ef 100644 --- a/cores/arduino/stm32/dma.h +++ b/cores/arduino/stm32/dma.h @@ -46,6 +46,19 @@ extern "C" { #include +/** + * @brief This function will get the interrupt number for a DMA + * @param dma_handle : dma channel or strea + * @retval None + */ +IRQn_Type get_dma_interrupt( +#if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) + DMA_Stream_TypeDef +#else + DMA_Channel_TypeDef +#endif + *instance); + /** * @brief This function will store the DMA handle in the appropriate slot * @param dma_handle : dma handle diff --git a/libraries/DMA/src/DMATransfer.cpp b/libraries/DMA/src/DMATransfer.cpp index 3ca8074d82..f6fa26c680 100644 --- a/libraries/DMA/src/DMATransfer.cpp +++ b/libraries/DMA/src/DMATransfer.cpp @@ -7,14 +7,14 @@ * @param settings : dma transfer settings * @retval None */ -void DMATransferClass::prepare(dmatransfer_t *settings) +void DMATransferClass::prepare(DMA_HandleTypeDef *settings) { if (!_prepared) { // TODO - figure out which DMA to enable the clock for. __HAL_RCC_DMA1_CLK_ENABLE(); - memcpy(&_transfer_settings, settings, sizeof(dmatransfer_t)); - + memcpy(&_dma, settings, sizeof(DMA_HandleTypeDef)); + /* _transfer_settings.dma_settings.Init.Direction = _transfer_settings.transfer_direction; _transfer_settings.dma_settings.Init.PeriphInc = DMA_PINC_DISABLE; _transfer_settings.dma_settings.Init.MemInc = DMA_MINC_DISABLE; @@ -24,12 +24,17 @@ void DMATransferClass::prepare(dmatransfer_t *settings) _transfer_settings.dma_settings.Init.Priority = DMA_PRIORITY_VERY_HIGH; _transfer_settings.dma_settings.Instance = _transfer_settings.channel_stream; // TODO - intialize the callbacks. + */ // Perform HAL Initialization first. - HAL_DMA_Init(&_transfer_settings.dma_settings); + HAL_DMA_Init(&_dma); + _dma.XferCpltCallback = settings->XferCpltCallback; + _dma.XferHalfCpltCallback = settings->XferHalfCpltCallback; + _dma.XferErrorCallback = settings->XferErrorCallback; + _dma.XferAbortCallback = settings->XferAbortCallback; // Call dma prepare - prepare_dma(&_transfer_settings.dma_settings); + prepare_dma(&_dma); _prepared = true; } @@ -39,23 +44,31 @@ void DMATransferClass::prepare(dmatransfer_t *settings) * @brief Begin the DMA transfer * @retval None */ -void DMATransferClass::begin(int bytes_to_transfer) +void DMATransferClass::begin(uint32_t source, uint32_t destination, int bytes_to_transfer, bool use_interrupt) { if (!_prepared) { // call dma prepare - prepare_dma(&_transfer_settings.dma_settings); + prepare_dma(&_dma); } // Reset flags so it starts over - __HAL_DMA_CLEAR_FLAG(&_transfer_settings.dma_settings, DMA_FLAG_TC2 | DMA_FLAG_HT2 | DMA_FLAG_TE2); + __HAL_DMA_CLEAR_FLAG(&_dma, DMA_FLAG_TC2 | DMA_FLAG_HT2 | DMA_FLAG_TE2); // Set size to transfer - _transfer_settings.dma_settings.Instance->CNDTR = bytes_to_transfer; + _dma.Instance->CNDTR = bytes_to_transfer; // and enable it - __HAL_DMA_ENABLE(&_transfer_settings.dma_settings); + __HAL_DMA_ENABLE(&_dma); - HAL_DMA_Start(&_transfer_settings.dma_settings, _transfer_settings.source, _transfer_settings.destination, bytes_to_transfer); + if (use_interrupt) { + IRQn_Type interrupt_number = get_dma_interrupt(_dma.Instance); + HAL_NVIC_SetPriority(interrupt_number, 0, 0); + HAL_NVIC_EnableIRQ(interrupt_number); + HAL_DMA_Start_IT(&_dma, source, destination, bytes_to_transfer); + } + else { + HAL_DMA_Start(&_dma, source, destination, bytes_to_transfer); + } } /** @@ -65,10 +78,10 @@ void DMATransferClass::begin(int bytes_to_transfer) void DMATransferClass::end() { - __HAL_DMA_DISABLE(&_transfer_settings.dma_settings); + __HAL_DMA_DISABLE(&_dma); if (_prepared) { - end_dma(&_transfer_settings.dma_settings); + end_dma(&_dma); _prepared = false; } } diff --git a/libraries/DMA/src/DMATransfer.h b/libraries/DMA/src/DMATransfer.h index f7e0c29ae3..58e0adfa87 100644 --- a/libraries/DMA/src/DMATransfer.h +++ b/libraries/DMA/src/DMATransfer.h @@ -11,30 +11,20 @@ typedef DMA_Stream_TypeDef DMA_CS_Selection; typedef DMA_Channel_TypeDef DMA_CS_Selection; #endif - -struct dmatransfer_s { - /* Keep this the first member so casting back and forth is easy - */ - DMA_HandleTypeDef dma_settings; - DMA_CS_Selection *channel_stream; - uint32_t transfer_direction; - boolean circular; - uint32_t source; - uint32_t destination; - void (*transferComplete)(DMA_HandleTypeDef *); - void (*transferHalfComplete)(DMA_HandleTypeDef *); - void (*transferError)(DMA_HandleTypeDef *); -}; - typedef class DMATransferClass { public: - void prepare(dmatransfer_t *settings); - void begin(int bytes_to_transfer); + /* + DMATransferClass(uint32_t transfer_direction, boolean circular, uint32_t source, uint32_t destination){ + this->dma.Init. + }*/ + + void prepare(DMA_HandleTypeDef *settings); + void begin(uint32_t source, uint32_t destination, int bytes_to_transfer, bool use_interrupt = false); void end(); private: bool _prepared; - dmatransfer_t _transfer_settings; + DMA_HandleTypeDef _dma; } DMATransfer; From 01ee2d4459e513da13696ed80bddadedcbb62f0d Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Thu, 1 Aug 2019 11:59:45 -1000 Subject: [PATCH 10/18] Minor fix. --- libraries/DMA/src/DMATransfer.cpp | 39 ++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/libraries/DMA/src/DMATransfer.cpp b/libraries/DMA/src/DMATransfer.cpp index f6fa26c680..18bffe070a 100644 --- a/libraries/DMA/src/DMATransfer.cpp +++ b/libraries/DMA/src/DMATransfer.cpp @@ -11,8 +11,12 @@ void DMATransferClass::prepare(DMA_HandleTypeDef *settings) { if (!_prepared) { // TODO - figure out which DMA to enable the clock for. - __HAL_RCC_DMA1_CLK_ENABLE(); - + #ifdef DMA1_BASE + __HAL_RCC_DMA1_CLK_ENABLE(); + #endif + #ifdef DMA2_BASE + __HAL_RCC_DMA2_CLK_ENABLE(); + #endif memcpy(&_dma, settings, sizeof(DMA_HandleTypeDef)); /* _transfer_settings.dma_settings.Init.Direction = _transfer_settings.transfer_direction; @@ -46,16 +50,45 @@ void DMATransferClass::prepare(DMA_HandleTypeDef *settings) */ void DMATransferClass::begin(uint32_t source, uint32_t destination, int bytes_to_transfer, bool use_interrupt) { + // Make sure we're set to initialize + this->end(); + if (!_prepared) { // call dma prepare prepare_dma(&_dma); } + /** + * @brief Clear the DMA Stream pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval None + */ + // Reset flags so it starts over - __HAL_DMA_CLEAR_FLAG(&_dma, DMA_FLAG_TC2 | DMA_FLAG_HT2 | DMA_FLAG_TE2); + __HAL_DMA_CLEAR_FLAG(&_dma, __HAL_DMA_GET_TC_FLAG_INDEX(&_dma)); + __HAL_DMA_CLEAR_FLAG(&_dma, __HAL_DMA_GET_HT_FLAG_INDEX(&_dma)); + __HAL_DMA_CLEAR_FLAG(&_dma, __HAL_DMA_GET_TE_FLAG_INDEX(&_dma)); + + #if defined(STM32F2xx) || #defined(STM32F4xx) || #defined(STM32F7xx) + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + #endif // Set size to transfer + + #if defined(__HAL_DMA_SET_COUNTER) + __HAL_DMA_SET_COUNTER(&_dma, bytes_to_transfer); + #else _dma.Instance->CNDTR = bytes_to_transfer; + #endif // and enable it __HAL_DMA_ENABLE(&_dma); From 8b92b35f5ed53a3b73984de9df4ba8d2c817b1fe Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Mon, 9 Dec 2019 20:48:11 -0800 Subject: [PATCH 11/18] Astyle fixes. --- cores/arduino/stm32/dma.c | 418 +++++++++++++++++++------------------- cores/arduino/stm32/dma.h | 6 +- 2 files changed, 212 insertions(+), 212 deletions(-) diff --git a/cores/arduino/stm32/dma.c b/cores/arduino/stm32/dma.c index d2115c1fa8..b74c64f5ef 100644 --- a/cores/arduino/stm32/dma.c +++ b/cores/arduino/stm32/dma.c @@ -45,99 +45,99 @@ extern "C" { typedef enum { #ifdef DMA1_Channel1 - DMA1_CHANNEL1_INDEX, + DMA1_CHANNEL1_INDEX, #endif #ifdef DMA1_Channel2 - DMA1_CHANNEL2_INDEX, + DMA1_CHANNEL2_INDEX, #endif #ifdef DMA1_Channel3 - DMA1_CHANNEL3_INDEX, + DMA1_CHANNEL3_INDEX, #endif #ifdef DMA1_Channel4 - DMA1_CHANNEL4_INDEX, + DMA1_CHANNEL4_INDEX, #endif #ifdef DMA1_Channel5 - DMA1_CHANNEL5_INDEX, + DMA1_CHANNEL5_INDEX, #endif #ifdef DMA1_Channel6 - DMA1_CHANNEL6_INDEX, + DMA1_CHANNEL6_INDEX, #endif #ifdef DMA1_Channel7 - DMA1_CHANNEL7_INDEX, + DMA1_CHANNEL7_INDEX, #endif #ifdef DMA2_Channel1 - DMA2_CHANNEL1_INDEX, + DMA2_CHANNEL1_INDEX, #endif #ifdef DMA2_Channel2 - DMA2_CHANNEL2_INDEX, + DMA2_CHANNEL2_INDEX, #endif #ifdef DMA2_Channel3 - DMA2_CHANNEL3_INDEX, + DMA2_CHANNEL3_INDEX, #endif #ifdef DMA2_Channel4 - DMA2_CHANNEL4_INDEX, + DMA2_CHANNEL4_INDEX, #endif #ifdef DMA2_Channel5 - DMA2_CHANNEL5_INDEX, + DMA2_CHANNEL5_INDEX, #endif #ifdef DMA2_Channel6 - DMA2_CHANNEL6_INDEX, + DMA2_CHANNEL6_INDEX, #endif #ifdef DMA2_Channel7 - DMA2_CHANNEL7_INDEX, + DMA2_CHANNEL7_INDEX, #endif #ifdef DMA2_Channel8 - DMA2_CHANNEL8_INDEX, + DMA2_CHANNEL8_INDEX, #endif #ifdef DMA1_Stream0 - DMA1_STREAM0_INDEX, + DMA1_STREAM0_INDEX, #endif #ifdef DMA1_Stream1 - DMA1_STREAM1_INDEX, + DMA1_STREAM1_INDEX, #endif #ifdef DMA1_Stream2 - DMA1_STREAM2_INDEX, + DMA1_STREAM2_INDEX, #endif #ifdef DMA1_Stream3 - DMA1_STREAM3_INDEX, + DMA1_STREAM3_INDEX, #endif #ifdef DMA1_Stream4 - DMA1_STREAM4_INDEX, + DMA1_STREAM4_INDEX, #endif #ifdef DMA1_Stream5 - DMA1_STREAM5_INDEX, + DMA1_STREAM5_INDEX, #endif #ifdef DMA1_Stream6 - DMA1_STREAM6_INDEX, + DMA1_STREAM6_INDEX, #endif #ifdef DMA1_Stream7 - DMA1_STREAM7_INDEX, + DMA1_STREAM7_INDEX, #endif #ifdef DMA2_Stream0 - DMA2_STREAM0_INDEX, + DMA2_STREAM0_INDEX, #endif #ifdef DMA2_Stream1 - DMA2_STREAM1_INDEX, + DMA2_STREAM1_INDEX, #endif #ifdef DMA2_Stream2 - DMA2_STREAM2_INDEX, + DMA2_STREAM2_INDEX, #endif #ifdef DMA2_Stream3 - DMA2_STREAM3_INDEX, + DMA2_STREAM3_INDEX, #endif #ifdef DMA2_Stream4 - DMA2_STREAM4_INDEX, + DMA2_STREAM4_INDEX, #endif #ifdef DMA2_Stream5 - DMA2_STREAM5_INDEX, + DMA2_STREAM5_INDEX, #endif #ifdef DMA2_Stream6 - DMA2_STREAM6_INDEX, + DMA2_STREAM6_INDEX, #endif #ifdef DMA2_Stream7 - DMA2_STREAM7_INDEX, + DMA2_STREAM7_INDEX, #endif - DMA_CHANNEL_NUM + DMA_CHANNEL_NUM } dma_index_t; #define NC (dma_index_t)-1 @@ -151,140 +151,140 @@ static DMA_HandleTypeDef *dma_handles[DMA_CHANNEL_NUM] = {NULL}; */ static dma_index_t get_dma_index( #if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) - DMA_Stream_TypeDef + DMA_Stream_TypeDef #else - DMA_Channel_TypeDef + DMA_Channel_TypeDef #endif - *instance) + *instance) { - switch ((uint32_t)instance) { + switch ((uint32_t)instance) { #ifdef DMA1_Channel1 case (uint32_t)DMA1_Channel1: - return DMA1_CHANNEL1_INDEX; + return DMA1_CHANNEL1_INDEX; #endif #ifdef DMA1_Channel2 case (uint32_t)DMA1_Channel2: - return DMA1_CHANNEL2_INDEX; + return DMA1_CHANNEL2_INDEX; #endif #ifdef DMA1_Channel3 case (uint32_t)DMA1_Channel3: - return DMA1_CHANNEL3_INDEX; + return DMA1_CHANNEL3_INDEX; #endif #ifdef DMA1_Channel4 case (uint32_t)DMA1_Channel4: - return DMA1_CHANNEL4_INDEX; + return DMA1_CHANNEL4_INDEX; #endif #ifdef DMA1_Channel5 case (uint32_t)DMA1_Channel5: - return DMA1_CHANNEL5_INDEX; + return DMA1_CHANNEL5_INDEX; #endif #ifdef DMA1_Channel6 case (uint32_t)DMA1_Channel6: - return DMA1_CHANNEL6_INDEX; + return DMA1_CHANNEL6_INDEX; #endif #ifdef DMA1_Channel7 case (uint32_t)DMA1_Channel7: - return DMA1_CHANNEL7_INDEX; + return DMA1_CHANNEL7_INDEX; #endif #ifdef DMA2_Channel1 case (uint32_t)DMA2_Channel1: - return DMA2_CHANNEL1_INDEX; + return DMA2_CHANNEL1_INDEX; #endif #ifdef DMA2_Channel2 case (uint32_t)DMA2_Channel2: - return DMA2_CHANNEL2_INDEX; + return DMA2_CHANNEL2_INDEX; #endif #ifdef DMA2_Channel3 case (uint32_t)DMA2_Channel3: - return DMA2_CHANNEL3_INDEX; + return DMA2_CHANNEL3_INDEX; #endif #ifdef DMA2_Channel4 case (uint32_t)DMA2_Channel4: - return DMA2_CHANNEL4_INDEX; + return DMA2_CHANNEL4_INDEX; #endif #ifdef DMA2_Channel5 case (uint32_t)DMA2_Channel5: - return DMA2_CHANNEL5_INDEX; + return DMA2_CHANNEL5_INDEX; #endif #ifdef DMA2_Channel6 case (uint32_t)DMA2_Channel6: - return DMA2_CHANNEL6_INDEX; + return DMA2_CHANNEL6_INDEX; #endif #ifdef DMA2_Channel7 case (uint32_t)DMA2_Channel7: - return DMA2_CHANNEL7_INDEX; + return DMA2_CHANNEL7_INDEX; #endif #ifdef DMA2_Channel8 case (uint32_t)DMA2_Channel8: - return DMA2_CHANNEL8_INDEX; + return DMA2_CHANNEL8_INDEX; #endif #ifdef DMA1_Stream0 case (uint32_t)DMA1_Stream0: - return DMA1_STREAM0_INDEX; + return DMA1_STREAM0_INDEX; #endif #ifdef DMA1_Stream1 case (uint32_t)DMA1_Stream1: - return DMA1_STREAM1_INDEX; + return DMA1_STREAM1_INDEX; #endif #ifdef DMA1_Stream2 case (uint32_t)DMA1_Stream2: - return DMA1_STREAM2_INDEX; + return DMA1_STREAM2_INDEX; #endif #ifdef DMA1_Stream3 case (uint32_t)DMA1_Stream3: - return DMA1_STREAM3_INDEX; + return DMA1_STREAM3_INDEX; #endif #ifdef DMA1_Stream4 case (uint32_t)DMA1_Stream4: - return DMA1_STREAM4_INDEX; + return DMA1_STREAM4_INDEX; #endif #ifdef DMA1_Stream5 case (uint32_t)DMA1_Stream5: - return DMA1_STREAM5_INDEX; + return DMA1_STREAM5_INDEX; #endif #ifdef DMA1_Stream6 case (uint32_t)DMA1_Stream6: - return DMA1_STREAM6_INDEX; + return DMA1_STREAM6_INDEX; #endif #ifdef DMA1_Stream7 case (uint32_t)DMA1_Stream7: - return DMA1_STREAM7_INDEX; + return DMA1_STREAM7_INDEX; #endif #ifdef DMA2_Stream0 case (uint32_t)DMA2_Stream0: - return DMA2_STREAM0_INDEX; + return DMA2_STREAM0_INDEX; #endif #ifdef DMA2_Stream1 case (uint32_t)DMA2_Stream1: - return DMA2_STREAM1_INDEX; + return DMA2_STREAM1_INDEX; #endif #ifdef DMA2_Stream2 case (uint32_t)DMA2_Stream2: - return DMA2_STREAM2_INDEX; + return DMA2_STREAM2_INDEX; #endif #ifdef DMA2_Stream3 case (uint32_t)DMA2_Stream3: - return DMA2_STREAM3_INDEX; + return DMA2_STREAM3_INDEX; #endif #ifdef DMA2_Stream4 case (uint32_t)DMA2_Stream4: - return DMA2_STREAM4_INDEX; + return DMA2_STREAM4_INDEX; #endif #ifdef DMA2_Stream5 case (uint32_t)DMA2_Stream5: - return DMA2_STREAM5_INDEX; + return DMA2_STREAM5_INDEX; #endif #ifdef DMA2_Stream6 case (uint32_t)DMA2_Stream6: - return DMA2_STREAM6_INDEX; + return DMA2_STREAM6_INDEX; #endif #ifdef DMA2_Stream7 case (uint32_t)DMA2_Stream7: - return DMA2_STREAM7_INDEX; + return DMA2_STREAM7_INDEX; #endif default: - return NC; - } + return NC; + } } /** @@ -294,140 +294,140 @@ static dma_index_t get_dma_index( */ IRQn_Type get_dma_interrupt( #if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) - DMA_Stream_TypeDef + DMA_Stream_TypeDef #else - DMA_Channel_TypeDef + DMA_Channel_TypeDef #endif - *instance) + *instance) { - switch ((uint32_t)instance) { + switch ((uint32_t)instance) { #ifdef DMA1_Channel1 case (uint32_t)DMA1_Channel1: - return DMA1_Channel1_IRQn; + return DMA1_Channel1_IRQn; #endif #ifdef DMA1_Channel2 case (uint32_t)DMA1_Channel2: - return DMA1_Channel2_IRQn; + return DMA1_Channel2_IRQn; #endif #ifdef DMA1_Channel3 case (uint32_t)DMA1_Channel3: - return DMA1_Channel3_IRQn; + return DMA1_Channel3_IRQn; #endif #ifdef DMA1_Channel4 case (uint32_t)DMA1_Channel4: - return DMA1_Channel4_IRQn; + return DMA1_Channel4_IRQn; #endif #ifdef DMA1_Channel5 case (uint32_t)DMA1_Channel5: - return DMA1_Channel5_IRQn; + return DMA1_Channel5_IRQn; #endif #ifdef DMA1_Channel6 case (uint32_t)DMA1_Channel6: - return DMA1_Channel6_IRQn; + return DMA1_Channel6_IRQn; #endif #ifdef DMA1_Channel7 case (uint32_t)DMA1_Channel7: - return DMA1_Channel7_IRQn; + return DMA1_Channel7_IRQn; #endif #ifdef DMA2_Channel1 case (uint32_t)DMA2_Channel1: - return DMA2_Channel1_IRQn; + return DMA2_Channel1_IRQn; #endif #ifdef DMA2_Channel2 case (uint32_t)DMA2_Channel2: - return DMA2_Channel2_IRQn; + return DMA2_Channel2_IRQn; #endif #ifdef DMA2_Channel3 case (uint32_t)DMA2_Channel3: - return DMA2_Channel3_IRQn; + return DMA2_Channel3_IRQn; #endif #ifdef DMA2_Channel4 case (uint32_t)DMA2_Channel4: - return DMA2_Channel4_IRQn; + return DMA2_Channel4_IRQn; #endif #ifdef DMA2_Channel5 case (uint32_t)DMA2_Channel5: - return DMA2_Channel5_IRQn; + return DMA2_Channel5_IRQn; #endif #ifdef DMA2_Channel6 case (uint32_t)DMA2_Channel6: - return DMA2_Channel6_IRQn; + return DMA2_Channel6_IRQn; #endif #ifdef DMA2_Channel7 case (uint32_t)DMA2_Channel7: - return DMA2_Channel7_IRQn; + return DMA2_Channel7_IRQn; #endif #ifdef DMA2_Channel8 case (uint32_t)DMA2_Channel8: - return DMA2_Channel8_IRQn; + return DMA2_Channel8_IRQn; #endif #ifdef DMA1_Stream0 case (uint32_t)DMA1_Stream0: - return DMA1_Stream0_IRQn; + return DMA1_Stream0_IRQn; #endif #ifdef DMA1_Stream1 case (uint32_t)DMA1_Stream1: - return DMA1_Stream1_IRQn; + return DMA1_Stream1_IRQn; #endif #ifdef DMA1_Stream2 case (uint32_t)DMA1_Stream2: - return DMA1_Stream2_IRQn; + return DMA1_Stream2_IRQn; #endif #ifdef DMA1_Stream3 case (uint32_t)DMA1_Stream3: - return DMA1_Stream3_IRQn; + return DMA1_Stream3_IRQn; #endif #ifdef DMA1_Stream4 case (uint32_t)DMA1_Stream4: - return DMA1_Stream4_IRQn; + return DMA1_Stream4_IRQn; #endif #ifdef DMA1_Stream5 case (uint32_t)DMA1_Stream5: - return DMA1_Stream5_IRQn; + return DMA1_Stream5_IRQn; #endif #ifdef DMA1_Stream6 case (uint32_t)DMA1_Stream6: - return DMA1_Stream6_IRQn; + return DMA1_Stream6_IRQn; #endif #ifdef DMA1_Stream7 case (uint32_t)DMA1_Stream7: - return DMA1_Stream7_IRQn; + return DMA1_Stream7_IRQn; #endif #ifdef DMA2_Stream0 case (uint32_t)DMA2_Stream0: - return DMA2_Stream0_IRQn; + return DMA2_Stream0_IRQn; #endif #ifdef DMA2_Stream1 case (uint32_t)DMA2_Stream1: - return DMA2_Stream1_IRQn; + return DMA2_Stream1_IRQn; #endif #ifdef DMA2_Stream2 case (uint32_t)DMA2_Stream2: - return DMA2_Stream2_IRQn; + return DMA2_Stream2_IRQn; #endif #ifdef DMA2_Stream3 case (uint32_t)DMA2_Stream3: - return DMA2_Stream3_IRQn; + return DMA2_Stream3_IRQn; #endif #ifdef DMA2_Stream4 case (uint32_t)DMA2_Stream4: - return DMA2_Stream4_IRQn; + return DMA2_Stream4_IRQn; #endif #ifdef DMA2_Stream5 case (uint32_t)DMA2_Stream5: - return DMA2_Stream5_IRQn; + return DMA2_Stream5_IRQn; #endif #ifdef DMA2_Stream6 case (uint32_t)DMA2_Stream6: - return DMA2_Stream6_IRQn; + return DMA2_Stream6_IRQn; #endif #ifdef DMA2_Stream7 case (uint32_t)DMA2_Stream7: - return DMA2_Stream7_IRQn; + return DMA2_Stream7_IRQn; #endif default: - return NC; - } + return NC; + } } /** @@ -437,11 +437,11 @@ IRQn_Type get_dma_interrupt( */ void prepare_dma(DMA_HandleTypeDef *dma_handle) { - dma_index_t dma_index = get_dma_index(dma_handle->Instance); - if (dma_index == NC) { - return; - } - dma_handles[dma_index] = dma_handle; + dma_index_t dma_index = get_dma_index(dma_handle->Instance); + if (dma_index == NC) { + return; + } + dma_handles[dma_index] = dma_handle; } /** @@ -451,11 +451,11 @@ void prepare_dma(DMA_HandleTypeDef *dma_handle) */ void end_dma(DMA_HandleTypeDef *dma_handle) { - dma_index_t dma_index = get_dma_index(dma_handle->Instance); - if (dma_index == NC) { - return; - } - dma_handles[dma_index] = NULL; + dma_index_t dma_index = get_dma_index(dma_handle->Instance); + if (dma_index == NC) { + return; + } + dma_handles[dma_index] = NULL; } #ifdef DMA1_Channel1 @@ -466,9 +466,9 @@ void end_dma(DMA_HandleTypeDef *dma_handle) */ void DMA1_Channel1_IRQHandler() { - if (dma_handles[DMA1_CHANNEL1_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL1_INDEX]); - } + if (dma_handles[DMA1_CHANNEL1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL1_INDEX]); + } } #endif @@ -480,9 +480,9 @@ void DMA1_Channel1_IRQHandler() */ void DMA1_Channel2_IRQHandler() { - if (dma_handles[DMA1_CHANNEL2_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL2_INDEX]); - } + if (dma_handles[DMA1_CHANNEL2_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL2_INDEX]); + } } #endif @@ -494,9 +494,9 @@ void DMA1_Channel2_IRQHandler() */ void DMA1_Channel3_IRQHandler() { - if (dma_handles[DMA1_CHANNEL3_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL3_INDEX]); - } + if (dma_handles[DMA1_CHANNEL3_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL3_INDEX]); + } } #endif @@ -508,9 +508,9 @@ void DMA1_Channel3_IRQHandler() */ void DMA1_Channel4_IRQHandler() { - if (dma_handles[DMA1_CHANNEL4_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL4_INDEX]); - } + if (dma_handles[DMA1_CHANNEL4_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL4_INDEX]); + } } #endif @@ -522,9 +522,9 @@ void DMA1_Channel4_IRQHandler() */ void DMA1_Channel5_IRQHandler() { - if (dma_handles[DMA1_CHANNEL5_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL5_INDEX]); - } + if (dma_handles[DMA1_CHANNEL5_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL5_INDEX]); + } } #endif @@ -535,9 +535,9 @@ void DMA1_Channel5_IRQHandler() */ void DMA1_Channel6_IRQHandler() { - if (dma_handles[DMA1_CHANNEL6_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL6_INDEX]); - } + if (dma_handles[DMA1_CHANNEL6_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL6_INDEX]); + } } #endif @@ -549,9 +549,9 @@ void DMA1_Channel6_IRQHandler() */ void DMA1_Channel7_IRQHandler() { - if (dma_handles[DMA1_CHANNEL7_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL7_INDEX]); - } + if (dma_handles[DMA1_CHANNEL7_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL7_INDEX]); + } } #endif @@ -563,9 +563,9 @@ void DMA1_Channel7_IRQHandler() */ void DMA2_Channel1_IRQHandler() { - if (dma_handles[DMA2_CHANNEL1_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL1_INDEX]); - } + if (dma_handles[DMA2_CHANNEL1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL1_INDEX]); + } } #endif @@ -577,9 +577,9 @@ void DMA2_Channel1_IRQHandler() */ void DMA2_Channel2_IRQHandler() { - if (dma_handles[DMA2_CHANNEL2_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL2_INDEX]); - } + if (dma_handles[DMA2_CHANNEL2_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL2_INDEX]); + } } #endif @@ -591,9 +591,9 @@ void DMA2_Channel2_IRQHandler() */ void DMA2_Channel3_IRQHandler() { - if (dma_handles[DMA2_CHANNEL3_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL3_INDEX]); - } + if (dma_handles[DMA2_CHANNEL3_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL3_INDEX]); + } } #endif @@ -605,9 +605,9 @@ void DMA2_Channel3_IRQHandler() */ void DMA2_Channel4_IRQHandler() { - if (dma_handles[DMA2_CHANNEL4_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL4_INDEX]); - } + if (dma_handles[DMA2_CHANNEL4_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL4_INDEX]); + } } #endif @@ -619,9 +619,9 @@ void DMA2_Channel4_IRQHandler() */ void DMA2_Channel5_IRQHandler() { - if (dma_handles[DMA2_CHANNEL5_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL5_INDEX]); - } + if (dma_handles[DMA2_CHANNEL5_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL5_INDEX]); + } } #endif @@ -633,9 +633,9 @@ void DMA2_Channel5_IRQHandler() */ void DMA2_Channel6_IRQHandler() { - if (dma_handles[DMA2_CHANNEL6_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL6_INDEX]); - } + if (dma_handles[DMA2_CHANNEL6_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL6_INDEX]); + } } #endif @@ -647,9 +647,9 @@ void DMA2_Channel6_IRQHandler() */ void DMA2_Channel7_IRQHandler() { - if (dma_handles[DMA2_CHANNEL7_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL7_INDEX]); - } + if (dma_handles[DMA2_CHANNEL7_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL7_INDEX]); + } } #endif @@ -661,153 +661,153 @@ void DMA2_Channel7_IRQHandler() */ void DMA2_Channel8_IRQHandler() { - if (dma_handles[DMA2_CHANNEL8_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL8_INDEX]); - } + if (dma_handles[DMA2_CHANNEL8_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL8_INDEX]); + } } #endif #ifdef DMA1_Stream0 void DMA1_Stream0_IRQHandler() { - if (dma_handles[DMA1_STREAM0_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM0_INDEX]); - } + if (dma_handles[DMA1_STREAM0_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM0_INDEX]); + } } #endif #ifdef DMA1_Stream1 void DMA1_Stream1_IRQHandler() { - if (dma_handles[DMA1_STREAM1_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM1_INDEX]); - } + if (dma_handles[DMA1_STREAM1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM1_INDEX]); + } } #endif #ifdef DMA1_Stream2 void DMA1_Stream2_IRQHandler() { - if (dma_handles[DMA1_STREAM2_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM2_INDEX]); - } + if (dma_handles[DMA1_STREAM2_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM2_INDEX]); + } } #endif #ifdef DMA1_Stream3 void DMA1_Stream3_IRQHandler() { - if (dma_handles[DMA1_STREAM3_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM3_INDEX]); - } + if (dma_handles[DMA1_STREAM3_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM3_INDEX]); + } } #endif #ifdef DMA1_Stream4 void DMA1_Stream4_IRQHandler() { - if (dma_handles[DMA1_STREAM4_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM4_INDEX]); - } + if (dma_handles[DMA1_STREAM4_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM4_INDEX]); + } } #endif #ifdef DMA1_Stream5 void DMA1_Stream5_IRQHandler() { - if (dma_handles[DMA1_STREAM5_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM5_INDEX]); - } + if (dma_handles[DMA1_STREAM5_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM5_INDEX]); + } } #endif #ifdef DMA1_Stream6 void DMA1_Stream6_IRQHandler() { - if (dma_handles[DMA1_STREAM6_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM6_INDEX]); - } + if (dma_handles[DMA1_STREAM6_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM6_INDEX]); + } } #endif #ifdef DMA1_Stream7 void DMA1_Stream7_IRQHandler() { - if (dma_handles[DMA1_STREAM7_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM7_INDEX]); - } + if (dma_handles[DMA1_STREAM7_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM7_INDEX]); + } } #endif #ifdef DMA2_Stream0 void DMA2_Stream0_IRQHandler() { - if (dma_handles[DMA2_STREAM0_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM0_INDEX]); - } + if (dma_handles[DMA2_STREAM0_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM0_INDEX]); + } } #endif #ifdef DMA2_Stream1 void DMA2_Stream1_IRQHandler() { - if (dma_handles[DMA2_STREAM1_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM1_INDEX]); - } + if (dma_handles[DMA2_STREAM1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM1_INDEX]); + } } #endif #ifdef DMA2_Stream2 void DMA2_Stream2_IRQHandler() { - if (dma_handles[DMA2_STREAM2_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM2_INDEX]); - } + if (dma_handles[DMA2_STREAM2_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM2_INDEX]); + } } #endif #ifdef DMA2_Stream3 void DMA2_Stream3_IRQHandler() { - if (dma_handles[DMA2_STREAM3_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM3_INDEX]); - } + if (dma_handles[DMA2_STREAM3_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM3_INDEX]); + } } #endif #ifdef DMA2_Stream4 void DMA2_Stream4_IRQHandler() { - if (dma_handles[DMA2_STREAM4_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM4_INDEX]); - } + if (dma_handles[DMA2_STREAM4_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM4_INDEX]); + } } #endif #ifdef DMA2_Stream5 void DMA2_Stream5_IRQHandler() { - if (dma_handles[DMA2_STREAM5_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM5_INDEX]); - } + if (dma_handles[DMA2_STREAM5_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM5_INDEX]); + } } #endif #ifdef DMA2_Stream6 void DMA2_Stream6_IRQHandler() { - if (dma_handles[DMA2_STREAM6_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM6_INDEX]); - } + if (dma_handles[DMA2_STREAM6_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM6_INDEX]); + } } #endif #ifdef DMA2_Stream7 void DMA2_Stream7_IRQHandler() { - if (dma_handles[DMA2_STREAM7_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM7_INDEX]); - } + if (dma_handles[DMA2_STREAM7_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM7_INDEX]); + } } #endif diff --git a/cores/arduino/stm32/dma.h b/cores/arduino/stm32/dma.h index 0909dd60ef..596897ac08 100644 --- a/cores/arduino/stm32/dma.h +++ b/cores/arduino/stm32/dma.h @@ -53,11 +53,11 @@ extern "C" { */ IRQn_Type get_dma_interrupt( #if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) - DMA_Stream_TypeDef + DMA_Stream_TypeDef #else - DMA_Channel_TypeDef + DMA_Channel_TypeDef #endif - *instance); + *instance); /** * @brief This function will store the DMA handle in the appropriate slot From 8bf7a47bc53a3132aad783872de624070366bf44 Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Mon, 9 Dec 2019 20:52:29 -0800 Subject: [PATCH 12/18] Remove non functional library. --- libraries/DMA/kewords.txt | 21 ------ libraries/DMA/library.properties | 8 -- libraries/DMA/src/DMATransfer.cpp | 120 ------------------------------ libraries/DMA/src/DMATransfer.h | 31 -------- 4 files changed, 180 deletions(-) delete mode 100644 libraries/DMA/kewords.txt delete mode 100644 libraries/DMA/library.properties delete mode 100644 libraries/DMA/src/DMATransfer.cpp delete mode 100644 libraries/DMA/src/DMATransfer.h diff --git a/libraries/DMA/kewords.txt b/libraries/DMA/kewords.txt deleted file mode 100644 index 43f1c9b43e..0000000000 --- a/libraries/DMA/kewords.txt +++ /dev/null @@ -1,21 +0,0 @@ -####################################### -# Syntax Coloring Map For DMA -####################################### - -####################################### -# Datatypes (KEYWORD1) -####################################### - -DMA KEYWORD1 -DMA1 KEYWORD1 -DMA2 KEYWORD2 - -####################################### -# Methods and Functions (KEYWORD2) -####################################### - -start KEYWORD2 - -####################################### -# Constants (LITERAL1) -####################################### diff --git a/libraries/DMA/library.properties b/libraries/DMA/library.properties deleted file mode 100644 index 9de7ffeff0..0000000000 --- a/libraries/DMA/library.properties +++ /dev/null @@ -1,8 +0,0 @@ -name=DMA -version=0.0.1 -author=J.C. Nelson -maintainer=xC0000005 -sentence=Enables Direct Memory Access Transfers. -paragraph=This library allows use of Direct Memory Access (DMA) for transfer between memory locations, to and from peripherals. -category=Uncategorized -architectures=stm32 diff --git a/libraries/DMA/src/DMATransfer.cpp b/libraries/DMA/src/DMATransfer.cpp deleted file mode 100644 index 18bffe070a..0000000000 --- a/libraries/DMA/src/DMATransfer.cpp +++ /dev/null @@ -1,120 +0,0 @@ -#include -#include - -/** - * @brief Prepares for DMA Transfer by enabling clocks - * and storing the settings in the slots - * @param settings : dma transfer settings - * @retval None - */ -void DMATransferClass::prepare(DMA_HandleTypeDef *settings) -{ - if (!_prepared) { - // TODO - figure out which DMA to enable the clock for. - #ifdef DMA1_BASE - __HAL_RCC_DMA1_CLK_ENABLE(); - #endif - #ifdef DMA2_BASE - __HAL_RCC_DMA2_CLK_ENABLE(); - #endif - memcpy(&_dma, settings, sizeof(DMA_HandleTypeDef)); - /* - _transfer_settings.dma_settings.Init.Direction = _transfer_settings.transfer_direction; - _transfer_settings.dma_settings.Init.PeriphInc = DMA_PINC_DISABLE; - _transfer_settings.dma_settings.Init.MemInc = DMA_MINC_DISABLE; - _transfer_settings.dma_settings.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; - _transfer_settings.dma_settings.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; - _transfer_settings.dma_settings.Init.Mode = _transfer_settings.circular ? DMA_CIRCULAR : DMA_NORMAL; - _transfer_settings.dma_settings.Init.Priority = DMA_PRIORITY_VERY_HIGH; - _transfer_settings.dma_settings.Instance = _transfer_settings.channel_stream; - // TODO - intialize the callbacks. - */ - - // Perform HAL Initialization first. - HAL_DMA_Init(&_dma); - _dma.XferCpltCallback = settings->XferCpltCallback; - _dma.XferHalfCpltCallback = settings->XferHalfCpltCallback; - _dma.XferErrorCallback = settings->XferErrorCallback; - _dma.XferAbortCallback = settings->XferAbortCallback; - - // Call dma prepare - prepare_dma(&_dma); - - _prepared = true; - } -} - -/** - * @brief Begin the DMA transfer - * @retval None - */ -void DMATransferClass::begin(uint32_t source, uint32_t destination, int bytes_to_transfer, bool use_interrupt) -{ - // Make sure we're set to initialize - this->end(); - - if (!_prepared) { - // call dma prepare - prepare_dma(&_dma); - } - - /** - * @brief Clear the DMA Stream pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Transfer complete flag. - * @arg DMA_FLAG_HTIFx: Half transfer complete flag. - * @arg DMA_FLAG_TEIFx: Transfer error flag. - * @arg DMA_FLAG_DMEIFx: Direct mode error flag. - * @arg DMA_FLAG_FEIFx: FIFO error flag. - * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. - * @retval None - */ - - // Reset flags so it starts over - __HAL_DMA_CLEAR_FLAG(&_dma, __HAL_DMA_GET_TC_FLAG_INDEX(&_dma)); - __HAL_DMA_CLEAR_FLAG(&_dma, __HAL_DMA_GET_HT_FLAG_INDEX(&_dma)); - __HAL_DMA_CLEAR_FLAG(&_dma, __HAL_DMA_GET_TE_FLAG_INDEX(&_dma)); - - #if defined(STM32F2xx) || #defined(STM32F4xx) || #defined(STM32F7xx) - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); - #endif - - // Set size to transfer - - #if defined(__HAL_DMA_SET_COUNTER) - __HAL_DMA_SET_COUNTER(&_dma, bytes_to_transfer); - #else - _dma.Instance->CNDTR = bytes_to_transfer; - #endif - - // and enable it - __HAL_DMA_ENABLE(&_dma); - - if (use_interrupt) { - IRQn_Type interrupt_number = get_dma_interrupt(_dma.Instance); - HAL_NVIC_SetPriority(interrupt_number, 0, 0); - HAL_NVIC_EnableIRQ(interrupt_number); - HAL_DMA_Start_IT(&_dma, source, destination, bytes_to_transfer); - } - else { - HAL_DMA_Start(&_dma, source, destination, bytes_to_transfer); - } -} - -/** - * @brief End the DMA transfer - * @retval None - */ -void DMATransferClass::end() -{ - - __HAL_DMA_DISABLE(&_dma); - - if (_prepared) { - end_dma(&_dma); - _prepared = false; - } -} diff --git a/libraries/DMA/src/DMATransfer.h b/libraries/DMA/src/DMATransfer.h deleted file mode 100644 index 58e0adfa87..0000000000 --- a/libraries/DMA/src/DMATransfer.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __DMATRANSFER_H__ -#define __DMATRANSFER_H__ - -#include "Arduino.h" - -typedef struct dmatransfer_s dmatransfer_t; - -#if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) -typedef DMA_Stream_TypeDef DMA_CS_Selection; -#else -typedef DMA_Channel_TypeDef DMA_CS_Selection; -#endif - -typedef class DMATransferClass { - - public: - /* - DMATransferClass(uint32_t transfer_direction, boolean circular, uint32_t source, uint32_t destination){ - this->dma.Init. - }*/ - - void prepare(DMA_HandleTypeDef *settings); - void begin(uint32_t source, uint32_t destination, int bytes_to_transfer, bool use_interrupt = false); - void end(); - private: - bool _prepared; - DMA_HandleTypeDef _dma; -} DMATransfer; - - -#endif /* __DMATRANSFER_H__ */ From 6804f8eca50575543ae0071e64b27358696af348 Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Mon, 9 Dec 2019 21:42:26 -0800 Subject: [PATCH 13/18] Ran astyle.py. --- cores/arduino/stm32/dma.c | 418 +++++++++++++++++++------------------- cores/arduino/stm32/dma.h | 6 +- 2 files changed, 212 insertions(+), 212 deletions(-) diff --git a/cores/arduino/stm32/dma.c b/cores/arduino/stm32/dma.c index b74c64f5ef..d2115c1fa8 100644 --- a/cores/arduino/stm32/dma.c +++ b/cores/arduino/stm32/dma.c @@ -45,99 +45,99 @@ extern "C" { typedef enum { #ifdef DMA1_Channel1 - DMA1_CHANNEL1_INDEX, + DMA1_CHANNEL1_INDEX, #endif #ifdef DMA1_Channel2 - DMA1_CHANNEL2_INDEX, + DMA1_CHANNEL2_INDEX, #endif #ifdef DMA1_Channel3 - DMA1_CHANNEL3_INDEX, + DMA1_CHANNEL3_INDEX, #endif #ifdef DMA1_Channel4 - DMA1_CHANNEL4_INDEX, + DMA1_CHANNEL4_INDEX, #endif #ifdef DMA1_Channel5 - DMA1_CHANNEL5_INDEX, + DMA1_CHANNEL5_INDEX, #endif #ifdef DMA1_Channel6 - DMA1_CHANNEL6_INDEX, + DMA1_CHANNEL6_INDEX, #endif #ifdef DMA1_Channel7 - DMA1_CHANNEL7_INDEX, + DMA1_CHANNEL7_INDEX, #endif #ifdef DMA2_Channel1 - DMA2_CHANNEL1_INDEX, + DMA2_CHANNEL1_INDEX, #endif #ifdef DMA2_Channel2 - DMA2_CHANNEL2_INDEX, + DMA2_CHANNEL2_INDEX, #endif #ifdef DMA2_Channel3 - DMA2_CHANNEL3_INDEX, + DMA2_CHANNEL3_INDEX, #endif #ifdef DMA2_Channel4 - DMA2_CHANNEL4_INDEX, + DMA2_CHANNEL4_INDEX, #endif #ifdef DMA2_Channel5 - DMA2_CHANNEL5_INDEX, + DMA2_CHANNEL5_INDEX, #endif #ifdef DMA2_Channel6 - DMA2_CHANNEL6_INDEX, + DMA2_CHANNEL6_INDEX, #endif #ifdef DMA2_Channel7 - DMA2_CHANNEL7_INDEX, + DMA2_CHANNEL7_INDEX, #endif #ifdef DMA2_Channel8 - DMA2_CHANNEL8_INDEX, + DMA2_CHANNEL8_INDEX, #endif #ifdef DMA1_Stream0 - DMA1_STREAM0_INDEX, + DMA1_STREAM0_INDEX, #endif #ifdef DMA1_Stream1 - DMA1_STREAM1_INDEX, + DMA1_STREAM1_INDEX, #endif #ifdef DMA1_Stream2 - DMA1_STREAM2_INDEX, + DMA1_STREAM2_INDEX, #endif #ifdef DMA1_Stream3 - DMA1_STREAM3_INDEX, + DMA1_STREAM3_INDEX, #endif #ifdef DMA1_Stream4 - DMA1_STREAM4_INDEX, + DMA1_STREAM4_INDEX, #endif #ifdef DMA1_Stream5 - DMA1_STREAM5_INDEX, + DMA1_STREAM5_INDEX, #endif #ifdef DMA1_Stream6 - DMA1_STREAM6_INDEX, + DMA1_STREAM6_INDEX, #endif #ifdef DMA1_Stream7 - DMA1_STREAM7_INDEX, + DMA1_STREAM7_INDEX, #endif #ifdef DMA2_Stream0 - DMA2_STREAM0_INDEX, + DMA2_STREAM0_INDEX, #endif #ifdef DMA2_Stream1 - DMA2_STREAM1_INDEX, + DMA2_STREAM1_INDEX, #endif #ifdef DMA2_Stream2 - DMA2_STREAM2_INDEX, + DMA2_STREAM2_INDEX, #endif #ifdef DMA2_Stream3 - DMA2_STREAM3_INDEX, + DMA2_STREAM3_INDEX, #endif #ifdef DMA2_Stream4 - DMA2_STREAM4_INDEX, + DMA2_STREAM4_INDEX, #endif #ifdef DMA2_Stream5 - DMA2_STREAM5_INDEX, + DMA2_STREAM5_INDEX, #endif #ifdef DMA2_Stream6 - DMA2_STREAM6_INDEX, + DMA2_STREAM6_INDEX, #endif #ifdef DMA2_Stream7 - DMA2_STREAM7_INDEX, + DMA2_STREAM7_INDEX, #endif - DMA_CHANNEL_NUM + DMA_CHANNEL_NUM } dma_index_t; #define NC (dma_index_t)-1 @@ -151,140 +151,140 @@ static DMA_HandleTypeDef *dma_handles[DMA_CHANNEL_NUM] = {NULL}; */ static dma_index_t get_dma_index( #if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) - DMA_Stream_TypeDef + DMA_Stream_TypeDef #else - DMA_Channel_TypeDef + DMA_Channel_TypeDef #endif - *instance) + *instance) { - switch ((uint32_t)instance) { + switch ((uint32_t)instance) { #ifdef DMA1_Channel1 case (uint32_t)DMA1_Channel1: - return DMA1_CHANNEL1_INDEX; + return DMA1_CHANNEL1_INDEX; #endif #ifdef DMA1_Channel2 case (uint32_t)DMA1_Channel2: - return DMA1_CHANNEL2_INDEX; + return DMA1_CHANNEL2_INDEX; #endif #ifdef DMA1_Channel3 case (uint32_t)DMA1_Channel3: - return DMA1_CHANNEL3_INDEX; + return DMA1_CHANNEL3_INDEX; #endif #ifdef DMA1_Channel4 case (uint32_t)DMA1_Channel4: - return DMA1_CHANNEL4_INDEX; + return DMA1_CHANNEL4_INDEX; #endif #ifdef DMA1_Channel5 case (uint32_t)DMA1_Channel5: - return DMA1_CHANNEL5_INDEX; + return DMA1_CHANNEL5_INDEX; #endif #ifdef DMA1_Channel6 case (uint32_t)DMA1_Channel6: - return DMA1_CHANNEL6_INDEX; + return DMA1_CHANNEL6_INDEX; #endif #ifdef DMA1_Channel7 case (uint32_t)DMA1_Channel7: - return DMA1_CHANNEL7_INDEX; + return DMA1_CHANNEL7_INDEX; #endif #ifdef DMA2_Channel1 case (uint32_t)DMA2_Channel1: - return DMA2_CHANNEL1_INDEX; + return DMA2_CHANNEL1_INDEX; #endif #ifdef DMA2_Channel2 case (uint32_t)DMA2_Channel2: - return DMA2_CHANNEL2_INDEX; + return DMA2_CHANNEL2_INDEX; #endif #ifdef DMA2_Channel3 case (uint32_t)DMA2_Channel3: - return DMA2_CHANNEL3_INDEX; + return DMA2_CHANNEL3_INDEX; #endif #ifdef DMA2_Channel4 case (uint32_t)DMA2_Channel4: - return DMA2_CHANNEL4_INDEX; + return DMA2_CHANNEL4_INDEX; #endif #ifdef DMA2_Channel5 case (uint32_t)DMA2_Channel5: - return DMA2_CHANNEL5_INDEX; + return DMA2_CHANNEL5_INDEX; #endif #ifdef DMA2_Channel6 case (uint32_t)DMA2_Channel6: - return DMA2_CHANNEL6_INDEX; + return DMA2_CHANNEL6_INDEX; #endif #ifdef DMA2_Channel7 case (uint32_t)DMA2_Channel7: - return DMA2_CHANNEL7_INDEX; + return DMA2_CHANNEL7_INDEX; #endif #ifdef DMA2_Channel8 case (uint32_t)DMA2_Channel8: - return DMA2_CHANNEL8_INDEX; + return DMA2_CHANNEL8_INDEX; #endif #ifdef DMA1_Stream0 case (uint32_t)DMA1_Stream0: - return DMA1_STREAM0_INDEX; + return DMA1_STREAM0_INDEX; #endif #ifdef DMA1_Stream1 case (uint32_t)DMA1_Stream1: - return DMA1_STREAM1_INDEX; + return DMA1_STREAM1_INDEX; #endif #ifdef DMA1_Stream2 case (uint32_t)DMA1_Stream2: - return DMA1_STREAM2_INDEX; + return DMA1_STREAM2_INDEX; #endif #ifdef DMA1_Stream3 case (uint32_t)DMA1_Stream3: - return DMA1_STREAM3_INDEX; + return DMA1_STREAM3_INDEX; #endif #ifdef DMA1_Stream4 case (uint32_t)DMA1_Stream4: - return DMA1_STREAM4_INDEX; + return DMA1_STREAM4_INDEX; #endif #ifdef DMA1_Stream5 case (uint32_t)DMA1_Stream5: - return DMA1_STREAM5_INDEX; + return DMA1_STREAM5_INDEX; #endif #ifdef DMA1_Stream6 case (uint32_t)DMA1_Stream6: - return DMA1_STREAM6_INDEX; + return DMA1_STREAM6_INDEX; #endif #ifdef DMA1_Stream7 case (uint32_t)DMA1_Stream7: - return DMA1_STREAM7_INDEX; + return DMA1_STREAM7_INDEX; #endif #ifdef DMA2_Stream0 case (uint32_t)DMA2_Stream0: - return DMA2_STREAM0_INDEX; + return DMA2_STREAM0_INDEX; #endif #ifdef DMA2_Stream1 case (uint32_t)DMA2_Stream1: - return DMA2_STREAM1_INDEX; + return DMA2_STREAM1_INDEX; #endif #ifdef DMA2_Stream2 case (uint32_t)DMA2_Stream2: - return DMA2_STREAM2_INDEX; + return DMA2_STREAM2_INDEX; #endif #ifdef DMA2_Stream3 case (uint32_t)DMA2_Stream3: - return DMA2_STREAM3_INDEX; + return DMA2_STREAM3_INDEX; #endif #ifdef DMA2_Stream4 case (uint32_t)DMA2_Stream4: - return DMA2_STREAM4_INDEX; + return DMA2_STREAM4_INDEX; #endif #ifdef DMA2_Stream5 case (uint32_t)DMA2_Stream5: - return DMA2_STREAM5_INDEX; + return DMA2_STREAM5_INDEX; #endif #ifdef DMA2_Stream6 case (uint32_t)DMA2_Stream6: - return DMA2_STREAM6_INDEX; + return DMA2_STREAM6_INDEX; #endif #ifdef DMA2_Stream7 case (uint32_t)DMA2_Stream7: - return DMA2_STREAM7_INDEX; + return DMA2_STREAM7_INDEX; #endif default: - return NC; - } + return NC; + } } /** @@ -294,140 +294,140 @@ static dma_index_t get_dma_index( */ IRQn_Type get_dma_interrupt( #if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) - DMA_Stream_TypeDef + DMA_Stream_TypeDef #else - DMA_Channel_TypeDef + DMA_Channel_TypeDef #endif - *instance) + *instance) { - switch ((uint32_t)instance) { + switch ((uint32_t)instance) { #ifdef DMA1_Channel1 case (uint32_t)DMA1_Channel1: - return DMA1_Channel1_IRQn; + return DMA1_Channel1_IRQn; #endif #ifdef DMA1_Channel2 case (uint32_t)DMA1_Channel2: - return DMA1_Channel2_IRQn; + return DMA1_Channel2_IRQn; #endif #ifdef DMA1_Channel3 case (uint32_t)DMA1_Channel3: - return DMA1_Channel3_IRQn; + return DMA1_Channel3_IRQn; #endif #ifdef DMA1_Channel4 case (uint32_t)DMA1_Channel4: - return DMA1_Channel4_IRQn; + return DMA1_Channel4_IRQn; #endif #ifdef DMA1_Channel5 case (uint32_t)DMA1_Channel5: - return DMA1_Channel5_IRQn; + return DMA1_Channel5_IRQn; #endif #ifdef DMA1_Channel6 case (uint32_t)DMA1_Channel6: - return DMA1_Channel6_IRQn; + return DMA1_Channel6_IRQn; #endif #ifdef DMA1_Channel7 case (uint32_t)DMA1_Channel7: - return DMA1_Channel7_IRQn; + return DMA1_Channel7_IRQn; #endif #ifdef DMA2_Channel1 case (uint32_t)DMA2_Channel1: - return DMA2_Channel1_IRQn; + return DMA2_Channel1_IRQn; #endif #ifdef DMA2_Channel2 case (uint32_t)DMA2_Channel2: - return DMA2_Channel2_IRQn; + return DMA2_Channel2_IRQn; #endif #ifdef DMA2_Channel3 case (uint32_t)DMA2_Channel3: - return DMA2_Channel3_IRQn; + return DMA2_Channel3_IRQn; #endif #ifdef DMA2_Channel4 case (uint32_t)DMA2_Channel4: - return DMA2_Channel4_IRQn; + return DMA2_Channel4_IRQn; #endif #ifdef DMA2_Channel5 case (uint32_t)DMA2_Channel5: - return DMA2_Channel5_IRQn; + return DMA2_Channel5_IRQn; #endif #ifdef DMA2_Channel6 case (uint32_t)DMA2_Channel6: - return DMA2_Channel6_IRQn; + return DMA2_Channel6_IRQn; #endif #ifdef DMA2_Channel7 case (uint32_t)DMA2_Channel7: - return DMA2_Channel7_IRQn; + return DMA2_Channel7_IRQn; #endif #ifdef DMA2_Channel8 case (uint32_t)DMA2_Channel8: - return DMA2_Channel8_IRQn; + return DMA2_Channel8_IRQn; #endif #ifdef DMA1_Stream0 case (uint32_t)DMA1_Stream0: - return DMA1_Stream0_IRQn; + return DMA1_Stream0_IRQn; #endif #ifdef DMA1_Stream1 case (uint32_t)DMA1_Stream1: - return DMA1_Stream1_IRQn; + return DMA1_Stream1_IRQn; #endif #ifdef DMA1_Stream2 case (uint32_t)DMA1_Stream2: - return DMA1_Stream2_IRQn; + return DMA1_Stream2_IRQn; #endif #ifdef DMA1_Stream3 case (uint32_t)DMA1_Stream3: - return DMA1_Stream3_IRQn; + return DMA1_Stream3_IRQn; #endif #ifdef DMA1_Stream4 case (uint32_t)DMA1_Stream4: - return DMA1_Stream4_IRQn; + return DMA1_Stream4_IRQn; #endif #ifdef DMA1_Stream5 case (uint32_t)DMA1_Stream5: - return DMA1_Stream5_IRQn; + return DMA1_Stream5_IRQn; #endif #ifdef DMA1_Stream6 case (uint32_t)DMA1_Stream6: - return DMA1_Stream6_IRQn; + return DMA1_Stream6_IRQn; #endif #ifdef DMA1_Stream7 case (uint32_t)DMA1_Stream7: - return DMA1_Stream7_IRQn; + return DMA1_Stream7_IRQn; #endif #ifdef DMA2_Stream0 case (uint32_t)DMA2_Stream0: - return DMA2_Stream0_IRQn; + return DMA2_Stream0_IRQn; #endif #ifdef DMA2_Stream1 case (uint32_t)DMA2_Stream1: - return DMA2_Stream1_IRQn; + return DMA2_Stream1_IRQn; #endif #ifdef DMA2_Stream2 case (uint32_t)DMA2_Stream2: - return DMA2_Stream2_IRQn; + return DMA2_Stream2_IRQn; #endif #ifdef DMA2_Stream3 case (uint32_t)DMA2_Stream3: - return DMA2_Stream3_IRQn; + return DMA2_Stream3_IRQn; #endif #ifdef DMA2_Stream4 case (uint32_t)DMA2_Stream4: - return DMA2_Stream4_IRQn; + return DMA2_Stream4_IRQn; #endif #ifdef DMA2_Stream5 case (uint32_t)DMA2_Stream5: - return DMA2_Stream5_IRQn; + return DMA2_Stream5_IRQn; #endif #ifdef DMA2_Stream6 case (uint32_t)DMA2_Stream6: - return DMA2_Stream6_IRQn; + return DMA2_Stream6_IRQn; #endif #ifdef DMA2_Stream7 case (uint32_t)DMA2_Stream7: - return DMA2_Stream7_IRQn; + return DMA2_Stream7_IRQn; #endif default: - return NC; - } + return NC; + } } /** @@ -437,11 +437,11 @@ IRQn_Type get_dma_interrupt( */ void prepare_dma(DMA_HandleTypeDef *dma_handle) { - dma_index_t dma_index = get_dma_index(dma_handle->Instance); - if (dma_index == NC) { - return; - } - dma_handles[dma_index] = dma_handle; + dma_index_t dma_index = get_dma_index(dma_handle->Instance); + if (dma_index == NC) { + return; + } + dma_handles[dma_index] = dma_handle; } /** @@ -451,11 +451,11 @@ void prepare_dma(DMA_HandleTypeDef *dma_handle) */ void end_dma(DMA_HandleTypeDef *dma_handle) { - dma_index_t dma_index = get_dma_index(dma_handle->Instance); - if (dma_index == NC) { - return; - } - dma_handles[dma_index] = NULL; + dma_index_t dma_index = get_dma_index(dma_handle->Instance); + if (dma_index == NC) { + return; + } + dma_handles[dma_index] = NULL; } #ifdef DMA1_Channel1 @@ -466,9 +466,9 @@ void end_dma(DMA_HandleTypeDef *dma_handle) */ void DMA1_Channel1_IRQHandler() { - if (dma_handles[DMA1_CHANNEL1_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL1_INDEX]); - } + if (dma_handles[DMA1_CHANNEL1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL1_INDEX]); + } } #endif @@ -480,9 +480,9 @@ void DMA1_Channel1_IRQHandler() */ void DMA1_Channel2_IRQHandler() { - if (dma_handles[DMA1_CHANNEL2_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL2_INDEX]); - } + if (dma_handles[DMA1_CHANNEL2_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL2_INDEX]); + } } #endif @@ -494,9 +494,9 @@ void DMA1_Channel2_IRQHandler() */ void DMA1_Channel3_IRQHandler() { - if (dma_handles[DMA1_CHANNEL3_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL3_INDEX]); - } + if (dma_handles[DMA1_CHANNEL3_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL3_INDEX]); + } } #endif @@ -508,9 +508,9 @@ void DMA1_Channel3_IRQHandler() */ void DMA1_Channel4_IRQHandler() { - if (dma_handles[DMA1_CHANNEL4_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL4_INDEX]); - } + if (dma_handles[DMA1_CHANNEL4_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL4_INDEX]); + } } #endif @@ -522,9 +522,9 @@ void DMA1_Channel4_IRQHandler() */ void DMA1_Channel5_IRQHandler() { - if (dma_handles[DMA1_CHANNEL5_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL5_INDEX]); - } + if (dma_handles[DMA1_CHANNEL5_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL5_INDEX]); + } } #endif @@ -535,9 +535,9 @@ void DMA1_Channel5_IRQHandler() */ void DMA1_Channel6_IRQHandler() { - if (dma_handles[DMA1_CHANNEL6_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL6_INDEX]); - } + if (dma_handles[DMA1_CHANNEL6_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL6_INDEX]); + } } #endif @@ -549,9 +549,9 @@ void DMA1_Channel6_IRQHandler() */ void DMA1_Channel7_IRQHandler() { - if (dma_handles[DMA1_CHANNEL7_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL7_INDEX]); - } + if (dma_handles[DMA1_CHANNEL7_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL7_INDEX]); + } } #endif @@ -563,9 +563,9 @@ void DMA1_Channel7_IRQHandler() */ void DMA2_Channel1_IRQHandler() { - if (dma_handles[DMA2_CHANNEL1_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL1_INDEX]); - } + if (dma_handles[DMA2_CHANNEL1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL1_INDEX]); + } } #endif @@ -577,9 +577,9 @@ void DMA2_Channel1_IRQHandler() */ void DMA2_Channel2_IRQHandler() { - if (dma_handles[DMA2_CHANNEL2_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL2_INDEX]); - } + if (dma_handles[DMA2_CHANNEL2_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL2_INDEX]); + } } #endif @@ -591,9 +591,9 @@ void DMA2_Channel2_IRQHandler() */ void DMA2_Channel3_IRQHandler() { - if (dma_handles[DMA2_CHANNEL3_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL3_INDEX]); - } + if (dma_handles[DMA2_CHANNEL3_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL3_INDEX]); + } } #endif @@ -605,9 +605,9 @@ void DMA2_Channel3_IRQHandler() */ void DMA2_Channel4_IRQHandler() { - if (dma_handles[DMA2_CHANNEL4_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL4_INDEX]); - } + if (dma_handles[DMA2_CHANNEL4_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL4_INDEX]); + } } #endif @@ -619,9 +619,9 @@ void DMA2_Channel4_IRQHandler() */ void DMA2_Channel5_IRQHandler() { - if (dma_handles[DMA2_CHANNEL5_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL5_INDEX]); - } + if (dma_handles[DMA2_CHANNEL5_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL5_INDEX]); + } } #endif @@ -633,9 +633,9 @@ void DMA2_Channel5_IRQHandler() */ void DMA2_Channel6_IRQHandler() { - if (dma_handles[DMA2_CHANNEL6_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL6_INDEX]); - } + if (dma_handles[DMA2_CHANNEL6_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL6_INDEX]); + } } #endif @@ -647,9 +647,9 @@ void DMA2_Channel6_IRQHandler() */ void DMA2_Channel7_IRQHandler() { - if (dma_handles[DMA2_CHANNEL7_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL7_INDEX]); - } + if (dma_handles[DMA2_CHANNEL7_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL7_INDEX]); + } } #endif @@ -661,153 +661,153 @@ void DMA2_Channel7_IRQHandler() */ void DMA2_Channel8_IRQHandler() { - if (dma_handles[DMA2_CHANNEL8_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL8_INDEX]); - } + if (dma_handles[DMA2_CHANNEL8_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL8_INDEX]); + } } #endif #ifdef DMA1_Stream0 void DMA1_Stream0_IRQHandler() { - if (dma_handles[DMA1_STREAM0_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM0_INDEX]); - } + if (dma_handles[DMA1_STREAM0_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM0_INDEX]); + } } #endif #ifdef DMA1_Stream1 void DMA1_Stream1_IRQHandler() { - if (dma_handles[DMA1_STREAM1_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM1_INDEX]); - } + if (dma_handles[DMA1_STREAM1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM1_INDEX]); + } } #endif #ifdef DMA1_Stream2 void DMA1_Stream2_IRQHandler() { - if (dma_handles[DMA1_STREAM2_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM2_INDEX]); - } + if (dma_handles[DMA1_STREAM2_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM2_INDEX]); + } } #endif #ifdef DMA1_Stream3 void DMA1_Stream3_IRQHandler() { - if (dma_handles[DMA1_STREAM3_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM3_INDEX]); - } + if (dma_handles[DMA1_STREAM3_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM3_INDEX]); + } } #endif #ifdef DMA1_Stream4 void DMA1_Stream4_IRQHandler() { - if (dma_handles[DMA1_STREAM4_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM4_INDEX]); - } + if (dma_handles[DMA1_STREAM4_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM4_INDEX]); + } } #endif #ifdef DMA1_Stream5 void DMA1_Stream5_IRQHandler() { - if (dma_handles[DMA1_STREAM5_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM5_INDEX]); - } + if (dma_handles[DMA1_STREAM5_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM5_INDEX]); + } } #endif #ifdef DMA1_Stream6 void DMA1_Stream6_IRQHandler() { - if (dma_handles[DMA1_STREAM6_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM6_INDEX]); - } + if (dma_handles[DMA1_STREAM6_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM6_INDEX]); + } } #endif #ifdef DMA1_Stream7 void DMA1_Stream7_IRQHandler() { - if (dma_handles[DMA1_STREAM7_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM7_INDEX]); - } + if (dma_handles[DMA1_STREAM7_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM7_INDEX]); + } } #endif #ifdef DMA2_Stream0 void DMA2_Stream0_IRQHandler() { - if (dma_handles[DMA2_STREAM0_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM0_INDEX]); - } + if (dma_handles[DMA2_STREAM0_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM0_INDEX]); + } } #endif #ifdef DMA2_Stream1 void DMA2_Stream1_IRQHandler() { - if (dma_handles[DMA2_STREAM1_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM1_INDEX]); - } + if (dma_handles[DMA2_STREAM1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM1_INDEX]); + } } #endif #ifdef DMA2_Stream2 void DMA2_Stream2_IRQHandler() { - if (dma_handles[DMA2_STREAM2_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM2_INDEX]); - } + if (dma_handles[DMA2_STREAM2_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM2_INDEX]); + } } #endif #ifdef DMA2_Stream3 void DMA2_Stream3_IRQHandler() { - if (dma_handles[DMA2_STREAM3_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM3_INDEX]); - } + if (dma_handles[DMA2_STREAM3_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM3_INDEX]); + } } #endif #ifdef DMA2_Stream4 void DMA2_Stream4_IRQHandler() { - if (dma_handles[DMA2_STREAM4_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM4_INDEX]); - } + if (dma_handles[DMA2_STREAM4_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM4_INDEX]); + } } #endif #ifdef DMA2_Stream5 void DMA2_Stream5_IRQHandler() { - if (dma_handles[DMA2_STREAM5_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM5_INDEX]); - } + if (dma_handles[DMA2_STREAM5_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM5_INDEX]); + } } #endif #ifdef DMA2_Stream6 void DMA2_Stream6_IRQHandler() { - if (dma_handles[DMA2_STREAM6_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM6_INDEX]); - } + if (dma_handles[DMA2_STREAM6_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM6_INDEX]); + } } #endif #ifdef DMA2_Stream7 void DMA2_Stream7_IRQHandler() { - if (dma_handles[DMA2_STREAM7_INDEX] != NULL) { - HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM7_INDEX]); - } + if (dma_handles[DMA2_STREAM7_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM7_INDEX]); + } } #endif diff --git a/cores/arduino/stm32/dma.h b/cores/arduino/stm32/dma.h index 596897ac08..0909dd60ef 100644 --- a/cores/arduino/stm32/dma.h +++ b/cores/arduino/stm32/dma.h @@ -53,11 +53,11 @@ extern "C" { */ IRQn_Type get_dma_interrupt( #if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) - DMA_Stream_TypeDef + DMA_Stream_TypeDef #else - DMA_Channel_TypeDef + DMA_Channel_TypeDef #endif - *instance); + *instance); /** * @brief This function will store the DMA handle in the appropriate slot From f5e6b7dcd44cb85d2b24c2390fd39e62c2636aff Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Wed, 11 Dec 2019 12:49:16 -0800 Subject: [PATCH 14/18] Move files to SRCWrapper Library. --- .../stm32 => libraries/SrcWrapper}/dma.c | 36 +++++++++++++++++++ .../stm32 => libraries/SrcWrapper}/dma.h | 13 ------- 2 files changed, 36 insertions(+), 13 deletions(-) rename {cores/arduino/stm32 => libraries/SrcWrapper}/dma.c (95%) rename {cores/arduino/stm32 => libraries/SrcWrapper}/dma.h (89%) diff --git a/cores/arduino/stm32/dma.c b/libraries/SrcWrapper/dma.c similarity index 95% rename from cores/arduino/stm32/dma.c rename to libraries/SrcWrapper/dma.c index d2115c1fa8..d1b045a6e1 100644 --- a/cores/arduino/stm32/dma.c +++ b/libraries/SrcWrapper/dma.c @@ -667,6 +667,42 @@ void DMA2_Channel8_IRQHandler() } #endif + +/* Combined handlers +DMA1_Ch2_3_DMA2_Ch1_2_IRQn +DMA1_Ch4_7_DMA2_Ch3_5_IRQn +DMA1_Channel2_3_IRQn +DMA1_Channel4_5_6_7_IRQn +DMA1_Channel4_5_IRQn +DMA2_Channel4_5_IRQn +*/ + +#if defined(DMA1_Channel2) && defined(DMA1_Channel3) && defined(DMA2_Channel1) && defined(DMA2_Channel2) +/** + * @brief DMA1 and DMA2 hander for channels 2,3 and 1,2 + * @param None + * @retval None + */ +void DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler() +{ + if (dma_handles[DMA1_CHANNEL2_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL2_INDEX]); + } + + if (dma_handles[DMA1_CHANNEL3_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL3_INDEX]); + } + + if (dma_handles[DMA2_CHANNEL1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL1_INDEX]); + } + + if (dma_handles[DMA2_CHANNEL1_INDEX] != NULL) { + HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL2_INDEX]); + } +} +#endif + #ifdef DMA1_Stream0 void DMA1_Stream0_IRQHandler() { diff --git a/cores/arduino/stm32/dma.h b/libraries/SrcWrapper/dma.h similarity index 89% rename from cores/arduino/stm32/dma.h rename to libraries/SrcWrapper/dma.h index 0909dd60ef..85d21d54f4 100644 --- a/cores/arduino/stm32/dma.h +++ b/libraries/SrcWrapper/dma.h @@ -46,19 +46,6 @@ extern "C" { #include -/** - * @brief This function will get the interrupt number for a DMA - * @param dma_handle : dma channel or strea - * @retval None - */ -IRQn_Type get_dma_interrupt( -#if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) - DMA_Stream_TypeDef -#else - DMA_Channel_TypeDef -#endif - *instance); - /** * @brief This function will store the DMA handle in the appropriate slot * @param dma_handle : dma handle From 8ab6ad944b913f313caaa10758c2b80c200f8f65 Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Wed, 11 Dec 2019 17:53:13 -0800 Subject: [PATCH 15/18] Astyle fixes. --- libraries/SrcWrapper/dma.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/libraries/SrcWrapper/dma.c b/libraries/SrcWrapper/dma.c index d1b045a6e1..036333b4cb 100644 --- a/libraries/SrcWrapper/dma.c +++ b/libraries/SrcWrapper/dma.c @@ -669,12 +669,12 @@ void DMA2_Channel8_IRQHandler() /* Combined handlers -DMA1_Ch2_3_DMA2_Ch1_2_IRQn -DMA1_Ch4_7_DMA2_Ch3_5_IRQn -DMA1_Channel2_3_IRQn -DMA1_Channel4_5_6_7_IRQn -DMA1_Channel4_5_IRQn -DMA2_Channel4_5_IRQn +DMA1_Ch2_3_DMA2_Ch1_2_IRQn +DMA1_Ch4_7_DMA2_Ch3_5_IRQn +DMA1_Channel2_3_IRQn +DMA1_Channel4_5_6_7_IRQn +DMA1_Channel4_5_IRQn +DMA2_Channel4_5_IRQn */ #if defined(DMA1_Channel2) && defined(DMA1_Channel3) && defined(DMA2_Channel1) && defined(DMA2_Channel2) From a89fb0f6d03caeb296c52945965cad947582174a Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Wed, 11 Dec 2019 18:02:32 -0800 Subject: [PATCH 16/18] Fix move location. --- libraries/SrcWrapper/{ => src/stm32}/dma.c | 0 libraries/SrcWrapper/{ => src/stm32}/dma.h | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename libraries/SrcWrapper/{ => src/stm32}/dma.c (100%) rename libraries/SrcWrapper/{ => src/stm32}/dma.h (100%) diff --git a/libraries/SrcWrapper/dma.c b/libraries/SrcWrapper/src/stm32/dma.c similarity index 100% rename from libraries/SrcWrapper/dma.c rename to libraries/SrcWrapper/src/stm32/dma.c diff --git a/libraries/SrcWrapper/dma.h b/libraries/SrcWrapper/src/stm32/dma.h similarity index 100% rename from libraries/SrcWrapper/dma.h rename to libraries/SrcWrapper/src/stm32/dma.h From df8e3edb2e58484c9e8a72a041df080f3d2ebdb0 Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Sat, 14 Dec 2019 09:44:03 -0800 Subject: [PATCH 17/18] Only the .c file needs to be in the library. --- {libraries/SrcWrapper/src => cores/arduino}/stm32/dma.h | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename {libraries/SrcWrapper/src => cores/arduino}/stm32/dma.h (100%) diff --git a/libraries/SrcWrapper/src/stm32/dma.h b/cores/arduino/stm32/dma.h similarity index 100% rename from libraries/SrcWrapper/src/stm32/dma.h rename to cores/arduino/stm32/dma.h From 3cabef85fdb8d2c9571d168dadab6be309ca9317 Mon Sep 17 00:00:00 2001 From: xC0000005 <32139633+xC0000005@users.noreply.github.com> Date: Sat, 14 Dec 2019 13:56:00 -0800 Subject: [PATCH 18/18] Remove IRQn function since DMA class isn't part of PR. --- libraries/SrcWrapper/src/stm32/dma.c | 143 --------------------------- 1 file changed, 143 deletions(-) diff --git a/libraries/SrcWrapper/src/stm32/dma.c b/libraries/SrcWrapper/src/stm32/dma.c index 036333b4cb..0b3aeb5a16 100644 --- a/libraries/SrcWrapper/src/stm32/dma.c +++ b/libraries/SrcWrapper/src/stm32/dma.c @@ -287,149 +287,6 @@ static dma_index_t get_dma_index( } } -/** - * @brief This function will get the interrupt number for a DMA - * @param dma_handle : dma channel or strea - * @retval None - */ -IRQn_Type get_dma_interrupt( -#if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) - DMA_Stream_TypeDef -#else - DMA_Channel_TypeDef -#endif - *instance) -{ - switch ((uint32_t)instance) { -#ifdef DMA1_Channel1 - case (uint32_t)DMA1_Channel1: - return DMA1_Channel1_IRQn; -#endif -#ifdef DMA1_Channel2 - case (uint32_t)DMA1_Channel2: - return DMA1_Channel2_IRQn; -#endif -#ifdef DMA1_Channel3 - case (uint32_t)DMA1_Channel3: - return DMA1_Channel3_IRQn; -#endif -#ifdef DMA1_Channel4 - case (uint32_t)DMA1_Channel4: - return DMA1_Channel4_IRQn; -#endif -#ifdef DMA1_Channel5 - case (uint32_t)DMA1_Channel5: - return DMA1_Channel5_IRQn; -#endif -#ifdef DMA1_Channel6 - case (uint32_t)DMA1_Channel6: - return DMA1_Channel6_IRQn; -#endif -#ifdef DMA1_Channel7 - case (uint32_t)DMA1_Channel7: - return DMA1_Channel7_IRQn; -#endif -#ifdef DMA2_Channel1 - case (uint32_t)DMA2_Channel1: - return DMA2_Channel1_IRQn; -#endif -#ifdef DMA2_Channel2 - case (uint32_t)DMA2_Channel2: - return DMA2_Channel2_IRQn; -#endif -#ifdef DMA2_Channel3 - case (uint32_t)DMA2_Channel3: - return DMA2_Channel3_IRQn; -#endif -#ifdef DMA2_Channel4 - case (uint32_t)DMA2_Channel4: - return DMA2_Channel4_IRQn; -#endif -#ifdef DMA2_Channel5 - case (uint32_t)DMA2_Channel5: - return DMA2_Channel5_IRQn; -#endif -#ifdef DMA2_Channel6 - case (uint32_t)DMA2_Channel6: - return DMA2_Channel6_IRQn; -#endif -#ifdef DMA2_Channel7 - case (uint32_t)DMA2_Channel7: - return DMA2_Channel7_IRQn; -#endif -#ifdef DMA2_Channel8 - case (uint32_t)DMA2_Channel8: - return DMA2_Channel8_IRQn; -#endif -#ifdef DMA1_Stream0 - case (uint32_t)DMA1_Stream0: - return DMA1_Stream0_IRQn; -#endif -#ifdef DMA1_Stream1 - case (uint32_t)DMA1_Stream1: - return DMA1_Stream1_IRQn; -#endif -#ifdef DMA1_Stream2 - case (uint32_t)DMA1_Stream2: - return DMA1_Stream2_IRQn; -#endif -#ifdef DMA1_Stream3 - case (uint32_t)DMA1_Stream3: - return DMA1_Stream3_IRQn; -#endif -#ifdef DMA1_Stream4 - case (uint32_t)DMA1_Stream4: - return DMA1_Stream4_IRQn; -#endif -#ifdef DMA1_Stream5 - case (uint32_t)DMA1_Stream5: - return DMA1_Stream5_IRQn; -#endif -#ifdef DMA1_Stream6 - case (uint32_t)DMA1_Stream6: - return DMA1_Stream6_IRQn; -#endif -#ifdef DMA1_Stream7 - case (uint32_t)DMA1_Stream7: - return DMA1_Stream7_IRQn; -#endif -#ifdef DMA2_Stream0 - case (uint32_t)DMA2_Stream0: - return DMA2_Stream0_IRQn; -#endif -#ifdef DMA2_Stream1 - case (uint32_t)DMA2_Stream1: - return DMA2_Stream1_IRQn; -#endif -#ifdef DMA2_Stream2 - case (uint32_t)DMA2_Stream2: - return DMA2_Stream2_IRQn; -#endif -#ifdef DMA2_Stream3 - case (uint32_t)DMA2_Stream3: - return DMA2_Stream3_IRQn; -#endif -#ifdef DMA2_Stream4 - case (uint32_t)DMA2_Stream4: - return DMA2_Stream4_IRQn; -#endif -#ifdef DMA2_Stream5 - case (uint32_t)DMA2_Stream5: - return DMA2_Stream5_IRQn; -#endif -#ifdef DMA2_Stream6 - case (uint32_t)DMA2_Stream6: - return DMA2_Stream6_IRQn; -#endif -#ifdef DMA2_Stream7 - case (uint32_t)DMA2_Stream7: - return DMA2_Stream7_IRQn; -#endif - default: - return NC; - } -} - /** * @brief This function will store the DMA handle in the appropriate slot * @param dma_handle : dma handle pFad - Phonifier reborn

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