fix single port ram code (#160)

ucbjrl · bqwer · web-flow · commit 37d7f752c568 · 2020-05-20T11:08:26.000-07:00
Co-authored-by: bqwer &lt;liventsev@gmail.com&gt;
diff --git a/doc/tutorial/tutorial-2.tex b/doc/tutorial/tutorial-2.tex
@@ -1339,10 +1339,10 @@ \subsection{Mem}
 \begin{scala}
 val ram1p = 
   Mem(UInt(width = 32), 1024, seqRead = true)
-val reg_raddr = Reg(UInt())
-when (wen) { ram1p(waddr) := wdata }
-.elsewhen (ren) { reg_raddr := raddr }
-val rdata = ram1p(reg_raddr)
+val reg_addr = Reg(UInt())
+when (wen) { ram1p(addr) := wdata }
+.elsewhen (ren) { reg_addr := addr }
+val rdata = ram1p(reg_addr)
 \end{scala}
 
 If the same \code{Mem} address is both written and sequentially read on the same clock
diff --git a/doc/tutorial/tutorial.tex b/doc/tutorial/tutorial.tex
@@ -1278,10 +1278,10 @@ \subsection{Mem}
 
 \begin{scala}
 val ram1p = Mem(1024, UInt(32.W))
-val reg_raddr = Reg(UInt())
-when (wen) { ram1p(waddr) := wdata }
-.elsewhen (ren) { reg_raddr := raddr }
-val rdata = ram1p(reg_raddr)
+val reg_addr = Reg(UInt())
+when (wen) { ram1p(addr) := wdata }
+.elsewhen (ren) { reg_addr := addr }
+val rdata = ram1p(reg_addr)
 \end{scala}
 
 If the same \code{Mem} address is both written and sequentially read on the same clock
