Initialize Reg()'s.

ucbjrl · ucbjrl · commit ff15687a8f1c · 2015-08-04T15:25:40.000-07:00
diff --git a/solutions/VecShiftRegisterSimple.scala b/solutions/VecShiftRegisterSimple.scala
@@ -7,7 +7,7 @@ class VecShiftRegisterSimple extends Module {
     val in  = UInt(INPUT,  8)
     val out = UInt(OUTPUT, 8)
   }
-  val delays = Vec.fill(4){ Reg(UInt(width = 8)) }
+  val delays = Vec.fill(4){ Reg(UInt(width = 8), init=UInt(0)) }
   delays(0) := io.in
   delays(1) := delays(0)
   delays(2) := delays(1)

Original file line number	Diff line number	Diff line change
`@@ -7,7 +7,7 @@ class VecShiftRegisterSimple extends Module {`
`7`	`7`	`val in = UInt(INPUT, 8)`
`8`	`8`	`val out = UInt(OUTPUT, 8)`
`9`	`9`	`}`
`10`		`- val delays = Vec.fill(4){ Reg(UInt(width = 8)) }`
	`10`	`+ val delays = Vec.fill(4){ Reg(UInt(width = 8), init=UInt(0)) }`
`11`	`11`	`delays(0) := io.in`
`12`	`12`	`delays(1) := delays(0)`
`13`	`13`	`delays(2) := delays(1)`