Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors
Bellas, Nikolaos
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https://hdl.handle.net/2142/81278
Description
Title
Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors
Author(s)
Bellas, Nikolaos
Issue Date
1999
Doctoral Committee Chair(s)
Ibrahim Hajj
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Date of Ingest
2015-09-25T20:10:22Z
Keyword(s)
Energy
Language
eng
Abstract
More specifically, we propose a technique that uses an additional mini cache located between the instruction cache (I-Cache) and the CPU core; the mini cache buffers instructions that are nested within loops and are continuously fetched from the I-Cache. This mechanism can create very substantial energy savings, since the I-Cache unit is one of the main power consumers in most of today's high-performance microprocessors. Results are reported for the SPEC95 benchmarks in the R-4400 processor which implements the MIPS2 instruction set architecture.
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