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Investigation of the Memory Operations in the 3D NAND Flash with More Realistic Geometry with Wavey Channel in the Tapered Channel Hole

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Abstract

Recent developments in 3D NAND flash memory technology have greatly enhanced memory capacity and integration density compared to 2D NAND, addressing the growing demand for high-performance storage in various fields. This study investigates the effects of wavey shape factor (WF) and taper angle on the programming characteristics of 3D NAND flash memory by a series of technology computer-aided design (TCAD) device simulations. Our analysis reveals that both WF and taper angle significantly impact the threshold voltage (VTH) and trapped charge in memory cells. Specifically, as the taper angle increases, the bottom memory cell experiences more pronounced variations in VTH and trapped charge due to a smaller channel radius and altered electric field distribution. This study also shows that larger taper angles affect the tunneling oxide region more significantly than the blocking oxide region, leading to greater performance variations. These investigations highlight the need for optimized design strategies to minimize performance non-uniformity and improve the reliability of next-generation NAND memory technologies.

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Acknowledgements

This research was supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT of Korea (MSIT) (Grants RS-2023-00258527 and RS-2024-00402495). The EDA tool was supported by the IC Design Education Center (IDEC), Korea.

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Authors and Affiliations

  1. Department of Electronic Engineering, Myongji University, Yongin-si, Gyeonggi-do, 17058, Republic of Korea

    Hyun-Seo Oh, Yun-Jae Oh, Hyeongjun So, Jueun Kim & Il Hwan Cho

  2. Department of Electronic and Electrical Engineering, Ewha Womans University, Seoul, 03760, Republic of Korea

    Soomin Kim, So Won Son & Seongjae Cho

  3. I-Nano FAB Center, Incheon National University, Incheon, 22012, Republic of Korea

    Tae Hun Kim

  4. Semiconductor Research Center, Samsung Electronics, Yongin-si, 17113, Gyeonggi-do, Republic of Korea

    Tae Hun Kim

  5. Department of Next Generation Semiconductor Convergence and Open Sharing System, Seoul National University, Seoul, 08826, Republic of Korea

    Daewoong Kang

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  1. Hyun-Seo Oh
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Correspondence to Seongjae Cho or Il Hwan Cho.

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Seongjae Cho, and Il Hwan Cho declare that we have no competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

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Oh, HS., Oh, YJ., So, H. et al. Investigation of the Memory Operations in the 3D NAND Flash with More Realistic Geometry with Wavey Channel in the Tapered Channel Hole. J. Electr. Eng. Technol. (2025). https://doi.org/10.1007/s42835-025-02171-z

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