Abstract
The papers presented in this combined topic consider issues related to the broad theme of computer architecture research. The program reflects the current emphasis of research on the exploitation of instruction-level parallelism and thread-level parallelism, with the papers presented covering several important aspects on both approaches: branch prediction, speculative multitheading, pipelining and superscalar architecture design, SIMD extensions, and dynamic scheduling issues in multithreaded architectures.
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© 2001 Springer-Verlag Berlin Heidelberg
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Ayguadé, E. et al. (2001). Instruction-Level Parallelism and Computer Architecture. In: Sakellariou, R., Gurd, J., Freeman, L., Keane, J. (eds) Euro-Par 2001 Parallel Processing. Euro-Par 2001. Lecture Notes in Computer Science, vol 2150. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44681-8_56
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DOI: https://doi.org/10.1007/3-540-44681-8_56
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