Imprecise Exceptions in Distributed Parallel Components

Abstract

Modern microprocessors have sacrificed the exactness of exceptions for improved performance long ago. This is a side effect of reordering instructions so that the microprocessor can execute instructions which were not to be executed due to an exception. By throwing more circuits at the problem, microprocessors are designed so that they are able to roll back to the instruction causing the exception. However, some microprocessors, like the HP Alpha, do not roll back and impose a paradigm of inaccurate exceptions. This decision can reduce circuit complexity and increase speed. We propose a similar method of handling exceptions in a component environment that achieves high performance by sacrificing exception accuracy when dealing with parallel Single Program Multiple Data (SPMD) components. The particular domain this design is intended for is high performance computing, which requires maximum resource use and efficiency. A performance-centric way to handle exceptions is explained as well as additional methodology to enforce exception strictness if required.

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