Scribd
Upload
376 views1 page

ASIC Question Paper

The document is a 3 page exam paper for an ASIC Design and Modelling course. It contains 8 questions split into two sections. The first section focuses on ASIC design flow, IC fabrication process, types of simulation including static timing analysis, clock tree synthesis, and design for test flow. The second section asks students to find a minimal test set to cover stuck at faults for a given circuit diagram.

Uploaded by

humtum_shri5736
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
376 views1 page

ASIC Question Paper

The document is a 3 page exam paper for an ASIC Design and Modelling course. It contains 8 questions split into two sections. The first section focuses on ASIC design flow, IC fabrication process, types of simulation including static timing analysis, clock tree synthesis, and design for test flow. The second section asks students to find a minimal test set to cover stuck at faults for a given circuit diagram.

Uploaded by

humtum_shri5736
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

Total No.

of Questions : 8]

[Total No. of Pages : 3

P1632

[3665]-575
M.E. (VLSI & Embedded System)
ASIC DESIGN AND MODELLING (2008 Course)

Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates : 1) Answer any 3 questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Assume suitable data, if necessary.

SECTION - I Q1) a) b) Q2) a) b) Q3) a) b) Draw and explain in detail the flow chart relating to ASIC design Flow? [12] Draw and explain simplified Fabrication Process of an IC chip layout?[6] What are different types of Simulation? Explain in detail Static Timing Analysis and how it differs from circuit and logic simulation. [12] How do you optimize Skew / Insertion delays in Clock tree synthesis?[6] Explain Step by Step process to be followed in Design for Test flow in ASIC? [6] find a minimal Test Set for the circuit to Show the coverage of various Stuck at faults for the circuit shown in Fig. 1. [10]

P.T.O.

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy