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AUGUST 2007 Number 8 Itcob4 (ISSN 1063-8210) : Special Section Papers

This document is the August 2007 issue of ITCOB4, a journal on system-level interconnect prediction. The issue contains a special section on this topic with 7 papers describing tools and methods for predicting and optimizing on-chip interconnect performance at the system level during the design process. There are also 2 regular papers on random number generation and repeater insertion for low-power VLSI circuits, as well as 2 transactions briefs on testing communication peripherals and code decompression unit design.

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Sudhakar Spartan
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55 views1 page

AUGUST 2007 Number 8 Itcob4 (ISSN 1063-8210) : Special Section Papers

This document is the August 2007 issue of ITCOB4, a journal on system-level interconnect prediction. The issue contains a special section on this topic with 7 papers describing tools and methods for predicting and optimizing on-chip interconnect performance at the system level during the design process. There are also 2 regular papers on random number generation and repeater insertion for low-power VLSI circuits, as well as 2 transactions briefs on testing communication peripherals and code decompression unit design.

Uploaded by

Sudhakar Spartan
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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AUGUST 2007

VOLUME 15

NUMBER 8

ITCOB4

(ISSN 1063-8210)

SPECIAL SECTION ON SYSTEM-LEVEL INTERCONNECT PREDICTION


Guest Editorial .... ......... ........ ......... ......... ........ ......... ......... ........ ......... ....... J. Dambre and M. Hutton

853

SPECIAL SECTION PAPERS

Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks ...... ........ ......... ......... ..
.. ........ ......... ......... ........ ......... ......... ........ ......... ... V. Soteriou, N. Eisley, H. Wang, B. Li, and L.-S. Peh
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors ....... ......... ..
.. ........ ......... ......... ........ ..... S. Murali, D. Atienza, P. Meloni, S. Carta, L. Benini, G. De Micheli, and L. Raffo
Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication . ......... ......... ..
.. ........ ......... ......... ........ ......... ......... ........ ......... ......... ... J. Kim, I. Verbauwhede, and M.-C. F. Chang
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow ... ......... ......... ........ ......... ......... ..
.. ........ ......... ......... ........ ......... ......... ........ .. V. Manohararajah, G. R. Chiu, D. P. Singh, and S. D. Brown
Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement ...... ......... ......... ..
.. ........ ......... ......... ........ ......... ......... ........ ......... ......... ........ ....... A. B. Kahng, B. Liu, and Q. Wang
Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models ... ........ X. Ye, F. Y. Liu, and P. Li
Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect .. .. I. OConnor, F. Tissafi-Drissi,
F. Gaffiot, J. Dambre, M. De Wilde, J. Van Campenhout, D. Van Thourhout, J. Van Campenhout, and D. Stroobandt

855
869
881
895
904
913
927

SPECIAL SECTION TRANSACTIONS BRIEFS

Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture ........ ......... ......... ..
.. ........ ......... ......... ........ ......... ......... ........ ......... ... J. Guo, A. Papanikolaou, H. Zhang, and F. Catthoor
Post-Placement Interconnect Entropy .... ......... ........ ......... ......... ........ ......... ....... W. Feng and J. W. Greene
Routability of Network Topologies in FPGAs .... . .... M. Saldaa, L. Shannon, J. S. Yue, S. Bian, J. Craig, and P. Chow

941
945
948

REGULAR ISSUE PAPERS

Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion
Method ......... ......... ........ ......... ......... ........ ...... R. C. C. Cheung, D.-U. Lee, W. Luk, and J. D. Villasenor
Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits ..... ......... ... J. C. Ku and Y. Ismail

952
963

TRANSACTIONS BRIEFS

Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip ........ ........ ......... ......... ..
.. ........ ......... ......... ........ ......... ......... ........ . A. Apostolakis, M. Psarakis, D. Gizopoulos, and A. Paschalis
Code Decompression Unit Design for VLIW Embedded Processors ..... ........ ......... Y. Xie, W. Wolf, and H. Lekatsas

971
975

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