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ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA

The document discusses the implementation of a 2x4 decoder and full adder using VHDL. It includes the VHDL code, output waveforms, and schematics for a 2x4 decoder, behavioral model full adder, and structural full adder. It also provides the device utilization and timing summary of the implemented design on a Xilinx FPGA.

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M Madan Gopal
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45 views8 pages

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA

The document discusses the implementation of a 2x4 decoder and full adder using VHDL. It includes the VHDL code, output waveforms, and schematics for a 2x4 decoder, behavioral model full adder, and structural full adder. It also provides the device utilization and timing summary of the implemented design on a Xilinx FPGA.

Uploaded by

M Madan Gopal
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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TITLE:

Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________ AIM:To write the program to implement operation of 2x4 Decoder and observe wave forms SOFTWARE REQUIRED:Xilinx software THEORY:

DECODERS

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

TITLE:

Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________


VHDL CODE FOR DECODER_2x4_DF: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity DECODER_2x4_DF is Port ( A : in STD_LOGIC; B : in STD_LOGIC; D0 : out STD_LOGIC; D1 : out STD_LOGIC; D2 : out STD_LOGIC; D3 : out STD_LOGIC); end DECODER_2x4_DF; architecture DF of DECODER_2x4_DF is Signal Abar,Bbar : STD_LOGIC; begin Abar <= not A; Bbar <= not B; D0 <= Abar and Bbar; D1 <= Abar and B; D2 <= A and Bbar; D3 <= A and B; end DF; OUTPUT WAVEFORM FOR DECODER_2x4_DF:

DECODERS

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

TITLE:

Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________


RTL SCHEMATIC FOR FA_DF GATE: TOPVIEW

DECODERS

INTERNAL HARDWARE CIRCUIT DIAGRAM

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

TITLE:

Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________

DECODERS

VHDL CODE FOR FA-BEHAVIORAL GATE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_Behavioral is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; SUM : out STD_LOGIC; Cout : out STD_LOGIC); end FA_Behavioral; architecture Behavioral of FA_Behavioral is begin process (A,B,Cin) begin if (A = '0' and B = '0' and Cin = '0') then SUM <= '0'; Cout <= '0'; elsif (A = '0' and B = '0' and Cin = '1') then SUM <= '1'; Cout <= '0'; elsif (A = '0' and B = '1' and Cin = '0') then SUM <= '1'; Cout <= '0'; elsif (A = '0' and B = '1' and Cin = '1') then SUM <= '0'; Cout <= '1'; elsif (A = '1' and B = '0' and Cin = '0') then SUM <= '1'; Cout <= '0'; elsif (A = '1' and B = '0' and Cin = '1') then SUM <= '0'; Cout <= '1'; elsif (A = '1' and B = '1' and Cin = '0') then SUM <= '0'; Cout <= '1'; else SUM <= '1'; Cout <= '1'; end if; end process; end Behavioral; OUTPUT WAVEFORM FOR FA-BEHAVIORAL GATE:

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

TITLE:

Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________

DECODERS

RTL SCHEMATIC FOR FA-BEHAVIORAL GATE: TOPVIEW

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

TITLE:

Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________


INTERNAL HARDWARE CIRCUIT DIAGRAM

DECODERS

VHDL CODE FOR FA-STRUCTURAL:


library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_STRUC is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; S : out STD_LOGIC; Cout : out STD_LOGIC); end FA_STRUC; architecture STRUCTURAL of FA_STRUC is component HA1 is Port ( L : in STD_LOGIC; M : in STD_LOGIC; X : out STD_LOGIC; Y : out STD_LOGIC); end component; component OR_GATE is Port ( P : in STD_LOGIC; Q : in STD_LOGIC; Y_OR : out STD_LOGIC); end component; signal SUM1,SUM2,CARRY1,CARRY2:STD_LOGIC; begin H1: HA1 port map (A,B,SUM1,CARRY1); H2: HA1 port map (SUM1,Cin,S,CARRY2); O1: OR_GATE port map (CARRY1,CARRY2,Cout); end STRUCTURAL;

OUTPUT WAVEFORM FOR FA-STRUCTURAL:

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

TITLE:

Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________

DECODERS

RTL SCHEMATIC FOR FA-STRUCTURAL: TOPVIEW

INTERNAL HARDWARE CIRCUIT DIAGRAM

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

TITLE:

Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________

DECODERS

RESULTS:
Device utilization summary:
--------------------------Selected Device : 3s500efg320-4 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 1 2 5 5 out of out of out of 4656 9312 232 0% 0% 2%

Timing Summary:
--------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 6.236ns

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

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