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CS-423 Dick Steflik

The I2C bus is a multi-master, two wire bus developed by Philips for connecting low speed peripherals. It uses a single data line (SDA) and clock line (SCL) to transmit data up to 100 kbits/sec. Each slave device has a unique 7-bit address. Data transfers are initiated by a master which controls the clock and addresses specific slaves to read from or write to. Transfers use start and stop conditions to synchronize communication between multiple masters and slaves on the shared bus.

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30 views9 pages

CS-423 Dick Steflik

The I2C bus is a multi-master, two wire bus developed by Philips for connecting low speed peripherals. It uses a single data line (SDA) and clock line (SCL) to transmit data up to 100 kbits/sec. Each slave device has a unique 7-bit address. Data transfers are initiated by a master which controls the clock and addresses specific slaves to read from or write to. Transfers use start and stop conditions to synchronize communication between multiple masters and slaves on the shared bus.

Uploaded by

prasanth_vedantham
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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2

IC

CS-423
Dick Steflik

Inter-Integrated Circuit

Developed and patented by Philips for


connecting low speed peripherals to a
motherboard, embedded system or cell phone
Multi-master, two wire bus , up to 100 kbits/sec

One data line (SDA)

One clock line (SCL)

Master controls clock for slaves

Each connected slave has a unique 7-bit address

Protocol

Transfers are byte oriented, msb first

Start: SDA goes low while SCL is high

Master sends address of slave (7-bits) on next


7 clocks
Master sends read/write request bit

0-write to slave

1-read from slave

Slave ACKs by pulling SDA low on next clock

Data transfers now commence

Terminology

Transmitter The device sending data to the bus

Receiver Device receiving data from the bus

Master device initiating a transfer, generates to clock


and terminates a transfer

Slave Device addressed by the master


Multi-master more than one master can attempt to
control the bus
Arbitration procedure to insure that only one master has
control of ther bus at any instant
Synchronization procedure to sync then clocks of two or
more devices

Master-to-Slave Data Transfer

Clock is controlled by master

Data is written to slave on next 8 clock pulses

Data receipt is ACKed by slave on 9th pulse by


pulling SDA low
When slave releases SDA master can send
next byte
Master will eventually set a Stop condition by
making a low to high transition on SDA with
SCL is high

Complete I2C Transfer

Master Writes to Slave

Master Reads from Slave

I2C Extensions

10 bit addressing (up to 1024 addresses)

Fast mode up to 400 kbits/sec

High-Speed up to 3.4 Mbits/sec

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