Computer Architecture

Lecture 4
Scoreboard
(Appendix A in textbook)

Ping-Liang Lai ( )

Computer Architecture Ch4-1

Scoreboard: a Bookkeeping
Technique
Out-of-order execution divides ID stage

Issue: decode instructions, check for structural hazards;

Read operands: wait until no data hazards, then read operands.

Scoreboards date to CDC6600 in 1963.

Instructions execute whenever not dependent on previous

instructions and no hazards.

CDC 6600: In order issue, out-of-order execution, out-of-order
commit (or completion).

No forwarding!
Imprecise interrupt/exception model for now.

Computer Architecture Ch4-2

Registers

FP
FPMult
Mult
FP
FPMult
Mult

FP
FPDivide
Divide

FP
FPAdd
Add

Integer
Integer

SCOREBOARD
SCOREBOARD

Functional Units

Scoreboard Architecture(CDC 6600)

Memory
Computer Architecture Ch4-3

Scoreboard Implications
Out-of-order completion WAR, WAW hazards?
Solutions for WAR

Stall writeback until registers have been read;

Read registers only during Read Operands stage.

Solution for WAW

Detect hazard and stall issue of new instruction until other instruction
completes.

No register renaming!
Need to have multiple instructions in execution phase multiple

execution units or pipelined execution units

Scoreboard keeps track of dependencies between instructions that
have already issued.
Scoreboard replaces ID, EX, WB with 4 stages.
Computer Architecture Ch4-4

Four Stages of Scoreboard Control

Issue: decode instructions & check for structural hazards (ID1)

Instructions issued in program order (for hazard checking);

Dont issue if structural hazard;
Dont issue if instruction is output dependent on any previously issued but
uncompleted instruction (no WAW hazards).

Read operands: wait until no data hazards, then read operands

(ID2)

All real dependencies (RAW hazards) resolved in this stage, since we wait
for instructions to write back data;
No forwarding of data in this model!

Computer Architecture Ch4-5

Four Stages of Scoreboard Control

Execution: operate on operands (EX)

The functional unit begins execution upon receiving operands. When the
result is ready, it notifies the scoreboard that it has completed execution.

Write result: finish execution (WB)

Stall until no WAR hazards with previous instructions:

Example:

DIVD F0, F2, F4

ADDD F10, F0, F8
SUBD F8, F8, F14

CDC 6600 scoreboard would stall SUBD until ADDD reads operands.

Computer Architecture Ch4-6

Three Parts of the Scoreboard

Instruction status: which of 4 steps the instruction is in.
Functional unit status: indicates the state of the functional unit

(FU). 9 fields for each functional unit.

Busy:

Indicates whether the unit is busy or not

Op:

Operation to perform in the unit (e.g., + or )

Fi:

Destination register

Fj,Fk:

Source-register numbers

Qj,Qk:

Functional units producing source registers Fj, Fk

Rj,Rk:

Flags indicating when Fj, Fk are ready

Register result status: indicates which functional unit will write

each register, if one exists. Blank when no pending instructions

will write that register.

Computer Architecture Ch4-7

Scoreboard Example
Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
Divide

Busy

S1
Fj

S2
Fk

F2

F4

F6

F8

FU
Qj

FU
Qk

Fj?
Rj

Fk?
Rk

...

F30

No
No
No
No
No

Register result status:

F0
Clock
FU

Op

dest
Fi

F10 F12

Scoreboard Example: Cycle 1

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

Read Exec Write

k Issue Oper Comp Result
R2
R3
F4
F2
F6
F2

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
Divide

Busy

Op

dest
Fi

Yes
No
No
No
No

Load

F6

F2

F4

Register result status:

F0
Clock
1

FU

S1
Fj

S2
Fk

FU
Qj

FU
Qk

Fj?
Rj

R2

F6
Integer

F8 F10 F12

Fk?
Rk
Yes

...

F30

Scoreboard Example: Cycle 2

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
Divide

Busy

Op

dest
Fi

Yes
No
No
No
No

Load

F6

F2

F4

Register result status:

F0
Clock
2

FU

Issue 2nd LD?

S1
Fj

S2
Fk

FU
Qj

FU
Qk

Fj?
Rj

R2

F6
Integer

F8 F10 F12

Fk?
Rk
Yes

...

F30

Scoreboard Example: Cycle 3

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1

Busy

Op

dest
Fi

Yes
No
No
No
No

Load

F6

F2

F4

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
Divide

Register result status:

F0
Clock
3

Issue MULT?

FU

S1
Fj

S2
Fk

FU
Qj

FU
Qk

Fj?
Rj

R2

F6
Integer

F8 F10 F12

Fk?
Rk
No

...

F30

Scoreboard Example: Cycle 4

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1

Op

dest
Fi

S1
Fj

S2
Fk

FU
Qk

Fj?
Rj

Fk?
Rk

F2

F4

F6

F8 F10 F12

...

F30

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
Divide

Busy
No
No
No
No
No

Register result status:

F0
Clock
4

FU

FU
Qj

Integer

Scoreboard Example: Cycle 5

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5

Busy

Op

dest
Fi

S1
Fj

Yes
No
No
No
No

Load

F2

F2

F4

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
Divide

Register result status:

F0
Clock
5

FU

Integer

S2
Fk

FU
Qj

FU
Qk

Fj?
Rj

R3

F6

F8 F10 F12

Fk?
Rk
Yes

...

F30

Scoreboard Example: Cycle 6

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6

2
6

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
Divide

S1
Fj

S2
Fk
R3
F4

Busy

Op

dest
Fi

Yes
Yes
No
No
No

Load
Mult

F2
F0

F2

F2

F4

F6

Register result status:

F0
Clock
6

FU Mult1 Integer

FU
Qj

FU
Qk

Fj?
Rj

Fk?
Rk

Integer

No

Yes
Yes

F8 F10 F12

...

F30

Scoreboard Example: Cycle 7

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7

2
6

3
7

Busy

Op

dest
Fi

S1
Fj

S2
Fk

Yes
Yes
No
Yes
No

Load
Mult

F2
F0

F2

R3
F4

Sub

F8

F6

F2

F2

F4

F6

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
Divide

Register result status:

F0
Clock
7

FU Mult1 Integer

Read multiply operands?

FU
Qj

FU
Qk

Integer
Integer

F8 F10 F12
Add

Fj?
Rj

Fk?
Rk

No

No
Yes

Yes

No

...

F30

Scoreboard Example: Cycle 8a

(First half

of CC)
Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8

2
6

3
7

Busy

Op

dest
Fi

S1
Fj

S2
Fk

Yes
Yes
No
Yes
Yes

Load
Mult

F2
F0

F2

R3
F4

Sub
Div

F8
F10

F6
F0

F2
F6

F2

F4

F6

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
Divide

Register result status:

F0
Clock
8

FU Mult1 Integer

FU
Qj

FU
Qk

Fj?
Rj

Fk?
Rk

No

No
Yes

Mult1

Yes
No

No
Yes

F8 F10 F12

...

F30

Integer
Integer

Add Divide

Scoreboard Example: Cycle 8b

(Second

half of CC)
Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8

2
6

3
7

4
8

Op

dest
Fi

S1
Fj

S2
Fk

Mult

F0

F2

Sub
Div

F8
F10

F6
F0

F2

F4

F6

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
Divide

Busy
No
Yes
No
Yes
Yes

Register result status:

F0
Clock
8

FU Mult1

FU
Qj

Fj?
Rj

Fk?
Rk

F4

Yes

Yes

F2
F6

Mult1

Yes
No

Yes
Yes

F8 F10 F12

...

F30

Add Divide

FU
Qk

Scoreboard Example: Cycle 9

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8

2
6
9
9

3
7

4
8

Op

dest
Fi

S1
Fj

S2
Fk

Mult

F0

F2

Sub
Div

F8
F10

F6
F0

F2

F4

F6

Functional unit status:

Time Name
Integer
10 Mult1
Mult2
2 Add
Divide

Note
Remaining

Busy
No
Yes
No
Yes
Yes

Register result status:

F0
Clock
9

FU Mult1

FU
Qj

FU
Qk

Fj?
Rj

Fk?
Rk

F4

Yes

Yes

F2
F6

Mult1

Yes
No

Yes
Yes

F8 F10 F12

...

F30

Add Divide

Read operands for MULT & SUB? Issue ADDD?

Scoreboard Example: Cycle 10

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8

2
6
9
9

3
7

4
8

Op

dest
Fi

S1
Fj

S2
Fk

Mult

F0

F2

Sub
Div

F8
F10

F6
F0

F2

F4

F6

Functional unit status:

Time Name
Integer
9 Mult1
Mult2
1 Add
Divide

Busy
No
Yes
No
Yes
Yes

Register result status:

F0
Clock
10

FU Mult1

FU
Qj

Fj?
Rj

Fk?
Rk

F4

No

No

F2
F6

Mult1

No
No

No
Yes

F8 F10 F12

...

F30

Add Divide

FU
Qk

Scoreboard Example: Cycle 11

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8

2
6
9
9

11

Op

dest
Fi

S1
Fj

S2
Fk

Mult

F0

F2

Sub
Div

F8
F10

F6
F0

F2

F4

F6

Functional unit status:

Time Name
Integer
8 Mult1
Mult2
0 Add
Divide

Busy
No
Yes
No
Yes
Yes

Register result status:

F0
Clock
11

FU Mult1

3
7

4
8

FU
Qj

Fj?
Rj

Fk?
Rk

F4

No

No

F2
F6

Mult1

No
No

No
Yes

F8 F10 F12

...

F30

Add Divide

FU
Qk

Scoreboard Example: Cycle 12

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8

2
6
9
9

3
7

4
8

11

12

Op

dest
Fi

S1
Fj

S2
Fk

Mult

F0

F2

F4

Div

F10

F0

F6

F2

F4

F6

Functional unit status:

Time Name
Integer
7 Mult1
Mult2
Add
Divide

Busy
No
Yes
No
No
Yes

Register result status:

F0
Clock
12

FU Mult1

Read operands for DIVD?

FU
Qj

Fj?
Rj

Fk?
Rk

No

No

Mult1

No

Yes

F8 F10 F12

...

F30

Divide

FU
Qk

Scoreboard Example: Cycle 13

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8
13

2
6
9
9

3
7

4
8

11

12

Op

dest
Fi

S1
Fj

S2
Fk

Mult

F0

F2

Add
Div

F6
F10

F8
F0

F2

F4

Functional unit status:

Time Name
Integer
6 Mult1
Mult2
Add
Divide

Busy
No
Yes
No
Yes
Yes

Register result status:

F0
Clock
13

FU Mult1

FU
Qj

FU
Qk

Fj?
Rj

Fk?
Rk

F4

No

No

F2
F6

Mult1

Yes
No

Yes
Yes

F6

F8 F10 F12

...

F30

Add

Divide

Scoreboard Example: Cycle 14

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8
13

2
6
9
9

3
7

4
8

11

12

Op

dest
Fi

S1
Fj

S2
Fk

Mult

F0

F2

Add
Div

F6
F10

F8
F0

F2

F4

14

Functional unit status:

Time Name
Integer
5 Mult1
Mult2
2 Add
Divide

Busy
No
Yes
No
Yes
Yes

Register result status:

F0
Clock
14

FU Mult1

FU
Qj

FU
Qk

Fj?
Rj

Fk?
Rk

F4

No

No

F2
F6

Mult1

Yes
No

Yes
Yes

F6

F8 F10 F12

...

F30

Add

Divide

Scoreboard Example: Cycle 15

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8
13

2
6
9
9

3
7

4
8

11

12

Op

dest
Fi

S1
Fj

S2
Fk

Mult

F0

F2

Add
Div

F6
F10

F8
F0

F2

F4

14

Functional unit status:

Time Name
Integer
4 Mult1
Mult2
1 Add
Divide

Busy
No
Yes
No
Yes
Yes

Register result status:

F0
Clock
15

FU Mult1

FU
Qj

FU
Qk

Fj?
Rj

Fk?
Rk

F4

No

No

F2
F6

Mult1

No
No

No
Yes

F6

F8 F10 F12

...

F30

Add

Divide

Scoreboard Example: Cycle 16

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8
13

2
6
9
9

3
7

4
8

11

12

14

16

Op

dest
Fi

S1
Fj

S2
Fk

Mult

F0

F2

Add
Div

F6
F10

F8
F0

F2

F4

Functional unit status:

Time Name
Integer
3 Mult1
Mult2
0 Add
Divide

Busy
No
Yes
No
Yes
Yes

Register result status:

F0
Clock
16

FU Mult1

FU
Qj

FU
Qk

Fj?
Rj

Fk?
Rk

F4

No

No

F2
F6

Mult1

No
No

No
Yes

F6

F8 F10 F12

...

F30

Add

Divide

Scoreboard Example: Cycle 17

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8
13

2
6
9
9

3
7

4
8

11

12

14

16

Op

dest
Fi

S1
Fj

S2
Fk

Mult

F0

F2

Add
Div

F6
F10

F8
F0

F2

F4

Functional unit status:

Time Name
Integer
2 Mult1
Mult2
Add
Divide

Busy
No
Yes
No
Yes
Yes

Register result status:

F0
Clock
17

FU Mult1

WAR Hazard!
Fj?
Rj

Fk?
Rk

F4

No

No

F2
F6

Mult1

No
No

No
Yes

F6

F8 F10 F12

...

F30

Add

Divide

Why not write result of ADD???

FU
Qj

FU
Qk

Scoreboard Example: Cycle 18

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8
13

2
6
9
9

3
7

4
8

11

12

14

16

Op

dest
Fi

S1
Fj

S2
Fk

Mult

F0

F2

Add
Div

F6
F10

F8
F0

F2

F4

Functional unit status:

Time Name
Integer
1 Mult1
Mult2
Add
Divide

Busy
No
Yes
No
Yes
Yes

Register result status:

F0
Clock
18

FU Mult1

FU
Qj

FU
Qk

Fj?
Rj

Fk?
Rk

F4

No

No

F2
F6

Mult1

No
No

No
Yes

F6

F8 F10 F12

...

F30

Add

Divide

Scoreboard Example: Cycle 19

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8
13

2
6
9
9

3
7
19
11

14

16

Op

dest
Fi

S1
Fj

S2
Fk

Mult

F0

F2

Add
Div

F6
F10

F8
F0

F2

F4

Functional unit status:

Time Name
Integer
0 Mult1
Mult2
Add
Divide

Busy
No
Yes
No
Yes
Yes

Register result status:

F0
Clock
19

FU Mult1

4
8
12

FU
Qj

FU
Qk

Fj?
Rj

Fk?
Rk

F4

No

No

F2
F6

Mult1

No
No

No
Yes

F6

F8 F10 F12

...

F30

Add

Divide

Scoreboard Example: Cycle 20

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8
13

2
6
9
9

3
7
19
11

14

16

Busy

Op

dest
Fi

S1
Fj

S2
Fk

No
No
No
Yes
Yes

Add
Div

F6
F10

F8
F0

F2
F6

Register result status:

F0
Clock

F2

F4

F6

F8 F10 F12

Add

Divide

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
Divide

20

FU

4
8
20
12

FU
Qj

FU
Qk

Fj?
Rj

Fk?
Rk

No
Yes

No
Yes

...

F30

Scoreboard Example: Cycle 21

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8
13

2
6
9
9
21
14

Functional unit status:

3
7
19
11

4
8
20
12

16

Busy

Op

dest
Fi

No
No
No
Yes
Yes

Add
Div

F6
F10

F8
F0

Register result status:

F0
Clock

F2

F4

F6

F8 F10 F12

Add

Divide

Time Name
Integer
Mult1
Mult2
Add
Divide

21

FU

WAR Hazard is now gone...

S1
Fj

S2
Fk

F2
F6

FU
Qj

FU
Qk

Fj?
Rj

Fk?
Rk

No
Yes

No
Yes

...

F30

Scoreboard Example: Cycle 22

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8
13

2
6
9
9
21
14

Functional unit status:

3
7
19
11

4
8
20
12

16

22

S1
Fj

S2
Fk

F6

Busy

Op

dest
Fi

No
No
No
No
Yes

Div

F10

F0

Register result status:

F0
Clock

F2

F4

F6

Time Name
Integer
Mult1
Mult2
Add
39 Divide

22

FU

FU
Qj

FU
Qk

F8 F10 F12
Divide

Fj?
Rj

Fk?
Rk

No

No

...

F30

Faster than light

computation
(skip a couple of cycles)

Computer Architecture Ch4-32

Scoreboard Example: Cycle 61

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8
13

2
6
9
9
21
14

3
7
19
11
61
16

4
8
20
12

Busy

Op

dest
Fi

S1
Fj

S2
Fk

No
No
No
No
Yes

Div

F10

F0

F6

Register result status:

F0
Clock

F2

F4

F6

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
0 Divide

61

FU

22

FU
Qj

FU
Qk

F8 F10 F12
Divide

Fj?
Rj

Fk?
Rk

No

No

...

F30

Scoreboard Example: Cycle 62

Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8
13

2
6
9
9
21
14

3
7
19
11
61
16

4
8
20
12
62
22

Op

dest
Fi

S1
Fj

S2
Fk

FU
Qk

Fj?
Rj

Fk?
Rk

F2

F4

F6

F8 F10 F12

...

F30

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
Divide

Busy
No
No
No
No
No

Register result status:

F0
Clock
62

FU

FU
Qj

Review: Scoreboard Example: Cycle

62
Instruction status:
Instruction
LD
F6
LD
F2
MULTD F0
SUBD
F8
DIVD
F10
ADDD
F6

j
34+
45+
F2
F6
F0
F8

k
R2
R3
F4
F2
F6
F2

Read Exec Write

Issue Oper Comp Result
1
5
6
7
8
13

2
6
9
9
21
14

3
7
19
11
61
16

4
8
20
12
62
22

Op

dest
Fi

S1
Fj

S2
Fk

FU
Qk

Fj?
Rj

Fk?
Rk

F2

F4

F6

F8 F10 F12

...

F30

Functional unit status:

Time Name
Integer
Mult1
Mult2
Add
Divide

Busy
No
No
No
No
No

Register result status:

F0
Clock
62

FU
Qj

FU

In-order issue; out-of-order execute & commit

CDC 6600 Scoreboard

Speedup 1.7 from compiler; 2.5 by hand

BUT slow memory (no cache) limits benefit

Limitations of 6600 scoreboard

No forwarding hardware;
Limited to instructions in basic block (small window);
Small number of functional units (structural hazards), especially;
;integer/load store units;
Do not issue on structural hazards;
Wait for WAR hazards;
Prevent WAW hazards.

Computer Architecture Ch4-36