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A Practical Guide to
High-Speed Printed Circuit
Board Layout
John Ardizzoni
Analog Devices

Dennis Falls
Avnet Electronics Marketing

Agenda
g
Overview
Schematic
Location,

location, location
Trust no one
Power supply bypassing
Parasitics
Ground and power planes
Packaging
RF Signal
g
routing
g and shielding
g
Checking the layout
Summary

Overview
PCB

layout
y
is one of the last steps
p in the design
g process
p
and
often one of the most critical
High-speed circuit performance is heavily dependant on
layout
y
A high-performance design can be rendered useless due to a
poor or sloppy layout
Today
Todays
s presentation will help:
z Improve

the layout process

z Ensure expected circuit performance is achieved
z Reduce design time
z Lower cost
z Lower stress for you and the PCB designer

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Schematic

Schematic
The

strength
g of any
y structure (including
(
g PCBs)) is only
y as
good as the foundation on which it built upon!
A good layout starts with a good Schematic!
Schematic flow and content
Include as much information as you can
What should you include?

Items to Include on a Schematic

Notes
Component

tolerances and case sizes

Part numbers (internal/external/alternative)
Board stack up
Tests
T t or alignment
li
t procedures
d
Power dissipation
Controlled impedance and line matching
Component de
de-rating
rating
Thermal requirements
Keep outs
Mechanical considerations
Critical component placement
Warning flags
What ever else y
you can think of!

Schematic
+5V

C1
0.1uF

Place this cap right at pin 14 to digital ground

R6
301

40 MHz
U1

S1

40 MHz
OSC Out

+5V

Run 40MHz traces on bottom

of the board ensure signal
trace is the same length
U2

R7
50

R3
562

R1
1K

R5
562

ADA48601

R2
50

+5V

C3
SAT

C2
SAT

C7
2.2uF

REF DES

VALUE

R1

1K

RATING
62mW

R3

C1

5
6
7

C2
C3
U1

U2

-5V

U3
Linear Regulator

D1
8
1N4148
ACTUAL
10mW

C8 +
10uF
Case
size
1210
D2
1N4148

C9
0.01
uF

C11
0.1uF
Linear Regulator

-12V

+5
V

+
C14
0.1uF

NOTES:
1.0 All resistors and capacitors are 0603 case size unless noted otherwise.
2.0 All Resistors in ohms unless noted otherwise.
3.0 All capacitors in pF unless noted otherwise.
4.0 Run analog traces on Signal 1 layer, run digital traces on Signal 2 layer
5.0 Remove ground plane on all layers under the mounting pins of U2
6 0 U1 SOIC
6.0
SOIC-14
14, U2 SOT
SOT-23-6
23 6, U3,
U3 SOIC
SOIC-8
8, U4 SOIC
SOIC-8
8

+ C12
10uF
Case
size
1210

U4
Temperature
Sensor

+5
V
+5V

-5V

AD590

VOUT

R8
1K

-5V
C16
+ 10uF
Case size
1210

U5
C13
10uf
Case
size
1210

See critical component placement

drawing for location

ADP667

+12V

R2

Must be right at
op amp supply
pins

FREQUENCY ADJUST
1.0 C2=C3, use these 2 capacitors to adjust the -3dB BW

VOUT

C6
0.01uF

VIN

D ti T
Derating
Table
bl

Must be right at
op amp supply
pins

C4
2.2uF

C5
0.01uF
R4
210

40 MHz
OSC Out

ITEM
1

Put C4 and C7 on
back of board
right under the
power supply pin.

C15
0.1uF
BOARD STACK UP
Signal 1
Analog Ground 1
Power plane
Digital Ground
A l G
Analog
Ground
d2
Signal 2

0.062"

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Location, location, location!

Location,, Location,, Location

Just

as in real estate location is everything!

Input/output and power connections are typically
definedEverything else is undefined
z Critical

component placement
z Signal routing
z Circuit and component proximity

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Trust No One

Trust No One
If

y
youre
doing
gy
your own
layout, thats one thing.
If youre not .

11

Trust No One
If

y
youre
doing
gy
your own
layout, thats one thing.
If youre not .
z Don
Dontt

assume the CAD group is

going to read your mind and get
it right!

12

Trust No One
If

y
youre
doing
gy
your own
layout, thats one thing.
If youre not .
z Don
Dontt

assume the CAD group is

going to read your mind and get
it right!
z In the end youre responsible
for making it work!

13

Trust No One
If

y
youre
doing
gy
your own
layout, thats one thing.
If youre not .
z Don
Dontt

assume the CAD group is

going to read your mind and get
it right!
z Youre responsible for making it
work!
When

Group

14

working with the CAD

Trust No One
If

y
youre
doing
gy
your own
layout, thats one thing.
If youre not .
z Don
Dontt

assume the CAD group is

going to read your mind and get
it right!
z Youre responsible for making it
work!
When

Group
z Make

working with the CAD

sure you and the designer

are on the same page

15

Trust No One
If

y
youre
doing
gy
your own
layout, thats one thing.
If youre not .
z Don
Dontt

assume the CAD group is

going to read your mind and get
it right!
z Youre responsible for making it
work!
When

Group
z Make

working with the CAD

sure you and the designer

are on the same page
z Brief circuit explanation

16

Trust No One
If

y
youre
doing
gy
your own
layout, thats one thing.
If youre not .
z Don
Dontt

assume the CAD group is

going to read your mind and get
it right!
z Youre responsible for making it
work!
When

Group
z Make

working with the CAD

sure you and the designer

are on the same page
z Brief circuit explanation
z Critical
C iti l componentt placement
l
t
17

Trust No One
If

youre doing your own

layout, thats one thing.
If youre not .
z Dont

assume the CAD group is

going to read your mind and get
it right!
z Youre responsible for making it
work!
When

Group
z Make

working with the CAD

sure you and the designer

are on the same page
z Brief circuit explanation
z Critical component placement
z Input/Output connections
18

Trust No One
If

youre doing your own layout,

th t one thi
thats
thing.
If youre not .
Dont assume the CAD group is
going
g
g to read your
y
mind and get
g it
right!
z Youre responsible for making it
work!
z

When

Group

working with the CAD

Make sure you and the designer

are on the same page
z Brief circuit explanation
z Critical component placement
z Input/Output connections
z Board outline drawing and stack up
z

19

Trust No One
If youre doing your own layout,
thats one thing
thing.
If youre not .
z Dont assume the CAD group is
going to read your mind and get it
right!
i ht!
z Youre responsible for making it
work!
When working with the CAD Group
z Make sure you and the designer
are on the same page
z Brief circuit explanation
z Critical component
p
placement
p
z Input/Output connections
z Board outline, stack up
z Tell them to call you if they have a
question!

20

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Power Supply Bypassing

Power Supply
pp y Bypassing
yp
g
Bypassing
yp
g

is essential to
high speed circuit
performance

22

Power Supply
pp y Bypassing
yp
g
Bypassing
yp
g

is essential to
high speed circuit
performance
Capacitors
p
right
g at power
p
supply pins

23

Power Supply
pp y Bypassing
yp
g
Bypassing
yp
g

is essential to
high speed circuit
performance
Capacitors
p
right
g at power
p
supply pins
z Capacitors

provide low AC
impedance to ground
z Provide local charge storage
for fast rising/falling edges

24

Power Supply
pp y Bypassing
yp
g
Bypassing
yp
g

is essential to
high speed circuit
performance
Capacitors
p
right
g at power
p
supply pins
provide low AC
impedance to ground
z Provide local charge storage
for fast rising/falling edges

L1

IC

1H
C1
0.1F

z Capacitors

Keep

trace lengths short

EQUIVALENT DECOUPLED POWER

LINE CIRCUIT RESONATES AT:
f =

1
2 LC

f = 500kHz
25

+VS

Power Supply
pp y Bypassing
yp
g
Bypassing
yp
g

is essential to
high speed circuit
performance
Capacitors
p
right
g at power
p
supply pins
z Capacitors

provide low AC
impedance to ground
z Provide local charge storage
for fast rising/falling edges
Keep

26

trace lengths short

Power Supply
pp y Bypassing
yp
g
Bypassing
yp
g

is essential to
high speed circuit
performance
Capacitors
p
right
g at power
p
supply pins
z Capacitors

provide low AC
impedance to ground
z Provide local charge storage
for fast rising/falling edges
Keep

trace lengths short

Close to load return
z Helps

minimize transient
currents in the ground plane

27

Power Supply
pp y Bypassing
yp
g
Bypassing

is essential to
high speed circuit
performance
Capacitors right at power
supply pins
z Capacitors

provide low AC
impedance to ground
z Provide local charge
g storage
g
for fast rising/falling edges
Keep

trace lengths short

Close to load return
z Helps

minimize transient
currents in the ground plane

Values
z Individual

28

circuit performance

Power Supply
pp y Bypassing
yp
g
Bypassing

is essential to
high speed circuit
performance
Capacitors right at power
supply pins
Capacitors provide low AC
impedance to ground
z Provide local charge storage for
fast rising/falling edges
z

Keep

trace lengths short

Close to load return
z

Helps minimize transient currents

in the ground plane

Values

Individual circuit performance

z Maintains low AC impedance
z

29

Power Supply
pp y Bypassing
yp
g
Bypassing

is essential to
high speed circuit
performance
Capacitors right at power
supply pins

Capacitors provide low AC

impedance to ground
z Provide local charge storage for
fast rising/falling edges
z

Keep

trace lengths short

Close to load return
z

Helps minimize transient currents

in the ground plane

Values
V l

Individual circuit performance

z Maintains low AC impedance
z Multiple
p resonances
z

30

Power Supply
pp y Bypassing
yp
g
Bypassing

is essential to high
speed
d circuit
i
it performance
f
Capacitors right at power
supply pins
Capacitors provide low
impedance AC return
z Provide local charge storage for
fast rising/falling edges
z

Keep

trace lengths short

Close to load return
z

Helps minimize transient currents

in the ground plane

Values
V l

Individual circuit performance

z Maintains low AC impedance
z Multiple resonances
z

Ferrite
31

beads

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Parasitics

Parasitics
Parasite

An organism
g
that grows,
g
, feeds,, and is sheltered on
or in a different organism while contributing nothing to the
survival of its host.

Parasitics

in high-speed PCBs, can destroy circuit

performance!

33

Parasitics
PCB

parasites take the form of undesired capacitors,

inductors and resistors embedded within the PCB
Parasitics are extremely difficult to remove from a PCB
Prevention is the best method to minimize parasitics

34

Trace/Pad Capacitance
p

C=

kA
11.3d

K = relative dielectric constant

A = area in cm2
d = spacing between plates in cm

35

Trace/Pad Capacitance
p

Example: Pad of SOIC

L = 0.2cm W = 0.063cm
K= 4.7

C=

kA
11.3d

A = 0.0126cm2
d = 0.073cm
C = 0.072pF

K = relative dielectric constant

A = area in cm2
d = spacing between plates in cm

36

Trace/Pad Capacitance
p
Example: Pad of SOIC
L = 0.2cm
0 2cm W = 0
0.063cm
063cm
A

K= 4.7
A = 0.0126cm2
d = 0.073cm

kA
C=
11.3d
K = relative dielectric constant
A = area in cm2
d = spacing between plates in cm

37

C = 0.072pF
p

Reduce Capacitance
C
1) Increase board thickness or layers
2) Reduce trace/pad area
3) Remove ground plane

Approximate
pp
Trace Inductance

All dimensions are in mm

38

Approximate
pp
Trace Inductance

All dimensions are in mm

Example
L= 25.4mm
W = .25mm
H = .035mm (1oz copper)
Strip Inductance = 28.8nH
At 10MHz
10MH ZL = 1.86
1 86 a 3
3.6%
6% error
in a 50 system
39

Approximate
pp
Trace Inductance

All dimensions are in mm

Example
L= 2.54cm =25.4mm
W = .25mm
H = .035mm (1oz copper)
Strip Inductance = 28.8nH
At 10MHz
10MH ZL = 1.86
1 86 a 3
3.6%
6% error
in a 50 system
40

Minimize Inductance
1) Use Ground plane
2) Keep length short (halving
the length reduces
inductance by 44%)
3) Doubling width only
reduces inductance by
11%

Via Parasitics
Via Inductance
44hh
L 2h ln + 1 nH
d
L = inductance of the via, nH
H = length of via, cm
D = diameter of via, cm
Given:
H= 0.157 cm thick board,
D= 0.041 cm

L ~ 1.2nh

Via Capacitance
C

0.55 r TD1 pF
D2 D1

D2 = diameter of clearance hole in the

ground plane, cm
D1 = diameter
di
t off pad
d surrounding
di via,
i cm
T = thickness of printed circuit board, cm
r = relative electric permeability of circuit
board material
C = parasitic via capacitance, pF

Given:
T = 0.157cm,
D1=0.071cm
0 071
D2 = 0.127

C ~ 0.51pf

41

Via Cross Section

D2
T&H
D1
D

42

Capacitor
p
Parasitic Model
RP

RS
r

C
RDA

CDA

C = Capacitor
RP = insulation resistance
RS = equivalent series resistance (ESR)
L = series inductance of the leads and plates
RDA = dielectric absorption
CDA = dielectric absorption
43

Resistor Parasitic Model

L

CP

R = Resistor
CP = Parallel capacitance
L= equivalent series inductance (ESL)
44

Low Frequency
q
y Op
p Amp
p Schematic

45

High
g Speed
p
Op
p Amp
p
Schematic

46

High
g Speed
p
Op
p Amp
p
Schematic
Parasitic Capacitance

47

http://www.analog.com/en/design-tools/dt-multisim-spice-program-download/design-center/index.html

48

Stray
y Capacitance
p
Simulation Schematic

49

Frequency
q
y Response
p
with 2pF
p Stray
y Capacitance
p

1.8dB peaking
1.8dB peaking

50

Stray
y Inductance

Parasitic Inductance

51

Parasitic Inductance Simulation Schematic

AD8055

52

24.5mm x .25mm =29nH

Pulse Response
p
With and Without Ground
Plane
0.6dB overshoot

53

Transient Response
p
AD8009
1GHz Current Feedback Amplifier
RF

402
+5V
10uF

RG

402
0.1uF
0.1uF

150
10 F
10uF

-5V

54

Small Changes
g
Can Make a Big
g Difference!

Circuit A
55

Circuit B

Improper
p p Use of Scope
p Probe Ground Clip
p

56

Effect of Clip
p Lead Inductance

57

Proper
p Grounding
g for Scope
p Probe in Highg
Speed Measurments

58

Small Changes
g
Make Big
g Differences
Circuit A

21ns

Circuit B

17ns

25% reduction in ringing duration and amplitude

59

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Ground and Power Planes

Ground and Power Planes Provide

A

common reference point

p
Shielding
Lower noise
Lower resistance
Lower impedance
Reduces parasitics
Heat sink
Power distribution

61

Ground Plane
I

62

Ground Plane and Trace Routing

Wrong Way
Clock
Circuitry

Analog
Circuitry

Resistor

Input Connector

Digital
Circuitry

Sensitive Analog
Circuitry Disrupted by
Digital Supply Noise

ID
IA
+
VD

63

+
VA
GND
REF

INCORRECT
ANALOG
CIRCUITS

VIN
IA + ID

DIGITAL
CIRCUITS
ID

Wrong Way
Clock
Circuitry

Analog
Circuitry

Resistor

Ground Plane and Trace Routing

Digital
Circuitry

Sensitive Analog
Circuitry Disrupted by
Digital Supply Noise

ID
IA
+
VD

64

+
VA
GND
REF

INCORRECT
ANALOG
CIRCUITS

VIN
IA + ID

DIGITAL
CIRCUITS
ID

Resistor

Ground Plane and Trace Routing

Right Way

Analog
Circuitry

Digital
Circuitry

Sensitive Analog
Circuitry Safe from
Digital Supply Noise

Clock
Circuitry

ID
IA
+
VD

+
VA
GND
REF

65

VIN

CORRECT
ANALOG
CIRCUITS
IA
ID

DIGITAL
CIRCUITS

Resistor

Ground Plane and Trace Routing

Right Way

Analog
Circuitry

Digital
Circuitry

Sensitive Analog
Circuitry Safe from
Digital Supply Noise

Clock
Circuitry

ID
IA
+
VD

+
VA
GND
REF

66

VIN

CORRECT
ANALOG
CIRCUITS
IA
ID

DIGITAL
CIRCUITS

Ground Plane and Trace Routing

Resistor

Grounding Example:

Top
p layer
y is solid g
ground.
Bottom has a trace/transmission line
connecting the RF connector to the
load.
R t
Return
currentt fl
flows iin the
th top
t layer
l
ground plane directly above the trace
on the opposite side.

Signal
Input

Termination
Resistor

Top Side

Bottom side
67

Ground Plane and Trace Routing

AC current
follows the
path of least
impedance

68

In a split or broken ground, the return

currents follow the path of least
i
impedance
d
At DC, the current follows the path of
least resistance
As the frequency increases
increases, the
current follows the path of least
inductance
Since there is now a loop the
inductance can be quite high and the
circuit can now propagate EMI/RFI

Resistor

Grounding Example: DC Current vs. AC

Current:

DC current
follows the
path of least
resistance

Grounding
g Mixed Signal
g
ICs: Single
g PC Board

VA

VD
VA

MIXED
SIGNAL
DEVICE

ANALOG
CIRCUITS
SYSTEM
STAR
GROUND

AGND

69

DIGITAL
CIRCUITS

DGND

ANALOG
GROUND PLANE

ANALOG
SUPPLY

VD

DIGITAL
GROUND PLANE
D
DIGITAL
SUPPLY

Ground Plane Recommendations

There

is no single grounding method which is guaranteed to work

100% of the time!
Remove
R
ground
d plane
l
under
d op amps to
t reduce
d
parasitic
iti
capacitance
At least one layer on each PC board MUST be dedicated to ground
p
plane!
Provide as much ground plane as possible especially under traces
that operate at high frequency
Use thickest metal as feasible (reduces resistance and provides
improved thermal transfer)
Use multiple vias to connect same ground planes together
Do initial layout with split analog and digital ground planes
Follow recommendations on device data sheet (read datasheet)
Keep bypass capacitors and load returns close to reduce distortion
Connect analog, digital and RF grounds at one point

70

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Packaging and Pinout

Op
p Amp
p Packaging
g g and Pinout
Packaging
g g

plays
p y a large
g role in high-speed
g
p
applications
pp
Smaller packages
z Better

at higher speeds
z Less parasitics
z Compact layout
Analog

Devices Low Distortion Pinout

z Intuitively

makes more sense

z Compact layout
z Streamline signal flow
z Lower distortion

72

Op
p Amp
p SOIC Packaging
g g
Traditional

SOIC-8 layout
Feedback routed around or underneath amplifier
p

73

Op
p Amp
p SOIC Packaging
g g
Traditional

SOIC-8 layout
Feedback routed around or underneath amplifier
p

74

Analog
g Devices Low Distortion Pinout
Pinout

layout

Original Pin-Out

enables compact
p
FB
NC

IN

+IN

VS

Disable

+VS

VOUT

NC

NC

+VS

FEEDBACK

OUTPUT

IN

NC

+IN

VS

LFCSP
75

0481
14-0-001

SOIC

Analog
g Devices Low Distortion Pinout
Pinout

Original Pin-Out

enables compact
p

layout
Lower distortion

FB

Disable

IN

+VS

+IN

VOUT

VS

NC

NC

+VS

FEEDBACK

OUTPUT

IN

NC

+IN

VS

LFCSP
76

04814-0-001

SOIC

Analog
g Devices Low Distortion Pinout
Pinout

Original Pin-Out

enables compact
p

layout
Lower distortion
Improved thermal
performance

FB

Disable

IN

+VS

+IN

VOUT

VS

NC

NC

+VS

FEEDBACK

OUTPUT

IN

NC

+IN

VS

LFCSP
77

04814-0-001

SOIC

Analog
g Devices Low Distortion Pinout
Original Pin-Out

enables compact
p

layout
Lower distortion
Improved thermal
performance
LFCSP

FB

Disable

IN

+VS

+IN

VOUT

VS

NC

SOIC

z AD8099,
AD8099

AD8045,
AD8045 AD8000
AD8000,
ADA4899, ADA4857, ADA4817
NC

+VS

FEEDBACK

OUTPUT

IN

NC

+IN

VS

LFCSP
78

04814-0-001

Pinout

Low distortion p
pinout enables compact
p
and streamline layout

79

Low distortion p
pinout enable compact
p
and
streamline layout

RT

C
AD80XX

RG

R
RF

Tantalum

0
C
Tantalum

80

RL

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RF Signal Routing and

Shielding

In This Section
RF

Components from Analog Devices

PC Board Circuit Material Types
yp and Minimizing
g Losses
Microstrip and Stripline Transmission Lines
Ground Plane Layout Considerations
Developing a RF Printed Circuit Board
Using Discrete Components with RF Devices
Shielding of RF Circuit Boards

82

RF Components from Analog Devices

http://www.analog.com/en/rfif-components/products/index.html
p
g
p
p

83

Analog Devices Components Requiring Matched

RF Interfaces
AD60x,

AD8xxx and ADL533x series of RF/IF and Variable Gain

Amplifiers

ADF70xx

and 702x series Radio Transmitters and

Transceivers
AD4xxx and ADF7xxx series of PLL Synthesizers and VCOs
AD84xx and ADL53xx series of Modulators and Demodulators
AD83xx and ADL539x series of Mixers and Multipliers
AD83xx and ADL5519 series of Log Amps and Detectors
AD836x and ADL550x series of RMS Detectors
ADG9xx
ADG9 series
i off RF Switches
S it h

84

PC Board Circuit Material Type and Minimizing

Losses
PC

board material selection is usually based on price verses

performance
Select PC board dielectric material to have the lowest loss tangent
Some types of FR4
FR4 dielectric materials are low loss below 8-10
GHz
PTFE(Teflon) dielectric material is usually used for the lowest loss
g
RF and microwave frequency
q
y ranges,
g , but at a much
at the higher
higher price
Be sure that the correct impedance transmission line is used for the
interconnection of the RF devices
Use as wide of a transmission line as possible for the correct
impedance, and try to keep it short to reduce Skin Effect losses
Use high Q, or low loss passive components for all RF matching,
coupling and bypassing requirements
coupling,
85

Microstrip
p and Stripline
p
Transmission Lines
50

ohm interfaces are most often used between most integrated

RF devices
Interconnects less than 1/20 of a wavelength long can usually be
made without a matched transmission line
Avoid long
g microstrip
p lines as they
y could become
antennas(microstrip) and radiate RF
To minimize coupling to the transmission line, DO NOT place other
traces or ground plane closer than three times of the dielectric
h i ht
height
Use proper technique for making bends in microstrip lines
Locate the microstrip lines on the component side of the board if
possible

86

Microstrip
p Transmission Lines

Microstrip
Controlled Impedance Line
C
Cross
S
Section
ti
Advantages:
Transmission line on outside layer
of board
Easy to attach components to trace
Components can be placed at
different locations along the line to
aid in tuning
Aid in RF testing as you are able to
measure levels along the line

Disadvantages:
g
Slightly higher loss
Not shielded and could radiate RF
signal

87

ZO =

87
5.98H
ln
r + 1.41 (0.8W + T )

Stripline Transmission Lines

Stripline

Controlled Impedance Line

Cross Section
Advantages:
Lower loss at higher microwave
frequencies
Shielded transmission line, no RF
radiation from board
Disavantages:
Requires vias to connect to line
No ability to connect tuning or
termination components to line
No access to line to make
adjustments or connections to line
for RF testing
Higher PCB cost

88

60 1.9(B)
ZO () = ln
r (0.8W + T)

Microstrip
p and Stripline
p
Transmission Lines
Bends

in Microstrip and Stripline

In order to preserve a constant

impedance around a bend, some
general layout rules MUST be
followed
DO NOT make a right angle bend as
shown
A right
i ht angle
l bend
b d can be
b made
d with
ith
a swept bend, or a Mitered bend
Bends in a transmission line that are
less than 90 degrees
g
can also be
mitered as shown

89

Ground Plane Layout

y
Considerations
Do

NOT have breaks or voids in the RF ground plane under, or over

RF transmission lines
Ground plane Vias around the RF circuits should be spaced closer
than 1/20 of a wavelength as a minimum, or closer if possible at the
higher frequencies
Use as large size vias as practical to minimize inductance
Stitch the top and bottom ground planes together with as many
vias as possible
Signal and bias lines can be placed below RF ground plane layer
followed by another power ground plane layer for the DC and
digital returns
Under components that require heat sinking,
sinking have solid ground
plane with many closely spaced vias to transfer heat to all ground
plane layers

90

Ground Plane Layout

y
Considerations
Closely spaced vias under
components requiring heat
sinking
50 ohm microstrip
transmission line

Vias placed in ground

plane at each end of
the DC bias bypass
components

Proper spacing of ground plane

away from transmission line
(gap= 3 times dielectric height)

Closely spaced
G
Ground
d plane
l
vias
i
along transmission
line
Stitch ground
planes
l
ttogether
th
with multiple vias
91

Proper layout pattern for

connecting edge mounted
RF connector to PC board

Maximum amount of ground plane

on top and bottom sides of PC board

Developing a RF Printed Circuit Board

Draw

Schematic of circuit to be placed on the PC board

Have data sheets on components to indicate pkg size, pinouts, etc
Determine location and orientation of active devices to optimize RF
interfaces
Place RF matching/terminating components around the device to
provide the shortest possible connections
Use as small of mounting pad as possible with discrete RF
components to keep stray capacitance to a minimum
Observe proper orientation of discrete components if placed next to
each
h other
th to
t avoid
id coupling
li
effects
ff t
Separate inductors from each other in the layout, or place
perpendicular to each other to prevent coupling of their magnetic
fields
Make sure that components that are connected to the ground plane
have a via(s) as close to the end of the component as possible
Use wide power traces if possible to lower DC losses and provide
higher stray capacitance to ground(will also act as a RF bypass cap)
92

Designing a RF Printed Circuit Board

Draw Schematic of circuit

Draw layout of components to optimize parts placement and interconnections

93

ADL5523

AD5350

LNA

Mixer

AD8353
IF AMP

Designing a RF Printed Circuit Board

Ground plane Ground vias at end Place bias line bypassing
Matching
Large number of vias under devices
Is not close to of RF and bypass
components close to RF components placed
to provide good RF grounds and
transmission
components
device
close to RF device
thermal conductivity
line to reduce
coupling

RF Input

ADL5523
LNA

AD5350

AD8353

Mixer

IF AMP

IF
Output

LO Input

RF attenuator RF devices placed in a straight Inductors placed at right

placed close to
line to aid in overall circuit angles to reduce coupling
board connector
stability
of their magnetic fields

94

Short interstage RF
transmission lines
between stages

Very short ground

leads from device
to ground plane

Shielding
g on RF Circuit Boards
On multilayer circuit boards, use Stripline transmission lines if possible
Route DC bias and signal traces on inner layers between the ground planes
If required,
equ ed, place
p ace shielded
s e ded enclosures
e c osu es a
around
ou d tthe
e RF stages o
on tthe
e boa
board
d
Be careful as to the physical size of the shielded enclosures, as it could
become a resonate cavity at the higher frequencies
Traces going to or from shielded sections should be routed on inner layers
if possible
Shield enclosure outlines

DC bias line on inner layer

D C Bias

RF Input
ADL5523

AD5350

AD8353

LNA

Mixer

IF AMP

L O Input

All board mounting holes should be

plated through to provide good RF
grounds to the external housing

95

On multilayer board use stripline

transmission lines to provide
shielding

IF Output

Th W
The
World
ld LLeader
d iin Hi
High
h Performance
P f
Signal
Si l P
Processing
i Solutions
S l ti

Checking the Layout

Checking
g the Layout
y
Design
g

review
Colleague review

97

Checking
g the Layout
y
Design
g

review
Colleague
Colored pencils
z Old

School
z Helps trace signal path on
schematic and PCB

98

Checking
g the Layout
y
Design
g

review
Colleague
Colored pencils
z Old

School
z Helps trace signal path on
schematic and PCB
Sit

with the designer when

board corrections are made
z Trust

no one
z A change in one area of the
board could inadvertently
change another part of the
board

99

Next Steps
p
Order

Boards
Build and test
Evaluate performance
Iterate and try again if required
Successful High Speed/RF PCB design is a combination of
education and experience

100

Th W
The
World
ld LLeader
d iin Hi
High
h Performance
P f
Signal
Si l P
Processing
i Solutions
S l ti

Summary

Summary
y
High speed PCB design requires deliberate thought and attention to detail!
Load the schematic with as much information as possible
Where you put individual components on the board is just as important as
to where you put entire circuits
Take the lead when laying out your board, dont leave anything to chance
Use multiple capacitors for power supply bypassing
Parasitics must be considered and dealt with
Ground and Power planes play a key role in reducing noise and parasitics
New packaging and pinout options allow for improved performance and
more compact layouts
There are many options for signal distribution, make sure you choose the
right one for your application
Check
Ch k th
the llayoutt and
d check
h k it again
i
Successful High Speed PCB design is a combination of education and
experience and sometimes a little luck!

102

Summary
y
Work

directly with PC board designer as they most likely will not

understand proper RF layout techniques
Provide
P
id designer
d i
with
ith a drawing
d
i off the
th location
l
ti off the
th critical
iti l high
hi h
frequency components and transmission lines
Instruct the board designer that transmission line widths and
g
are very
y critical and must be exactly
y as calculated
lengths
Place the components to minimize the length of RF
interconnections
Generally try to place components in a straight line to avoid
feedback loops and instabilities
Place circuit blocks such as oscillators, mixers, amplifiers in
separate sections on the board if possible
Do NOT mix digital,
g , low level analog,
g, or bias traces with RF
interconnects to avoid unwanted coupling
Locate the components operating at the highest frequencies close
to board interconnects
With the PC board designer
designer, check
check, and recheck the layout before
sending out for fabrication
103

References
Ardizzoni,

John A Practical Guide to High-Speed Printed-CircuitBoard Layout

Ardizzoni, John, Keep
Keep High
High-Speed
Speed Circuit
Circuit-Board
Board Layout on Track,
Track,
EE Times, May 23, 2005.
Brokaw, Paul, An IC Amplifier Users Guide to Decoupling,
Grounding, and Making Things Go Right for a Change, Analog
Devices Application Note AN-202.
Brokaw, Paul and Jeff Barrow, Grounding for Low- and HighFrequency Circuits, Analog Devices Application Note AN-345.
Buxton, Joe, Careful Design Tames High-Speed Op Amps, Analog
Devices Application Note AN-257.
DiSanto, Greg, Proper PC-Board Layout Improves Dynamic
Range, EDN, November 11, 2004.
Grant, Doug and Scott Wurcer, Avoiding Passive-Component
Pitfalls, Analog Devices Application Note AN-348
Johnson, Howard W., and Martin Graham, High-Speed Digital
Design, a Handbook of Black Magic, Prentice Hall, 1993.
Jung, Walt, ed., Op Amp Applications Handbook, Elsevier-Newnes,
2005 available on Amazon.com
Kester, Walt, The Data Conversion Handbook, Elsevier-Newnes,
2005 available on Amazon.com
104

References
Hartley,
y

Rick, RF / Microwave PC Board Design

g and Layout
y
Reed, Dale, RF and Microwave Basics Impact PCB Design
Mercer, Sean, Minimizing RF PCB Electromagnetic Emissions, RF
Design, January 1999.
Fabian Kung Wai Lee, Open notes on High-Speed Printed Circuit
Board (PCB) Design (August 2008) Available at
http://persona.mmu.edu.my/~wlkung/ADS/ads.htm
Howe,
H
H
Harlan,
l
St
Stripline
i li Circuit
Ci
it Design
D i
Rogers Corporation, A Low cost Laminate for Wireless
Applications, Microwave Journal, Sept 1996
Rogers Corporation,
Corporation Microwave Impedance Calculator (MWIJ 1
1.0)
0)

105

Contact Information
John Ardizzoni
Analog Devices, Inc.
804 Woburn Street
Wilmington MA 01887-1017
Wilmington,
01887 1017
Email:
john.ardizzoni@analog.com

106

Dennis Falls
Avnet Electronics Marketing
9200 Indian Creek Parkway
Suite 600
Overland Park, Kansas 66210
E-mail:
Dennis.falls@avnet.com

Th W
The
World
ld LLeader
d iin Hi
High
h Performance
P f
Signal
Si l P
Processing
i Solutions
S l ti

Thank You