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Tait T801 Frequency Reference
User manual with schematics for the Tait T801 frequency reference.
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Tait T801 Frequency Reference
User manual with schematics for the Tait T801 frequency reference.
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T801 Frequency Reference Module (01-00) Issue A Tait Service ManualM801-00 CONTENTS Page SECTION 1 GENERAL INFORMATION 1.1 Introduction La 1.2. Specifications 12 1.2.1 General 1.2 1.2.2 TF-4010A Rubidium Frequency Standard (If Fitted) 1.2 SECTION 2_ CONTROLS & OUTPUTS 2.1. Introduction 2d 2.2. Front Panel Controls 24 2.3. Rear Panel Inputs & Outputs 2.2 2.4 Monitoring And Status Indication 23 2.5 Local Control Of Frequency Offsets 23 2.6 Remote Control Of Frequency Offsets 2.8 2.7 Selection Of Internal Or External Frequency Standard 2.9 SECTION 3 OPERATING INSTRUCTIONS 3.1 SECTION 4 CIRCUIT DESCRIPTION 4 SECTION 5 TUNING & ADJUSTMENT 5.1 VCTCXO Alignment Sal 5.2. Calibration Of The Rubidium Standard a 5.2.1 General oa 5.2.2 Range Of Adjustment 5.2 5.2.3 Adjustment Procedure 5.2 SECTION 6 INSTALLATION 6.1 Mounting & Connection 6.1 6.2 Power Supply 6.1 6.3. Configuration 6.1 6.4 Fitting The Rubidium Standard 6.2 May 29/92 Page 5 Copyright TELMg01-00 SECTION 7 INTRODUCTION TO SERVICING 7.1 General 71 7.1.1 Notes 71 7.1.2 Technical Instructions 7 7.2. Mechanical 7 7.2.1 Pozidriv Recess Head Screws 7 7.3 Component Replacement 72 7.3.1 Leaded Components 72 7.3.1.1 Desoldering Iron Method 7.2 7.3.1.2 Component Cutting Method 72 SECTION 8 FAULT FINDING 8&1 Visual Checks al 8.2 General Faults 81 8.3 Lock Detect Conditions 81 3.4 Fault Finding Charts 8.2 8.4.1 All Loops Fail To Lock 8.2 B.2 df & df2 Loops Fail To Lock a3 SECTION 9__ PCB INFORMATION Parts Lists Grid Reference Index Using CAD Circuit Diagrams Parts List 220-01252-02 Grid Reference Index PCB Layout - Bottom Side PCB Layout - Top Side Circuit Diagram Wiring Diagram LIST OF ILLUSTRATIONS Figure 2.1. Front Panel Controls Figure 2.2 Rear Panel Inputs & Outputs Figure 4.1 T801 Circuit Block Diagram Figure 5.1 Rubidium Standard Adjustment Details Figure 7.1. Typical Anti-Static Bench Set-Up 21 22 41 52 71 TABLES Table 2.1 Use Of Offset Multiplier Switch Table 2.2 Frequency & ppm Offsets Table 2.3. D-Range Wiring For Remote Control Of Frequency Offsets May 29/92 Page 6 Copyright TELM801-00.General Information SECTION |__GENERAL INFORMATION 1_INTRODUCTION The T801 Frequency Reference Module is intended for use with T800 series base station equipment. Its function is to provide a high stability frequency source to which the synthesiser within the T800 base station can be locked. This will provide T800 transmitters with the frequency stability required for simulcast transmission. The master standard within the T801 is primarily intended to be rubidium, although high quality ovenised crystal oscillators can also be used in applications where more frequent readjustment of frequency is acceptable. ‘The T801 converts the output frequency from its master standard to the 12.8MHz required by the T800 base station. ‘Small frequency offsets with a minimum step size of 4.3x10-9 can be programmed to allow the elimination of static nulls in the coverage overlap area of two or more simulcast transmitters. May 29/92 Page Lt Copyright TELM801-00 General Information 1.2 _ SPECIFICATIONS 1.2.1 GENERAL Input Supply Voltage ++ 410.8 to +16V DC Operating Temperature Range + “10°C to +55°C ambient Input Supply Current: No Internal Standard + 1A peak, 150mA typical TF-4O10A Rubidium Standard... 4A peak, 1.6A typical Note: The current is at maximum at switch-on, but settles to approximately L.6A at 13.8V and room temperature with the internal rubidium standard. df1* And df2* Outputs: Output Amplitude ++ 43dBm 31.54Bm, 50 ohms Harmonic Distortion = -254Be Frequency s+ as per Table 2.2 Section 2 “Lower case "d" is used instead of the delta symbol in this manual because of typographic limitations, External Standard Inputs Required Level -15 to +10dBm, 50 ohms Harmonic Distortion o = -30dBe VCTCXO Stability When Not Locked .. 41-5ppm Minimum Offset Increment ++ 4.38x10-3ppm_ Maximum Offset Increment ++ 6.08ppm_ Dimensions: Height 90mm Width 483mm. Length 400mm. Weight a 49K Mounting 483mm (19") rack, 2U high 010A RUBIDIUM FREQUENCY STANDARD (IF FITTED) Frequency Accuracy «= 5x10-I] at shipment Frequency Stability aw Ixto-th Temperature Sensitivity «+ 3x10-10 over temperature range -10°C to +55°C Supply Voltage Sensitivity + <2x10-11 over module 3 minutes to lock Warm-Up Time 5 minutes to 2x10-11 Output Amplitude ++ +8dBm 32dBm sine 50 ohms Frequency + LOMHz May 29/92 Page 1.2 Copyright TELM801-00 Controls & Outputs SECTION 2 CONTROLS & OUTPUTS 2.1 INTRODUCTION ‘The T801 frequency reference module provides six synthesised outputs for use as frequency references for T800 base stations, The master standard can be either internal or external to the T801. These six outputs can be offset by small increments in frequency, varying the 12.8MHz mean frequency by up to approximately +5ppm. They are available as two groups of three: dil A,B,C df2 A,B,C. The frequency accuracy and stability are dependent on the frequency standard used. If for some reason the internal or external frequency standard fails, the six outputs default to 12.8MHz +1.5ppm, The T801 requires a 13.8V DC (nominal) power supply and uses a dedicated microprocessor to control the synthesis. 2__FRONT PANEL CONTROLS oS igure 2.1 Front Panel Controls LEDI Illuminates when the internal standard is phase locked. If not illuminated, the internal standard is not phase locked, LEDI will remain illuminated if an externa! standard is used. TPL The DC monitor point referred to the GND test point (TPS) as in all DC monitoring. Between 4 and 11V should be present when the internal standard is phase locked. No voltage will be present if an external standard is used. LED2 When illuminated, indicates the “in phase lock" status of the reference loop. TP2 Used to measure the loop control voltage, which should be 3V 41V between TP2 and TPS (GND). LED3 Iluminates when df synthesiser loop is locked. TP3 Used to monitor the synthesiser loop control voltage, which should be 2.5V +0.1V with no offset. Extreme offsets such as 43pm will read approximately +1V/-3ppm, to +4.2V/+3ppm. May 29/92 Page 2.1 Copyright TELOl oO) Oo M801-00 Controls & Outputs LED4 Illuminates when df2 synthesiser loop is locked. TP4 Used to monitor the synthesiser loop control voltages, which are similar to those for TP3 above. LEDS luminates when the key switch is on and the circuitry is energised. Key Switch When turned on, the key switch connects power from the rear fernal circuitry. panel connector to the TPS Ground, 2.3__REAR PANEL INPUTS & OUTPUTS FUSE 5A 14" fast blow fuse, in line with the 13.8V DC switched supply directly after the key switch. TERMINAL 1 Nominal 13.8V DC (4A) supply connection (polarity indicated). Swi df MSD hex switch for programming df1 synthesiser offsets. sw2 dfL LSD hex switch for programming df1 synthesiser offsets. sw3 df2 MSD hex switch for programming df2 synthesiser offsets. sw4 df2 LSD hex switch for programming df2 synthesiser offsets. sws Offset multiplier hex switch for programming x10 offsets, as shown below: SW5 Position SWI, SW2 SW3, SW4 0 xl xt 1 x10 xl 2 xl x10 3 x10 x10 May 29/92 Page 2.2 Copyright TELM801-00 Controls & Outputs swe Used to select the internal or external standard according to frequency. Position 0 corresponds to an external or internal standard of 10MHz, Positions 1-9 correspond to an external or internal standard of 1-9MHz, Positions A-F correspond to an external or internal standard of 12.8MHz. U, 12,3 df synthesiser outputs (+3dBm 41.54B), Th, 33, 16 412 synthesiser outputs (+3dBm #1.5dB). a The external standard input with the following input requirements: input amplitude; _->/=-15dBm, =+104Bm frequency: 1-10MHz of 12.8MHz accuracy: =tlppm. 8 The internal standard output. Where an- internal standard is used, e.g. the TF-4010A rubidium standard, this signal is connected directly to 37. The TF-4010A output frequency is 1OMHz with an amplitude of +8dBm 22dBm/50 ohms. If another internal standard is used, refer to its specifications. 2.4 MONITORING AND STATUS INDICATION Monitor test points are located on the front panel to allow DC voltages to be measured between the earth test point and the labelled loop test points. Five ted LED status indicators on the front panel show (when illuminated) that all loops are locked and that DC power is on, 2.5 LOCAL CONTROL OF FREQUENCY OFFSETS There are two separate synthesisers providing the two groups of three outputs to six female BNC connectors located on the rear panel. These two groups are Jabelled dfl A, B & C and df2 A, B & C. The three output signals in each group are identical except that each is buffered separately. ‘The dfl synthesiser is programmed with the “dfl SET" rear panel hex switches, and the df2 synthesiser with the "df2 SET" rear panel switches. Each group's status and synthesiser control loop can be monitored by an LED and voltage test point corresponding to that group on the front panel, When an LED is not illuminated, the corresponding loop is not locked and the DC. voltage on its test point measured with respect to the front panel ground test point will be either 0 or 5V DC (the negative and positive limits of the circuitry's supply voltage). May 29/92 Page 2.3 Copyright TELM801-00 Controls & Outputs When a loop is in phase lock, its front panel status LED is illuminated and its synthesiser loop voltage measured on its front panel test point will indicate (by the DC measured) in what direction the offset is, The sense of the synthesiser circuitry is positive, hence a positive frequency offset indicates a more positive voltage on the loop test point with respect to the zero offset condition, and likewise a negative offset indicates a more negative voltage with respect to the zero offset condition, The smallest offset is approximately +4.383x10-3ppm or 4.21Hz at a carrier of 960MHz, With no offsets and the loops locked, the synthesiser loop voltages measured on the test points will be 2.3V 10.1V. A negative offset of -0.3098ppm (switch position 47, refer to Table 2.2) will show 2.345V +0.1V, approximately 0.155V lower than zero offset. The sensitivity is approximately [.9ppm/V. From this it can be seen that very small increments will be difficult to measure on a low resolution digital voltmeter, approximately 1.8mV change per smallest increment. Greater increments are possible by use of the offset multiplier switch located on the rear panel. When the switches are set to (00), zero offset occurs, even if the offset multiplier switch is in a position other than zero. Table 2.1 indicates what offset is available with the offset multiplier switch when the df and df2 switches are not set to (00). Table 2.1 Offset Multiplier Group Group Switch oft fa 0 xl xi 1 x10 xl 2 xt x10 3 x10 x10 Table 2.2 shows all the frequency and ppm offsets available. Note that for offsets larger that +3ppm, it may be necessary to open the cabinet and adjust the VCTCXO modules (trimmer capacitors) on the synthesiser in question (df1 or df2) to ensure that the control line (which can be monitored on the front panel) lies between 1 and 4V. When df1 outputs are not used and df2 are, it is desirable to set df1 to the same switch position as df2, and vice versa. May 29/92 Page 2.4 Copyright TELTable 2.2 Frequency offset of reference ouputs selected by df, df2 and x10 switches. Not: the TCXO centre frequency. Refer to Section 5.1. Offsets greater than 3pm (shaded in the table) may require retuning of x1 x1 x10 x10 x x1 x10 x10 Sw Hz =~ PPM Hz Pem |Sw = Hz PPM Hz PPM 00 0.000 0.0000 0.000 0.0000]80 0.000 0.0000 0.000 0.0000 01 -0.056 -.0044 -0.561 -0.0438/81 0.056 0.0044 0.561 0.0439 02 -0.112 -.0088 ~-1-121 -0.0876/82 0.112 0.0088 1.124 0.0878 03 -0.168 -.0132 -1.680 -0.1313/83 0.168 0.0132 1.687 0.1318 04 -0.224 -.0175 -2.239 -0.1749]/84 0.225 0.0175 2.250 0.1758 05 -0.280 -.0219 -2.796 -0.2185/85 0.281 0.0219 2.815 0.2199 06 -0.337 -.0263 -3.353 -0.2620|/86 0.337 0.0263 3.380 0.2641 07 -0.393 -.0307 -3.910 -0.3054/87 0.393 0.0307 3.946 0.3083 08 -0.449 -.0351 -4.465 -0.3489/88 0.449 0.0351 4.513 0.3526 09 -0.505 -.0394 -5.020 -0.3922|89 0.505 0.0395 5.080 0.3969 OA -0.561 -.0438 -5.574 -0.4355|8A 0.561 0.0439 5.649 0.4413 OB -0.617 -.0482 ~-6.128 -0.4787/8B 0.618 0.0483 6.218 0.4857 0C -0.673 -.0526 -6.680 -0.5219|8C 0.674 0.0526 6.787 0.5303 OD -0.729 -.0569 -7.232 -0.5650/8D 0.730 0.0570 7.358 0.5748 OE -0.785 -.0613 -7.784 -0.6081|8E 0.786 0.0614 7.929 0.6195 OF -0.841 -.0657 -8.334 -0.6511/8F 0.843 0.0658 8.501 0.6642 10 -0.897 -.0701 -8.884 -0.6940/90 0.899 0.0702 9.074 0.7089 11 -0.953 -.0744 -9.433 -0.7369]91 0.955 0.0746 9.648 0.7537 12 -1.009 -.0788 -9.981 -0.7798|92 1.011 0.0790 10.222 0.7986 13 -1.065 -.0832 -10.529 -0.8226|93 1.067 0.0834 10.797 0.8435 14 -1.121 -.0876 -11.076 -0.8653/94 1.124 0.0878 11.373 0.8885 15 -1.177 ~.0919 -11.622 -0.9080/95 1.180 0.0922 11.950 0.9336 16 -1.233 -.0963 -12.167 -0.9506/96 1.236 0.0966 12.527 0.9787 17 1.289 ~.1007 -12.712 -0.9931|97 1.293 0.1010 13.105 1.0239 18 -1.345 -.1050 -13.256 -1.0356/98 1.349 0.1054 13.684 1.0691 19 -1.400 -.1094 -13.800 -1.0781/99 1.405 0.1098 14.264 YA -1.456 -.1138 -14.342 -1.1205/9A 1.461 0.1142 14.845 1B -1.512 -.1181 -14.884 -1.1628/9B 1.518 0.1186 15.426 1.2052 1c -11568 -.1225 -15.425 -1.2051|9C 1.574 0.1230 16.008 1.2506 1D -1.624 -.1269 -15.966 -1.2473|9D 1.630 0.1274 16.591 1.2962 1E -1.680 -11313 -16.506 -1.2895|9E 1.687 0.1318 17.175 1.3418 F -1.736 -11356 -17.045 -1.3316|9F 1.743 0.1362 17.759 1.3874 continued ... May 29/92 Page 2.5 Copyright TELM801-00 Controls & Outputs Table 2.2 (continued) x1 xL x10 x10 x1 x1 x10 x10 Sw Hz PPM Hz PpM |Sw 9 Hz = PPM Hz PPM .792 -.1400 -17.583 =+1443 -18.121 1531 -19.194 =.1574 -19.730 1618 -20.265 1662 -20.799 =:1705 -21.333 -.1749 -21.866 +1792 -22.398 1836 -22.929 1880 -23.460 1923 -23.990 1967 -24.520 2010 -25.049 2054 -25.577 2098 -26.104 -:2141 -26.631 +2185 -27.157 +2228 -27.682 +2272 -28.207 2.928 +2315 -28.731 -2.2446|B5 2.984 +2359 -29.254 -2.2855|B6 3.041 +2402 -29.777 -2.3263|B7 3.097 4.286 4.343 4.399 4.456 -.3315, -.3358 -.3402 & -13445 24 +2446 -30.299 -2.3671|/B8 3.154 12489 -30.821 -2.4079/B9 3.210 -.2533 -31.341 -2.4485/BA 3.267 ~+2576 -31.861 -2.4892|BB 3.324 12620 -32.381 -2.5297|BC 3.380 -+2663 -32.899 -2.5703|BD 3.437 -+2707 -33.418 -2.6107|BE 3.493 -:2750 -33.935 -2.6512|BF 3.550 -+2794 -34.452 -2.6915|co 3.606 ~+2837 -34.968 -2.7319|C1 3.663 -:2881 -35.483 -2.2721|/C2 3.720 -:2924 -35.998 -2.8123/C3 3.776 ~+2968 -36.512 -2.8525|/C4 3.833 -.3011 -37.026 -2.8926|/C5 3.889 -+3054 -37.538 -2.9327/C6 3.946 --3098 c7 4.003 ~-3141 cB 4.059 ~.3185 co 4.116 - +3228 CA 4.173 ~ +3272 CB 4.229 co cD cE CF Continued ... May 29/92 Page 2.6 Copyright TELTable 2.2 (continued) M801-00 Controls & Outputs x1 x1 x1 x1 sw Hz PPM Hz PPM 50 -4.465 -.3489 4.513 0.3526 51 -4.521 -.3532 4.570 0.3570 52 -4.576 -.3575 4.626 0.3614 53 -4.632 -.3619 4.683 0.3659 54 -4.687 -.3662 4.740 0.3703 55 -4.743 -.3705 4.797 0.3747 56 -4.798 -.3749 7853 0.3792 57 -4.854 ~.3792 4.910 0.3836 58 -4.909 -.3835 4.967 0.3880 59 -4.965 -.3879 5.024 0.3925 © SA -5.020 -.3922 5.080 0.3969 5B -5.076 -.3965 5.137 0.4013 SC 5.131 -.4009 5.194 0.4058 5D -5.186 -.4052 5.251 0.4102 SE -5.242 -.4095 5.308 0.4147 SF -5.297 -.4139 5.364 0.4191 60 -5.353 -.4182 5.421 0.4235 61 -5.408 -.4225 5.478 0.4280 62 5.464 ~.4268 5.535 0.4324 63 -5.519 -.4312 5.592 0.4369 59 64 -5.574 -.4355 5.649 0.4413 60: 65 -5.630 -.4398 5.705 0.4457 66 -5.685 -.4441 5.762 0.4502 67 5.740 -.4485 5.819 0.4546 68 -5.796 -.4528 5.876 0.4591 69 -5.851 -.4571 5.933 0.4635 6A 5.906 ~.4614 5.990 0.4680 6B -5.962 -.4658 6.047 0.4724 6C ~6.017 -.4701 6.104 0.4769 6D -6.072 -.4744 6.161 0.4813 6E -6.128 -.4787 6.218 0.4857 GF -6.183 -.4830 6.275 0.4902 70 -6.238 -.4874 6.331 0.4946 71 -6.294 -.4917 6.388 0.4991 72 -6.349 -.4960 6.445 0.5035 73 -6.404 -.5003 6.502 0.5080 74 -6.459 -.5046 6.559 0.5124 | 75 -6.515 -.5090 6.616 0.5169 76 -6.570 -.5133 = 6.673 0.5214 TI -6.625 -.5176 6.730 0.5258 78 -6.680 -.5219 6.787 0.5303 79 -6.736 -.5262 6.844 0.5347 TA ~6.791 ~.5305 6.901 0.5392 7B -6.846 ~.5348 =63 6.958 0.5436 Te -6.901 -.5392 7.015 0.5481 7D -6.956 -.5435 7.073 0.5525 TE -7.012 --5478 7.130 0.5570 TE -7.067 -.5521 7.187 0.5615 May 29/92 Page 2.7 Copyright TELM801-00 Controls & Outputs 2.6 _REMOTE CONTROL OF FREQUENCY OFFSETS Remote control of the offsets of df1 and df2 outputs (not the x10 multiplier) is possible, as well as remote monitoring of alarm status. This is accomplished by wiring a 25-way D-range connector to the PCB mounted on the inside of the rear panel. This connector (not supplied) may be mounted by removing the blanking plate on the rear panel. Table 2.3 shows the connections. Note: When selecting remote operation, set dfl and df2 switches to (00). Use a “~~ flat blade tool (2.5x0,5mm) for rotating the switches, Table 2.3 PCB Terminal S10 su S12 S13 Slt SIS S16 si7 s2i S22 Logic "I" selects the bit. Label df dil dil dil dil dil dtl df MsD ot LsD HN ee out of lock alarm (open collector fz fz fz fz tz fz fz fz + ov 22 ohm sink resistance) MsD Ne oe ae LSD DC (caution: not protected) Switch codes are according to the hex numbers given in Table 2.2. May 29/92 Page 2.8 Copyright TELM801-00 Controls & Outputs 2.7 __SELECTION OF INTERNAL OR EXTERNAL FREQUENCY STANDARD, The T801 allows for the following frequency standard frequencies to be.used. The rear panel "STD. FREQ. SELECT" hex switch must be set to the corresponding position, 3 g. 5 Frequency Of Standard 1OMHz IMHz 2MHz 3MHz 4MHz, 5MHz 6MHz 7MHz 8MHz 9MHz 12.8MHz wWeraueunno a 4 The TF-#010A rubidium frequency standard is a 10MHz output and the switch selector is thus set to zero, When the internal standard is used, a coaxial cable (provided) couples the internal standard output connector to the external standard input connector. May 29/92 Page 2.9 Copyright TELM801-00 Operating Instructions SECTION 3__ OPERATING INSTRUCTIONS For this description it is assumed that the internal standard is used (TF-4010A rubidium). Note: If an external standard is used, it must have an accuracy of better than +ippm. * Connect a 4A 12V DC power source to the rear panel power terminals, * Connect the dfl A, B & C and df2 A,B & C outputs to the equipment they are driving (outputs can be left disconnected if they are not used). * Check that the coaxial cable coupling the internal standard output connector (J8) to the external standard input connector (7) is in place, * Programme the rear panel hex switches. * Insert the key into the front panel switch and turn it ons check that the "On" LED illuminates. Approximately 30 seconds later the "Reference Loop" LED will illuminate. Check that the loop voltage measures 3V DC +1V. The reference loop is now locked. * After typically 3 minutes the "Internal Standard" LED will illuminate, indicating that its loop is locked. Check that the loop voltage measures between 4 and LIV. * The dfl and df2 loop LEDs on the front panel will illuminate in approximately 5-7 minutes for low offsets and longer for larger offsets. The maximum time from power on to both dfl and df2 loops being locked ‘can be up to 21 minutes. If the loop is not locked by this time, the alarm (if connected to terminal 9 as per Table 2.3) will be activated and the loop that is not locked will have its control line open circuited and its output will revert to 12.8MHz L.Sppm. The synthesiser can be reset by either turning the power key off then on again (in which case the TF-4010A will need to lock again) or turning one of the rear panel hex switches momentarily off and then back to its original position. * If the T801 "On" LED fails to illuminate, check the 5A fuse in the rear panel fuse holder. ‘The internal standard operates from a 12V to 24V DC-DC up-convertor with two fuses on the filter PCB. Check and replace if necessary. The fuse types are 1}" 5A fast blow and 14" 2A fast blow. May 29/92 Page 3.1 Copyright TELM801-00 Circuit Description SECTION 4 CIRCUIT DESCRIPTION tev p12 cawennen Pf Since sore ‘se |? | \ oe a ' fe > ' 1 ' termes Too sits |—f 6 abe [8 et ote DH 7 p> >| an vmopenmmaum [TBA ros fn Tee [Ta } ont es Figure 4.1 TR01 Block Diagram igure 4.1 shows the T801 circuitry. There are three PLL synthesisers and the two offset loops (df1 and df2) are locked to the frequency standard via the reference PLL. ‘The reference synthesiser divides the frequency standard output frequency down to a reference of 847.4576271Hz. This is multiplied by the synthesiser to 12,79915254MHz which is then used as a reference for the offset loops (df and f2). May 29/92 Page 4.1 Copyright TELM801-00 Circuit Description To achieve the required fine offsets, the offset loops first divide the reference signal by N-1, then multiply it by N. If N is incremented by 1, then it can be shown that the incremental change in output frequency closely approximates 1/N? of that frequency. If N = 15104, then the output frequency is 12.8MHz, i.e. no frequency offset. For this value of N, the incremental offset is 4.383x10-9, which equates to 4.21Hz at a transmitter frequency of 960MHz, or 0.289Hz at 66MHz. The frequency offsets are defined by codes on hex switches SWI to SW4. The codes are divided into two equal regions, 0 to 127 (00 to 7F) and 128 to 255 (80 to. FF). The first region directly equates to the synthesiser division ratio N+(0 to 127) and provides a negative offset. The second region (80 to FF) equates to N-(0 to 127) and provides a positive offset. The offsets can be multiplied by a factor of 10 by using the multiplier switch, sw5. The full range of possible offsets lies in the range N+/-1270, which corresponds to -5.136ppm and +6.078ppm, The frequency offsets given in ppm for the various switch codes are given in Table 2.2, When the T801 leaves the factory, its VCTCXOs are adjusted so that their maximum control voltages are approximately at the middle of their tuning range. a3ppm is the maximum offset available without readjustment of the VCTCXOs. Considerable care must be exercised when making this adjustment since the VCTCXO trimmers are very delicate (refer to Section 5). Each of the three PLLs uses a single dedicated synthesiser IC which is controlled by a single, common, one-time programmable microprocessor. The micro- processor outputs the synthesiser data streams only following power-up, or if one of the hex switches changes state. Note: When ordering a spare, it is necessary to specify a programmed version of this device. The synthesisers are serially loaded by a single data stream in order of the reference loop, followed by the df and then the df2 loops; i.e. the reference loop is the last to receive its data. All three synthesisers share common data latch and clock lines. The VCTCXOs of the df1 and df2 loops have a control line sensitivity of only 1.9ppm/V which gives these loops relatively long lock-up times. The reference loop VCXO has a control line sensitivity of approximately 30ppm/V and locks at 12.79915254MHz. The control line voltage is monitored by the lock detect circuit which provides (LD2) a logic "I" output when the loop is locked. Similarly, the df1 and df2 loops have lock detect signals, LD3 and LD4& respectively, which are passed to the microprocessor. If the rubidium standard is used, its lock detect output is also passed to the microprocessor (LD1). Note that this line is pulled high by a 100k resistor, for when no rubidium standard is fitted, so that a false out-of-lock condition is not detected by the microprocessor. If the microprocessor detects an out-of-lock condition, the dfl and df2 loops are "disabled", i.e, left to free run, This means that the overall stability of the T801 is then reduced to the inherent stability of the VCTCXOs, +1.5ppm. May 29/92 Page 4.2 Copyright TELgo! The microprocessor will disable the df1 and df2 loops if either the rubidium standard ot the reference loops do not lock within 6 minutes from power-up. Alternatively, it will disable either of dfl or df2 loops if one or other does not lock in 21 minutes from power-up. Similarly, during normal operation, a fault in either the rubidium standard or the reference loop will disable both dfi and df2. If, however, a fault occurs in either {1 or df2, then only the faulty loop wil be disabled, Whichever loops are disabled will be indicated by the front panel LEDs. If the fault was momentary, one of the hex switches could be toggled to avoid having to wait another 21 minutes. May 29/92 Page 4.3 Copyright TELM801-00 Alignment & Adjustment SECTION 5__ TUNING & ADJUSTMENT 5el_-VCTCXO ALIGNMENT It may be necessary from time to time to realign the VCTCXOs because of natural ageing, or if a frequency offset greater than +3ppm is required. The adjustment is made by the trimmer on the top of each YCTCXO and must be performed so that the loop control voltage falls within the correct voltage window for the programmed offset. Example The required offset selected from Table 2.2 is +5.0483ppm, hex code EBx10, for loop dil, * Set hex switches SWI, SW2 and SW3 for +3ppm offset (C2x10) and wait for the loop to lock, Adjust the trimmer for a loop voltage of 1V, measured at front panel test point TP3, * Set SWI and SW2 for an offset of +5.0483ppm (EBx10) and the loop will lock at between 2 and 3V, To return to zero offset, the reverse procedure applies. If for any reason the loop loses lock (e.g. incorrect adjustment of the trimmer) and the microprocessor disables the loop, the recovery procedure is as follows, * Measure the output frequency of the offset loop in question to an accuracy ‘of 0.5ppm or better. * Tune the trimmer for an offset of Oppm. * Programme the hex switches for Oppm offset. * Allow the loop to lock, then adjust the trimmer for a loop voltage of 2.5V 40.1V. 5.2_ CALIBRATION OF THE RUBIDIUM STANDARD 3 NERAL 1 If the Quartzlock model TF-4010A rubidium frequency standard is fitted, adjustment will be necessary from time to time. The frequency of readjustment will depend on the magnitude of the frequency offset employed. Zero frequency offset will require the most frequent adjustment. To give some idea of the likely period between recalibration, the ageing characteristics of the TF-4010A are as follows: 5x10-11 per month, starting at the second month, 5x10-10 per year for the first year, 2x10-10 per year after the first year. May 29/92 Page 5.1 Copyright TELM801-00 Alignment & Adjustment 3 RANGE OF ADJUSTMENT ‘As taken from the manufacturer's specifications (Dartington Frequency Standards). The following adjustment is possible: Mechanical Adjustment w+ 3x10-9 Electrical Adjustment ct 3x10-9 For electrical adjustment, pin 2 of the D-range connector can be 0-10V DC. adjustable voltage. The frequency will increase for positive change in voltage, i.e. OV gives a lower frequency and 10V gives a higher frequency. This allows 41.5x10-9 around the mechanical adjustment set point. Pin 3 is the electrical adjustment return, Note that there is no provision for electrical adjustment of the rubidium standard within the T801 as standard, and that it will normally be necessary to trim the frequency via the mechanical adjustment. ADJUSTMENT PROCEDURE The following is an extract from the manufacturer's data sheet: Frequency drift should be less then 5x10-11 per month starting from th second month, 5x10-10 per year for the first year, and afterwards 2x10"! per year. Therefore, a periodical frequency calibration is recommended, depending on the specific application. Frequency adjustment is performed via the frequency adjustment trimmer located on top of the unit, accessible by removing the closing sticker. One turn equals approximately 5x10-10. The adjustment may be done as follows (refer to Figure 5.1): The unit is compared with a reference (Cs clock or a calibrated Rb standard) via a phase comparator, TF-3009A. Phase drift of 2/100, at IMHz, during 1000s, corresponds to a frequency offset of 1x10-! & Figure 5.1_Rubidium Standard Adjustment Details Alternatively, a frequency counter may be used, provided that adequately long. gate times are possible and that its reference clock is guaranteed to be invariant between individual transmitters. Locking to a broadcast high stability frequency standard is ideal for this purpose. May 29/92 Page 5.2 Copyright TELM801-00 Installation SECTION 6 _ INSTALLATION 6.1__MOUNTING & CONNECTION The T801 is designed to mount in a 483mm (19") rack frame, It requires a depth of approximately 400mm to allow clearance for the rear connector and cable entry, and a clearance in height of approximately 95mm to allow for adequate air flow around the unit. All coax connectors are BNC female, while the DC input is via a connector block mounted on the rear panel. Note: In order that the internal rubidium standard (if fitted) can keep within its “~~ operating limits at high ambient temperatures, it is important that an adequate convective air flow can be maintained over the T8Ol. Installations with closely packed equipment or unventilated cabinets should be avoided. 6.2__POWER SUPPLY Because frequency stability is critical in simulcast applications, it may be desirable, for the sake of system reliability, to use a battery based power supply. This Is because the rubidium frequency standard requires a warm-up time of 3 minutes to lock and 5 minutes to 2x10-11, and once out-of-lock, the T801 can take up to 21 minutes to acquire lock. The power supply to the T801 is controlled by a key switch to prevent unauthorised or inadvertent power-down of the unit. Note: When power is removed from the T801, the transmitters which are referenced to it will cease to transmit. A momentary loss of power will result in a frequency stability of only +1.5ppm until lock is once again acquired. 6.3__CONFIGURATION The T801 may be configured as a stand-alone frequency reference with its own internal reference standard, such as the TF-4010A rubidium standard, or even a high stability ovenised crystal oscillator. * If the TF-4O10A rubidium standard is used, connect BNC connector J8 on the rear panel to J7 with the short coaxial link supplied. Set SW6 to position "0" as the reference frequency is 1OMHz. * If an external frequency standard is used, connect its output to the external standard input BNC connector (37) via a 50 ohm cable. Programme SW6 to accept the frequency of the external standard, which must be in the range of 1 to 1OMHz in IMHz steps, or 12.8MHz. * If there is a rubidium standard in the T801 and it is not being used, it must be disabled by unplugging its D-range connector and removing the 10A fuse (F3) on the filter PCB. May 29/92 Page 6.1 Copyright TELM801-00 Introduction To Servicing SECTION7 INTRODUCTION TO SERVICING 7.1_.GENERAL NOTES If further information is required about the T801 or this Manual, it may be obtained from Tait Electronics Ltd or accredited agents. When requesting this information, please quote either the equipment serial number or works order number (found on a label at the back of the set). In the case of the Service Manual quote the Tait Internal Part Number (IPN) and Issue, and for Circuit Diagrams quote the 'Title’ and ‘Issue’. CAUTION: CMOS DEVICES This equipment contains CMOS Devices which are susceptible to damage from static charges, Care when handling these devices is essential. For correct handling procedures refer to manufacturers' data books covering CMOS devices, e.g. Philips Data Handbook Covering CMOS Devices; Motorola CMOS Data Book Section 5 (Handling Procedures), etc. To BUNDING EARTH NOT MANS EARTH ‘ai Senes eSSIOR wera. ae Figure 7.1_ Typical Anti-Static Bench Set-U 7.1.2 TECHNICAL INSTRUCTIONS (TI's) From time to time T's are issued by Tait Electronics Engineering Division. These TI's may be used to update equipment or information, or to meet specific operational requirements. 7.2__MECHANICAL 1_POZIDRIV RECESS HEAD SCREWS Pozidriv recess head screws are the preferred standard on all Tait manufactured equipment. The very real advantages of this type of screw will not be realised unless the correct screwdrivers are used by servicing personnel. May 29/92 Page 7.1 Copyright TELM801-00 Introduction To Servicing 7.3__COMPONENT REPLACEMENT 7.3.1__LEADED COMPONENTS Whenever components are removed from or fitted to the PCB, care must be taken to avoid damage to the track. The two satisfactory methods of removing ‘components from PTH PCB's are detailed below. Note: The first method requires the use of a desoldering station, e.g. Philips SBC 314 or Pace MBT-100E. 7.3.1.1 _Desoldering Iron Method Place the tip over the lead and, as the solder starts to melt, move the tip in a circular motion, Start the suction and continue the movement until 3 or 4 circles have been completed, Remove the tip while continuing suction to ensure that all solder is removed from the joint, then stop the suction. Before pulling the lead out, ensure it is not stuck to the plating. If the lead is still not free, resolder the joint and try again. Note: The desoldering iron does not usually have enough heat to desolder leads from the ground plane. Additional heat may be applied by holding a soldering iron on the tip of the desoldering iron (this may require some additional help). 2. Component Cutting Method Cut the leads on the component side of the PCB. Heat the solder joint sufficiently to allow easy removal of the lead by drawing it ut from the component sider de not use undue torce. Fill the hole with solder and then clear with solderwick. May 29/92 Page 7.2 Copyright TEL,M801-00 Fault Finding SECTION 8 FAULT FINDING 8.1 VISUAL CHECKS Remove the top cover from the T801 and inspect the PCBs for damaged or broken components. Check for defective solder joints, If repair or replacement is considered necessary, refer to Section 7.3. 8.2_.GENERAL FAULTS The reference loop and the internal standard must be locked within 6 minutes from power-up or the dfl and df2 loops will be disabled by the microprocessor. Similarly, the df and df2 loops must be locked within 21 minutes from power-up or they will be disabled by the microprocessor. The microprocessor has its programme stored within its one-time programmable ROM. Its function is to programme and control the synthesisers. If the microprocessor is faulty, the synthesiser will be loaded with incorrect data or no data at all. The df1 and df2 loops will not lock if the reference loop is not locked, or if the reference loop is driven by a frequency that is more than 23pm from its correct operating frequency (assuming the VCTCXOs are not trimmed in this way). This will cause the df1 and df2 loops to trip the associated lock detect circuit and the microprocessor to disable the loops. The in-lock voltage window of the lock detect circuits is between 0.4 and 4.6V. Check the standard for the required frequency. 8.3 LOCK DETECT CONDITIONS Item Fault Effect Internal Goes out of lock after 6 minutes have The microprocessor disables the Standard elapsed from power-up. £1 and df2 control loops. Note: If an external standard is used, no lock information is available: the microprocessor “senses a locked condition permanently. Reference Goes out of lock after 6 minutes have The microprocessor disables both Loop elapsed from power-up or after 21 df1 and df2 control loops. minutes have elapsed since df1 & df2 acquired lock. Note: If the fault condition is momentary (occurred during checking), toggle any of the hex switches and wait for the loop to lock. dt1/at2 Either or both loops fail to lock before The 1oop(s) will be disabled by Loops 21 minutes have elapsed from power-up. the microprocessor. Either or both loops go out of lock The loop(s) will be disabled by after 21 minutes, the microprocessor. Note: The microprocessor disables the df and df2 loops by holding their control lines open. Pulling pins 6 & 13 of analogue switch IC13 low opens the switches of dfl and df2 respectively. May 29/92 Page 8.1 Copyright TELM&01-00 Fault Finding 8.4 FAULT FINDING CHARTS 8 1__ALL LOOPS FAIL TO LOCK RO gta. & net, Ioope Fail to tock 'in' 16 Re otd conmected to D-Renge, Connect 9 Fe sridone-2d G6 to oc |S of teats Be, 'bs necosaary, Is TF-40108 1000 voltage on TPi stv sTiv'eeminutoe after | y orp? [NJ te tock detest gional Bresont £ LED! avtver Bireute on. titer PCo Oc? I (Coax Link between U7 & Replace on repair 8 OKT [> as necessary. Replace Ab eta, Replace 104 or 05, iran z ST Vv ea TTTE] y . Bees OOS. 7 apt ment mean TE : pore eee een y_ must: ordered from : # Te SWB In, position ipagosttton | Nise v6. y Does ref Loop lock? Check ref 18 Tr2 voi tage sv s1V7 Tei ce PAY ts LED3, I Tamtnatea? Replace If necesaary. May 29/92 Page 8.2 Copyright TELM801-00 Fault Finding 8.2 df J & df2 LOOPS FAIL TO LOCK SE rer, Are, JI J, out N ic butfere Soden 1 Sed® |__S | oom ek ect 12.80 £i: Sppa? check "rcot'€ ‘too2. Y Set Svi-su5. Check 103 pins 6 & 13 ——t __ heck JAP a SFE " 7 10 (0008 10k in al Ties titers, Check. ininuteo? lock dgtoct sincule che ge are ayn. 5 ie" Have bean ‘peogrenned, Ts off & are output |_W Gheck ret eta 2 : 126005002 [+h] Y ‘Ott & af2 loope Ox. May 29/92 Page 8.3 Copyright TELM801-00 PCB Information SECTION 9__ PCB INFORMATION PARTS LISTS The 10 digit numbers (000-00000-00) in this Parts List are "internal part numbers" (IPN's). Your spare parts orders can be handled more efficiently if you quote: equipment type, circuit reference and IPN, along with a brief description of the part. The components listed in this Parts List are divided into two main types: those with a circuit reference (e.g. C2, D1, R121, etc) and those without (miscellaneous and mechanical). Those with a circuit reference are grouped by component type in numerical order. Each component entry comprises three columns: the circuit reference, IPN and description. The miscellaneous and mechanical section lists the variant and common parts in IPN order. GRID REFERENCE INDEX To assist in locating components and labelled pads on the PCB layout and Circuit Diagram, a component grid reference index has been provided. This index lists the components and pads in alphabetical order, along with the appropriate alphanumeric grid references. The first digit in the Circuit Diagram reference is the sheet number, and the last two characters give the location of the component on that sheet. The first digit in the PCB layout reference is a "1" or "2", indicating the top or bottom side layout respectively, and the last two characters give the location of the component on that diagram. USING CAD CIRCUIT DIAGRAMS Reading a CAD Circuit Diagram is similar to reading a road map, in that both have an alphanumeric border. The Circuit Diagrams in this Manual use letters to represent the horizontal axis, and numbers for the vertical axis, These Circuit Diagram "grid references" are useful in following a circuit that is spread over two or more sheets. When a line representing part of the circuitry is discontinued, a reference will be given at the end of the line to indicate where the rest of the circuitry is located. The first digit refers to the sheet number (printed on the bottom right hand corner of the CAD diagram) and the last two characters refer to the location on that sheet of the continuation of the circuit (e.g. 1-D4). If more than one line is represented (indicated by a double thickness line), a dot with a reference label will follow the route each individual line represents. May 29/92 Page 9.1 Copyright TELRERRRRRRRGLSIGTIGGSSIRRRRR LARGER ARR ARSRSLLLSPERoReRApReRRIeReeRgeaRE ‘Go oourieg on oa ‘Se vou on 0007 ‘Se tvourec out eae ‘Se wowourwc ante ot030y May 29/92 f aaz gas engagcone CBSRrg gneae seegrg g geeceseens 2 2g2gaaanaran2 ¢ HEAT i i il BRRBERRRRRREREEzzz2 DescRIPTION Ssmacsameceronn Tose nr 60 Copyright TELM801-00 PCB Information new DESCRIPTION Ber pw DESCRIPTION = erences as min eee nesreunaaendmrana SSeS Meruumeemataae mi Seven fesraunaaanecmant nee mm Seain Se Seeman. hacer amauaacc coment raven waist ‘See Raincrmear nat Se samen Tantaupostrocuox coat Ti Sees Marae oneara aa, Sie esas © rianartnowemrcnure = seruatormeean a fers dewneose Set tamar na rnuroncanton = Sra mucin at jor hemes Tootemeestarra coro smcaea ‘fesruiaan verona A i May 29/92 Page 9.3 Copyright TELM801-00 PCB Information ‘7801 MECHANICAL & MISCELLANEOUS PARTS ww DESCRIPTION ew DeSonTION cm cnet Buca May 29/92 Page 9.4 Copyright TEL‘M801-00 PCB Information 1801 GRID REFERENCE INDEX (220-01252-02) DEVICE PCB CIRCUT DEVICE PCB CIRCUIT DEVICE PCB CIRCUIT DEVICE_ Pes CIRCUIT ; o = = os & & os os Mm i z 2 a fe 2 i See = z 2 8 ‘ = 5 = ES 2 i ie E ta g ees A z 2s S a 7 x. es MA 483 ¢ 8 Ws 5 iS g en 2 & a a & ey & & = zt E = # oo = = 2 . = & = = ae = & 2 3 = s = & = 2 5S 5 = B 4 2 e = = 8 eI 2 eI a om = S a 8 = gS 3 =» 2 2 & & Ss 2 2 & # # £e & = eae te fF Be & & i Seer et eee = i RE & a = 2 #8 & eee 2 &P 8 # 7 eee = a & 8 ae ee aes. ibe 2 : ta me mom ES = 2 fe 3B 2 2 2 2 ee = pa in os = = & eee = ae eee cee e 2 2 ie a 8 eee 2 8 =e & = Fa eee £ @ B 8 eos aaa 2 #2 & eee eee 2 & & & z 2 & aS g & Fe 2 a & = a» i ae 8 & os = & aes g eae a OE = ie 2 & a 8 Steere eae a & = = 2 & 3 8 - & 3 eS mn iw BE = i & a 8 = 3 = eee eae & Sete cee = i 2 2 #2 & PA 2 2 #2 & * 2 & a : #2 & See 2 222 8 Secu es Hoe = 22 = Boe eS = es 2 £8 EF RE Ro. & May 29/92 Page 9.5 Copyright TEL6 er dddaggangees ws te wre we 18 ue toe i an May 29/92 M&01-00 PCB Information Page 9.6 Copyright TELoLvive By « Ae ee re re oe a Oe cP Ee. ware Bary 8 = aes Om | maHt Ons oot eet UE] pen mye] sea Orage pees , | 20g Oo 7 pat | Sar@~ 8 }3 | ea ‘ | jt + = TITLE — as = ie" — mente ——[ueetce tame fo RREQUENCYM801-00 PCB Information T Way 23799 Copyright TEL FILE NAwE GOLFRL@A FILE DATE: 2570/82 TAIT ELECTRONICS NEW ZEALAND a4 ao 8 ae onnwine no. C782 SHEET 4 NCE MODULE se 220-01252-02 ors | ae To Toa ‘Te01 CIRCUIT DIAGRAM Page 9.9
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